Unknown W. Brackets
df313bd296
riscv: Fix rounding mode setting.
2023-07-25 20:33:56 -07:00
Unknown W. Brackets
9157d992ac
jit-ir: Implement cfc1/ctc1.
...
This makes it so we can track rounding mode changes.
2023-07-25 20:33:56 -07:00
Unknown W. Brackets
05360d5c7a
riscv: Implement simplest float ops.
2023-07-25 20:33:56 -07:00
Unknown W. Brackets
a8edf5fa24
riscv: Reduce bloat in jit fallbacks.
2023-07-25 19:42:04 -07:00
Unknown W. Brackets
b2d3c750f1
irjit: Define a specific IRReg type.
2023-07-23 18:01:00 -07:00
Unknown W. Brackets
e271e43ec5
riscv: Initial staffolding for IR based jit.
2023-07-23 18:01:00 -07:00
Unknown W. Brackets
3468423bb4
Debugger: Handle missing crash/block ptrs better.
2023-07-23 18:01:00 -07:00
Unknown W. Brackets
e4f9c72fe9
riscv: Avoid unaligned mem combine in IR.
2023-07-16 16:20:58 -07:00
Unknown W. Brackets
d4e689b096
irjit: Allow IRInterpret() on partial block.
...
For later if we want to fallback from native to IR interpret.
2023-07-16 16:19:53 -07:00
Unknown W. Brackets
6da10463f9
Debugger: Make reg names safer, stop using v000.
...
Better to use S000, etc. as that's more clear throughout.
2023-04-29 09:48:33 -07:00
Unknown W. Brackets
46101581c0
Core: Cleanup disasm buffer usage.
2023-04-29 09:07:25 -07:00
Henrik Rydgård
fc62d587c0
Fix whitespace issues
2023-04-02 16:36:39 +02:00
Герман Семенов
8d5af48efd
Core: using if constexpr C++17 optimization
2023-04-02 16:35:57 +02:00
Henrik Rydgård
d586ec0d5e
Don't create Host objects except in headless/unittest
2023-03-25 10:47:01 +01:00
Unknown W. Brackets
d97790e28e
irjit: Fix vi2us/vi2s with non-consecutive.
...
Vec2ClampToZero and similar assume consecutive.
2023-03-15 21:30:35 -07:00
Henrik Rydgård
700a018ef0
IRInterpreter: Use alignment as access size in exceptions
2023-01-01 20:48:16 +01:00
Henrik Rydgård
aa80659530
Memory exception: Add facility to track size
...
Might theoretically help in tracking some things down.
Not fully utilized yet, the fault handler needs to extract the
information from the faulting instruction. But we can use it for
GetPointerRange etc.
2023-01-01 20:30:29 +01:00
Unknown W. Brackets
9cfcbc46e6
Global: Cleanup initialization/pointer checks.
...
Cleaning up a lot of cases of uninitialized data, unchecked return values
for failures, and similar.
2022-12-10 21:13:36 -08:00
Unknown W. Brackets
a7b7bf7826
Global: Set many read-only params as const.
...
This makes what they do and which args to use clearer, if nothing else.
2022-12-10 21:13:36 -08:00
Unknown W. Brackets
f44852bb18
Global: Cleanup virtual/override specifiers.
...
Also missing virtual destructors, hidden non-overrides, etc.
2022-12-10 21:13:36 -08:00
Unknown W. Brackets
c085413326
irjit: Consistently check vec4 safety.
...
Just to prevent confusion/surprises, this is clearer.
2022-11-18 19:06:50 -08:00
Unknown W. Brackets
ada0674415
irjit: Allow VV2Op SIMD with exact overlap.
...
None of these look at other lanes.
2022-11-18 17:54:58 -08:00
Unknown W. Brackets
2419e5680a
irjit: Correct VV2Op SIMD check.
...
It's unlikely, but possible, uninitialized data could cause
IsConsecutive4() to return true when n < 4.
2022-11-18 17:53:53 -08:00
Henrik Rydgård
e97d5498c6
Merge pull request #16306 from unknownbrackets/ir-prefixes
...
irjit: Correct prefix validation
2022-10-31 09:11:52 +01:00
Unknown W. Brackets
eef29d5e95
irjit: Correct prefix validation.
...
Some vcmps, etc. were perfectly valid but were forcing to interp.
This also catches more cases that should go to interp correctly.
2022-10-30 23:15:54 -07:00
