Unknown W. Brackets
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2b964fd3b0
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irjit: Handle more common Vec4 prefix cases.
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2023-08-06 13:38:00 -07:00 |
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Unknown W. Brackets
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79ca880ac7
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irjit: Implement vqmul, add Vec4Blend.
Should be useful more places.
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2023-08-06 13:38:00 -07:00 |
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Unknown W. Brackets
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85ee7c85c1
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irjit: Allow masked vneg.q.
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2023-08-06 13:38:00 -07:00 |
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Henrik Rydgård
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d90dbcb28e
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Merge pull request #17857 from unknownbrackets/ir-vfpuctrl
irjit: Fix mfvc eating prefixes
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2023-08-06 17:56:22 +02:00 |
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Unknown W. Brackets
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a32889d3ca
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irjit: Consistently dirty vfpuctrl in IR.
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2023-08-06 08:36:19 -07:00 |
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Unknown W. Brackets
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a29a35b91a
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irjit: Fix mfvc eating prefixes.
It doesn't and shouldn't, which is why it's marked as not.
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2023-08-06 08:28:25 -07:00 |
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Henrik Rydgård
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70622e0d4e
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Merge pull request #17853 from Nemoumbra/buildfix
Buildfix for VS2017
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2023-08-06 14:29:04 +02:00 |
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Nemoumbra
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c2f9ae2e16
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Buildfix for VS2017
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2023-08-06 15:06:54 +03:00 |
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Unknown W. Brackets
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93e3d35f5d
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irjit: Move more to IRNativeBackend, split.
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2023-08-06 00:16:43 -07:00 |
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Unknown W. Brackets
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691799a0ca
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irjit: Centralize native jit compile dispatch.
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2023-08-03 23:14:58 -07:00 |
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Unknown W. Brackets
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b03398a46c
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Merge pull request #17815 from unknownbrackets/riscv-jit
riscv: Spill registers more intelligently
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2023-07-30 14:49:37 -07:00 |
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Unknown W. Brackets
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f870271011
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riscv: Spill registers more intelligently.
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2023-07-30 14:24:12 -07:00 |
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Unknown W. Brackets
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f3240393fa
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irjit: Use vf for vfpu regs, v0 is a gpr.
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2023-07-30 14:16:17 -07:00 |
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Unknown W. Brackets
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6819acd29f
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irjit: Fix flag on float cond move.
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2023-07-30 14:16:17 -07:00 |
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Unknown W. Brackets
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5db6b11ef2
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irjit: Cleanup self-fmovs.
These were sometimes getting emitted.
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2023-07-30 14:16:17 -07:00 |
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Unknown W. Brackets
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c24e3ef831
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riscv: Implement ll/sc.
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2023-07-30 00:45:51 -07:00 |
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Henrik Rydgård
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b93275bb35
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Merge pull request #17800 from unknownbrackets/riscv-jit
More RISC-V jit ops
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2023-07-30 09:26:22 +02:00 |
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Henrik Rydgård
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c8447ff4b7
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Merge pull request #17801 from unknownbrackets/irjit-vminmax
irjit: Fix vmin/vmax nan handling
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2023-07-30 09:18:25 +02:00 |
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Henrik Rydgård
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180bda6f6b
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Merge pull request #17799 from unknownbrackets/irjit-lsu
Add ll/sc to IR and x86jit
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2023-07-30 09:15:55 +02:00 |
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Unknown W. Brackets
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6aa4b0c5e1
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irjit: Fix vmin/vmax nan handling.
Should be relevant to NFS MW and possibly other game bugs.
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2023-07-29 19:13:12 -07:00 |
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Unknown W. Brackets
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8d60c10a64
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riscv: Use jit address offsets directly.
We'll have IR able to use block number or target offset.
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2023-07-29 19:02:15 -07:00 |
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Unknown W. Brackets
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e228748449
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irjit: Add FCvtScaledSW to safely scale vi2f.
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2023-07-29 18:30:15 -07:00 |
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Unknown W. Brackets
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a5a2671af3
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irjit: Implement vf2ix.
Used in LittleBigPlanet when playing intro movies.
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2023-07-29 18:01:08 -07:00 |
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Unknown W. Brackets
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df2462b1d9
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irjit: Implement ll/sc.
These occur more than I expected in LittleBigPlanet while loading.
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2023-07-29 17:57:44 -07:00 |
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Unknown W. Brackets
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48586ed0ad
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irjit: Combine Load32Left/Right even on unaligned.
This helps on devices that don't allow unaligned load/store.
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2023-07-29 17:57:25 -07:00 |
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