Unknown W. Brackets
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2e6dbab5fa
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irjit: Add flag to prefer Vec4, use for add/sub.
This will improve things when using SIMD.
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2023-08-13 18:10:40 -07:00 |
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Unknown W. Brackets
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e0be6858b8
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irjit: Implement vcrs.t.
As used in Jeanne d'Arc.
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2023-08-13 18:10:12 -07:00 |
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Unknown W. Brackets
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217a1837ed
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irjit: Allow typical prefixes in vdiv/vasin/etc.
Some of these behave strangely, but there are some common usages that work
fine.
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2023-08-13 18:10:07 -07:00 |
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Henrik Rydgård
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2cdcc413b7
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Merge pull request #17898 from unknownbrackets/irjit-vfputemps
irjit: Cleanup/purge FPU/VFPU temps
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2023-08-13 21:08:00 +02:00 |
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Henrik Rydgård
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d6cdb6e5d9
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Merge pull request #17900 from unknownbrackets/irjit-vsgelt
irjit: Implement vsge/vslt
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2023-08-13 19:59:14 +02:00 |
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Unknown W. Brackets
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23c79f8e7f
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irjit: Implement vsge/vslt.
These are not ideal especially for SIMD, but they do work.
Improves performance in Silent Hill on RISC-V by like 20%.
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2023-08-13 10:40:47 -07:00 |
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Unknown W. Brackets
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5d20f2aabd
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irjit: Simplify VecDo3.
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2023-08-13 10:40:47 -07:00 |
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Unknown W. Brackets
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2b36e0a625
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irjit: ZeroFpCond -> FpCondFromReg.
We already have a zero reg, so this is more useful and symmetrical.
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2023-08-13 10:40:47 -07:00 |
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Unknown W. Brackets
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fa53b80574
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irjit: Cleanup/purge FPU/VFPU temps.
A lot of cases are followed by an FMov that just moved the temp to a
regular register, from VFPU instructions playing safe about overlaps.
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2023-08-13 10:14:10 -07:00 |
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Unknown W. Brackets
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81f67c717c
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riscv: Fix block link for prev blocks.
Oops, was just reversed so never linking.
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2023-08-12 10:48:39 -07:00 |
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Unknown W. Brackets
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fcc90095f7
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riscv: Enable block linking.
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2023-08-12 09:37:02 -07:00 |
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Unknown W. Brackets
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247788806a
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irjit: Add direct helper for start PC.
It's annoying always fetching length too.
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2023-08-12 09:37:02 -07:00 |
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Unknown W. Brackets
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b3cdf06c5a
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riscv: Write fixup on block invalidation.
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2023-08-12 09:37:02 -07:00 |
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Unknown W. Brackets
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3757ebca2d
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irjit: Invalidate/finalize target blocks.
Doesn't actually do anything yet, but adds plumbing.
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2023-08-12 09:37:02 -07:00 |
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Henrik Rydgård
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2342c4522c
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Merge pull request #17875 from unknownbrackets/riscv-jit
RISC-V: Implement a few more ops
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2023-08-09 09:30:15 +02:00 |
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Henrik Rydgård
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bac4e8d42d
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Merge pull request #17874 from unknownbrackets/irjit-exits
IR: Simplify exits to ExitToConst when viable
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2023-08-09 09:11:52 +02:00 |
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Unknown W. Brackets
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28c58c1d24
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irjit: Allow more forms of vmidt.
Mildly worth it.
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2023-08-08 23:17:32 -07:00 |
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Unknown W. Brackets
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ad4cbbab8e
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riscv: Don't cache mipState on backend.
Bad sign if we're trying to use it, anyway.
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2023-08-08 23:17:32 -07:00 |
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Unknown W. Brackets
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31ff23746c
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irjit: Prefer ExitToConst over ExitToReg.
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2023-08-08 23:14:01 -07:00 |
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Unknown W. Brackets
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3f97545f99
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irjit: Reduce exits from constants.
This reduces bloat a bit, and may help with common funcs that enter short
loops.
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2023-08-08 23:05:14 -07:00 |
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Unknown W. Brackets
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5f9a8fd1a1
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irjit: Rename IRRegCache to IRImmRegCache.
For clarity, since it's not a native regcache.
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2023-08-08 23:05:14 -07:00 |
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Unknown W. Brackets
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e73c203984
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irjit: Fix Vec4Shuffle overlap issue.
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2023-08-08 23:00:39 -07:00 |
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Henrik Rydgård
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e9431d0d1e
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Merge pull request #17859 from unknownbrackets/irjit-vec4
irjit: Use Vec4 a bit more
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2023-08-06 23:05:33 +02:00 |
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Unknown W. Brackets
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3dc71cff75
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irjit: Keep a couple more ops in Vec4.
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2023-08-06 13:46:24 -07:00 |
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Unknown W. Brackets
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6a1dbd4cde
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irjit: Allow Vec4 to be used with masks.
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2023-08-06 13:46:24 -07:00 |
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