Unknown W. Brackets
ab809bd19e
jit: Apply hasSetRounding at compile time.
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Otherwise, the block will be executed with the wrong rounding mode the
first time rounding is set. This could be important if it was set for a
single operation.
This is only a problem the first time it's set.
2018-04-01 10:36:16 -07:00
Unknown W. Brackets
09e307b097
arm64jit: Update rounding mode on thread switch.
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Since fcr31 is per-thread, we must update jit state when it changes.
This also fixes the rounding mode on load state and jit/interp switch.
2018-04-01 10:12:32 -07:00
Henrik Rydgård
34f79904fd
IR: This optimization is safe when all three regs are consecutive, so avoid disabling it unnecessarily.
2018-01-10 09:19:27 +01:00
Henrik Rydgård
fb0e81484b
Minor cleanup
2018-01-10 09:19:27 +01:00
Henrik Rydgård
4a32ec3102
Merge pull request #10516 from unknownbrackets/irjit-lwr
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irjit: Optimize out more temps and lwl/lwr operations
2018-01-10 09:11:10 +01:00
Unknown W. Brackets
b6bb0159e3
irjit: Remove Comp_ITypeMemLR.
2018-01-09 18:06:25 -08:00
Unknown W. Brackets
f01e06aefd
irjit: Improve multiple lwr in a row.
2018-01-07 21:06:02 -08:00
Unknown W. Brackets
fbeedd333b
irjit: Swap moves when it may allow clobbering.
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Example:
addiu a0, a1, a2
mov s0, a0
addiu a0, a2, a3
By swapping the mov, we can eliminate it.
Only going one back because it's common and didn't want to track reads.
2018-01-07 21:06:02 -08:00
Unknown W. Brackets
d27e428659
irjit: Convert lwr and friends to easier code.
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This makes it easier to write a (working) jit backend from IR, since these
ops are always annoying to get right.
2018-01-07 21:06:00 -08:00
Unknown W. Brackets
b11f00cead
irjit: Combine lwl/lwr and swl/swr, like before.
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Still want to inline the operation, because the backend shouldn't have to
redo it every time, and we want the temps cleaned up if possible.
2018-01-07 21:05:58 -08:00
Unknown W. Brackets
c6d690e9b8
irjit: Handle Left/Right ops in passes.
2018-01-07 21:05:57 -08:00
Unknown W. Brackets
6dda053365
irjit: Add dedicated ops for lwl/swl and friends.
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Temporarily removes optimizations.
2018-01-07 21:05:57 -08:00
Unknown W. Brackets
cd3f4881a5
irjit: Optimize out temp lhs copies.
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Common example:
li v0, 1
beq s2, v0, somewhere
li v0, 2
Which was copying s2 before. This pattern generally doesn't happen in
MIPS code, though, so really only catches that (very common) case.
2018-01-07 12:11:16 -08:00
Unknown W. Brackets
97674b80bd
irjit: Skip preloading blocks with jump to 0.
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These will be changed before executing anyway.
2018-01-06 17:23:53 -08:00
Unknown W. Brackets
cc8e9a93c3
irjit: For debug, return the best block at addr.
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Invalidation may result in multiple matching blocks, prefer any that is
currently valid.
2018-01-06 17:08:54 -08:00
Unknown W. Brackets
463b2a90c7
irjit: Allow precompiling funcs at start.
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This can take a second, but cuts down on jitc spikes throughout runtime.
Note: bits of the game will still be recompiled as games change code.
This is basically the same operation as loading from cache, without the
cache yet.
2018-01-06 17:06:53 -08:00
Unknown W. Brackets
ccd562d934
irjit: Add a safety check for block num overflow.
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In case a game is very frequently modifying some block.
2018-01-04 23:24:15 -08:00
Unknown W. Brackets
0bfab27b46
irjit: Calculate bloat statistics.
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At least based on IR for now. Can do something else later.
memset() was causing a crash on the std::map.
2018-01-04 23:09:03 -08:00
Henrik Rydgård
2709472abd
Merge pull request #10506 from hrydgard/ir-interpreter-simd
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More IR interpreter SIMD
2018-01-05 01:21:32 +01:00
Henrik Rydgård
8c3a50d089
Merge pull request #10505 from hrydgard/ir-disasm-jit-compare
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Show IR disassembly in JIT Compare screen
2018-01-05 01:20:49 +01:00
Henrik Rydgård
d1d01bfdcb
Cleanup GetBlockNumberFromStartAddress
2018-01-05 01:20:10 +01:00
Henrik Rydgård
331a8f91e8
Fix that weird unordered compare mode, hopefully
2018-01-04 20:06:26 +01:00
Henrik Rydgård
18be23eccc
IR: More fixes. Still something wrong with VFPU compares (not caused by this PR).
2018-01-04 19:38:36 +01:00
Henrik Rydgård
ca9050b84c
On Linux, can't even include nmmintrin without explicitly enabling SSE 4.2 support.
2018-01-04 18:27:19 +01:00
Henrik Rydgård
fe88d12055
IR interpreter: Add some braces to allow variable declaration in the switch cases.
2018-01-04 18:27:19 +01:00
