Commit Graph

398 Commits

Author SHA1 Message Date
Henrik Rydgård
ea6b72d4c9 Merge pull request #8888 from unknownbrackets/warnings
Warning fixes
2016-08-06 10:59:06 +02:00
Unknown W. Brackets
fd546ff21d Fix some type comparison warnings. 2016-08-05 10:47:45 -07:00
Unknown W. Brackets
e55198f7e7 Correct some initialization order warnings.
Also, another missing init with IRBlocks.
2016-08-05 10:46:11 -07:00
Unknown W. Brackets
9972e5b10a Debugger: Allow logging on CPU breakpoints. 2016-08-04 12:39:29 -07:00
Henrik Rydgard
eb72a746b9 Fix one possible (reproducible!) startup crash in IRJit. May help #8848 2016-07-25 00:21:01 +02:00
Henrik Rydgård
c6d4966067 Make really sure we're not using the IRBlock copy constructor other than on Symbian.
Turns out it ended up being used on Mac, and our asserts just debugprint and don't actually assert...
2016-07-09 09:32:41 +02:00
Henrik Rydgard
e0845b876f Fix some bugs in the IRJit. Hopefully helps #8848 2016-07-08 00:05:44 +02:00
Henrik Rydgård
1091fd2dc0 Merge pull request #8840 from unknownbrackets/ir-vfpu
Minor IR cleanup in the VFPU
2016-07-04 10:02:52 +02:00
Unknown W. Brackets
1de4943632 jit-ir: Avoid crash in stack walk.
This can happen if something is data, I suppose, and not a valid block.
2016-07-02 20:51:06 -07:00
Unknown W. Brackets
4578c3cb54 jit-ir: Implement memory breakpoints.
These generally work, but likely delay slots will make downcount slightly
off, and won't resume when you hit run again without manually stepping
through them.
2016-07-02 16:38:30 -07:00
Unknown W. Brackets
7cd666c351 jit-ir: Decrease downcount after delayslot.
Except for likely delay slots.  This makes breakpoints work more
correctly when they trigger within a delay slot.
2016-07-02 16:35:56 -07:00
Unknown W. Brackets
1df08518ae jit-ir: Implement basic icache clear. 2016-07-01 17:27:24 -07:00
Unknown W. Brackets
6fb34d0bee jit-ir: Add initial breakpoint support.
No memory breakpoints yet, and cache isn't cleared yet so these don't work
exactly the way you might expect...
2016-07-01 17:15:57 -07:00
Unknown W. Brackets
8fab3dc91b jit-ir: Allow 3x3 and 2x2 vmmov in IR.
While this will generate a lot of FMovs, it should still be better than
bailing to interp.
2016-07-01 14:08:32 -07:00
Unknown W. Brackets
65394f1dba jit-ir: Fix vbfy with overlap. 2016-07-01 14:08:31 -07:00
Unknown W. Brackets
4761c0aa3f jit-ir: Allow SIMD on vabs/vneg. 2016-07-01 14:08:31 -07:00
Unknown W. Brackets
a450a79f52 jit-ir: Optimize loads to transfers if possible.
These (especially float <-> gpr) happen in all games, but gpr->gpr is
especially common in some minis.  Good to reduce bloat.
2016-05-29 18:34:41 -07:00
Unknown W. Brackets
b09c2b1f75 Add some missing override definitions. 2016-05-21 09:29:03 -07:00
Unknown W. Brackets
ee31f09b67 Buildfix. 2016-05-18 07:12:21 -07:00
Unknown W. Brackets
5534fba72c jit-ir: Add load/store reorder and merge passes.
Can do more in merge, potentially.  Maybe it's not useful...
2016-05-17 21:24:13 -07:00
Unknown W. Brackets
a9cdf7651e jit-ir: Mark prefixes unknown in mtv. 2016-05-17 21:22:57 -07:00
Unknown W. Brackets
b1c7f3dd3f jit-ir: Correct vx2i with partial overlap. 2016-05-17 21:22:23 -07:00
Henrik Rydgard
fff898b526 Log the block when "uneaten prefix" happens 2016-05-16 00:05:03 +02:00
Henrik Rydgard
dc772e6f3a Add missing cases to simplify pass 2016-05-15 23:39:42 +02:00
Henrik Rydgard
f544364c4a Fix bug in vus2i (thanks unknown), recognize vectors in IR disasm 2016-05-15 23:35:33 +02:00