Unknown W. Brackets
cd3f4881a5
irjit: Optimize out temp lhs copies.
...
Common example:
li v0, 1
beq s2, v0, somewhere
li v0, 2
Which was copying s2 before. This pattern generally doesn't happen in
MIPS code, though, so really only catches that (very common) case.
2018-01-07 12:11:16 -08:00
Unknown W. Brackets
cffb2d61a7
irjit: Embed constant inside IRInst.
...
This simplifies a bunch of code and improves compile performance by about
30%, at the cost of a bit more memory.
2018-01-03 23:24:04 -08:00
Unknown W. Brackets
b37ba9e599
irjit: Add options for compile/optimize steps.
...
This way the backend can set flags for the type of IR it wants. It's
seems too complex to combine certain things like lwl/lwr in a pass.
2018-01-01 08:38:12 -08:00
Unknown W. Brackets
671be24105
irjit: Add extra temps to make lwl/swl/etc. easier.
2018-01-01 08:38:11 -08:00
Henrik Rydgard
5d5f10d956
Attempts to counter crashes seen in the Google Play developer console
2016-12-01 22:07:03 +01:00
Unknown W. Brackets
4578c3cb54
jit-ir: Implement memory breakpoints.
...
These generally work, but likely delay slots will make downcount slightly
off, and won't resume when you hit run again without manually stepping
through them.
2016-07-02 16:38:30 -07:00
Unknown W. Brackets
a450a79f52
jit-ir: Optimize loads to transfers if possible.
...
These (especially float <-> gpr) happen in all games, but gpr->gpr is
especially common in some minis. Good to reduce bloat.
2016-05-29 18:34:41 -07:00
Unknown W. Brackets
ee31f09b67
Buildfix.
2016-05-18 07:12:21 -07:00
Unknown W. Brackets
5534fba72c
jit-ir: Add load/store reorder and merge passes.
...
Can do more in merge, potentially. Maybe it's not useful...
2016-05-17 21:24:13 -07:00
Henrik Rydgard
dc772e6f3a
Add missing cases to simplify pass
2016-05-15 23:39:42 +02:00
Henrik Rydgard
f544364c4a
Fix bug in vus2i (thanks unknown), recognize vectors in IR disasm
2016-05-15 23:35:33 +02:00
Unknown W. Brackets
6413b44434
jit-ir: Enable IR for madd(u)/msub(u).
2016-05-14 19:23:51 -07:00
Unknown W. Brackets
4ac773e8b4
jit-ir: Implement bit reverse instruction.
2016-05-14 18:21:42 -07:00
Henrik Rydgard
0541fe36df
Symbian buildfix, fix for fpu test
2016-05-14 15:26:43 +02:00
Henrik Rydgard
91bc3c31a5
Warning fixes
2016-05-14 14:01:27 +02:00
Henrik Rydgard
7a7c3b9b9f
More VFPU, vmmul thoughts
2016-05-14 14:00:01 +02:00
Unknown W. Brackets
efc8a8e353
Hack to make Symbian build.
2016-05-13 23:56:17 -07:00
Henrik Rydgard
b7091a8f5d
Simplifications and fixes
2016-05-13 21:02:23 +02:00
Henrik Rydgard
5b2504120d
Optimize some common prefixes
2016-05-13 20:15:20 +02:00
Henrik Rydgard
91a6cf5e44
Add a couple more passes (2-op, optimize f<->v fp moves)
2016-05-13 20:14:03 +02:00
Henrik Rydgard
f636b2a315
Minor build and other fixes
2016-05-13 19:31:27 +02:00
Unknown W. Brackets
9e3572dc63
jit-ir: Improve vidt to handle more cases.
2016-05-12 22:40:26 -07:00
Unknown W. Brackets
57b3dbff7e
jit-ir: Avoid flushing on a few Vec4 ops.
2016-05-12 21:01:46 -07:00
Unknown W. Brackets
9f183c97ba
jit-ir: Prevent reading ahead for each reg write.
2016-05-12 18:30:55 -07:00
Unknown W. Brackets
d06c6c080c
jit-ir: Expand unused regs to regular GPRs.
2016-05-12 18:30:55 -07:00
