mirror of
https://github.com/izzy2lost/Diddy-Kong-Racing.git
synced 2026-06-19 01:16:26 -07:00
Update libultra asm (#701)
* Update func_8008FF1C to a closer match * Update formatting * single reg diff * Generate end labels for all ucodes, rename the boot to rspboot, and have them all get generated together into the same object file, and standardize how they're defined in the headers. * Use glabel, dlabel, and jlabel for different purposes in asm * Working compile with ido for asm files. * Fix other versions bss declaration * Update exceptasm to show other build versions * Fix NON_MATCHING build ld script * Remove a change to libultra that we don't need anymore. * Get it building with GCC, but it doesn't seem to boot... * Slightly cleaned up the GCC builds by still ignoring warnings in libultra, and adding some extra assembly line breaks and flags.
This commit is contained in:
Ryan Myers
@@ -12,10 +12,14 @@ endif
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COMPILER ?= ido
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$(eval $(call validate-option,NON_MATCHING,ido gcc))
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ifneq ($(COMPILER),ido)
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NON_MATCHING := 1
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endif
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# Define a custom boot file if desired to use something other than the vanilla one
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BOOT_CUSTOM ?= mods/boot_custom.bin
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LIBULTRA_VERSION_DEFINE := -DBUILD_VERSION=4 -DBUILD_VERSION_STRING=\"2.0G\"
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LIBULTRA_VERSION_DEFINE := -DBUILD_VERSION=VERSION_G -DBUILD_VERSION_STRING=\"2.0G\"
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# Whether to hide commands or not
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VERBOSE ?= 0
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@@ -121,6 +125,7 @@ endif
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AS = $(CROSS)as
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LD = $(CROSS)ld
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OBJCOPY = $(CROSS)objcopy
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STRIP = $(CROSS)strip
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VENV = .venv
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PYTHON = $(VENV)/bin/python3
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GCC = gcc
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@@ -264,15 +269,21 @@ $(BUILD_DIR)/$(LIBULTRA_DIR)/src/sc/sched.c.o: MIPSISET := -mips1
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$(BUILD_DIR)/$(LIBULTRA_DIR)/src/io/motor.c.o: MIPSISET := -mips1
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$(BUILD_DIR)/$(LIBULTRA_DIR)/src/audio/env.c.o: MIPSISET := -mips1
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#Ignore warnings for libultra files
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$(BUILD_DIR)/$(LIBULTRA_DIR)/%.c.o: CC_WARNINGS := -w
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$(BUILD_DIR)/$(LIBULTRA_DIR)/%.c.o: CC_CHECK := :
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# ASM files more often than not need to be compiled with -mips2 -O1, but there are exceptions.
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$(BUILD_DIR)/$(LIBULTRA_DIR)/%.s.o: OPT_FLAGS := -O1
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$(BUILD_DIR)/$(LIBULTRA_DIR)/%.s.o: MIPSISET := -mips2
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$(BUILD_DIR)/$(LIBULTRA_DIR)/src/libc/%.s.o: OPT_FLAGS := -O2
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$(BUILD_DIR)/$(LIBULTRA_DIR)/src/os/exceptasm.s.o: MIPSISET := -mips3 -32
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# Allow dollar sign to be used in var names for this file alone
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# It allows us to return the current stack pointer
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$(BUILD_DIR)/$(SRC_DIR)/get_stack_pointer.c.o: OPT_FLAGS += -dollar
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endif
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#Ignore warnings for libultra files
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$(BUILD_DIR)/$(LIBULTRA_DIR)/%.c.o: CC_WARNINGS := -w
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$(BUILD_DIR)/$(LIBULTRA_DIR)/%.c.o: CC_CHECK := :
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### Targets
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ifeq ($(COMPILER),gcc)
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@@ -444,6 +455,26 @@ $(BUILD_DIR)/%.s.o: %.s | build_assets
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$(call print,Assembling:,$<,$@)
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$(V)$(AS) $(ASFLAGS) -MD $(BUILD_DIR)/$*.d -o $@ $<
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ifeq ($(COMPILER),ido)
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# libultra asm files - Compile with the ido compiler
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$(BUILD_DIR)/$(LIBULTRA_DIR)/%.s.o: $(LIBULTRA_DIR)/%.s | build_assets
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$(call print,Assembling Libultra:,$<,$@)
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$(V)$(CC) -c $(CFLAGS) $(CC_WARNINGS) $(OPT_FLAGS) $(MIPSISET) -o $@ $<
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$(V)$(STRIP) --strip-unneeded $@
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@if [ "$(MIPSISET)" = "-mips3 -32" ]; then \
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$(PYTHON) $(TOOLS_DIR)/python/patchmips3.py $@ || rm $@; \
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fi
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else
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# libultra asm files - Compile with the gcc c compiler
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$(BUILD_DIR)/$(LIBULTRA_DIR)/%.s.o: $(LIBULTRA_DIR)/%.s | build_assets
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$(call print,Assembling Libultra:,$<,$@)
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$(V)$(CROSS)gcc -x assembler-with-cpp \
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-w -nostdinc -c -G 0 -march=vr4300 -mgp32 -mfp32 -mno-abicalls \
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-DMIPSEB -D_LANGUAGE_ASSEMBLY -D_MIPS_SIM=1 -D_ULTRA64 -DMODERN_CC -D__USE_ISOC99 \
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-mips3 -Os -ggdb3 -ffast-math -fno-unsafe-math-optimizations -c $(C_DEFINES) $(INCLUDE_CFLAGS) \
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-o $@ $<
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endif
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# Specifically override the header file from what splat extracted to be replaced by what we have in the hasm folder
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$(BUILD_DIR)/asm/header.s.o: src/hasm/header.s | build_assets
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$(call print,Assembling Header:,$<,$@)
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@@ -30,7 +30,7 @@ extern "C" {
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#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
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#include "os_internal_reg.h"
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// #include "os_internal_exception.h" //TODO: Why does this include break things?
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#include "os_internal_exception.h"
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#include "os_internal_tlb.h"
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#include "os_internal_si.h"
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#include "os_internal_rsp.h"
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@@ -7,6 +7,18 @@
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.set K2BASE, 0xC0000000
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.macro glabel label
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.global \label
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.type \label, @function
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\label:
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.endm
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.macro dlabel label
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.global \label
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.type \label, @object
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\label:
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.endm
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.macro jlabel label
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.global \label
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\label:
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.endm
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@@ -26,6 +38,7 @@
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.macro leaf label
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.global \label
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.type \label, @function
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\label:
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.ent \label
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.endm
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@@ -33,6 +46,7 @@
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# Used for alternative entries for Sin functions
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.macro altleaf label
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.global \label
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.type \label, @function
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\label:
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.aent \label
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.endm
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@@ -0,0 +1,96 @@
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#include "PR/os_internal.h"
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#include "PR/rcp.h"
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#include "PR/rdb.h"
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// not included in final rom, but __osThreadSave is here for some reason
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OSThread __osThreadSave;
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extern OSThread *__osRunningThread;
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extern u32 __osRdb_IP6_Empty;
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#ifndef _FINALROM
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static u8 buffer[12];
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static u32 numChars = 0;
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static u32 string_to_u32(u8* s) {
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u32 k;
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k = ((s[0] & 0xFF) << 0x18);
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k |= ((s[1] & 0xFF) << 0x10);
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k |= ((s[2] & 0xFF) << 0x8);
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k |= (s[3] & 0xFF);
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return k;
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}
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static void send_packet(u8* s, u32 n) {
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rdbPacket packet;
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u32 i;
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packet.type = 0xC;
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packet.length = n;
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for (i = 0; i < n; i++) {
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packet.buf[i] = s[i];
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}
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*(vu32*)RDB_BASE_REG = *(u32*)&packet;
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}
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static void clear_IP6(void) {
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while (!(__osGetCause() & CAUSE_IP6)) {
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;
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}
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*(vu32*)RDB_READ_INTR_REG = 0;
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while (__osGetCause() & CAUSE_IP6) {
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;
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}
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}
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static void send(u8* s, u32 n) {
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u32 ct;
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u32 i = 0;
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u32 getLastIP6;
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if (!__osRdb_IP6_Empty) {
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clear_IP6();
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getLastIP6 = FALSE;
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} else {
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getLastIP6 = TRUE;
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}
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while (n != 0) {
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ct = (n < 3) ? n : 3;
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send_packet(s + i, ct);
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n -= ct;
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i += ct;
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if (n != 0) {
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clear_IP6();
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}
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}
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if (getLastIP6) {
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clear_IP6();
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}
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}
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void kdebugserver(rdbPacket packet) {
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u32 i;
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u32 length;
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u8* addr;
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for (i = 0; i < 3; i++) {
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buffer[numChars++] = packet.buf[i];
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}
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if (buffer[0] == 2) {
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send((char*)&__osRunningThread->context, sizeof(__OSThreadContext));
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numChars = 0;
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} else if (numChars >= 9 && buffer[0] == 1) {
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addr = string_to_u32(&buffer[1]);
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length = string_to_u32(&buffer[5]);
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send(addr, length);
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numChars = 0;
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}
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}
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#endif
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+22
-10
@@ -1,13 +1,25 @@
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.include "macro.inc"
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/**************************************************************************
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* *
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* Copyright (C) 1994, Silicon Graphics, Inc. *
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* *
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* These coded instructions, statements, and computer programs contain *
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* unpublished proprietary information of Silicon Graphics, Inc., and *
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* are protected by Federal copyright law. They may not be disclosed *
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* to third parties or copied or duplicated in any form, in whole or *
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* in part, without the prior written consent of Silicon Graphics, Inc. *
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* *
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**************************************************************************/
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/* assembler directives */
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.set noat /* allow manual use of $at */
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.set noreorder /* don't insert nops after branches */
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.set gp=64 /* allow use of 64-bit general purpose registers */
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/*
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* Due to compiler bug, it won't insert a sqrt.s opcode in the stream so we
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* make a function and call it for now. When compiler fixed, also remove the
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* seperate Makefile rules
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*/
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.section .text, "ax"
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#include "sys/asm.h"
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#include "sys/regdef.h"
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leaf sqrtf
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jr $ra
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sqrt.s $f0, $f12
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.end sqrtf
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LEAF(sqrtf)
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sqrt.s fv0, fa0
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j ra
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END(sqrtf)
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+92
-91
@@ -1,95 +1,96 @@
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.include "macro.inc"
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#include "PR/R4300.h"
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#include "sys/asm.h"
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#include "sys/regdef.h"
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/* assembler directives */
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.set noat /* allow manual use of $at */
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.set noreorder /* don't insert nops after branches */
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.set gp=64 /* allow use of 64-bit general purpose registers */
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.text
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#ifdef __sgi
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WEAK(bcmp, _bcmp)
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#else
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#define _bcmp bcmp
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#endif
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LEAF(_bcmp)
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xor v0, a0, a1
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blt a2, 16, bytecmp
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.section .text, "ax"
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andi v0, v0, 0x3
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negu t8, a0
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bnez v0, unalgncmp
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/* Generated by spimdisasm 1.30.0 */
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andi t8, t8, 0x3
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subu a2, a2, t8
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beqz t8, wordcmp
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move v0, v1
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lwl v0, 0(a0)
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lwl v1, 0(a1)
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addu a0, a0, t8
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addu a1, a1, t8
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bne v0, v1, cmpne
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leaf bcmp
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/* CEC50 800CE050 28C10010 */ slti $at, $a2, 0x10
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/* CEC54 800CE054 14200037 */ bnez $at, .L800CE134
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/* CEC58 800CE058 00851026 */ xor $v0, $a0, $a1
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/* CEC5C 800CE05C 30420003 */ andi $v0, $v0, 0x3
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/* CEC60 800CE060 14400019 */ bnez $v0, .L800CE0C8
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/* CEC64 800CE064 0004C023 */ negu $t8, $a0
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/* CEC68 800CE068 33180003 */ andi $t8, $t8, 0x3
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/* CEC6C 800CE06C 13000007 */ beqz $t8, .L800CE08C
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/* CEC70 800CE070 00D83023 */ subu $a2, $a2, $t8
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/* CEC74 800CE074 00601025 */ or $v0, $v1, $zero
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/* CEC78 800CE078 88820000 */ lwl $v0, 0x0($a0)
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/* CEC7C 800CE07C 88A30000 */ lwl $v1, 0x0($a1)
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/* CEC80 800CE080 00982021 */ addu $a0, $a0, $t8
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/* CEC84 800CE084 00B82821 */ addu $a1, $a1, $t8
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/* CEC88 800CE088 14430036 */ bne $v0, $v1, .L800CE164
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.L800CE08C:
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/* CEC8C 800CE08C 2401FFFC */ addiu $at, $zero, -0x4
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/* CEC90 800CE090 00C13824 */ and $a3, $a2, $at
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/* CEC94 800CE094 10E00027 */ beqz $a3, .L800CE134
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/* CEC98 800CE098 00C73023 */ subu $a2, $a2, $a3
|
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/* CEC9C 800CE09C 00E43821 */ addu $a3, $a3, $a0
|
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/* CECA0 800CE0A0 8C820000 */ lw $v0, 0x0($a0)
|
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.L800CE0A4:
|
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/* CECA4 800CE0A4 8CA30000 */ lw $v1, 0x0($a1)
|
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/* CECA8 800CE0A8 24840004 */ addiu $a0, $a0, 0x4
|
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/* CECAC 800CE0AC 24A50004 */ addiu $a1, $a1, 0x4
|
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/* CECB0 800CE0B0 1443002C */ bne $v0, $v1, .L800CE164
|
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/* CECB4 800CE0B4 00000000 */ nop
|
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/* CECB8 800CE0B8 5487FFFA */ bnel $a0, $a3, .L800CE0A4
|
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/* CECBC 800CE0BC 8C820000 */ lw $v0, 0x0($a0)
|
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/* CECC0 800CE0C0 1000001C */ b .L800CE134
|
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/* CECC4 800CE0C4 00000000 */ nop
|
||||
.L800CE0C8:
|
||||
/* CECC8 800CE0C8 00053823 */ negu $a3, $a1
|
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/* CECCC 800CE0CC 30E70003 */ andi $a3, $a3, 0x3
|
||||
/* CECD0 800CE0D0 10E0000A */ beqz $a3, .L800CE0FC
|
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/* CECD4 800CE0D4 00C73023 */ subu $a2, $a2, $a3
|
||||
/* CECD8 800CE0D8 00E43821 */ addu $a3, $a3, $a0
|
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/* CECDC 800CE0DC 90820000 */ lbu $v0, 0x0($a0)
|
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.L800CE0E0:
|
||||
/* CECE0 800CE0E0 90A30000 */ lbu $v1, 0x0($a1)
|
||||
/* CECE4 800CE0E4 24840001 */ addiu $a0, $a0, 0x1
|
||||
/* CECE8 800CE0E8 24A50001 */ addiu $a1, $a1, 0x1
|
||||
/* CECEC 800CE0EC 1443001D */ bne $v0, $v1, .L800CE164
|
||||
/* CECF0 800CE0F0 00000000 */ nop
|
||||
/* CECF4 800CE0F4 5487FFFA */ bnel $a0, $a3, .L800CE0E0
|
||||
/* CECF8 800CE0F8 90820000 */ lbu $v0, 0x0($a0)
|
||||
.L800CE0FC:
|
||||
/* CECFC 800CE0FC 2401FFFC */ addiu $at, $zero, -0x4
|
||||
/* CED00 800CE100 00C13824 */ and $a3, $a2, $at
|
||||
/* CED04 800CE104 10E0000B */ beqz $a3, .L800CE134
|
||||
/* CED08 800CE108 00C73023 */ subu $a2, $a2, $a3
|
||||
/* CED0C 800CE10C 00E43821 */ addu $a3, $a3, $a0
|
||||
/* CED10 800CE110 88820000 */ lwl $v0, 0x0($a0)
|
||||
.L800CE114:
|
||||
/* CED14 800CE114 8CA30000 */ lw $v1, 0x0($a1)
|
||||
/* CED18 800CE118 98820003 */ lwr $v0, 0x3($a0)
|
||||
/* CED1C 800CE11C 24840004 */ addiu $a0, $a0, 0x4
|
||||
/* CED20 800CE120 24A50004 */ addiu $a1, $a1, 0x4
|
||||
/* CED24 800CE124 1443000F */ bne $v0, $v1, .L800CE164
|
||||
/* CED28 800CE128 00000000 */ nop
|
||||
/* CED2C 800CE12C 5487FFF9 */ bnel $a0, $a3, .L800CE114
|
||||
/* CED30 800CE130 88820000 */ lwl $v0, 0x0($a0)
|
||||
.L800CE134:
|
||||
/* CED34 800CE134 18C00009 */ blez $a2, .L800CE15C
|
||||
/* CED38 800CE138 00C43821 */ addu $a3, $a2, $a0
|
||||
/* CED3C 800CE13C 90820000 */ lbu $v0, 0x0($a0)
|
||||
.L800CE140:
|
||||
/* CED40 800CE140 90A30000 */ lbu $v1, 0x0($a1)
|
||||
/* CED44 800CE144 24840001 */ addiu $a0, $a0, 0x1
|
||||
/* CED48 800CE148 24A50001 */ addiu $a1, $a1, 0x1
|
||||
/* CED4C 800CE14C 14430005 */ bne $v0, $v1, .L800CE164
|
||||
/* CED50 800CE150 00000000 */ nop
|
||||
/* CED54 800CE154 5487FFFA */ bnel $a0, $a3, .L800CE140
|
||||
/* CED58 800CE158 90820000 */ lbu $v0, 0x0($a0)
|
||||
.L800CE15C:
|
||||
/* CED5C 800CE15C 03E00008 */ jr $ra
|
||||
/* CED60 800CE160 00001025 */ or $v0, $zero, $zero
|
||||
.L800CE164:
|
||||
/* CED64 800CE164 03E00008 */ jr $ra
|
||||
/* CED68 800CE168 24020001 */ addiu $v0, $zero, 0x1
|
||||
/* CED6C 800CE16C 00000000 */ nop
|
||||
.end bcmp
|
||||
wordcmp:
|
||||
and a3, a2, ~3
|
||||
subu a2, a2, a3
|
||||
beqz a3, bytecmp
|
||||
|
||||
addu a3, a3, a0
|
||||
1:
|
||||
lw v0, 0(a0)
|
||||
lw v1, 0(a1)
|
||||
addiu a0, a0, 4
|
||||
addiu a1, a1, 4
|
||||
bne v0, v1, cmpne
|
||||
bne a0, a3, 1b
|
||||
|
||||
b bytecmp
|
||||
unalgncmp:
|
||||
negu a3, a1
|
||||
andi a3, a3, 0x3
|
||||
subu a2, a2, a3
|
||||
beqz a3, partaligncmp
|
||||
|
||||
addu a3, a3, a0
|
||||
|
||||
1:
|
||||
lbu v0, 0(a0)
|
||||
lbu v1, 0(a1)
|
||||
addiu a0, a0, 1
|
||||
addiu a1, a1, 1
|
||||
bne v0, v1, cmpne
|
||||
bne a0, a3, 1b
|
||||
|
||||
partaligncmp:
|
||||
and a3, a2, ~3
|
||||
subu a2, a2, a3
|
||||
beqz a3, bytecmp
|
||||
|
||||
addu a3, a3, a0
|
||||
|
||||
1:
|
||||
lwl v0, 0(a0)
|
||||
lwr v0, 3(a0)
|
||||
lw v1, 0(a1)
|
||||
addiu a0, a0, 4
|
||||
addiu a1, a1, 4
|
||||
bne v0, v1, cmpne
|
||||
bne a0, a3, 1b
|
||||
|
||||
bytecmp:
|
||||
addu a3, a2, a0
|
||||
blez a2, cmpdone
|
||||
|
||||
1:
|
||||
lbu v0, 0(a0)
|
||||
lbu v1, 0(a1)
|
||||
addiu a0, a0, 1
|
||||
addiu a1, a1, 1
|
||||
bne v0, v1, cmpne
|
||||
bne a0, a3, 1b
|
||||
|
||||
cmpdone:
|
||||
move v0, zero
|
||||
jr ra
|
||||
cmpne:
|
||||
li v0, 1
|
||||
jr ra
|
||||
|
||||
.end _bcmp
|
||||
|
||||
+216
-226
@@ -1,230 +1,220 @@
|
||||
.include "macro.inc"
|
||||
#include "PR/R4300.h"
|
||||
#include "sys/asm.h"
|
||||
#include "sys/regdef.h"
|
||||
|
||||
/* assembler directives */
|
||||
.set noat /* allow manual use of $at */
|
||||
.set noreorder /* don't insert nops after branches */
|
||||
.set gp=64 /* allow use of 64-bit general purpose registers */
|
||||
.text
|
||||
#ifdef __sgi
|
||||
WEAK(bcopy, _bcopy)
|
||||
#else
|
||||
#define _bcopy bcopy
|
||||
#endif
|
||||
LEAF(_bcopy)
|
||||
move a3, a1
|
||||
beqz a2, ret
|
||||
beq a0, a1, ret
|
||||
blt a1, a0, goforwards
|
||||
|
||||
add v0, a0, a2
|
||||
bge a1, v0, goforwards
|
||||
b gobackwards
|
||||
|
||||
.section .text, "ax"
|
||||
goforwards:
|
||||
|
||||
/* Generated by spimdisasm 1.30.0 */
|
||||
blt a2, 16, forwards_bytecopy
|
||||
|
||||
andi v0, a0, 0x3
|
||||
andi v1, a1, 0x3
|
||||
beq v0, v1, forwalignable
|
||||
|
||||
|
||||
/* Handwritten function */
|
||||
leaf bcopy
|
||||
/* CA9A0 800C9DA0 10C0001A */ beqz $a2, .L800C9E0C
|
||||
/* CA9A4 800C9DA4 00A03825 */ or $a3, $a1, $zero
|
||||
/* CA9A8 800C9DA8 10850018 */ beq $a0, $a1, .L800C9E0C
|
||||
/* CA9AC 800C9DAC 00A4082A */ slt $at, $a1, $a0
|
||||
/* CA9B0 800C9DB0 54200008 */ bnel $at, $zero, .L800C9DD4
|
||||
/* CA9B4 800C9DB4 28C10010 */ slti $at, $a2, 0x10
|
||||
/* CA9B8 800C9DB8 00861020 */ add $v0, $a0, $a2 /* handwritten instruction */
|
||||
/* CA9BC 800C9DBC 00A2082A */ slt $at, $a1, $v0
|
||||
/* CA9C0 800C9DC0 50200004 */ beql $at, $zero, .L800C9DD4
|
||||
/* CA9C4 800C9DC4 28C10010 */ slti $at, $a2, 0x10
|
||||
/* CA9C8 800C9DC8 1000005B */ b .L800C9F38
|
||||
/* CA9CC 800C9DCC 28C10010 */ slti $at, $a2, 0x10
|
||||
/* CA9D0 800C9DD0 28C10010 */ slti $at, $a2, 0x10
|
||||
.L800C9DD4:
|
||||
/* CA9D4 800C9DD4 14200005 */ bnez $at, .L800C9DEC
|
||||
/* CA9D8 800C9DD8 00000000 */ nop
|
||||
/* CA9DC 800C9DDC 30820003 */ andi $v0, $a0, 0x3
|
||||
/* CA9E0 800C9DE0 30A30003 */ andi $v1, $a1, 0x3
|
||||
/* CA9E4 800C9DE4 1043000B */ beq $v0, $v1, .L800C9E14
|
||||
/* CA9E8 800C9DE8 00000000 */ nop
|
||||
.L800C9DEC:
|
||||
/* CA9EC 800C9DEC 10C00007 */ beqz $a2, .L800C9E0C
|
||||
/* CA9F0 800C9DF0 00000000 */ nop
|
||||
/* CA9F4 800C9DF4 00861821 */ addu $v1, $a0, $a2
|
||||
.L800C9DF8:
|
||||
/* CA9F8 800C9DF8 80820000 */ lb $v0, 0x0($a0)
|
||||
/* CA9FC 800C9DFC 24840001 */ addiu $a0, $a0, 0x1
|
||||
/* CAA00 800C9E00 24A50001 */ addiu $a1, $a1, 0x1
|
||||
/* CAA04 800C9E04 1483FFFC */ bne $a0, $v1, .L800C9DF8
|
||||
/* CAA08 800C9E08 A0A2FFFF */ sb $v0, -0x1($a1)
|
||||
.L800C9E0C:
|
||||
/* CAA0C 800C9E0C 03E00008 */ jr $ra
|
||||
/* CAA10 800C9E10 00E01025 */ or $v0, $a3, $zero
|
||||
.L800C9E14:
|
||||
/* CAA14 800C9E14 10400018 */ beqz $v0, .L800C9E78
|
||||
/* CAA18 800C9E18 24010001 */ addiu $at, $zero, 0x1
|
||||
/* CAA1C 800C9E1C 1041000F */ beq $v0, $at, .L800C9E5C
|
||||
/* CAA20 800C9E20 24010002 */ addiu $at, $zero, 0x2
|
||||
/* CAA24 800C9E24 50410008 */ beql $v0, $at, .L800C9E48
|
||||
/* CAA28 800C9E28 84820000 */ lh $v0, 0x0($a0)
|
||||
/* CAA2C 800C9E2C 80820000 */ lb $v0, 0x0($a0)
|
||||
/* CAA30 800C9E30 24840001 */ addiu $a0, $a0, 0x1
|
||||
/* CAA34 800C9E34 24A50001 */ addiu $a1, $a1, 0x1
|
||||
/* CAA38 800C9E38 24C6FFFF */ addiu $a2, $a2, -0x1
|
||||
/* CAA3C 800C9E3C 1000000E */ b .L800C9E78
|
||||
/* CAA40 800C9E40 A0A2FFFF */ sb $v0, -0x1($a1)
|
||||
/* CAA44 800C9E44 84820000 */ lh $v0, 0x0($a0)
|
||||
.L800C9E48:
|
||||
/* CAA48 800C9E48 24840002 */ addiu $a0, $a0, 0x2
|
||||
/* CAA4C 800C9E4C 24A50002 */ addiu $a1, $a1, 0x2
|
||||
/* CAA50 800C9E50 24C6FFFE */ addiu $a2, $a2, -0x2
|
||||
/* CAA54 800C9E54 10000008 */ b .L800C9E78
|
||||
/* CAA58 800C9E58 A4A2FFFE */ sh $v0, -0x2($a1)
|
||||
.L800C9E5C:
|
||||
/* CAA5C 800C9E5C 80820000 */ lb $v0, 0x0($a0)
|
||||
/* CAA60 800C9E60 84830001 */ lh $v1, 0x1($a0)
|
||||
/* CAA64 800C9E64 24840003 */ addiu $a0, $a0, 0x3
|
||||
/* CAA68 800C9E68 24A50003 */ addiu $a1, $a1, 0x3
|
||||
/* CAA6C 800C9E6C 24C6FFFD */ addiu $a2, $a2, -0x3
|
||||
/* CAA70 800C9E70 A0A2FFFD */ sb $v0, -0x3($a1)
|
||||
/* CAA74 800C9E74 A4A3FFFE */ sh $v1, -0x2($a1)
|
||||
.L800C9E78:
|
||||
/* CAA78 800C9E78 28C10020 */ slti $at, $a2, 0x20
|
||||
/* CAA7C 800C9E7C 54200016 */ bnel $at, $zero, .L800C9ED8
|
||||
/* CAA80 800C9E80 28C10010 */ slti $at, $a2, 0x10
|
||||
/* CAA84 800C9E84 8C820000 */ lw $v0, 0x0($a0)
|
||||
/* CAA88 800C9E88 8C830004 */ lw $v1, 0x4($a0)
|
||||
/* CAA8C 800C9E8C 8C880008 */ lw $t0, 0x8($a0)
|
||||
/* CAA90 800C9E90 8C89000C */ lw $t1, 0xC($a0)
|
||||
/* CAA94 800C9E94 8C8A0010 */ lw $t2, 0x10($a0)
|
||||
/* CAA98 800C9E98 8C8B0014 */ lw $t3, 0x14($a0)
|
||||
/* CAA9C 800C9E9C 8C8C0018 */ lw $t4, 0x18($a0)
|
||||
/* CAAA0 800C9EA0 8C8D001C */ lw $t5, 0x1C($a0)
|
||||
/* CAAA4 800C9EA4 24840020 */ addiu $a0, $a0, 0x20
|
||||
/* CAAA8 800C9EA8 24A50020 */ addiu $a1, $a1, 0x20
|
||||
/* CAAAC 800C9EAC 24C6FFE0 */ addiu $a2, $a2, -0x20
|
||||
/* CAAB0 800C9EB0 ACA2FFE0 */ sw $v0, -0x20($a1)
|
||||
/* CAAB4 800C9EB4 ACA3FFE4 */ sw $v1, -0x1C($a1)
|
||||
/* CAAB8 800C9EB8 ACA8FFE8 */ sw $t0, -0x18($a1)
|
||||
/* CAABC 800C9EBC ACA9FFEC */ sw $t1, -0x14($a1)
|
||||
/* CAAC0 800C9EC0 ACAAFFF0 */ sw $t2, -0x10($a1)
|
||||
/* CAAC4 800C9EC4 ACABFFF4 */ sw $t3, -0xC($a1)
|
||||
/* CAAC8 800C9EC8 ACACFFF8 */ sw $t4, -0x8($a1)
|
||||
/* CAACC 800C9ECC 1000FFEA */ b .L800C9E78
|
||||
/* CAAD0 800C9ED0 ACADFFFC */ sw $t5, -0x4($a1)
|
||||
.L800C9ED4:
|
||||
/* CAAD4 800C9ED4 28C10010 */ slti $at, $a2, 0x10
|
||||
.L800C9ED8:
|
||||
/* CAAD8 800C9ED8 5420000E */ bnel $at, $zero, .L800C9F14
|
||||
/* CAADC 800C9EDC 28C10004 */ slti $at, $a2, 0x4
|
||||
/* CAAE0 800C9EE0 8C820000 */ lw $v0, 0x0($a0)
|
||||
/* CAAE4 800C9EE4 8C830004 */ lw $v1, 0x4($a0)
|
||||
/* CAAE8 800C9EE8 8C880008 */ lw $t0, 0x8($a0)
|
||||
/* CAAEC 800C9EEC 8C89000C */ lw $t1, 0xC($a0)
|
||||
/* CAAF0 800C9EF0 24840010 */ addiu $a0, $a0, 0x10
|
||||
/* CAAF4 800C9EF4 24A50010 */ addiu $a1, $a1, 0x10
|
||||
/* CAAF8 800C9EF8 24C6FFF0 */ addiu $a2, $a2, -0x10
|
||||
/* CAAFC 800C9EFC ACA2FFF0 */ sw $v0, -0x10($a1)
|
||||
/* CAB00 800C9F00 ACA3FFF4 */ sw $v1, -0xC($a1)
|
||||
/* CAB04 800C9F04 ACA8FFF8 */ sw $t0, -0x8($a1)
|
||||
/* CAB08 800C9F08 1000FFF2 */ b .L800C9ED4
|
||||
/* CAB0C 800C9F0C ACA9FFFC */ sw $t1, -0x4($a1)
|
||||
.L800C9F10:
|
||||
/* CAB10 800C9F10 28C10004 */ slti $at, $a2, 0x4
|
||||
.L800C9F14:
|
||||
/* CAB14 800C9F14 1420FFB5 */ bnez $at, .L800C9DEC
|
||||
/* CAB18 800C9F18 00000000 */ nop
|
||||
/* CAB1C 800C9F1C 8C820000 */ lw $v0, 0x0($a0)
|
||||
/* CAB20 800C9F20 24840004 */ addiu $a0, $a0, 0x4
|
||||
/* CAB24 800C9F24 24A50004 */ addiu $a1, $a1, 0x4
|
||||
/* CAB28 800C9F28 24C6FFFC */ addiu $a2, $a2, -0x4
|
||||
/* CAB2C 800C9F2C 1000FFF8 */ b .L800C9F10
|
||||
/* CAB30 800C9F30 ACA2FFFC */ sw $v0, -0x4($a1)
|
||||
/* CAB34 800C9F34 28C10010 */ slti $at, $a2, 0x10
|
||||
.L800C9F38:
|
||||
/* CAB38 800C9F38 00862020 */ add $a0, $a0, $a2 /* handwritten instruction */
|
||||
/* CAB3C 800C9F3C 14200005 */ bnez $at, .L800C9F54
|
||||
/* CAB40 800C9F40 00A62820 */ add $a1, $a1, $a2 /* handwritten instruction */
|
||||
/* CAB44 800C9F44 30820003 */ andi $v0, $a0, 0x3
|
||||
/* CAB48 800C9F48 30A30003 */ andi $v1, $a1, 0x3
|
||||
/* CAB4C 800C9F4C 1043000D */ beq $v0, $v1, .L800C9F84
|
||||
/* CAB50 800C9F50 00000000 */ nop
|
||||
.L800C9F54:
|
||||
/* CAB54 800C9F54 10C0FFAD */ beqz $a2, .L800C9E0C
|
||||
/* CAB58 800C9F58 00000000 */ nop
|
||||
/* CAB5C 800C9F5C 2484FFFF */ addiu $a0, $a0, -0x1
|
||||
/* CAB60 800C9F60 24A5FFFF */ addiu $a1, $a1, -0x1
|
||||
/* CAB64 800C9F64 00861823 */ subu $v1, $a0, $a2
|
||||
.L800C9F68:
|
||||
/* CAB68 800C9F68 80820000 */ lb $v0, 0x0($a0)
|
||||
/* CAB6C 800C9F6C 2484FFFF */ addiu $a0, $a0, -0x1
|
||||
/* CAB70 800C9F70 24A5FFFF */ addiu $a1, $a1, -0x1
|
||||
/* CAB74 800C9F74 1483FFFC */ bne $a0, $v1, .L800C9F68
|
||||
/* CAB78 800C9F78 A0A20001 */ sb $v0, 0x1($a1)
|
||||
/* CAB7C 800C9F7C 03E00008 */ jr $ra
|
||||
/* CAB80 800C9F80 00E01025 */ or $v0, $a3, $zero
|
||||
.L800C9F84:
|
||||
/* CAB84 800C9F84 10400018 */ beqz $v0, .L800C9FE8
|
||||
/* CAB88 800C9F88 24010003 */ addiu $at, $zero, 0x3
|
||||
/* CAB8C 800C9F8C 1041000F */ beq $v0, $at, .L800C9FCC
|
||||
/* CAB90 800C9F90 24010002 */ addiu $at, $zero, 0x2
|
||||
/* CAB94 800C9F94 50410008 */ beql $v0, $at, .L800C9FB8
|
||||
/* CAB98 800C9F98 8482FFFE */ lh $v0, -0x2($a0)
|
||||
/* CAB9C 800C9F9C 8082FFFF */ lb $v0, -0x1($a0)
|
||||
/* CABA0 800C9FA0 2484FFFF */ addiu $a0, $a0, -0x1
|
||||
/* CABA4 800C9FA4 24A5FFFF */ addiu $a1, $a1, -0x1
|
||||
/* CABA8 800C9FA8 24C6FFFF */ addiu $a2, $a2, -0x1
|
||||
/* CABAC 800C9FAC 1000000E */ b .L800C9FE8
|
||||
/* CABB0 800C9FB0 A0A20000 */ sb $v0, 0x0($a1)
|
||||
/* CABB4 800C9FB4 8482FFFE */ lh $v0, -0x2($a0)
|
||||
.L800C9FB8:
|
||||
/* CABB8 800C9FB8 2484FFFE */ addiu $a0, $a0, -0x2
|
||||
/* CABBC 800C9FBC 24A5FFFE */ addiu $a1, $a1, -0x2
|
||||
/* CABC0 800C9FC0 24C6FFFE */ addiu $a2, $a2, -0x2
|
||||
/* CABC4 800C9FC4 10000008 */ b .L800C9FE8
|
||||
/* CABC8 800C9FC8 A4A20000 */ sh $v0, 0x0($a1)
|
||||
.L800C9FCC:
|
||||
/* CABCC 800C9FCC 8082FFFF */ lb $v0, -0x1($a0)
|
||||
/* CABD0 800C9FD0 8483FFFD */ lh $v1, -0x3($a0)
|
||||
/* CABD4 800C9FD4 2484FFFD */ addiu $a0, $a0, -0x3
|
||||
/* CABD8 800C9FD8 24A5FFFD */ addiu $a1, $a1, -0x3
|
||||
/* CABDC 800C9FDC 24C6FFFD */ addiu $a2, $a2, -0x3
|
||||
/* CABE0 800C9FE0 A0A20002 */ sb $v0, 0x2($a1)
|
||||
/* CABE4 800C9FE4 A4A30000 */ sh $v1, 0x0($a1)
|
||||
.L800C9FE8:
|
||||
/* CABE8 800C9FE8 28C10020 */ slti $at, $a2, 0x20
|
||||
/* CABEC 800C9FEC 54200016 */ bnel $at, $zero, .L800CA048
|
||||
/* CABF0 800C9FF0 28C10010 */ slti $at, $a2, 0x10
|
||||
/* CABF4 800C9FF4 8C82FFFC */ lw $v0, -0x4($a0)
|
||||
/* CABF8 800C9FF8 8C83FFF8 */ lw $v1, -0x8($a0)
|
||||
/* CABFC 800C9FFC 8C88FFF4 */ lw $t0, -0xC($a0)
|
||||
/* CAC00 800CA000 8C89FFF0 */ lw $t1, -0x10($a0)
|
||||
/* CAC04 800CA004 8C8AFFEC */ lw $t2, -0x14($a0)
|
||||
/* CAC08 800CA008 8C8BFFE8 */ lw $t3, -0x18($a0)
|
||||
/* CAC0C 800CA00C 8C8CFFE4 */ lw $t4, -0x1C($a0)
|
||||
/* CAC10 800CA010 8C8DFFE0 */ lw $t5, -0x20($a0)
|
||||
/* CAC14 800CA014 2484FFE0 */ addiu $a0, $a0, -0x20
|
||||
/* CAC18 800CA018 24A5FFE0 */ addiu $a1, $a1, -0x20
|
||||
/* CAC1C 800CA01C 24C6FFE0 */ addiu $a2, $a2, -0x20
|
||||
/* CAC20 800CA020 ACA2001C */ sw $v0, 0x1C($a1)
|
||||
/* CAC24 800CA024 ACA30018 */ sw $v1, 0x18($a1)
|
||||
/* CAC28 800CA028 ACA80014 */ sw $t0, 0x14($a1)
|
||||
/* CAC2C 800CA02C ACA90010 */ sw $t1, 0x10($a1)
|
||||
/* CAC30 800CA030 ACAA000C */ sw $t2, 0xC($a1)
|
||||
/* CAC34 800CA034 ACAB0008 */ sw $t3, 0x8($a1)
|
||||
/* CAC38 800CA038 ACAC0004 */ sw $t4, 0x4($a1)
|
||||
/* CAC3C 800CA03C 1000FFEA */ b .L800C9FE8
|
||||
/* CAC40 800CA040 ACAD0000 */ sw $t5, 0x0($a1)
|
||||
.L800CA044:
|
||||
/* CAC44 800CA044 28C10010 */ slti $at, $a2, 0x10
|
||||
.L800CA048:
|
||||
/* CAC48 800CA048 5420000E */ bnel $at, $zero, .L800CA084
|
||||
/* CAC4C 800CA04C 28C10004 */ slti $at, $a2, 0x4
|
||||
/* CAC50 800CA050 8C82FFFC */ lw $v0, -0x4($a0)
|
||||
/* CAC54 800CA054 8C83FFF8 */ lw $v1, -0x8($a0)
|
||||
/* CAC58 800CA058 8C88FFF4 */ lw $t0, -0xC($a0)
|
||||
/* CAC5C 800CA05C 8C89FFF0 */ lw $t1, -0x10($a0)
|
||||
/* CAC60 800CA060 2484FFF0 */ addiu $a0, $a0, -0x10
|
||||
/* CAC64 800CA064 24A5FFF0 */ addiu $a1, $a1, -0x10
|
||||
/* CAC68 800CA068 24C6FFF0 */ addiu $a2, $a2, -0x10
|
||||
/* CAC6C 800CA06C ACA2000C */ sw $v0, 0xC($a1)
|
||||
/* CAC70 800CA070 ACA30008 */ sw $v1, 0x8($a1)
|
||||
/* CAC74 800CA074 ACA80004 */ sw $t0, 0x4($a1)
|
||||
/* CAC78 800CA078 1000FFF2 */ b .L800CA044
|
||||
/* CAC7C 800CA07C ACA90000 */ sw $t1, 0x0($a1)
|
||||
.L800CA080:
|
||||
/* CAC80 800CA080 28C10004 */ slti $at, $a2, 0x4
|
||||
.L800CA084:
|
||||
/* CAC84 800CA084 1420FFB3 */ bnez $at, .L800C9F54
|
||||
/* CAC88 800CA088 00000000 */ nop
|
||||
/* CAC8C 800CA08C 8C82FFFC */ lw $v0, -0x4($a0)
|
||||
/* CAC90 800CA090 2484FFFC */ addiu $a0, $a0, -0x4
|
||||
/* CAC94 800CA094 24A5FFFC */ addiu $a1, $a1, -0x4
|
||||
/* CAC98 800CA098 24C6FFFC */ addiu $a2, $a2, -0x4
|
||||
/* CAC9C 800CA09C 1000FFF8 */ b .L800CA080
|
||||
/* CACA0 800CA0A0 ACA20000 */ sw $v0, 0x0($a1)
|
||||
.end bcopy
|
||||
forwards_bytecopy:
|
||||
beqz a2, ret
|
||||
addu v1, a0, a2
|
||||
99:
|
||||
lb v0, 0(a0)
|
||||
addiu a0, a0, 1
|
||||
sb v0, 0(a1)
|
||||
addiu a1, a1, 1
|
||||
bne a0, v1, 99b
|
||||
ret:
|
||||
move v0, a3
|
||||
jr ra
|
||||
|
||||
forwalignable:
|
||||
beqz v0, forwards
|
||||
beq v0, 1, forw_copy3
|
||||
beq v0, 2, forw_copy2
|
||||
|
||||
lb v0, 0(a0)
|
||||
addiu a0, a0, 1
|
||||
sb v0, 0(a1)
|
||||
addiu a1, a1, 1
|
||||
addiu a2, a2, -1
|
||||
b forwards
|
||||
|
||||
forw_copy2:
|
||||
lh v0, 0(a0)
|
||||
addiu a0, a0, 2
|
||||
sh v0, 0(a1)
|
||||
addiu a1, a1, 2
|
||||
addiu a2, a2, -2
|
||||
b forwards
|
||||
|
||||
forw_copy3:
|
||||
lb v0, 0(a0)
|
||||
lh v1, 1(a0)
|
||||
addiu a0, a0, 3
|
||||
sb v0, 0(a1)
|
||||
sh v1, 1(a1)
|
||||
addiu a1, a1, 3
|
||||
addiu a2, a2, -3
|
||||
|
||||
forwards:
|
||||
forwards_32:
|
||||
blt a2, 32, forwards_16
|
||||
lw v0, 0(a0)
|
||||
lw v1, 4(a0)
|
||||
lw t0, 8(a0)
|
||||
lw t1, 12(a0)
|
||||
lw t2, 16(a0)
|
||||
lw t3, 20(a0)
|
||||
lw ta0, 24(a0)
|
||||
lw ta1, 28(a0)
|
||||
addiu a0, a0, 32
|
||||
sw v0, 0(a1)
|
||||
sw v1, 4(a1)
|
||||
sw t0, 8(a1)
|
||||
sw t1, 12(a1)
|
||||
sw t2, 16(a1)
|
||||
sw t3, 20(a1)
|
||||
sw ta0, 24(a1)
|
||||
sw ta1, 28(a1)
|
||||
addiu a1, a1, 32
|
||||
addiu a2, a2, -32
|
||||
b forwards_32
|
||||
|
||||
forwards_16:
|
||||
blt a2, 16, forwards_4
|
||||
lw v0, 0(a0)
|
||||
lw v1, 4(a0)
|
||||
lw t0, 8(a0)
|
||||
lw t1, 12(a0)
|
||||
addiu a0, a0, 16
|
||||
sw v0, 0(a1)
|
||||
sw v1, 4(a1)
|
||||
sw t0, 8(a1)
|
||||
sw t1, 12(a1)
|
||||
addiu a1, a1, 16
|
||||
addiu a2, a2, -16
|
||||
b forwards_16
|
||||
|
||||
forwards_4:
|
||||
blt a2, 4, forwards_bytecopy
|
||||
|
||||
lw v0, 0(a0)
|
||||
addiu a0, a0, 4
|
||||
sw v0, 0(a1)
|
||||
addiu a1, a1, 4
|
||||
addiu a2, a2, -4
|
||||
b forwards_4
|
||||
|
||||
gobackwards:
|
||||
add a0, a0, a2
|
||||
add a1, a1, a2
|
||||
blt a2, 16, backwards_bytecopy
|
||||
|
||||
andi v0, a0, 0x3
|
||||
andi v1, a1, 0x3
|
||||
beq v0, v1, backalignable
|
||||
|
||||
backwards_bytecopy:
|
||||
beqz a2, ret
|
||||
addiu a0, a0, -1
|
||||
addiu a1, a1, -1
|
||||
subu v1, a0, a2
|
||||
99:
|
||||
lb v0, 0(a0)
|
||||
addiu a0, a0, -1
|
||||
sb v0, 0(a1)
|
||||
addiu a1, a1, -1
|
||||
bne a0, v1, 99b
|
||||
|
||||
move v0, a3
|
||||
jr ra
|
||||
backalignable:
|
||||
beqz v0, backwards
|
||||
beq v0, 3, back_copy3
|
||||
beq v0, 2, back_copy2
|
||||
lb v0, -1(a0)
|
||||
addiu a0, a0, -1
|
||||
sb v0, -1(a1)
|
||||
addiu a1, a1, -1
|
||||
addiu a2, a2, -1
|
||||
b backwards
|
||||
|
||||
back_copy2:
|
||||
lh v0, -2(a0)
|
||||
addiu a0, a0, -2
|
||||
sh v0, -2(a1)
|
||||
addiu a1, a1, -2
|
||||
addiu a2, a2, -2
|
||||
b backwards
|
||||
|
||||
back_copy3:
|
||||
lb v0, -1(a0)
|
||||
lh v1, -3(a0)
|
||||
addiu a0, a0, -3
|
||||
sb v0, -1(a1)
|
||||
sh v1, -3(a1)
|
||||
addiu a1, a1, -3
|
||||
addiu a2, a2, -3
|
||||
|
||||
backwards:
|
||||
backwards_32:
|
||||
blt a2, 32, backwards_16
|
||||
lw v0, -4(a0)
|
||||
lw v1, -8(a0)
|
||||
lw t0, -12(a0)
|
||||
lw t1, -16(a0)
|
||||
lw t2, -20(a0)
|
||||
lw t3, -24(a0)
|
||||
lw ta0, -28(a0)
|
||||
lw ta1, -32(a0)
|
||||
addiu a0, a0, -32
|
||||
sw v0, -4(a1)
|
||||
sw v1, -8(a1)
|
||||
sw t0, -12(a1)
|
||||
sw t1, -16(a1)
|
||||
sw t2, -20(a1)
|
||||
sw t3, -24(a1)
|
||||
sw ta0, -28(a1)
|
||||
sw ta1, -32(a1)
|
||||
addiu a1, a1, -32
|
||||
addiu a2, a2, -32
|
||||
b backwards_32
|
||||
|
||||
backwards_16:
|
||||
blt a2, 16, backwards_4
|
||||
lw v0, -4(a0)
|
||||
lw v1, -8(a0)
|
||||
lw t0, -12(a0)
|
||||
lw t1, -16(a0)
|
||||
addiu a0, a0, -16
|
||||
sw v0, -4(a1)
|
||||
sw v1, -8(a1)
|
||||
sw t0, -12(a1)
|
||||
sw t1, -16(a1)
|
||||
addiu a1, a1, -16
|
||||
addiu a2, a2, -16
|
||||
b backwards_16
|
||||
|
||||
backwards_4:
|
||||
blt a2, 4, backwards_bytecopy
|
||||
lw v0, -4(a0)
|
||||
addiu a0, a0, -4
|
||||
sw v0, -4(a1)
|
||||
addiu a1, a1, -4
|
||||
addiu a2, a2, -4
|
||||
b backwards_4
|
||||
|
||||
.end _bcopy
|
||||
|
||||
+68
-56
@@ -1,60 +1,72 @@
|
||||
.include "macro.inc"
|
||||
#include "PR/R4300.h"
|
||||
#include "sys/asm.h"
|
||||
#include "sys/regdef.h"
|
||||
|
||||
/* assembler directives */
|
||||
.set noat /* allow manual use of $at */
|
||||
.set noreorder /* don't insert nops after branches */
|
||||
.set gp=64 /* allow use of 64-bit general purpose registers */
|
||||
.text
|
||||
#ifdef __sgi
|
||||
WEAK(bzero, _bzero)
|
||||
WEAK(blkclr, _blkclr)
|
||||
#else
|
||||
#define _bzero bzero
|
||||
#define _blkclr blkclr
|
||||
#endif
|
||||
LEAF(_bzero)
|
||||
XLEAF(_blkclr)
|
||||
negu v1, a0
|
||||
blt a1, 12, bytezero
|
||||
|
||||
.section .text, "ax"
|
||||
andi v1, v1, 0x3
|
||||
subu a1, a1, v1
|
||||
|
||||
/* Generated by spimdisasm 1.30.0 */
|
||||
beqz v1, blkzero
|
||||
swl zero, 0(a0)
|
||||
addu a0, a0, v1
|
||||
blkzero:
|
||||
/* align backwards to 0x20 */
|
||||
and a3, a1, ~31
|
||||
subu a1, a1, a3
|
||||
/* If the result is zero, the amount to zero is less than 0x20 bytes */
|
||||
beqz a3, wordzero
|
||||
|
||||
leaf bzero
|
||||
/* D10E0 800D04E0 28A1000C */ slti $at, $a1, 0xC
|
||||
/* D10E4 800D04E4 1420001D */ bnez $at, .L800D055C
|
||||
/* D10E8 800D04E8 00041823 */ negu $v1, $a0
|
||||
/* D10EC 800D04EC 30630003 */ andi $v1, $v1, 0x3
|
||||
/* D10F0 800D04F0 10600003 */ beqz $v1, .L800D0500
|
||||
/* D10F4 800D04F4 00A32823 */ subu $a1, $a1, $v1
|
||||
/* D10F8 800D04F8 A8800000 */ swl $zero, 0x0($a0)
|
||||
/* D10FC 800D04FC 00832021 */ addu $a0, $a0, $v1
|
||||
.L800D0500:
|
||||
/* D1100 800D0500 2401FFE0 */ addiu $at, $zero, -0x20
|
||||
/* D1104 800D0504 00A13824 */ and $a3, $a1, $at
|
||||
/* D1108 800D0508 10E0000C */ beqz $a3, .L800D053C
|
||||
/* D110C 800D050C 00A72823 */ subu $a1, $a1, $a3
|
||||
/* D1110 800D0510 00E43821 */ addu $a3, $a3, $a0
|
||||
.L800D0514:
|
||||
/* D1114 800D0514 24840020 */ addiu $a0, $a0, 0x20
|
||||
/* D1118 800D0518 AC80FFE0 */ sw $zero, -0x20($a0)
|
||||
/* D111C 800D051C AC80FFE4 */ sw $zero, -0x1C($a0)
|
||||
/* D1120 800D0520 AC80FFE8 */ sw $zero, -0x18($a0)
|
||||
/* D1124 800D0524 AC80FFEC */ sw $zero, -0x14($a0)
|
||||
/* D1128 800D0528 AC80FFF0 */ sw $zero, -0x10($a0)
|
||||
/* D112C 800D052C AC80FFF4 */ sw $zero, -0xC($a0)
|
||||
/* D1130 800D0530 AC80FFF8 */ sw $zero, -0x8($a0)
|
||||
/* D1134 800D0534 1487FFF7 */ bne $a0, $a3, .L800D0514
|
||||
/* D1138 800D0538 AC80FFFC */ sw $zero, -0x4($a0)
|
||||
.L800D053C:
|
||||
/* D113C 800D053C 2401FFFC */ addiu $at, $zero, -0x4
|
||||
/* D1140 800D0540 00A13824 */ and $a3, $a1, $at
|
||||
/* D1144 800D0544 10E00005 */ beqz $a3, .L800D055C
|
||||
/* D1148 800D0548 00A72823 */ subu $a1, $a1, $a3
|
||||
/* D114C 800D054C 00E43821 */ addu $a3, $a3, $a0
|
||||
.L800D0550:
|
||||
/* D1150 800D0550 24840004 */ addiu $a0, $a0, 0x4
|
||||
/* D1154 800D0554 1487FFFE */ bne $a0, $a3, .L800D0550
|
||||
/* D1158 800D0558 AC80FFFC */ sw $zero, -0x4($a0)
|
||||
.L800D055C:
|
||||
/* D115C 800D055C 18A00005 */ blez $a1, .L800D0574
|
||||
/* D1160 800D0560 00000000 */ nop
|
||||
/* D1164 800D0564 00A42821 */ addu $a1, $a1, $a0
|
||||
.L800D0568:
|
||||
/* D1168 800D0568 24840001 */ addiu $a0, $a0, 0x1
|
||||
/* D116C 800D056C 1485FFFE */ bne $a0, $a1, .L800D0568
|
||||
/* D1170 800D0570 A080FFFF */ sb $zero, -0x1($a0)
|
||||
.L800D0574:
|
||||
/* D1174 800D0574 03E00008 */ jr $ra
|
||||
/* D1178 800D0578 00000000 */ nop
|
||||
/* D117C 800D057C 00000000 */ nop
|
||||
.end bzero
|
||||
/* zero in blocks of 0x20 at a time */
|
||||
addu a3, a3, a0
|
||||
1:
|
||||
sw zero, 0(a0)
|
||||
sw zero, 4(a0)
|
||||
sw zero, 8(a0)
|
||||
sw zero, 12(a0)
|
||||
addiu a0, a0, 32
|
||||
sw zero, -16(a0)
|
||||
sw zero, -12(a0)
|
||||
sw zero, -8(a0)
|
||||
sw zero, -4(a0)
|
||||
bne a0, a3, 1b
|
||||
|
||||
wordzero:
|
||||
/* align backwards to 0x4 */
|
||||
and a3, a1, ~3
|
||||
subu a1, a1, a3
|
||||
/* If the result is zero, the amount to zero is less than 0x4 bytes */
|
||||
beqz a3, bytezero
|
||||
|
||||
/* zero one word at a time */
|
||||
addu a3, a3, a0
|
||||
1:
|
||||
addiu a0, a0, 4
|
||||
sw zero, -4(a0)
|
||||
bne a0, a3, 1b
|
||||
|
||||
bytezero:
|
||||
/* test if nothing left to zero */
|
||||
blez a1, zerodone
|
||||
|
||||
/* zero one byte at a time */
|
||||
addu a1, a1, a0
|
||||
1:
|
||||
addiu a0, a0, 1
|
||||
sb zero, -1(a0)
|
||||
bne a0, a1, 1b
|
||||
zerodone:
|
||||
jr ra
|
||||
|
||||
.end _bzero
|
||||
|
||||
+1339
-689
File diff suppressed because it is too large
Load Diff
@@ -1,14 +1,9 @@
|
||||
.include "macro.inc"
|
||||
#include "PR/R4300.h"
|
||||
#include "sys/asm.h"
|
||||
#include "sys/regdef.h"
|
||||
|
||||
/* assembler directives */
|
||||
.set noat /* allow manual use of $at */
|
||||
.set noreorder /* don't insert nops after branches */
|
||||
.set gp=64 /* allow use of 64-bit general purpose registers */
|
||||
|
||||
.section .text, "ax"
|
||||
|
||||
leaf osGetCount
|
||||
mfc0 $v0, $9 /* C0_COUNT */
|
||||
jr $ra
|
||||
nop
|
||||
.end osGetCount
|
||||
.text
|
||||
LEAF(osGetCount)
|
||||
MFC0( v0, C0_COUNT)
|
||||
jr ra
|
||||
END(osGetCount)
|
||||
|
||||
+8
-14
@@ -1,15 +1,9 @@
|
||||
.include "macro.inc"
|
||||
#include "PR/R4300.h"
|
||||
#include "sys/asm.h"
|
||||
#include "sys/regdef.h"
|
||||
|
||||
/* assembler directives */
|
||||
.set noat /* allow manual use of $at */
|
||||
.set noreorder /* don't insert nops after branches */
|
||||
.set gp=64 /* allow use of 64-bit general purpose registers */
|
||||
|
||||
.section .text, "ax"
|
||||
|
||||
leaf __osGetSR
|
||||
mfc0 $v0, $12 /* C0_SR */
|
||||
jr $ra
|
||||
nop
|
||||
nop
|
||||
.end __osGetSR
|
||||
.text
|
||||
LEAF(__osGetSR)
|
||||
MFC0( v0, C0_SR)
|
||||
jr ra
|
||||
END(__osGetSR)
|
||||
|
||||
+53
-27
@@ -1,29 +1,55 @@
|
||||
.include "macro.inc"
|
||||
#include "PR/R4300.h"
|
||||
#include "sys/asm.h"
|
||||
#include "sys/regdef.h"
|
||||
#include "PR/os_version.h"
|
||||
#include "threadasm.h"
|
||||
|
||||
/* assembler directives */
|
||||
.set noat /* allow manual use of $at */
|
||||
.set noreorder /* don't insert nops after branches */
|
||||
.set gp=64 /* allow use of 64-bit general purpose registers */
|
||||
.text
|
||||
.set noreorder
|
||||
LEAF(__osDisableInt)
|
||||
#if BUILD_VERSION >= VERSION_J
|
||||
la t2, __OSGlobalIntMask
|
||||
lw t3, (t2)
|
||||
andi t3, SR_IMASK
|
||||
mfc0 t0, C0_SR
|
||||
and t1, t0, ~SR_IE
|
||||
mtc0 t1, C0_SR
|
||||
andi v0, t0, SR_IE
|
||||
lw t0, (t2)
|
||||
andi t0, SR_IMASK
|
||||
beq t0, t3, No_Change_Global_Int
|
||||
# @bug this la should be lw, it may never come up in practice as to reach this code
|
||||
# the CPU bits of __OSGlobalIntMask must have changed while this function is running.
|
||||
la t2, __osRunningThread # this is intentionally a macro in the branch delay slot
|
||||
lw t1, THREAD_SR(t2)
|
||||
andi t2, t1, SR_IMASK
|
||||
and t2, t0
|
||||
and t1, ~SR_IMASK
|
||||
or t1, t2
|
||||
and t1, ~SR_IE
|
||||
mtc0 t1, C0_SR
|
||||
nop
|
||||
nop
|
||||
No_Change_Global_Int:
|
||||
jr ra
|
||||
nop
|
||||
#else
|
||||
mfc0 t0, C0_SR
|
||||
and t1, t0, ~SR_IE
|
||||
mtc0 t1, C0_SR
|
||||
andi v0, t0, SR_IE
|
||||
nop
|
||||
jr ra
|
||||
nop
|
||||
#endif
|
||||
END(__osDisableInt)
|
||||
|
||||
.section .text, "ax"
|
||||
|
||||
leaf __osDisableInt
|
||||
mfc0 $t0, $12
|
||||
addiu $at, $zero, -0x2
|
||||
and $t1, $t0, $at
|
||||
mtc0 $t1, $12
|
||||
andi $v0, $t0, 0x1
|
||||
nop
|
||||
jr $ra
|
||||
nop
|
||||
.end __osDisableInt
|
||||
|
||||
leaf __osRestoreInt
|
||||
mfc0 $t0, $12
|
||||
or $t0, $t0, $a0
|
||||
mtc0 $t0, $12
|
||||
nop
|
||||
nop
|
||||
jr $ra
|
||||
nop
|
||||
.end __osRestoreInt
|
||||
LEAF(__osRestoreInt)
|
||||
mfc0 t0, C0_SR
|
||||
or t0, t0, a0
|
||||
mtc0 t0, C0_SR
|
||||
nop
|
||||
nop
|
||||
jr ra
|
||||
nop
|
||||
END(__osRestoreInt)
|
||||
|
||||
@@ -1,62 +1,91 @@
|
||||
.include "macro.inc"
|
||||
#include "PR/R4300.h"
|
||||
#include "sys/asm.h"
|
||||
#include "sys/regdef.h"
|
||||
|
||||
/* assembler directives */
|
||||
.set noat /* allow manual use of $at */
|
||||
.set noreorder /* don't insert nops after branches */
|
||||
.set gp=64 /* allow use of 64-bit general purpose registers */
|
||||
.text
|
||||
/**
|
||||
* void osInvalDCache(void* vaddr, s32 nbytes);
|
||||
*
|
||||
* Invalidates the CPU Data Cache for `nbytes` at `vaddr`.
|
||||
* The cache is not automatically synced with physical memory, so cache
|
||||
* lines must be invalidated to ensure old data is not used in place of
|
||||
* newly available data supplied by an external agent in a DMA operation.
|
||||
*
|
||||
* If `vaddr` is not aligned to a cache line boundary, or nbytes is not a
|
||||
* multiple of the data cache line size (16 bytes) a larger region is
|
||||
* invalidated.
|
||||
*
|
||||
* If the amount to invalidate is at least the data cache size (DCACHE_SIZE),
|
||||
* the entire data cache is invalidated.
|
||||
*/
|
||||
LEAF(osInvalDCache)
|
||||
/* If the amount to invalidate is less than or equal to 0, return immediately */
|
||||
blez a1, 3f
|
||||
/*
|
||||
* If the amount to invalidate is as large as or larger than
|
||||
* the data cache size, invalidate all
|
||||
*/
|
||||
li t3, DCACHE_SIZE
|
||||
bgeu a1, t3, 4f
|
||||
|
||||
.section .text, "ax"
|
||||
/*
|
||||
* Ensure end address does not wrap around and end up smaller
|
||||
* than the start address
|
||||
*/
|
||||
move t0, a0
|
||||
addu t1, a0, a1
|
||||
bgeu t0, t1, 3f
|
||||
|
||||
/* Generated by spimdisasm 1.30.0 */
|
||||
/* Mask start with cache line */
|
||||
addiu t1, t1, -DCACHE_LINESIZE
|
||||
andi t2, t0, DCACHE_LINEMASK
|
||||
/* If mask is not zero, the start is not cache aligned */
|
||||
beqz t2, 1f
|
||||
|
||||
/* Handwritten function */
|
||||
leaf osInvalDCache
|
||||
/* D23F0 800D17F0 18A0001F */ blez $a1, .L800D1870
|
||||
/* D23F4 800D17F4 00000000 */ nop
|
||||
/* D23F8 800D17F8 240B2000 */ addiu $t3, $zero, 0x2000
|
||||
/* D23FC 800D17FC 00AB082B */ sltu $at, $a1, $t3
|
||||
/* D2400 800D1800 1020001D */ beqz $at, .L800D1878
|
||||
/* D2404 800D1804 00000000 */ nop
|
||||
/* D2408 800D1808 00804025 */ or $t0, $a0, $zero
|
||||
/* D240C 800D180C 00854821 */ addu $t1, $a0, $a1
|
||||
/* D2410 800D1810 0109082B */ sltu $at, $t0, $t1
|
||||
/* D2414 800D1814 10200016 */ beqz $at, .L800D1870
|
||||
/* D2418 800D1818 00000000 */ nop
|
||||
/* D241C 800D181C 310A000F */ andi $t2, $t0, 0xF
|
||||
/* D2420 800D1820 11400007 */ beqz $t2, .L800D1840
|
||||
/* D2424 800D1824 2529FFF0 */ addiu $t1, $t1, -0x10
|
||||
/* D2428 800D1828 010A4023 */ subu $t0, $t0, $t2
|
||||
/* D242C 800D182C BD150000 */ cache 0x15, 0x0($t0) /* handwritten instruction */
|
||||
/* D2430 800D1830 0109082B */ sltu $at, $t0, $t1
|
||||
/* D2434 800D1834 1020000E */ beqz $at, .L800D1870
|
||||
/* D2438 800D1838 00000000 */ nop
|
||||
/* D243C 800D183C 25080010 */ addiu $t0, $t0, 0x10
|
||||
.L800D1840:
|
||||
/* D2440 800D1840 312A000F */ andi $t2, $t1, 0xF
|
||||
/* D2444 800D1844 11400006 */ beqz $t2, .L800D1860
|
||||
/* D2448 800D1848 00000000 */ nop
|
||||
/* D244C 800D184C 012A4823 */ subu $t1, $t1, $t2
|
||||
/* D2450 800D1850 BD350010 */ cache 0x15, 0x10($t1) /* handwritten instruction */
|
||||
/* D2454 800D1854 0128082B */ sltu $at, $t1, $t0
|
||||
/* D2458 800D1858 14200005 */ bnez $at, .L800D1870
|
||||
/* D245C 800D185C 00000000 */ nop
|
||||
.L800D1860:
|
||||
/* D2460 800D1860 BD110000 */ cache 0x11, 0x0($t0) /* handwritten instruction */
|
||||
/* D2464 800D1864 0109082B */ sltu $at, $t0, $t1
|
||||
/* D2468 800D1868 1420FFFD */ bnez $at, .L800D1860
|
||||
/* D246C 800D186C 25080010 */ addiu $t0, $t0, 0x10
|
||||
.L800D1870:
|
||||
/* D2470 800D1870 03E00008 */ jr $ra
|
||||
/* D2474 800D1874 00000000 */ nop
|
||||
.L800D1878:
|
||||
/* D2478 800D1878 3C088000 */ lui $t0, 0x8000
|
||||
/* D247C 800D187C 010B4821 */ addu $t1, $t0, $t3
|
||||
/* D2480 800D1880 2529FFF0 */ addiu $t1, $t1, -0x10
|
||||
.L800D1884:
|
||||
/* D2484 800D1884 BD010000 */ cache 0x01, 0x0($t0) /* handwritten instruction */
|
||||
/* D2488 800D1888 0109082B */ sltu $at, $t0, $t1
|
||||
/* D248C 800D188C 1420FFFD */ bnez $at, .L800D1884
|
||||
/* D2490 800D1890 25080010 */ addiu $t0, $t0, (0x80000010 & 0xFFFF)
|
||||
/* D2494 800D1894 03E00008 */ jr $ra
|
||||
/* D2498 800D1898 00000000 */ nop
|
||||
.end osInvalDCache
|
||||
/* Subtract mask result to align to cache line */
|
||||
subu t0, t0, t2
|
||||
/* Hit-Writeback-Invalidate unaligned part */
|
||||
CACHE( (C_HWBINV | CACH_PD), (t0))
|
||||
/* If that is all there is to do, return early */
|
||||
bgeu t0, t1, 3f
|
||||
|
||||
|
||||
addiu t0, t0, DCACHE_LINESIZE
|
||||
1:
|
||||
/* Mask end with cache line */
|
||||
andi t2, t1, DCACHE_LINEMASK
|
||||
/* If mask is not zero, the end is not cache aligned */
|
||||
beqz t2, 2f
|
||||
|
||||
/* Subtract mask result to align to cache line */
|
||||
subu t1, t1, t2
|
||||
|
||||
/* Hit-Writeback-Invalidate unaligned part */
|
||||
CACHE( (C_HWBINV | CACH_PD), DCACHE_LINESIZE(t1))
|
||||
bltu t1, t0, 3f
|
||||
|
||||
2:
|
||||
/* Hit-Invalidate */
|
||||
CACHE( (C_HINV | CACH_PD), (t0))
|
||||
.set noreorder
|
||||
bltu t0, t1, 2b
|
||||
addiu t0, t0, DCACHE_LINESIZE
|
||||
.set reorder
|
||||
3:
|
||||
jr ra
|
||||
|
||||
4:
|
||||
li t0, K0BASE
|
||||
addu t1, t0, t3
|
||||
addiu t1, t1, -DCACHE_LINESIZE
|
||||
5:
|
||||
/* Index-Writeback-Invalidate */
|
||||
CACHE( (C_IINV | CACH_PD), (t0))
|
||||
.set noreorder
|
||||
bltu t0, t1, 5b
|
||||
addiu t0, t0, DCACHE_LINESIZE
|
||||
.set reorder
|
||||
|
||||
jr ra
|
||||
|
||||
END(osInvalDCache)
|
||||
|
||||
@@ -1,47 +1,51 @@
|
||||
.include "macro.inc"
|
||||
#include "PR/R4300.h"
|
||||
#include "sys/asm.h"
|
||||
#include "sys/regdef.h"
|
||||
|
||||
/* assembler directives */
|
||||
.set noat /* allow manual use of $at */
|
||||
.set noreorder /* don't insert nops after branches */
|
||||
.set gp=64 /* allow use of 64-bit general purpose registers */
|
||||
.text
|
||||
LEAF(osInvalICache)
|
||||
/* If the amount to invalidate is less than or equal to 0, return immediately */
|
||||
blez a1, 2f
|
||||
|
||||
.section .text, "ax"
|
||||
/*
|
||||
* If the amount to invalidate is as large as or larger than
|
||||
* the instruction cache size, invalidate all
|
||||
*/
|
||||
li t3, ICACHE_SIZE
|
||||
bgeu a1, t3, 3f
|
||||
|
||||
/* Generated by spimdisasm 1.30.0 */
|
||||
/*
|
||||
* ensure end address does not wrap around and end up smaller
|
||||
* than the start address
|
||||
*/
|
||||
move t0, a0
|
||||
addu t1, a0, a1
|
||||
bgeu t0, t1, 2f
|
||||
|
||||
/* Handwritten function */
|
||||
leaf osInvalICache
|
||||
/* D52B0 800D46B0 18A00011 */ blez $a1, .L800D46F8
|
||||
/* D52B4 800D46B4 00000000 */ nop
|
||||
/* D52B8 800D46B8 240B4000 */ addiu $t3, $zero, 0x4000
|
||||
/* D52BC 800D46BC 00AB082B */ sltu $at, $a1, $t3
|
||||
/* D52C0 800D46C0 1020000F */ beqz $at, .L800D4700
|
||||
/* D52C4 800D46C4 00000000 */ nop
|
||||
/* D52C8 800D46C8 00804025 */ or $t0, $a0, $zero
|
||||
/* D52CC 800D46CC 00854821 */ addu $t1, $a0, $a1
|
||||
/* D52D0 800D46D0 0109082B */ sltu $at, $t0, $t1
|
||||
/* D52D4 800D46D4 10200008 */ beqz $at, .L800D46F8
|
||||
/* D52D8 800D46D8 00000000 */ nop
|
||||
/* D52DC 800D46DC 310A001F */ andi $t2, $t0, 0x1F
|
||||
/* D52E0 800D46E0 2529FFE0 */ addiu $t1, $t1, -0x20
|
||||
/* D52E4 800D46E4 010A4023 */ subu $t0, $t0, $t2
|
||||
.L800D46E8:
|
||||
/* D52E8 800D46E8 BD100000 */ cache 0x10, 0x0($t0) /* handwritten instruction */
|
||||
/* D52EC 800D46EC 0109082B */ sltu $at, $t0, $t1
|
||||
/* D52F0 800D46F0 1420FFFD */ bnez $at, .L800D46E8
|
||||
/* D52F4 800D46F4 25080020 */ addiu $t0, $t0, 0x20
|
||||
.L800D46F8:
|
||||
/* D52F8 800D46F8 03E00008 */ jr $ra
|
||||
/* D52FC 800D46FC 00000000 */ nop
|
||||
.L800D4700:
|
||||
/* D5300 800D4700 3C088000 */ lui $t0, 0x8000
|
||||
/* D5304 800D4704 010B4821 */ addu $t1, $t0, $t3
|
||||
/* D5308 800D4708 2529FFE0 */ addiu $t1, $t1, -0x20
|
||||
.L800D470C:
|
||||
/* D530C 800D470C BD000000 */ cache 0x00, 0x0($t0) /* handwritten instruction */
|
||||
/* D5310 800D4710 0109082B */ sltu $at, $t0, $t1
|
||||
/* D5314 800D4714 1420FFFD */ bnez $at, .L800D470C
|
||||
/* D5318 800D4718 25080020 */ addiu $t0, $t0, (0x80000020 & 0xFFFF)
|
||||
/* D531C 800D471C 03E00008 */ jr $ra
|
||||
/* D5320 800D4720 00000000 */ nop
|
||||
.end osInvalICache
|
||||
/* Mask and subtract to align to cache line */
|
||||
addiu t1, t1, -ICACHE_LINESIZE
|
||||
andi t2, t0, ICACHE_LINEMASK
|
||||
subu t0, t0, t2
|
||||
1:
|
||||
CACHE( (C_HINV | CACH_PI), (t0))
|
||||
.set noreorder
|
||||
bltu t0, t1, 1b
|
||||
addiu t0, t0, ICACHE_LINESIZE
|
||||
.set reorder
|
||||
2:
|
||||
jr ra
|
||||
|
||||
3:
|
||||
li t0, K0BASE
|
||||
addu t1, t0, t3
|
||||
addiu t1, t1, -ICACHE_LINESIZE
|
||||
4:
|
||||
CACHE( (C_IINV | CACH_PI), (t0))
|
||||
.set noreorder
|
||||
bltu t0, t1, 4b
|
||||
addiu t0, t0, ICACHE_LINESIZE
|
||||
.set reorder
|
||||
|
||||
jr ra
|
||||
|
||||
END(osInvalICache)
|
||||
|
||||
+30
-35
@@ -1,36 +1,31 @@
|
||||
.include "macro.inc"
|
||||
#include "PR/R4300.h"
|
||||
#include "PR/rdb.h"
|
||||
#include "sys/asm.h"
|
||||
#include "sys/regdef.h"
|
||||
|
||||
/* assembler directives */
|
||||
.set noat /* allow manual use of $at */
|
||||
.set noreorder /* don't insert nops after branches */
|
||||
.set gp=64 /* allow use of 64-bit general purpose registers */
|
||||
|
||||
.section .text, "ax"
|
||||
|
||||
/* Generated by spimdisasm 1.30.0 */
|
||||
|
||||
/* Handwritten function */
|
||||
leaf osMapTLBRdb
|
||||
/* D5330 800D4730 40085000 */ mfc0 $t0, $10 /* handwritten instruction */
|
||||
/* D5334 800D4734 2409001F */ addiu $t1, $zero, 0x1F
|
||||
/* D5338 800D4738 40890000 */ mtc0 $t1, $0 /* handwritten instruction */
|
||||
/* D533C 800D473C 40802800 */ mtc0 $zero, $5 /* handwritten instruction */
|
||||
/* D5340 800D4740 240A0017 */ addiu $t2, $zero, 0x17
|
||||
/* D5344 800D4744 3C09C000 */ lui $t1, (0xC0000000 >> 16)
|
||||
/* D5348 800D4748 40895000 */ mtc0 $t1, $10 /* handwritten instruction */
|
||||
/* D534C 800D474C 3C098000 */ lui $t1, (0x80000000 >> 16)
|
||||
/* D5350 800D4750 00095982 */ srl $t3, $t1, 6
|
||||
/* D5354 800D4754 016A5825 */ or $t3, $t3, $t2
|
||||
/* D5358 800D4758 408B1000 */ mtc0 $t3, $2 /* handwritten instruction */
|
||||
/* D535C 800D475C 24090001 */ addiu $t1, $zero, 0x1
|
||||
/* D5360 800D4760 40891800 */ mtc0 $t1, $3 /* handwritten instruction */
|
||||
/* D5364 800D4764 00000000 */ nop
|
||||
/* D5368 800D4768 42000002 */ tlbwi /* handwritten instruction */
|
||||
/* D536C 800D476C 00000000 */ nop
|
||||
/* D5370 800D4770 00000000 */ nop
|
||||
/* D5374 800D4774 00000000 */ nop
|
||||
/* D5378 800D4778 00000000 */ nop
|
||||
/* D537C 800D477C 40885000 */ mtc0 $t0, $10 /* handwritten instruction */
|
||||
/* D5380 800D4780 03E00008 */ jr $ra
|
||||
/* D5384 800D4784 00000000 */ nop
|
||||
.end osMapTLBRdb
|
||||
.text
|
||||
.set noreorder
|
||||
LEAF(osMapTLBRdb)
|
||||
mfc0 t0, C0_ENTRYHI
|
||||
li t1, NTLBENTRIES
|
||||
mtc0 t1, C0_INX
|
||||
mtc0 zero, C0_PAGEMASK /* 4k */
|
||||
li t2, (TLBLO_UNCACHED | TLBLO_D | TLBLO_V | TLBLO_G)
|
||||
li t1, K2BASE
|
||||
mtc0 t1, C0_ENTRYHI
|
||||
li t1, RDB_BASE_VIRTUAL_ADDR
|
||||
srl t3, t1, TLBLO_PFNSHIFT
|
||||
or t3, t3, t2
|
||||
mtc0 t3, C0_ENTRYLO0
|
||||
li t1, TLBLO_G
|
||||
mtc0 t1, C0_ENTRYLO1
|
||||
nop
|
||||
tlbwi
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
mtc0 t0, C0_ENTRYHI
|
||||
jr ra
|
||||
nop
|
||||
END(osMapTLBRdb)
|
||||
|
||||
+84
-63
@@ -1,64 +1,85 @@
|
||||
.include "macro.inc"
|
||||
#include "PR/R4300.h"
|
||||
#include "sys/asm.h"
|
||||
#include "sys/regdef.h"
|
||||
|
||||
/* assembler directives */
|
||||
.set noat /* allow manual use of $at */
|
||||
.set noreorder /* don't insert nops after branches */
|
||||
.set gp=64 /* allow use of 64-bit general purpose registers */
|
||||
|
||||
.section .text, "ax"
|
||||
|
||||
/* Generated by spimdisasm 1.30.0 */
|
||||
|
||||
/* Handwritten function */
|
||||
leaf __osProbeTLB
|
||||
/* D41B0 800D35B0 40085000 */ mfc0 $t0, $10 /* handwritten instruction */
|
||||
/* D41B4 800D35B4 310900FF */ andi $t1, $t0, 0xFF
|
||||
/* D41B8 800D35B8 2401E000 */ addiu $at, $zero, -0x2000
|
||||
/* D41BC 800D35BC 00815024 */ and $t2, $a0, $at
|
||||
/* D41C0 800D35C0 012A4825 */ or $t1, $t1, $t2
|
||||
/* D41C4 800D35C4 40895000 */ mtc0 $t1, $10 /* handwritten instruction */
|
||||
/* D41C8 800D35C8 00000000 */ nop
|
||||
/* D41CC 800D35CC 00000000 */ nop
|
||||
/* D41D0 800D35D0 00000000 */ nop
|
||||
/* D41D4 800D35D4 42000008 */ tlbp /* handwritten instruction */
|
||||
/* D41D8 800D35D8 00000000 */ nop
|
||||
/* D41DC 800D35DC 00000000 */ nop
|
||||
/* D41E0 800D35E0 400B0000 */ mfc0 $t3, $0 /* handwritten instruction */
|
||||
/* D41E4 800D35E4 3C018000 */ lui $at, (0x80000000 >> 16)
|
||||
/* D41E8 800D35E8 01615824 */ and $t3, $t3, $at
|
||||
/* D41EC 800D35EC 1560001A */ bnez $t3, .L800D3658
|
||||
/* D41F0 800D35F0 00000000 */ nop
|
||||
/* D41F4 800D35F4 42000001 */ tlbr /* handwritten instruction */
|
||||
/* D41F8 800D35F8 00000000 */ nop
|
||||
/* D41FC 800D35FC 00000000 */ nop
|
||||
/* D4200 800D3600 00000000 */ nop
|
||||
/* D4204 800D3604 400B2800 */ mfc0 $t3, $5 /* handwritten instruction */
|
||||
/* D4208 800D3608 216B2000 */ addi $t3, $t3, 0x2000 /* handwritten instruction */
|
||||
/* D420C 800D360C 000B5842 */ srl $t3, $t3, 1
|
||||
/* D4210 800D3610 01646024 */ and $t4, $t3, $a0
|
||||
/* D4214 800D3614 15800004 */ bnez $t4, .L800D3628
|
||||
/* D4218 800D3618 216BFFFF */ addi $t3, $t3, -0x1 /* handwritten instruction */
|
||||
/* D421C 800D361C 40021000 */ mfc0 $v0, $2 /* handwritten instruction */
|
||||
/* D4220 800D3620 10000002 */ b .L800D362C
|
||||
/* D4224 800D3624 00000000 */ nop
|
||||
.L800D3628:
|
||||
/* D4228 800D3628 40021800 */ mfc0 $v0, $3 /* handwritten instruction */
|
||||
.L800D362C:
|
||||
/* D422C 800D362C 304D0002 */ andi $t5, $v0, 0x2
|
||||
/* D4230 800D3630 11A00009 */ beqz $t5, .L800D3658
|
||||
/* D4234 800D3634 00000000 */ nop
|
||||
/* D4238 800D3638 3C013FFF */ lui $at, (0x3FFFFFC0 >> 16)
|
||||
/* D423C 800D363C 3421FFC0 */ ori $at, $at, (0x3FFFFFC0 & 0xFFFF)
|
||||
/* D4240 800D3640 00411024 */ and $v0, $v0, $at
|
||||
/* D4244 800D3644 00021180 */ sll $v0, $v0, 6
|
||||
/* D4248 800D3648 008B6824 */ and $t5, $a0, $t3
|
||||
/* D424C 800D364C 004D1020 */ add $v0, $v0, $t5 /* handwritten instruction */
|
||||
/* D4250 800D3650 10000002 */ b .L800D365C
|
||||
/* D4254 800D3654 00000000 */ nop
|
||||
.L800D3658:
|
||||
/* D4258 800D3658 2402FFFF */ addiu $v0, $zero, -0x1
|
||||
.L800D365C:
|
||||
/* D425C 800D365C 40885000 */ mtc0 $t0, $10 /* handwritten instruction */
|
||||
/* D4260 800D3660 03E00008 */ jr $ra
|
||||
/* D4264 800D3664 00000000 */ nop
|
||||
.end __osProbeTLB
|
||||
.text
|
||||
.set noreorder
|
||||
/**
|
||||
* u32 __osProbeTLB(void* vaddr);
|
||||
*
|
||||
* Searches the TLB for the physical address associated with
|
||||
* the virtual address `vaddr`.
|
||||
*
|
||||
* Returns the physical address if found, or -1 if not found.
|
||||
*/
|
||||
LEAF(__osProbeTLB)
|
||||
/* Set C0_ENTRYHI based on supplied vaddr */
|
||||
mfc0 t0, C0_ENTRYHI
|
||||
andi t1, t0, TLBHI_PIDMASK
|
||||
and t2, a0, (TLBHI_VPN2MASK << 32) >> 32
|
||||
or t1, t1, t2
|
||||
mtc0 t1, C0_ENTRYHI
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
/*
|
||||
* TLB probe, sets C0_INX to a value matching C0_ENTRYHI.
|
||||
* If no match is found the TLBINX_PROBE bit is set to indicate this.
|
||||
*/
|
||||
tlbp
|
||||
nop
|
||||
nop
|
||||
/* Read result */
|
||||
mfc0 t3, C0_INX
|
||||
and t3, t3, TLBINX_PROBE
|
||||
/* Branch if no match was found */
|
||||
bnez t3, 3f
|
||||
nop
|
||||
/*
|
||||
* Read TLB, sets C0_ENTRYHI, C0_ENTRYLO0, C0_ENTRYLO1 and C0_PAGEMASK for the TLB
|
||||
* entry indicated by C0_INX
|
||||
*/
|
||||
tlbr
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
/* Calculate page size = (page mask + 0x2000) >> 1 */
|
||||
mfc0 t3, C0_PAGEMASK
|
||||
addi t3, t3, 0x2000
|
||||
srl t3, t3, 0x1
|
||||
/* & with vaddr */
|
||||
and ta0, t3, a0
|
||||
/* Select C0_ENTRYLO0 or C0_ENTRYLO1 */
|
||||
bnez ta0, 1f
|
||||
/* make bitmask out of page size */
|
||||
addi t3, t3, -1
|
||||
mfc0 v0, C0_ENTRYLO0
|
||||
b 2f
|
||||
nop
|
||||
1:
|
||||
mfc0 v0, C0_ENTRYLO1
|
||||
2:
|
||||
/* Check valid bit and branch if not valid */
|
||||
andi ta1, v0, TLBLO_V
|
||||
beqz ta1, 3f
|
||||
nop
|
||||
/* Extract the Page Frame Number from the entry */
|
||||
and v0, v0, TLBLO_PFNMASK
|
||||
sll v0, v0, TLBLO_PFNSHIFT
|
||||
/* Mask vaddr with page size mask */
|
||||
and ta1, a0, t3
|
||||
/* Add masked vaddr to pfn to obtain the physical address */
|
||||
add v0, v0, ta1
|
||||
b 4f
|
||||
nop
|
||||
3:
|
||||
/*
|
||||
* No physical address for the supplied virtual address was found,
|
||||
* return -1
|
||||
*/
|
||||
li v0, -1
|
||||
4:
|
||||
mtc0 t0, C0_ENTRYHI
|
||||
jr ra
|
||||
nop
|
||||
END(__osProbeTLB)
|
||||
|
||||
@@ -1,17 +1,9 @@
|
||||
.include "macro.inc"
|
||||
#include "PR/R4300.h"
|
||||
#include "sys/asm.h"
|
||||
#include "sys/regdef.h"
|
||||
|
||||
/* assembler directives */
|
||||
.set noat /* allow manual use of $at */
|
||||
.set noreorder /* don't insert nops after branches */
|
||||
.set gp=64 /* allow use of 64-bit general purpose registers */
|
||||
|
||||
.section .text, "ax"
|
||||
|
||||
/* Generated by spimdisasm 1.30.0 */
|
||||
|
||||
/* Handwritten function */
|
||||
leaf __osSetCompare
|
||||
/* D8060 800D7460 40845800 */ mtc0 $a0, $11 /* handwritten instruction */
|
||||
/* D8064 800D7464 03E00008 */ jr $ra
|
||||
/* D8068 800D7468 00000000 */ nop
|
||||
.end __osSetCompare
|
||||
.text
|
||||
LEAF(__osSetCompare)
|
||||
MTC0( a0, C0_COMPARE)
|
||||
jr ra
|
||||
END(__osSetCompare)
|
||||
|
||||
+13
-16
@@ -1,17 +1,14 @@
|
||||
.include "macro.inc"
|
||||
#include "PR/R4300.h"
|
||||
#include "sys/asm.h"
|
||||
#include "sys/regdef.h"
|
||||
|
||||
/* assembler directives */
|
||||
.set noat /* allow manual use of $at */
|
||||
.set noreorder /* don't insert nops after branches */
|
||||
.set gp=64 /* allow use of 64-bit general purpose registers */
|
||||
|
||||
.section .text, "ax"
|
||||
|
||||
/* Generated by spimdisasm 1.30.0 */
|
||||
|
||||
leaf __osSetFpcCsr
|
||||
cfc1 $v0, $31
|
||||
ctc1 $a0, $31
|
||||
jr $ra
|
||||
nop
|
||||
.end __osSetFpcCsr
|
||||
.text
|
||||
LEAF(__osSetFpcCsr)
|
||||
CFC1( v0, fcr31)
|
||||
CTC1( a0, fcr31)
|
||||
jr ra
|
||||
#ifndef MODERN_CC
|
||||
END(__osSetSR) # @bug: Should be __osSetFpcCsr
|
||||
#else
|
||||
END(__osSetFpcCsr)
|
||||
#endif
|
||||
|
||||
+156
-64
@@ -1,70 +1,162 @@
|
||||
.include "macro.inc"
|
||||
#include "PR/R4300.h"
|
||||
#include "PR/rcp.h"
|
||||
#include "PR/os.h"
|
||||
#include "sys/asm.h"
|
||||
#include "sys/regdef.h"
|
||||
|
||||
/* assembler directives */
|
||||
.set noat /* allow manual use of $at */
|
||||
.set noreorder /* don't insert nops after branches */
|
||||
.set gp=64 /* allow use of 64-bit general purpose registers */
|
||||
#define MI_INTR_MASK ((1 << 6) - 1)
|
||||
|
||||
.section .rodata
|
||||
.globl __osRcpImTable
|
||||
|
||||
glabel __osRcpImTable
|
||||
.text
|
||||
.set noreorder
|
||||
/**
|
||||
* OSIntMask osSetIntMask(OSIntMask);
|
||||
*
|
||||
* Sets the interrupt enable mask for the current thread. External interrupts
|
||||
* originating either in the CPU or the RCP may be "masked out" so that they
|
||||
* are not handled. This is sometimes important for critical code sections
|
||||
* that must not be interrupted.
|
||||
* Interrupts that are not enabled in the global interrupt mask __OSGlobalIntMask
|
||||
* cannot be set here. The global interrupt mask is OS-internal and is not
|
||||
* expected to change during runtime.
|
||||
* The returned value is the previous interrupt enable mask so that it can be
|
||||
* restored later.
|
||||
*
|
||||
* @bug Some usage of the global interrupt mask is broken both in here and in the
|
||||
* exception handler routines.
|
||||
* While a thread is running, the C0_SR interrupt enable bits contain the
|
||||
* interrupt enable bits for the current thread masked by the global
|
||||
* interrupt mask. There is an attempt to recover only the original interrupt
|
||||
* enable bits belonging to the thread itself using the operation
|
||||
* (SR | ~__OSGlobalIntMask).
|
||||
* However, this does not work as intended and can cause interrupts to end
|
||||
* up enabled when not intended to be. The same issue is present for the
|
||||
* RCP interrupt enable bits in MI_INTR_MASK_REG.
|
||||
* This does not cause issues in practice as __OSGlobalIntMask is almost always
|
||||
* OS_IM_ALL, so the operation is usually simply (SR | 0).
|
||||
*/
|
||||
LEAF(osSetIntMask)
|
||||
/* Extract interrupt enable bits from current SR */
|
||||
mfc0 ta0, C0_SR
|
||||
|
||||
andi v0, ta0, OS_IM_CPU
|
||||
|
||||
/* Get value of __OSGlobalIntMask */
|
||||
la t0, __OSGlobalIntMask
|
||||
lw t3, 0(t0)
|
||||
|
||||
/* Bitwise-OR in the disabled CPU bits of __OSGlobalIntMask */
|
||||
xor t0, t3, ~0
|
||||
andi t0, t0, SR_IMASK
|
||||
or v0, v0, t0
|
||||
|
||||
/* Fetch MI_INTR_MASK_REG */
|
||||
lw t2, PHYS_TO_K1(MI_INTR_MASK_REG)
|
||||
/* If there are RCP interrupts masked */
|
||||
beqz t2, 1f
|
||||
srl t1, t3, 0x10
|
||||
|
||||
/* Bitwise-OR in the disabled RCP bits of __OSGlobalIntMask */
|
||||
xor t1, t1, ~0
|
||||
andi t1, t1, (RCP_IMASK >> RCP_IMASKSHIFT)
|
||||
or t2, t2, t1
|
||||
1:
|
||||
/* Shift the RCP bits to not conflict with the CPU bits */
|
||||
sll t2, t2, RCP_IMASKSHIFT
|
||||
/* OR the CPU and RCP bits together */
|
||||
or v0, v0, t2
|
||||
|
||||
/* Extract RCP interrupt enable bits from requested mask and mask with __OSGlobalIntMask */
|
||||
and t0, a0, RCP_IMASK
|
||||
and t0, t0, t3
|
||||
/* Convert to a value for MI_INTR_MASK_REG and set it */
|
||||
srl t0, t0, (RCP_IMASKSHIFT - 1)
|
||||
lhu t2, __osRcpImTable(t0)
|
||||
sw t2, PHYS_TO_K1(MI_INTR_MASK_REG)
|
||||
|
||||
/* Extract CPU interrupt enable bits from requested mask and mask with __OSGlobalIntMask */
|
||||
andi t0, a0, OS_IM_CPU
|
||||
andi t1, t3, SR_IMASK
|
||||
and t0, t0, t1
|
||||
|
||||
and ta0, ta0, ~SR_IMASK
|
||||
/* Bitwise OR in the remaining bits of SR and set new SR */
|
||||
or ta0, ta0, t0
|
||||
|
||||
mtc0 ta0, C0_SR
|
||||
nop
|
||||
nop
|
||||
jr ra
|
||||
nop
|
||||
END(osSetIntMask)
|
||||
|
||||
.rdata
|
||||
EXPORT(__osRcpImTable)
|
||||
/* LUT to convert between MI_INTR and MI_INTR_MASK */
|
||||
/* MI_INTR is status for each interrupt whereas */
|
||||
/* MI_INTR_MASK has seperate bits for set/clr */
|
||||
.half 0x0555, 0x0556, 0x0559, 0x055A, 0x0565, 0x0566, 0x0569, 0x056A
|
||||
.half 0x0595, 0x0596, 0x0599, 0x059A, 0x05A5, 0x05A6, 0x05A9, 0x05AA
|
||||
.half 0x0655, 0x0656, 0x0659, 0x065A, 0x0665, 0x0666, 0x0669, 0x066A
|
||||
.half 0x0695, 0x0696, 0x0699, 0x069A, 0x06A5, 0x06A6, 0x06A9, 0x06AA
|
||||
.half 0x0955, 0x0956, 0x0959, 0x095A, 0x0965, 0x0966, 0x0969, 0x096A
|
||||
.half 0x0995, 0x0996, 0x0999, 0x099A, 0x09A5, 0x09A6, 0x09A9, 0x09AA
|
||||
.half 0x0A55, 0x0A56, 0x0A59, 0x0A5A, 0x0A65, 0x0A66, 0x0A69, 0x0A6A
|
||||
.half 0x0A95, 0x0A96, 0x0A99, 0x0A9A, 0x0AA5, 0x0AA6, 0x0AA9, 0x0AAA
|
||||
|
||||
.section .text, "ax"
|
||||
|
||||
/* Generated by spimdisasm 1.30.0 */
|
||||
|
||||
/* Handwritten function */
|
||||
leaf osSetIntMask
|
||||
/* CA630 800C9A30 400C6000 */ mfc0 $t4, $12 /* handwritten instruction */
|
||||
/* CA634 800C9A34 3182FF01 */ andi $v0, $t4, 0xFF01
|
||||
/* CA638 800C9A38 3C08800E */ lui $t0, %hi(__OSGlobalIntMask)
|
||||
/* CA63C 800C9A3C 250838AC */ addiu $t0, $t0, %lo(__OSGlobalIntMask)
|
||||
/* CA640 800C9A40 8D0B0000 */ lw $t3, 0x0($t0)
|
||||
/* CA644 800C9A44 2401FFFF */ addiu $at, $zero, -0x1
|
||||
/* CA648 800C9A48 01614026 */ xor $t0, $t3, $at
|
||||
/* CA64C 800C9A4C 3108FF00 */ andi $t0, $t0, 0xFF00
|
||||
/* CA650 800C9A50 00481025 */ or $v0, $v0, $t0
|
||||
/* CA654 800C9A54 3C0AA430 */ lui $t2, %hi(MI_INTR_MASK_REG)
|
||||
/* CA658 800C9A58 8D4A000C */ lw $t2, %lo(MI_INTR_MASK_REG)($t2)
|
||||
/* CA65C 800C9A5C 11400005 */ beqz $t2, .L800C9A74
|
||||
/* CA660 800C9A60 000B4C02 */ srl $t1, $t3, 16
|
||||
/* CA664 800C9A64 2401FFFF */ addiu $at, $zero, -0x1
|
||||
/* CA668 800C9A68 01214826 */ xor $t1, $t1, $at
|
||||
/* CA66C 800C9A6C 3129003F */ andi $t1, $t1, 0x3F
|
||||
/* CA670 800C9A70 01495025 */ or $t2, $t2, $t1
|
||||
.L800C9A74:
|
||||
/* CA674 800C9A74 000A5400 */ sll $t2, $t2, 16
|
||||
/* CA678 800C9A78 004A1025 */ or $v0, $v0, $t2
|
||||
/* CA67C 800C9A7C 3C01003F */ lui $at, (0x3F0000 >> 16)
|
||||
/* CA680 800C9A80 00814024 */ and $t0, $a0, $at
|
||||
/* CA684 800C9A84 010B4024 */ and $t0, $t0, $t3
|
||||
/* CA688 800C9A88 000843C2 */ srl $t0, $t0, 15
|
||||
/* CA68C 800C9A8C 3C0A800F */ lui $t2, %hi(__osRcpImTable)
|
||||
/* CA690 800C9A90 01485021 */ addu $t2, $t2, $t0
|
||||
/* CA694 800C9A94 954A94D0 */ lhu $t2, %lo(__osRcpImTable)($t2)
|
||||
/* CA698 800C9A98 3C01A430 */ lui $at, %hi(MI_INTR_MASK_REG)
|
||||
/* CA69C 800C9A9C AC2A000C */ sw $t2, %lo(MI_INTR_MASK_REG)($at)
|
||||
/* CA6A0 800C9AA0 3088FF01 */ andi $t0, $a0, 0xFF01
|
||||
/* CA6A4 800C9AA4 3169FF00 */ andi $t1, $t3, 0xFF00
|
||||
/* CA6A8 800C9AA8 01094024 */ and $t0, $t0, $t1
|
||||
/* CA6AC 800C9AAC 3C01FFFF */ lui $at, (0xFFFF00FF >> 16)
|
||||
/* CA6B0 800C9AB0 342100FF */ ori $at, $at, (0xFFFF00FF & 0xFFFF)
|
||||
/* CA6B4 800C9AB4 01816024 */ and $t4, $t4, $at
|
||||
/* CA6B8 800C9AB8 01886025 */ or $t4, $t4, $t0
|
||||
/* CA6BC 800C9ABC 408C6000 */ mtc0 $t4, $12 /* handwritten instruction */
|
||||
/* CA6C0 800C9AC0 00000000 */ nop
|
||||
/* CA6C4 800C9AC4 00000000 */ nop
|
||||
/* CA6C8 800C9AC8 03E00008 */ jr $ra
|
||||
/* CA6CC 800C9ACC 00000000 */ nop
|
||||
.end osSetIntMask
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
|
||||
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
|
||||
|
||||
+9
-17
@@ -1,18 +1,10 @@
|
||||
.include "macro.inc"
|
||||
#include "PR/R4300.h"
|
||||
#include "sys/asm.h"
|
||||
#include "sys/regdef.h"
|
||||
|
||||
/* assembler directives */
|
||||
.set noat /* allow manual use of $at */
|
||||
.set noreorder /* don't insert nops after branches */
|
||||
.set gp=64 /* allow use of 64-bit general purpose registers */
|
||||
|
||||
.section .text, "ax"
|
||||
|
||||
/* Generated by spimdisasm 1.30.0 */
|
||||
|
||||
/* Handwritten function */
|
||||
leaf __osSetSR
|
||||
mtc0 $a0, $12 /* handwritten instruction */
|
||||
nop
|
||||
jr $ra
|
||||
nop
|
||||
.end __osSetSR
|
||||
.text
|
||||
LEAF(__osSetSR)
|
||||
MTC0( a0, C0_SR)
|
||||
NOP
|
||||
jr ra
|
||||
END(__osSetSR)
|
||||
|
||||
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Reference in New Issue
Block a user