From 1d089fad9f62bacf79318714aa066d1577241b82 Mon Sep 17 00:00:00 2001 From: Ryan Myers Date: Tue, 2 Sep 2025 12:57:23 -0400 Subject: [PATCH] Update libultra asm (#701) * Update func_8008FF1C to a closer match * Update formatting * single reg diff * Generate end labels for all ucodes, rename the boot to rspboot, and have them all get generated together into the same object file, and standardize how they're defined in the headers. * Use glabel, dlabel, and jlabel for different purposes in asm * Working compile with ido for asm files. * Fix other versions bss declaration * Update exceptasm to show other build versions * Fix NON_MATCHING build ld script * Remove a change to libultra that we don't need anymore. * Get it building with GCC, but it doesn't seem to boot... * Slightly cleaned up the GCC builds by still ignoring warnings in libultra, and adding some extra assembly line breaks and flags. --- Makefile | 39 +- include/PR/os_internal.h | 2 +- include/macro.inc | 14 + libultra/src/debug/kdebugserver.c | 96 ++ libultra/src/gu/sqrtf.s | 32 +- libultra/src/libc/bcmp.s | 183 +-- libultra/src/libc/bcopy.s | 442 +++--- libultra/src/libc/bzero.s | 124 +- libultra/src/os/exceptasm.s | 2028 +++++++++++++++++--------- libultra/src/os/getcount.s | 21 +- libultra/src/os/getsr.s | 22 +- libultra/src/os/interrupt.s | 80 +- libultra/src/os/invaldcache.s | 145 +- libultra/src/os/invalicache.s | 90 +- libultra/src/os/maptlbrdb.s | 65 +- libultra/src/os/probetlb.s | 147 +- libultra/src/os/setcompare.s | 24 +- libultra/src/os/setfpccsr.s | 29 +- libultra/src/os/setintmask.s | 220 ++- libultra/src/os/setsr.s | 26 +- libultra/src/os/writebackdcache.s | 97 +- libultra/src/os/writebackdcacheall.s | 41 +- mods/dkr.custom.ld | 20 +- src/audiomgr.c | 4 +- src/hasm/collision.s | 10 +- src/hasm/entrypoint.s | 2 +- src/hasm/gzip_asm.s | 12 +- src/hasm/llmuldiv_gcc.s | 4 +- src/hasm/math_util.s | 10 +- src/menu.c | 193 ++- src/rcp_dkr.c | 16 +- src/rcp_dkr.h | 12 +- tools/m2c | 2 +- ver/splat/dkr.jpn.v79.yaml | 26 +- ver/splat/dkr.pal.v77.yaml | 26 +- ver/splat/dkr.pal.v80.yaml | 26 +- ver/splat/dkr.us.v77.yaml | 26 +- ver/splat/dkr.us.v80.yaml | 26 +- ver/symbols/symbol_addrs.jpn.v79.txt | 22 +- ver/symbols/symbol_addrs.pal.v77.txt | 22 +- ver/symbols/symbol_addrs.pal.v80.txt | 22 +- ver/symbols/symbol_addrs.us.v77.txt | 22 +- ver/symbols/symbol_addrs.us.v80.txt | 22 +- 43 files changed, 2725 insertions(+), 1767 deletions(-) create mode 100644 libultra/src/debug/kdebugserver.c diff --git a/Makefile b/Makefile index 6d02a75a..20b01527 100755 --- a/Makefile +++ b/Makefile @@ -12,10 +12,14 @@ endif COMPILER ?= ido $(eval $(call validate-option,NON_MATCHING,ido gcc)) +ifneq ($(COMPILER),ido) + NON_MATCHING := 1 +endif + # Define a custom boot file if desired to use something other than the vanilla one BOOT_CUSTOM ?= mods/boot_custom.bin -LIBULTRA_VERSION_DEFINE := -DBUILD_VERSION=4 -DBUILD_VERSION_STRING=\"2.0G\" +LIBULTRA_VERSION_DEFINE := -DBUILD_VERSION=VERSION_G -DBUILD_VERSION_STRING=\"2.0G\" # Whether to hide commands or not VERBOSE ?= 0 @@ -121,6 +125,7 @@ endif AS = $(CROSS)as LD = $(CROSS)ld OBJCOPY = $(CROSS)objcopy +STRIP = $(CROSS)strip VENV = .venv PYTHON = $(VENV)/bin/python3 GCC = gcc @@ -264,15 +269,21 @@ $(BUILD_DIR)/$(LIBULTRA_DIR)/src/sc/sched.c.o: MIPSISET := -mips1 $(BUILD_DIR)/$(LIBULTRA_DIR)/src/io/motor.c.o: MIPSISET := -mips1 $(BUILD_DIR)/$(LIBULTRA_DIR)/src/audio/env.c.o: MIPSISET := -mips1 -#Ignore warnings for libultra files -$(BUILD_DIR)/$(LIBULTRA_DIR)/%.c.o: CC_WARNINGS := -w -$(BUILD_DIR)/$(LIBULTRA_DIR)/%.c.o: CC_CHECK := : +# ASM files more often than not need to be compiled with -mips2 -O1, but there are exceptions. +$(BUILD_DIR)/$(LIBULTRA_DIR)/%.s.o: OPT_FLAGS := -O1 +$(BUILD_DIR)/$(LIBULTRA_DIR)/%.s.o: MIPSISET := -mips2 +$(BUILD_DIR)/$(LIBULTRA_DIR)/src/libc/%.s.o: OPT_FLAGS := -O2 +$(BUILD_DIR)/$(LIBULTRA_DIR)/src/os/exceptasm.s.o: MIPSISET := -mips3 -32 # Allow dollar sign to be used in var names for this file alone # It allows us to return the current stack pointer $(BUILD_DIR)/$(SRC_DIR)/get_stack_pointer.c.o: OPT_FLAGS += -dollar endif +#Ignore warnings for libultra files +$(BUILD_DIR)/$(LIBULTRA_DIR)/%.c.o: CC_WARNINGS := -w +$(BUILD_DIR)/$(LIBULTRA_DIR)/%.c.o: CC_CHECK := : + ### Targets ifeq ($(COMPILER),gcc) @@ -444,6 +455,26 @@ $(BUILD_DIR)/%.s.o: %.s | build_assets $(call print,Assembling:,$<,$@) $(V)$(AS) $(ASFLAGS) -MD $(BUILD_DIR)/$*.d -o $@ $< +ifeq ($(COMPILER),ido) +# libultra asm files - Compile with the ido compiler +$(BUILD_DIR)/$(LIBULTRA_DIR)/%.s.o: $(LIBULTRA_DIR)/%.s | build_assets + $(call print,Assembling Libultra:,$<,$@) + $(V)$(CC) -c $(CFLAGS) $(CC_WARNINGS) $(OPT_FLAGS) $(MIPSISET) -o $@ $< + $(V)$(STRIP) --strip-unneeded $@ + @if [ "$(MIPSISET)" = "-mips3 -32" ]; then \ + $(PYTHON) $(TOOLS_DIR)/python/patchmips3.py $@ || rm $@; \ + fi +else +# libultra asm files - Compile with the gcc c compiler +$(BUILD_DIR)/$(LIBULTRA_DIR)/%.s.o: $(LIBULTRA_DIR)/%.s | build_assets + $(call print,Assembling Libultra:,$<,$@) + $(V)$(CROSS)gcc -x assembler-with-cpp \ + -w -nostdinc -c -G 0 -march=vr4300 -mgp32 -mfp32 -mno-abicalls \ + -DMIPSEB -D_LANGUAGE_ASSEMBLY -D_MIPS_SIM=1 -D_ULTRA64 -DMODERN_CC -D__USE_ISOC99 \ + -mips3 -Os -ggdb3 -ffast-math -fno-unsafe-math-optimizations -c $(C_DEFINES) $(INCLUDE_CFLAGS) \ + -o $@ $< +endif + # Specifically override the header file from what splat extracted to be replaced by what we have in the hasm folder $(BUILD_DIR)/asm/header.s.o: src/hasm/header.s | build_assets $(call print,Assembling Header:,$<,$@) diff --git a/include/PR/os_internal.h b/include/PR/os_internal.h index 8da78b79..754d1ee2 100644 --- a/include/PR/os_internal.h +++ b/include/PR/os_internal.h @@ -30,7 +30,7 @@ extern "C" { #if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) #include "os_internal_reg.h" -// #include "os_internal_exception.h" //TODO: Why does this include break things? +#include "os_internal_exception.h" #include "os_internal_tlb.h" #include "os_internal_si.h" #include "os_internal_rsp.h" diff --git a/include/macro.inc b/include/macro.inc index 798dba02..0b283ffd 100644 --- a/include/macro.inc +++ b/include/macro.inc @@ -7,6 +7,18 @@ .set K2BASE, 0xC0000000 .macro glabel label + .global \label + .type \label, @function + \label: +.endm + +.macro dlabel label + .global \label + .type \label, @object + \label: +.endm + +.macro jlabel label .global \label \label: .endm @@ -26,6 +38,7 @@ .macro leaf label .global \label + .type \label, @function \label: .ent \label .endm @@ -33,6 +46,7 @@ # Used for alternative entries for Sin functions .macro altleaf label .global \label + .type \label, @function \label: .aent \label .endm diff --git a/libultra/src/debug/kdebugserver.c b/libultra/src/debug/kdebugserver.c new file mode 100644 index 00000000..948a4603 --- /dev/null +++ b/libultra/src/debug/kdebugserver.c @@ -0,0 +1,96 @@ +#include "PR/os_internal.h" +#include "PR/rcp.h" +#include "PR/rdb.h" + +// not included in final rom, but __osThreadSave is here for some reason +OSThread __osThreadSave; + +extern OSThread *__osRunningThread; +extern u32 __osRdb_IP6_Empty; + +#ifndef _FINALROM + +static u8 buffer[12]; +static u32 numChars = 0; + +static u32 string_to_u32(u8* s) { + u32 k; + + k = ((s[0] & 0xFF) << 0x18); + k |= ((s[1] & 0xFF) << 0x10); + k |= ((s[2] & 0xFF) << 0x8); + k |= (s[3] & 0xFF); + + return k; +} + +static void send_packet(u8* s, u32 n) { + rdbPacket packet; + u32 i; + + packet.type = 0xC; + packet.length = n; + + for (i = 0; i < n; i++) { + packet.buf[i] = s[i]; + } + *(vu32*)RDB_BASE_REG = *(u32*)&packet; +} + +static void clear_IP6(void) { + while (!(__osGetCause() & CAUSE_IP6)) { + ; + } + *(vu32*)RDB_READ_INTR_REG = 0; + + while (__osGetCause() & CAUSE_IP6) { + ; + } +} + +static void send(u8* s, u32 n) { + u32 ct; + u32 i = 0; + u32 getLastIP6; + + if (!__osRdb_IP6_Empty) { + clear_IP6(); + getLastIP6 = FALSE; + } else { + getLastIP6 = TRUE; + } + while (n != 0) { + ct = (n < 3) ? n : 3; + send_packet(s + i, ct); + n -= ct; + i += ct; + if (n != 0) { + clear_IP6(); + } + } + if (getLastIP6) { + clear_IP6(); + } +} + +void kdebugserver(rdbPacket packet) { + u32 i; + u32 length; + u8* addr; + + for (i = 0; i < 3; i++) { + buffer[numChars++] = packet.buf[i]; + } + + if (buffer[0] == 2) { + send((char*)&__osRunningThread->context, sizeof(__OSThreadContext)); + numChars = 0; + } else if (numChars >= 9 && buffer[0] == 1) { + addr = string_to_u32(&buffer[1]); + length = string_to_u32(&buffer[5]); + send(addr, length); + numChars = 0; + } +} + +#endif diff --git a/libultra/src/gu/sqrtf.s b/libultra/src/gu/sqrtf.s index c62b606f..475a827a 100644 --- a/libultra/src/gu/sqrtf.s +++ b/libultra/src/gu/sqrtf.s @@ -1,13 +1,25 @@ -.include "macro.inc" +/************************************************************************** + * * + * Copyright (C) 1994, Silicon Graphics, Inc. * + * * + * These coded instructions, statements, and computer programs contain * + * unpublished proprietary information of Silicon Graphics, Inc., and * + * are protected by Federal copyright law. They may not be disclosed * + * to third parties or copied or duplicated in any form, in whole or * + * in part, without the prior written consent of Silicon Graphics, Inc. * + * * + **************************************************************************/ -/* assembler directives */ -.set noat /* allow manual use of $at */ -.set noreorder /* don't insert nops after branches */ -.set gp=64 /* allow use of 64-bit general purpose registers */ +/* + * Due to compiler bug, it won't insert a sqrt.s opcode in the stream so we + * make a function and call it for now. When compiler fixed, also remove the + * seperate Makefile rules + */ -.section .text, "ax" +#include "sys/asm.h" +#include "sys/regdef.h" -leaf sqrtf -jr $ra -sqrt.s $f0, $f12 -.end sqrtf +LEAF(sqrtf) + sqrt.s fv0, fa0 + j ra +END(sqrtf) diff --git a/libultra/src/libc/bcmp.s b/libultra/src/libc/bcmp.s index 8a522337..def32355 100644 --- a/libultra/src/libc/bcmp.s +++ b/libultra/src/libc/bcmp.s @@ -1,95 +1,96 @@ -.include "macro.inc" +#include "PR/R4300.h" +#include "sys/asm.h" +#include "sys/regdef.h" -/* assembler directives */ -.set noat /* allow manual use of $at */ -.set noreorder /* don't insert nops after branches */ -.set gp=64 /* allow use of 64-bit general purpose registers */ +.text +#ifdef __sgi +WEAK(bcmp, _bcmp) +#else +#define _bcmp bcmp +#endif +LEAF(_bcmp) + xor v0, a0, a1 + blt a2, 16, bytecmp -.section .text, "ax" + andi v0, v0, 0x3 + negu t8, a0 + bnez v0, unalgncmp -/* Generated by spimdisasm 1.30.0 */ + andi t8, t8, 0x3 + subu a2, a2, t8 + beqz t8, wordcmp + + move v0, v1 + lwl v0, 0(a0) + lwl v1, 0(a1) + addu a0, a0, t8 + addu a1, a1, t8 + bne v0, v1, cmpne -leaf bcmp -/* CEC50 800CE050 28C10010 */ slti $at, $a2, 0x10 -/* CEC54 800CE054 14200037 */ bnez $at, .L800CE134 -/* CEC58 800CE058 00851026 */ xor $v0, $a0, $a1 -/* CEC5C 800CE05C 30420003 */ andi $v0, $v0, 0x3 -/* CEC60 800CE060 14400019 */ bnez $v0, .L800CE0C8 -/* CEC64 800CE064 0004C023 */ negu $t8, $a0 -/* CEC68 800CE068 33180003 */ andi $t8, $t8, 0x3 -/* CEC6C 800CE06C 13000007 */ beqz $t8, .L800CE08C -/* CEC70 800CE070 00D83023 */ subu $a2, $a2, $t8 -/* CEC74 800CE074 00601025 */ or $v0, $v1, $zero -/* CEC78 800CE078 88820000 */ lwl $v0, 0x0($a0) -/* CEC7C 800CE07C 88A30000 */ lwl $v1, 0x0($a1) -/* CEC80 800CE080 00982021 */ addu $a0, $a0, $t8 -/* CEC84 800CE084 00B82821 */ addu $a1, $a1, $t8 -/* CEC88 800CE088 14430036 */ bne $v0, $v1, .L800CE164 -.L800CE08C: -/* CEC8C 800CE08C 2401FFFC */ addiu $at, $zero, -0x4 -/* CEC90 800CE090 00C13824 */ and $a3, $a2, $at -/* CEC94 800CE094 10E00027 */ beqz $a3, .L800CE134 -/* CEC98 800CE098 00C73023 */ subu $a2, $a2, $a3 -/* CEC9C 800CE09C 00E43821 */ addu $a3, $a3, $a0 -/* CECA0 800CE0A0 8C820000 */ lw $v0, 0x0($a0) -.L800CE0A4: -/* CECA4 800CE0A4 8CA30000 */ lw $v1, 0x0($a1) -/* CECA8 800CE0A8 24840004 */ addiu $a0, $a0, 0x4 -/* CECAC 800CE0AC 24A50004 */ addiu $a1, $a1, 0x4 -/* CECB0 800CE0B0 1443002C */ bne $v0, $v1, .L800CE164 -/* CECB4 800CE0B4 00000000 */ nop -/* CECB8 800CE0B8 5487FFFA */ bnel $a0, $a3, .L800CE0A4 -/* CECBC 800CE0BC 8C820000 */ lw $v0, 0x0($a0) -/* CECC0 800CE0C0 1000001C */ b .L800CE134 -/* CECC4 800CE0C4 00000000 */ nop -.L800CE0C8: -/* CECC8 800CE0C8 00053823 */ negu $a3, $a1 -/* CECCC 800CE0CC 30E70003 */ andi $a3, $a3, 0x3 -/* CECD0 800CE0D0 10E0000A */ beqz $a3, .L800CE0FC -/* CECD4 800CE0D4 00C73023 */ subu $a2, $a2, $a3 -/* CECD8 800CE0D8 00E43821 */ addu $a3, $a3, $a0 -/* CECDC 800CE0DC 90820000 */ lbu $v0, 0x0($a0) -.L800CE0E0: -/* CECE0 800CE0E0 90A30000 */ lbu $v1, 0x0($a1) -/* CECE4 800CE0E4 24840001 */ addiu $a0, $a0, 0x1 -/* CECE8 800CE0E8 24A50001 */ addiu $a1, $a1, 0x1 -/* CECEC 800CE0EC 1443001D */ bne $v0, $v1, .L800CE164 -/* CECF0 800CE0F0 00000000 */ nop -/* CECF4 800CE0F4 5487FFFA */ bnel $a0, $a3, .L800CE0E0 -/* CECF8 800CE0F8 90820000 */ lbu $v0, 0x0($a0) -.L800CE0FC: -/* CECFC 800CE0FC 2401FFFC */ addiu $at, $zero, -0x4 -/* CED00 800CE100 00C13824 */ and $a3, $a2, $at -/* CED04 800CE104 10E0000B */ beqz $a3, .L800CE134 -/* CED08 800CE108 00C73023 */ subu $a2, $a2, $a3 -/* CED0C 800CE10C 00E43821 */ addu $a3, $a3, $a0 -/* CED10 800CE110 88820000 */ lwl $v0, 0x0($a0) -.L800CE114: -/* CED14 800CE114 8CA30000 */ lw $v1, 0x0($a1) -/* CED18 800CE118 98820003 */ lwr $v0, 0x3($a0) -/* CED1C 800CE11C 24840004 */ addiu $a0, $a0, 0x4 -/* CED20 800CE120 24A50004 */ addiu $a1, $a1, 0x4 -/* CED24 800CE124 1443000F */ bne $v0, $v1, .L800CE164 -/* CED28 800CE128 00000000 */ nop -/* CED2C 800CE12C 5487FFF9 */ bnel $a0, $a3, .L800CE114 -/* CED30 800CE130 88820000 */ lwl $v0, 0x0($a0) -.L800CE134: -/* CED34 800CE134 18C00009 */ blez $a2, .L800CE15C -/* CED38 800CE138 00C43821 */ addu $a3, $a2, $a0 -/* CED3C 800CE13C 90820000 */ lbu $v0, 0x0($a0) -.L800CE140: -/* CED40 800CE140 90A30000 */ lbu $v1, 0x0($a1) -/* CED44 800CE144 24840001 */ addiu $a0, $a0, 0x1 -/* CED48 800CE148 24A50001 */ addiu $a1, $a1, 0x1 -/* CED4C 800CE14C 14430005 */ bne $v0, $v1, .L800CE164 -/* CED50 800CE150 00000000 */ nop -/* CED54 800CE154 5487FFFA */ bnel $a0, $a3, .L800CE140 -/* CED58 800CE158 90820000 */ lbu $v0, 0x0($a0) -.L800CE15C: -/* CED5C 800CE15C 03E00008 */ jr $ra -/* CED60 800CE160 00001025 */ or $v0, $zero, $zero -.L800CE164: -/* CED64 800CE164 03E00008 */ jr $ra -/* CED68 800CE168 24020001 */ addiu $v0, $zero, 0x1 -/* CED6C 800CE16C 00000000 */ nop -.end bcmp +wordcmp: + and a3, a2, ~3 + subu a2, a2, a3 + beqz a3, bytecmp + + addu a3, a3, a0 +1: + lw v0, 0(a0) + lw v1, 0(a1) + addiu a0, a0, 4 + addiu a1, a1, 4 + bne v0, v1, cmpne + bne a0, a3, 1b + + b bytecmp +unalgncmp: + negu a3, a1 + andi a3, a3, 0x3 + subu a2, a2, a3 + beqz a3, partaligncmp + + addu a3, a3, a0 + +1: + lbu v0, 0(a0) + lbu v1, 0(a1) + addiu a0, a0, 1 + addiu a1, a1, 1 + bne v0, v1, cmpne + bne a0, a3, 1b + +partaligncmp: + and a3, a2, ~3 + subu a2, a2, a3 + beqz a3, bytecmp + + addu a3, a3, a0 + +1: + lwl v0, 0(a0) + lwr v0, 3(a0) + lw v1, 0(a1) + addiu a0, a0, 4 + addiu a1, a1, 4 + bne v0, v1, cmpne + bne a0, a3, 1b + +bytecmp: + addu a3, a2, a0 + blez a2, cmpdone + +1: + lbu v0, 0(a0) + lbu v1, 0(a1) + addiu a0, a0, 1 + addiu a1, a1, 1 + bne v0, v1, cmpne + bne a0, a3, 1b + +cmpdone: + move v0, zero + jr ra +cmpne: + li v0, 1 + jr ra + +.end _bcmp diff --git a/libultra/src/libc/bcopy.s b/libultra/src/libc/bcopy.s index d58980dd..08757413 100644 --- a/libultra/src/libc/bcopy.s +++ b/libultra/src/libc/bcopy.s @@ -1,230 +1,220 @@ -.include "macro.inc" +#include "PR/R4300.h" +#include "sys/asm.h" +#include "sys/regdef.h" -/* assembler directives */ -.set noat /* allow manual use of $at */ -.set noreorder /* don't insert nops after branches */ -.set gp=64 /* allow use of 64-bit general purpose registers */ +.text +#ifdef __sgi +WEAK(bcopy, _bcopy) +#else +#define _bcopy bcopy +#endif +LEAF(_bcopy) + move a3, a1 + beqz a2, ret + beq a0, a1, ret + blt a1, a0, goforwards + + add v0, a0, a2 + bge a1, v0, goforwards + b gobackwards -.section .text, "ax" +goforwards: -/* Generated by spimdisasm 1.30.0 */ + blt a2, 16, forwards_bytecopy + + andi v0, a0, 0x3 + andi v1, a1, 0x3 + beq v0, v1, forwalignable + -/* Handwritten function */ -leaf bcopy -/* CA9A0 800C9DA0 10C0001A */ beqz $a2, .L800C9E0C -/* CA9A4 800C9DA4 00A03825 */ or $a3, $a1, $zero -/* CA9A8 800C9DA8 10850018 */ beq $a0, $a1, .L800C9E0C -/* CA9AC 800C9DAC 00A4082A */ slt $at, $a1, $a0 -/* CA9B0 800C9DB0 54200008 */ bnel $at, $zero, .L800C9DD4 -/* CA9B4 800C9DB4 28C10010 */ slti $at, $a2, 0x10 -/* CA9B8 800C9DB8 00861020 */ add $v0, $a0, $a2 /* handwritten instruction */ -/* CA9BC 800C9DBC 00A2082A */ slt $at, $a1, $v0 -/* CA9C0 800C9DC0 50200004 */ beql $at, $zero, .L800C9DD4 -/* CA9C4 800C9DC4 28C10010 */ slti $at, $a2, 0x10 -/* CA9C8 800C9DC8 1000005B */ b .L800C9F38 -/* CA9CC 800C9DCC 28C10010 */ slti $at, $a2, 0x10 -/* CA9D0 800C9DD0 28C10010 */ slti $at, $a2, 0x10 -.L800C9DD4: -/* CA9D4 800C9DD4 14200005 */ bnez $at, .L800C9DEC -/* CA9D8 800C9DD8 00000000 */ nop -/* CA9DC 800C9DDC 30820003 */ andi $v0, $a0, 0x3 -/* CA9E0 800C9DE0 30A30003 */ andi $v1, $a1, 0x3 -/* CA9E4 800C9DE4 1043000B */ beq $v0, $v1, .L800C9E14 -/* CA9E8 800C9DE8 00000000 */ nop -.L800C9DEC: -/* CA9EC 800C9DEC 10C00007 */ beqz $a2, .L800C9E0C -/* CA9F0 800C9DF0 00000000 */ nop -/* CA9F4 800C9DF4 00861821 */ addu $v1, $a0, $a2 -.L800C9DF8: -/* CA9F8 800C9DF8 80820000 */ lb $v0, 0x0($a0) -/* CA9FC 800C9DFC 24840001 */ addiu $a0, $a0, 0x1 -/* CAA00 800C9E00 24A50001 */ addiu $a1, $a1, 0x1 -/* CAA04 800C9E04 1483FFFC */ bne $a0, $v1, .L800C9DF8 -/* CAA08 800C9E08 A0A2FFFF */ sb $v0, -0x1($a1) -.L800C9E0C: -/* CAA0C 800C9E0C 03E00008 */ jr $ra -/* CAA10 800C9E10 00E01025 */ or $v0, $a3, $zero -.L800C9E14: -/* CAA14 800C9E14 10400018 */ beqz $v0, .L800C9E78 -/* CAA18 800C9E18 24010001 */ addiu $at, $zero, 0x1 -/* CAA1C 800C9E1C 1041000F */ beq $v0, $at, .L800C9E5C -/* CAA20 800C9E20 24010002 */ addiu $at, $zero, 0x2 -/* CAA24 800C9E24 50410008 */ beql $v0, $at, .L800C9E48 -/* CAA28 800C9E28 84820000 */ lh $v0, 0x0($a0) -/* CAA2C 800C9E2C 80820000 */ lb $v0, 0x0($a0) -/* CAA30 800C9E30 24840001 */ addiu $a0, $a0, 0x1 -/* CAA34 800C9E34 24A50001 */ addiu $a1, $a1, 0x1 -/* CAA38 800C9E38 24C6FFFF */ addiu $a2, $a2, -0x1 -/* CAA3C 800C9E3C 1000000E */ b .L800C9E78 -/* CAA40 800C9E40 A0A2FFFF */ sb $v0, -0x1($a1) -/* CAA44 800C9E44 84820000 */ lh $v0, 0x0($a0) -.L800C9E48: -/* CAA48 800C9E48 24840002 */ addiu $a0, $a0, 0x2 -/* CAA4C 800C9E4C 24A50002 */ addiu $a1, $a1, 0x2 -/* CAA50 800C9E50 24C6FFFE */ addiu $a2, $a2, -0x2 -/* CAA54 800C9E54 10000008 */ b .L800C9E78 -/* CAA58 800C9E58 A4A2FFFE */ sh $v0, -0x2($a1) -.L800C9E5C: -/* CAA5C 800C9E5C 80820000 */ lb $v0, 0x0($a0) -/* CAA60 800C9E60 84830001 */ lh $v1, 0x1($a0) -/* CAA64 800C9E64 24840003 */ addiu $a0, $a0, 0x3 -/* CAA68 800C9E68 24A50003 */ addiu $a1, $a1, 0x3 -/* CAA6C 800C9E6C 24C6FFFD */ addiu $a2, $a2, -0x3 -/* CAA70 800C9E70 A0A2FFFD */ sb $v0, -0x3($a1) -/* CAA74 800C9E74 A4A3FFFE */ sh $v1, -0x2($a1) -.L800C9E78: -/* CAA78 800C9E78 28C10020 */ slti $at, $a2, 0x20 -/* CAA7C 800C9E7C 54200016 */ bnel $at, $zero, .L800C9ED8 -/* CAA80 800C9E80 28C10010 */ slti $at, $a2, 0x10 -/* CAA84 800C9E84 8C820000 */ lw $v0, 0x0($a0) -/* CAA88 800C9E88 8C830004 */ lw $v1, 0x4($a0) -/* CAA8C 800C9E8C 8C880008 */ lw $t0, 0x8($a0) -/* CAA90 800C9E90 8C89000C */ lw $t1, 0xC($a0) -/* CAA94 800C9E94 8C8A0010 */ lw $t2, 0x10($a0) -/* CAA98 800C9E98 8C8B0014 */ lw $t3, 0x14($a0) -/* CAA9C 800C9E9C 8C8C0018 */ lw $t4, 0x18($a0) -/* CAAA0 800C9EA0 8C8D001C */ lw $t5, 0x1C($a0) -/* CAAA4 800C9EA4 24840020 */ addiu $a0, $a0, 0x20 -/* CAAA8 800C9EA8 24A50020 */ addiu $a1, $a1, 0x20 -/* CAAAC 800C9EAC 24C6FFE0 */ addiu $a2, $a2, -0x20 -/* CAAB0 800C9EB0 ACA2FFE0 */ sw $v0, -0x20($a1) -/* CAAB4 800C9EB4 ACA3FFE4 */ sw $v1, -0x1C($a1) -/* CAAB8 800C9EB8 ACA8FFE8 */ sw $t0, -0x18($a1) -/* CAABC 800C9EBC ACA9FFEC */ sw $t1, -0x14($a1) -/* CAAC0 800C9EC0 ACAAFFF0 */ sw $t2, -0x10($a1) -/* CAAC4 800C9EC4 ACABFFF4 */ sw $t3, -0xC($a1) -/* CAAC8 800C9EC8 ACACFFF8 */ sw $t4, -0x8($a1) -/* CAACC 800C9ECC 1000FFEA */ b .L800C9E78 -/* CAAD0 800C9ED0 ACADFFFC */ sw $t5, -0x4($a1) -.L800C9ED4: -/* CAAD4 800C9ED4 28C10010 */ slti $at, $a2, 0x10 -.L800C9ED8: -/* CAAD8 800C9ED8 5420000E */ bnel $at, $zero, .L800C9F14 -/* CAADC 800C9EDC 28C10004 */ slti $at, $a2, 0x4 -/* CAAE0 800C9EE0 8C820000 */ lw $v0, 0x0($a0) -/* CAAE4 800C9EE4 8C830004 */ lw $v1, 0x4($a0) -/* CAAE8 800C9EE8 8C880008 */ lw $t0, 0x8($a0) -/* CAAEC 800C9EEC 8C89000C */ lw $t1, 0xC($a0) -/* CAAF0 800C9EF0 24840010 */ addiu $a0, $a0, 0x10 -/* CAAF4 800C9EF4 24A50010 */ addiu $a1, $a1, 0x10 -/* CAAF8 800C9EF8 24C6FFF0 */ addiu $a2, $a2, -0x10 -/* CAAFC 800C9EFC ACA2FFF0 */ sw $v0, -0x10($a1) -/* CAB00 800C9F00 ACA3FFF4 */ sw $v1, -0xC($a1) -/* CAB04 800C9F04 ACA8FFF8 */ sw $t0, -0x8($a1) -/* CAB08 800C9F08 1000FFF2 */ b .L800C9ED4 -/* CAB0C 800C9F0C ACA9FFFC */ sw $t1, -0x4($a1) -.L800C9F10: -/* CAB10 800C9F10 28C10004 */ slti $at, $a2, 0x4 -.L800C9F14: -/* CAB14 800C9F14 1420FFB5 */ bnez $at, .L800C9DEC -/* CAB18 800C9F18 00000000 */ nop -/* CAB1C 800C9F1C 8C820000 */ lw $v0, 0x0($a0) -/* CAB20 800C9F20 24840004 */ addiu $a0, $a0, 0x4 -/* CAB24 800C9F24 24A50004 */ addiu $a1, $a1, 0x4 -/* CAB28 800C9F28 24C6FFFC */ addiu $a2, $a2, -0x4 -/* CAB2C 800C9F2C 1000FFF8 */ b .L800C9F10 -/* CAB30 800C9F30 ACA2FFFC */ sw $v0, -0x4($a1) -/* CAB34 800C9F34 28C10010 */ slti $at, $a2, 0x10 -.L800C9F38: -/* CAB38 800C9F38 00862020 */ add $a0, $a0, $a2 /* handwritten instruction */ -/* CAB3C 800C9F3C 14200005 */ bnez $at, .L800C9F54 -/* CAB40 800C9F40 00A62820 */ add $a1, $a1, $a2 /* handwritten instruction */ -/* CAB44 800C9F44 30820003 */ andi $v0, $a0, 0x3 -/* CAB48 800C9F48 30A30003 */ andi $v1, $a1, 0x3 -/* CAB4C 800C9F4C 1043000D */ beq $v0, $v1, .L800C9F84 -/* CAB50 800C9F50 00000000 */ nop -.L800C9F54: -/* CAB54 800C9F54 10C0FFAD */ beqz $a2, .L800C9E0C -/* CAB58 800C9F58 00000000 */ nop -/* CAB5C 800C9F5C 2484FFFF */ addiu $a0, $a0, -0x1 -/* CAB60 800C9F60 24A5FFFF */ addiu $a1, $a1, -0x1 -/* CAB64 800C9F64 00861823 */ subu $v1, $a0, $a2 -.L800C9F68: -/* CAB68 800C9F68 80820000 */ lb $v0, 0x0($a0) -/* CAB6C 800C9F6C 2484FFFF */ addiu $a0, $a0, -0x1 -/* CAB70 800C9F70 24A5FFFF */ addiu $a1, $a1, -0x1 -/* CAB74 800C9F74 1483FFFC */ bne $a0, $v1, .L800C9F68 -/* CAB78 800C9F78 A0A20001 */ sb $v0, 0x1($a1) -/* CAB7C 800C9F7C 03E00008 */ jr $ra -/* CAB80 800C9F80 00E01025 */ or $v0, $a3, $zero -.L800C9F84: -/* CAB84 800C9F84 10400018 */ beqz $v0, .L800C9FE8 -/* CAB88 800C9F88 24010003 */ addiu $at, $zero, 0x3 -/* CAB8C 800C9F8C 1041000F */ beq $v0, $at, .L800C9FCC -/* CAB90 800C9F90 24010002 */ addiu $at, $zero, 0x2 -/* CAB94 800C9F94 50410008 */ beql $v0, $at, .L800C9FB8 -/* CAB98 800C9F98 8482FFFE */ lh $v0, -0x2($a0) -/* CAB9C 800C9F9C 8082FFFF */ lb $v0, -0x1($a0) -/* CABA0 800C9FA0 2484FFFF */ addiu $a0, $a0, -0x1 -/* CABA4 800C9FA4 24A5FFFF */ addiu $a1, $a1, -0x1 -/* CABA8 800C9FA8 24C6FFFF */ addiu $a2, $a2, -0x1 -/* CABAC 800C9FAC 1000000E */ b .L800C9FE8 -/* CABB0 800C9FB0 A0A20000 */ sb $v0, 0x0($a1) -/* CABB4 800C9FB4 8482FFFE */ lh $v0, -0x2($a0) -.L800C9FB8: -/* CABB8 800C9FB8 2484FFFE */ addiu $a0, $a0, -0x2 -/* CABBC 800C9FBC 24A5FFFE */ addiu $a1, $a1, -0x2 -/* CABC0 800C9FC0 24C6FFFE */ addiu $a2, $a2, -0x2 -/* CABC4 800C9FC4 10000008 */ b .L800C9FE8 -/* CABC8 800C9FC8 A4A20000 */ sh $v0, 0x0($a1) -.L800C9FCC: -/* CABCC 800C9FCC 8082FFFF */ lb $v0, -0x1($a0) -/* CABD0 800C9FD0 8483FFFD */ lh $v1, -0x3($a0) -/* CABD4 800C9FD4 2484FFFD */ addiu $a0, $a0, -0x3 -/* CABD8 800C9FD8 24A5FFFD */ addiu $a1, $a1, -0x3 -/* CABDC 800C9FDC 24C6FFFD */ addiu $a2, $a2, -0x3 -/* CABE0 800C9FE0 A0A20002 */ sb $v0, 0x2($a1) -/* CABE4 800C9FE4 A4A30000 */ sh $v1, 0x0($a1) -.L800C9FE8: -/* CABE8 800C9FE8 28C10020 */ slti $at, $a2, 0x20 -/* CABEC 800C9FEC 54200016 */ bnel $at, $zero, .L800CA048 -/* CABF0 800C9FF0 28C10010 */ slti $at, $a2, 0x10 -/* CABF4 800C9FF4 8C82FFFC */ lw $v0, -0x4($a0) -/* CABF8 800C9FF8 8C83FFF8 */ lw $v1, -0x8($a0) -/* CABFC 800C9FFC 8C88FFF4 */ lw $t0, -0xC($a0) -/* CAC00 800CA000 8C89FFF0 */ lw $t1, -0x10($a0) -/* CAC04 800CA004 8C8AFFEC */ lw $t2, -0x14($a0) -/* CAC08 800CA008 8C8BFFE8 */ lw $t3, -0x18($a0) -/* CAC0C 800CA00C 8C8CFFE4 */ lw $t4, -0x1C($a0) -/* CAC10 800CA010 8C8DFFE0 */ lw $t5, -0x20($a0) -/* CAC14 800CA014 2484FFE0 */ addiu $a0, $a0, -0x20 -/* CAC18 800CA018 24A5FFE0 */ addiu $a1, $a1, -0x20 -/* CAC1C 800CA01C 24C6FFE0 */ addiu $a2, $a2, -0x20 -/* CAC20 800CA020 ACA2001C */ sw $v0, 0x1C($a1) -/* CAC24 800CA024 ACA30018 */ sw $v1, 0x18($a1) -/* CAC28 800CA028 ACA80014 */ sw $t0, 0x14($a1) -/* CAC2C 800CA02C ACA90010 */ sw $t1, 0x10($a1) -/* CAC30 800CA030 ACAA000C */ sw $t2, 0xC($a1) -/* CAC34 800CA034 ACAB0008 */ sw $t3, 0x8($a1) -/* CAC38 800CA038 ACAC0004 */ sw $t4, 0x4($a1) -/* CAC3C 800CA03C 1000FFEA */ b .L800C9FE8 -/* CAC40 800CA040 ACAD0000 */ sw $t5, 0x0($a1) -.L800CA044: -/* CAC44 800CA044 28C10010 */ slti $at, $a2, 0x10 -.L800CA048: -/* CAC48 800CA048 5420000E */ bnel $at, $zero, .L800CA084 -/* CAC4C 800CA04C 28C10004 */ slti $at, $a2, 0x4 -/* CAC50 800CA050 8C82FFFC */ lw $v0, -0x4($a0) -/* CAC54 800CA054 8C83FFF8 */ lw $v1, -0x8($a0) -/* CAC58 800CA058 8C88FFF4 */ lw $t0, -0xC($a0) -/* CAC5C 800CA05C 8C89FFF0 */ lw $t1, -0x10($a0) -/* CAC60 800CA060 2484FFF0 */ addiu $a0, $a0, -0x10 -/* CAC64 800CA064 24A5FFF0 */ addiu $a1, $a1, -0x10 -/* CAC68 800CA068 24C6FFF0 */ addiu $a2, $a2, -0x10 -/* CAC6C 800CA06C ACA2000C */ sw $v0, 0xC($a1) -/* CAC70 800CA070 ACA30008 */ sw $v1, 0x8($a1) -/* CAC74 800CA074 ACA80004 */ sw $t0, 0x4($a1) -/* CAC78 800CA078 1000FFF2 */ b .L800CA044 -/* CAC7C 800CA07C ACA90000 */ sw $t1, 0x0($a1) -.L800CA080: -/* CAC80 800CA080 28C10004 */ slti $at, $a2, 0x4 -.L800CA084: -/* CAC84 800CA084 1420FFB3 */ bnez $at, .L800C9F54 -/* CAC88 800CA088 00000000 */ nop -/* CAC8C 800CA08C 8C82FFFC */ lw $v0, -0x4($a0) -/* CAC90 800CA090 2484FFFC */ addiu $a0, $a0, -0x4 -/* CAC94 800CA094 24A5FFFC */ addiu $a1, $a1, -0x4 -/* CAC98 800CA098 24C6FFFC */ addiu $a2, $a2, -0x4 -/* CAC9C 800CA09C 1000FFF8 */ b .L800CA080 -/* CACA0 800CA0A0 ACA20000 */ sw $v0, 0x0($a1) -.end bcopy +forwards_bytecopy: + beqz a2, ret + addu v1, a0, a2 +99: + lb v0, 0(a0) + addiu a0, a0, 1 + sb v0, 0(a1) + addiu a1, a1, 1 + bne a0, v1, 99b +ret: + move v0, a3 + jr ra + +forwalignable: + beqz v0, forwards + beq v0, 1, forw_copy3 + beq v0, 2, forw_copy2 + + lb v0, 0(a0) + addiu a0, a0, 1 + sb v0, 0(a1) + addiu a1, a1, 1 + addiu a2, a2, -1 + b forwards + +forw_copy2: + lh v0, 0(a0) + addiu a0, a0, 2 + sh v0, 0(a1) + addiu a1, a1, 2 + addiu a2, a2, -2 + b forwards + +forw_copy3: + lb v0, 0(a0) + lh v1, 1(a0) + addiu a0, a0, 3 + sb v0, 0(a1) + sh v1, 1(a1) + addiu a1, a1, 3 + addiu a2, a2, -3 + +forwards: +forwards_32: + blt a2, 32, forwards_16 + lw v0, 0(a0) + lw v1, 4(a0) + lw t0, 8(a0) + lw t1, 12(a0) + lw t2, 16(a0) + lw t3, 20(a0) + lw ta0, 24(a0) + lw ta1, 28(a0) + addiu a0, a0, 32 + sw v0, 0(a1) + sw v1, 4(a1) + sw t0, 8(a1) + sw t1, 12(a1) + sw t2, 16(a1) + sw t3, 20(a1) + sw ta0, 24(a1) + sw ta1, 28(a1) + addiu a1, a1, 32 + addiu a2, a2, -32 + b forwards_32 + +forwards_16: + blt a2, 16, forwards_4 + lw v0, 0(a0) + lw v1, 4(a0) + lw t0, 8(a0) + lw t1, 12(a0) + addiu a0, a0, 16 + sw v0, 0(a1) + sw v1, 4(a1) + sw t0, 8(a1) + sw t1, 12(a1) + addiu a1, a1, 16 + addiu a2, a2, -16 + b forwards_16 + +forwards_4: + blt a2, 4, forwards_bytecopy + + lw v0, 0(a0) + addiu a0, a0, 4 + sw v0, 0(a1) + addiu a1, a1, 4 + addiu a2, a2, -4 + b forwards_4 + +gobackwards: + add a0, a0, a2 + add a1, a1, a2 + blt a2, 16, backwards_bytecopy + + andi v0, a0, 0x3 + andi v1, a1, 0x3 + beq v0, v1, backalignable + +backwards_bytecopy: + beqz a2, ret + addiu a0, a0, -1 + addiu a1, a1, -1 + subu v1, a0, a2 +99: + lb v0, 0(a0) + addiu a0, a0, -1 + sb v0, 0(a1) + addiu a1, a1, -1 + bne a0, v1, 99b + + move v0, a3 + jr ra +backalignable: + beqz v0, backwards + beq v0, 3, back_copy3 + beq v0, 2, back_copy2 + lb v0, -1(a0) + addiu a0, a0, -1 + sb v0, -1(a1) + addiu a1, a1, -1 + addiu a2, a2, -1 + b backwards + +back_copy2: + lh v0, -2(a0) + addiu a0, a0, -2 + sh v0, -2(a1) + addiu a1, a1, -2 + addiu a2, a2, -2 + b backwards + +back_copy3: + lb v0, -1(a0) + lh v1, -3(a0) + addiu a0, a0, -3 + sb v0, -1(a1) + sh v1, -3(a1) + addiu a1, a1, -3 + addiu a2, a2, -3 + +backwards: +backwards_32: + blt a2, 32, backwards_16 + lw v0, -4(a0) + lw v1, -8(a0) + lw t0, -12(a0) + lw t1, -16(a0) + lw t2, -20(a0) + lw t3, -24(a0) + lw ta0, -28(a0) + lw ta1, -32(a0) + addiu a0, a0, -32 + sw v0, -4(a1) + sw v1, -8(a1) + sw t0, -12(a1) + sw t1, -16(a1) + sw t2, -20(a1) + sw t3, -24(a1) + sw ta0, -28(a1) + sw ta1, -32(a1) + addiu a1, a1, -32 + addiu a2, a2, -32 + b backwards_32 + +backwards_16: + blt a2, 16, backwards_4 + lw v0, -4(a0) + lw v1, -8(a0) + lw t0, -12(a0) + lw t1, -16(a0) + addiu a0, a0, -16 + sw v0, -4(a1) + sw v1, -8(a1) + sw t0, -12(a1) + sw t1, -16(a1) + addiu a1, a1, -16 + addiu a2, a2, -16 + b backwards_16 + +backwards_4: + blt a2, 4, backwards_bytecopy + lw v0, -4(a0) + addiu a0, a0, -4 + sw v0, -4(a1) + addiu a1, a1, -4 + addiu a2, a2, -4 + b backwards_4 + +.end _bcopy diff --git a/libultra/src/libc/bzero.s b/libultra/src/libc/bzero.s index f8b298c0..c3deec0a 100644 --- a/libultra/src/libc/bzero.s +++ b/libultra/src/libc/bzero.s @@ -1,60 +1,72 @@ -.include "macro.inc" +#include "PR/R4300.h" +#include "sys/asm.h" +#include "sys/regdef.h" -/* assembler directives */ -.set noat /* allow manual use of $at */ -.set noreorder /* don't insert nops after branches */ -.set gp=64 /* allow use of 64-bit general purpose registers */ +.text +#ifdef __sgi +WEAK(bzero, _bzero) +WEAK(blkclr, _blkclr) +#else +#define _bzero bzero +#define _blkclr blkclr +#endif +LEAF(_bzero) +XLEAF(_blkclr) + negu v1, a0 + blt a1, 12, bytezero -.section .text, "ax" + andi v1, v1, 0x3 + subu a1, a1, v1 -/* Generated by spimdisasm 1.30.0 */ + beqz v1, blkzero + swl zero, 0(a0) + addu a0, a0, v1 +blkzero: + /* align backwards to 0x20 */ + and a3, a1, ~31 + subu a1, a1, a3 + /* If the result is zero, the amount to zero is less than 0x20 bytes */ + beqz a3, wordzero -leaf bzero -/* D10E0 800D04E0 28A1000C */ slti $at, $a1, 0xC -/* D10E4 800D04E4 1420001D */ bnez $at, .L800D055C -/* D10E8 800D04E8 00041823 */ negu $v1, $a0 -/* D10EC 800D04EC 30630003 */ andi $v1, $v1, 0x3 -/* D10F0 800D04F0 10600003 */ beqz $v1, .L800D0500 -/* D10F4 800D04F4 00A32823 */ subu $a1, $a1, $v1 -/* D10F8 800D04F8 A8800000 */ swl $zero, 0x0($a0) -/* D10FC 800D04FC 00832021 */ addu $a0, $a0, $v1 -.L800D0500: -/* D1100 800D0500 2401FFE0 */ addiu $at, $zero, -0x20 -/* D1104 800D0504 00A13824 */ and $a3, $a1, $at -/* D1108 800D0508 10E0000C */ beqz $a3, .L800D053C -/* D110C 800D050C 00A72823 */ subu $a1, $a1, $a3 -/* D1110 800D0510 00E43821 */ addu $a3, $a3, $a0 -.L800D0514: -/* D1114 800D0514 24840020 */ addiu $a0, $a0, 0x20 -/* D1118 800D0518 AC80FFE0 */ sw $zero, -0x20($a0) -/* D111C 800D051C AC80FFE4 */ sw $zero, -0x1C($a0) -/* D1120 800D0520 AC80FFE8 */ sw $zero, -0x18($a0) -/* D1124 800D0524 AC80FFEC */ sw $zero, -0x14($a0) -/* D1128 800D0528 AC80FFF0 */ sw $zero, -0x10($a0) -/* D112C 800D052C AC80FFF4 */ sw $zero, -0xC($a0) -/* D1130 800D0530 AC80FFF8 */ sw $zero, -0x8($a0) -/* D1134 800D0534 1487FFF7 */ bne $a0, $a3, .L800D0514 -/* D1138 800D0538 AC80FFFC */ sw $zero, -0x4($a0) -.L800D053C: -/* D113C 800D053C 2401FFFC */ addiu $at, $zero, -0x4 -/* D1140 800D0540 00A13824 */ and $a3, $a1, $at -/* D1144 800D0544 10E00005 */ beqz $a3, .L800D055C -/* D1148 800D0548 00A72823 */ subu $a1, $a1, $a3 -/* D114C 800D054C 00E43821 */ addu $a3, $a3, $a0 -.L800D0550: -/* D1150 800D0550 24840004 */ addiu $a0, $a0, 0x4 -/* D1154 800D0554 1487FFFE */ bne $a0, $a3, .L800D0550 -/* D1158 800D0558 AC80FFFC */ sw $zero, -0x4($a0) -.L800D055C: -/* D115C 800D055C 18A00005 */ blez $a1, .L800D0574 -/* D1160 800D0560 00000000 */ nop -/* D1164 800D0564 00A42821 */ addu $a1, $a1, $a0 -.L800D0568: -/* D1168 800D0568 24840001 */ addiu $a0, $a0, 0x1 -/* D116C 800D056C 1485FFFE */ bne $a0, $a1, .L800D0568 -/* D1170 800D0570 A080FFFF */ sb $zero, -0x1($a0) -.L800D0574: -/* D1174 800D0574 03E00008 */ jr $ra -/* D1178 800D0578 00000000 */ nop -/* D117C 800D057C 00000000 */ nop -.end bzero + /* zero in blocks of 0x20 at a time */ + addu a3, a3, a0 +1: + sw zero, 0(a0) + sw zero, 4(a0) + sw zero, 8(a0) + sw zero, 12(a0) + addiu a0, a0, 32 + sw zero, -16(a0) + sw zero, -12(a0) + sw zero, -8(a0) + sw zero, -4(a0) + bne a0, a3, 1b + +wordzero: + /* align backwards to 0x4 */ + and a3, a1, ~3 + subu a1, a1, a3 + /* If the result is zero, the amount to zero is less than 0x4 bytes */ + beqz a3, bytezero + + /* zero one word at a time */ + addu a3, a3, a0 +1: + addiu a0, a0, 4 + sw zero, -4(a0) + bne a0, a3, 1b + +bytezero: + /* test if nothing left to zero */ + blez a1, zerodone + + /* zero one byte at a time */ + addu a1, a1, a0 +1: + addiu a0, a0, 1 + sb zero, -1(a0) + bne a0, a1, 1b +zerodone: + jr ra + +.end _bzero diff --git a/libultra/src/os/exceptasm.s b/libultra/src/os/exceptasm.s index 3d63241f..252741b0 100644 --- a/libultra/src/os/exceptasm.s +++ b/libultra/src/os/exceptasm.s @@ -1,708 +1,1358 @@ -.include "macro.inc" +#ifdef MODERN_CC +.set gp=64 +#endif -/* assembler directives */ -.set noat /* allow manual use of $at */ -.set noreorder /* don't insert nops after branches */ -.set gp=64 /* allow use of 64-bit general purpose registers */ +#include "PR/R4300.h" +#include "sys/asm.h" +#include "sys/regdef.h" +#include "PR/os.h" +#include "PR/rcp.h" +#include "PR/rdb.h" +#include "exceptasm.h" +#include "threadasm.h" +#include "PR/os_version.h" -.section .bss +#define KMC_CODE_ENTRY 0xBFF00014 +#define KMC_WPORT 0xBFF08000 +#define KMC_STAT 0xBFF08004 -glabel __osThreadSave -.space 0x1B0 +.rdata -.section .data +#define REDISPATCH 0x00 +#define SW1 0x04 +#define SW2 0x08 +#define RCP 0x0c +#define CART 0x10 +#define PRENMI 0x14 +#define IP6_HDLR 0x18 +#define IP7_HDLR 0x1c +#define COUNTER 0x20 -glabel __osHwIntTable -.word 0 -.word 0 -.word 0 -.word 0 -.word 0 +__osIntOffTable: + .byte REDISPATCH + .byte PRENMI + .byte IP6_HDLR + .byte IP6_HDLR + .byte IP7_HDLR + .byte IP7_HDLR + .byte IP7_HDLR + .byte IP7_HDLR + .byte COUNTER + .byte COUNTER + .byte COUNTER + .byte COUNTER + .byte COUNTER + .byte COUNTER + .byte COUNTER + .byte COUNTER + .byte REDISPATCH + .byte SW1 + .byte SW2 + .byte SW2 + .byte RCP + .byte RCP + .byte RCP + .byte RCP + .byte CART + .byte CART + .byte CART + .byte CART + .byte CART + .byte CART + .byte CART + .byte CART -.section .rodata +__osIntTable: + .word redispatch, sw1, sw2, rcp, cart, prenmi, IP6_Hdlr, IP7_Hdlr, counter -glabel __osIntOffTable -.byte 0x00 -.byte 0x14 -.byte 0x18 -.byte 0x18 -.byte 0x1C -.byte 0x1C -.byte 0x1C -.byte 0x1C -.byte 0x20 -.byte 0x20 -.byte 0x20 -.byte 0x20 -.byte 0x20 -.byte 0x20 -.byte 0x20 -.byte 0x20 -.byte 0x00 -.byte 0x04 -.byte 0x08 -.byte 0x08 -.byte 0x0C -.byte 0x0C -.byte 0x0C -.byte 0x0C -.byte 0x10 -.byte 0x10 -.byte 0x10 -.byte 0x10 -.byte 0x10 -.byte 0x10 -.byte 0x10 -.byte 0x10 +#ifndef _FINALROM +EXPORT(__osCauseTable_pt) + .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 + .byte 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0 +#endif -glabel __osIntTable -.word .L800D3168 -.word .L800D3130 -.word .L800D3110 -.word .L800D2F74 -.word .L800D2F20 -.word .L800D30B4 -.word .L800D2EE8 -.word .L800D2EF4 -.word .L800D2F00 +.data -.section .text, "ax" +#if BUILD_VERSION >= VERSION_J +EXPORT(__osHwIntTable) + .word 0, 0 + .word 0, 0 + .word 0, 0 + .word 0, 0 + .word 0, 0 -/* Generated by spimdisasm 1.30.0 */ +EXPORT(__osPiIntTable) + .word 0, 0 +#else +EXPORT(__osHwIntTable) + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 +#endif -leaf __osExceptionPreamble -/* D38B0 800D2CB0 3C1A800D */ lui $k0, %hi(__osException) /* handwritten instruction */ -/* D38B4 800D2CB4 275A2CC0 */ addiu $k0, $k0, %lo(__osException) /* handwritten instruction */ -/* D38B8 800D2CB8 03400008 */ jr $k0 -/* D38BC 800D2CBC 00000000 */ nop -.end __osExceptionPreamble +#ifndef _FINALROM +__osRdb_DbgRead_Ct: + .word 0 -leaf __osException -/* D38C0 800D2CC0 3C1A8013 */ lui $k0, %hi(__osThreadSave) /* handwritten instruction */ -/* D38C4 800D2CC4 275AD240 */ addiu $k0, $k0, %lo(__osThreadSave) /* handwritten instruction */ -/* D38C8 800D2CC8 FF410020 */ sd $at, 0x20($k0) /* handwritten instruction */ -/* D38CC 800D2CCC 401B6000 */ mfc0 $k1, $12 /* handwritten instruction */ -/* D38D0 800D2CD0 AF5B0118 */ sw $k1, 0x118($k0) /* handwritten instruction */ -/* D38D4 800D2CD4 2401FFFC */ addiu $at, $zero, -0x4 -/* D38D8 800D2CD8 0361D824 */ and $k1, $k1, $at -/* D38DC 800D2CDC 409B6000 */ mtc0 $k1, $12 /* handwritten instruction */ -/* D38E0 800D2CE0 FF480058 */ sd $t0, 0x58($k0) /* handwritten instruction */ -/* D38E4 800D2CE4 FF490060 */ sd $t1, 0x60($k0) /* handwritten instruction */ -/* D38E8 800D2CE8 FF4A0068 */ sd $t2, 0x68($k0) /* handwritten instruction */ -/* D38EC 800D2CEC AF400018 */ sw $zero, 0x18($k0) /* handwritten instruction */ -/* D38F0 800D2CF0 40086800 */ mfc0 $t0, $13 /* handwritten instruction */ -/* D38F4 800D2CF4 03404025 */ or $t0, $k0, $zero -/* D38F8 800D2CF8 3C1A800E */ lui $k0, %hi(__osRunningThread) /* handwritten instruction */ -/* D38FC 800D2CFC 8F5A4890 */ lw $k0, %lo(__osRunningThread)($k0) /* handwritten instruction */ -/* D3900 800D2D00 DD090020 */ ld $t1, 0x20($t0) -/* D3904 800D2D04 FF490020 */ sd $t1, 0x20($k0) /* handwritten instruction */ -/* D3908 800D2D08 DD090118 */ ld $t1, 0x118($t0) -/* D390C 800D2D0C FF490118 */ sd $t1, 0x118($k0) /* handwritten instruction */ -/* D3910 800D2D10 DD090058 */ ld $t1, 0x58($t0) -/* D3914 800D2D14 FF490058 */ sd $t1, 0x58($k0) /* handwritten instruction */ -/* D3918 800D2D18 DD090060 */ ld $t1, 0x60($t0) -/* D391C 800D2D1C FF490060 */ sd $t1, 0x60($k0) /* handwritten instruction */ -/* D3920 800D2D20 DD090068 */ ld $t1, 0x68($t0) -/* D3924 800D2D24 FF490068 */ sd $t1, 0x68($k0) /* handwritten instruction */ -/* D3928 800D2D28 8F5B0118 */ lw $k1, 0x118($k0) /* handwritten instruction */ -/* D392C 800D2D2C 00004012 */ mflo $t0 -/* D3930 800D2D30 FF480108 */ sd $t0, 0x108($k0) /* handwritten instruction */ -/* D3934 800D2D34 00004010 */ mfhi $t0 -/* D3938 800D2D38 3369FF00 */ andi $t1, $k1, 0xFF00 /* handwritten instruction */ -/* D393C 800D2D3C FF420028 */ sd $v0, 0x28($k0) /* handwritten instruction */ -/* D3940 800D2D40 FF430030 */ sd $v1, 0x30($k0) /* handwritten instruction */ -/* D3944 800D2D44 FF440038 */ sd $a0, 0x38($k0) /* handwritten instruction */ -/* D3948 800D2D48 FF450040 */ sd $a1, 0x40($k0) /* handwritten instruction */ -/* D394C 800D2D4C FF460048 */ sd $a2, 0x48($k0) /* handwritten instruction */ -/* D3950 800D2D50 FF470050 */ sd $a3, 0x50($k0) /* handwritten instruction */ -/* D3954 800D2D54 FF4B0070 */ sd $t3, 0x70($k0) /* handwritten instruction */ -/* D3958 800D2D58 FF4C0078 */ sd $t4, 0x78($k0) /* handwritten instruction */ -/* D395C 800D2D5C FF4D0080 */ sd $t5, 0x80($k0) /* handwritten instruction */ -/* D3960 800D2D60 FF4E0088 */ sd $t6, 0x88($k0) /* handwritten instruction */ -/* D3964 800D2D64 FF4F0090 */ sd $t7, 0x90($k0) /* handwritten instruction */ -/* D3968 800D2D68 FF500098 */ sd $s0, 0x98($k0) /* handwritten instruction */ -/* D396C 800D2D6C FF5100A0 */ sd $s1, 0xA0($k0) /* handwritten instruction */ -/* D3970 800D2D70 FF5200A8 */ sd $s2, 0xA8($k0) /* handwritten instruction */ -/* D3974 800D2D74 FF5300B0 */ sd $s3, 0xB0($k0) /* handwritten instruction */ -/* D3978 800D2D78 FF5400B8 */ sd $s4, 0xB8($k0) /* handwritten instruction */ -/* D397C 800D2D7C FF5500C0 */ sd $s5, 0xC0($k0) /* handwritten instruction */ -/* D3980 800D2D80 FF5600C8 */ sd $s6, 0xC8($k0) /* handwritten instruction */ -/* D3984 800D2D84 FF5700D0 */ sd $s7, 0xD0($k0) /* handwritten instruction */ -/* D3988 800D2D88 FF5800D8 */ sd $t8, 0xD8($k0) /* handwritten instruction */ -/* D398C 800D2D8C FF5900E0 */ sd $t9, 0xE0($k0) /* handwritten instruction */ -/* D3990 800D2D90 FF5C00E8 */ sd $gp, 0xE8($k0) /* handwritten instruction */ -/* D3994 800D2D94 FF5D00F0 */ sd $sp, 0xF0($k0) /* handwritten instruction */ -/* D3998 800D2D98 FF5E00F8 */ sd $fp, 0xF8($k0) /* handwritten instruction */ -/* D399C 800D2D9C FF5F0100 */ sd $ra, 0x100($k0) /* handwritten instruction */ -/* D39A0 800D2DA0 1120000D */ beqz $t1, .L800D2DD8 -/* D39A4 800D2DA4 FF480110 */ sd $t0, 0x110($k0) /* handwritten instruction */ -/* D39A8 800D2DA8 3C08800E */ lui $t0, %hi(__OSGlobalIntMask) -/* D39AC 800D2DAC 250838AC */ addiu $t0, $t0, %lo(__OSGlobalIntMask) -/* D39B0 800D2DB0 8D080000 */ lw $t0, 0x0($t0) -/* D39B4 800D2DB4 2401FFFF */ addiu $at, $zero, -0x1 -/* D39B8 800D2DB8 01014026 */ xor $t0, $t0, $at -/* D39BC 800D2DBC 3C01FFFF */ lui $at, (0xFFFF00FF >> 16) -/* D39C0 800D2DC0 3108FF00 */ andi $t0, $t0, 0xFF00 -/* D39C4 800D2DC4 342100FF */ ori $at, $at, (0xFFFF00FF & 0xFFFF) -/* D39C8 800D2DC8 01284825 */ or $t1, $t1, $t0 -/* D39CC 800D2DCC 0361D824 */ and $k1, $k1, $at -/* D39D0 800D2DD0 0369D825 */ or $k1, $k1, $t1 -/* D39D4 800D2DD4 AF5B0118 */ sw $k1, 0x118($k0) /* handwritten instruction */ -.L800D2DD8: -/* D39D8 800D2DD8 3C09A430 */ lui $t1, %hi(MI_INTR_MASK_REG) -/* D39DC 800D2DDC 8D29000C */ lw $t1, %lo(MI_INTR_MASK_REG)($t1) -/* D39E0 800D2DE0 1120000B */ beqz $t1, .L800D2E10 -/* D39E4 800D2DE4 00000000 */ nop -/* D39E8 800D2DE8 3C08800E */ lui $t0, %hi(__OSGlobalIntMask) -/* D39EC 800D2DEC 250838AC */ addiu $t0, $t0, %lo(__OSGlobalIntMask) -/* D39F0 800D2DF0 8D080000 */ lw $t0, 0x0($t0) -/* D39F4 800D2DF4 8F4C0128 */ lw $t4, 0x128($k0) /* handwritten instruction */ -/* D39F8 800D2DF8 2401FFFF */ addiu $at, $zero, -0x1 -/* D39FC 800D2DFC 00084402 */ srl $t0, $t0, 16 -/* D3A00 800D2E00 01014026 */ xor $t0, $t0, $at -/* D3A04 800D2E04 3108003F */ andi $t0, $t0, 0x3F -/* D3A08 800D2E08 010C4024 */ and $t0, $t0, $t4 -/* D3A0C 800D2E0C 01284825 */ or $t1, $t1, $t0 -.L800D2E10: -/* D3A10 800D2E10 AF490128 */ sw $t1, 0x128($k0) /* handwritten instruction */ -/* D3A14 800D2E14 40087000 */ mfc0 $t0, $14 /* handwritten instruction */ -/* D3A18 800D2E18 AF48011C */ sw $t0, 0x11C($k0) /* handwritten instruction */ -/* D3A1C 800D2E1C 8F480018 */ lw $t0, 0x18($k0) /* handwritten instruction */ -/* D3A20 800D2E20 11000014 */ beqz $t0, .L800D2E74 -/* D3A24 800D2E24 00000000 */ nop -/* D3A28 800D2E28 4448F800 */ cfc1 $t0, $31 -/* D3A2C 800D2E2C 00000000 */ nop -/* D3A30 800D2E30 AF48012C */ sw $t0, 0x12C($k0) /* handwritten instruction */ -/* D3A34 800D2E34 F7400130 */ sdc1 $f0, 0x130($k0) -/* D3A38 800D2E38 F7420138 */ sdc1 $f2, 0x138($k0) -/* D3A3C 800D2E3C F7440140 */ sdc1 $f4, 0x140($k0) -/* D3A40 800D2E40 F7460148 */ sdc1 $f6, 0x148($k0) -/* D3A44 800D2E44 F7480150 */ sdc1 $f8, 0x150($k0) -/* D3A48 800D2E48 F74A0158 */ sdc1 $f10, 0x158($k0) -/* D3A4C 800D2E4C F74C0160 */ sdc1 $f12, 0x160($k0) -/* D3A50 800D2E50 F74E0168 */ sdc1 $f14, 0x168($k0) -/* D3A54 800D2E54 F7500170 */ sdc1 $f16, 0x170($k0) -/* D3A58 800D2E58 F7520178 */ sdc1 $f18, 0x178($k0) -/* D3A5C 800D2E5C F7540180 */ sdc1 $f20, 0x180($k0) -/* D3A60 800D2E60 F7560188 */ sdc1 $f22, 0x188($k0) -/* D3A64 800D2E64 F7580190 */ sdc1 $f24, 0x190($k0) -/* D3A68 800D2E68 F75A0198 */ sdc1 $f26, 0x198($k0) -/* D3A6C 800D2E6C F75C01A0 */ sdc1 $f28, 0x1A0($k0) -/* D3A70 800D2E70 F75E01A8 */ sdc1 $f30, 0x1A8($k0) -.L800D2E74: -/* D3A74 800D2E74 40086800 */ mfc0 $t0, $13 /* handwritten instruction */ -/* D3A78 800D2E78 AF480120 */ sw $t0, 0x120($k0) /* handwritten instruction */ -/* D3A7C 800D2E7C 24090002 */ addiu $t1, $zero, 0x2 -/* D3A80 800D2E80 A7490010 */ sh $t1, 0x10($k0) /* handwritten instruction */ -/* D3A84 800D2E84 3109007C */ andi $t1, $t0, 0x7C -/* D3A88 800D2E88 240A0024 */ addiu $t2, $zero, 0x24 -/* D3A8C 800D2E8C 112A00B0 */ beq $t1, $t2, .L800D3150 -/* D3A90 800D2E90 00000000 */ nop -/* D3A94 800D2E94 240A002C */ addiu $t2, $zero, 0x2C -/* D3A98 800D2E98 112A00FF */ beq $t1, $t2, handle_CpU -/* D3A9C 800D2E9C 00000000 */ nop -/* D3AA0 800D2EA0 240A0000 */ addiu $t2, $zero, 0x0 -/* D3AA4 800D2EA4 152A00C3 */ bne $t1, $t2, .L800D31B4 -/* D3AA8 800D2EA8 00000000 */ nop -/* D3AAC 800D2EAC 03688024 */ and $s0, $k1, $t0 -.L800D2EB0: -/* D3AB0 800D2EB0 3209FF00 */ andi $t1, $s0, 0xFF00 -/* D3AB4 800D2EB4 00095302 */ srl $t2, $t1, 12 -/* D3AB8 800D2EB8 15400003 */ bnez $t2, .L800D2EC8 -/* D3ABC 800D2EBC 00000000 */ nop -/* D3AC0 800D2EC0 00095202 */ srl $t2, $t1, 8 -/* D3AC4 800D2EC4 214A0010 */ addi $t2, $t2, 0x10 /* handwritten instruction */ -.L800D2EC8: -/* D3AC8 800D2EC8 3C01800F */ lui $at, %hi(__osIntOffTable) -/* D3ACC 800D2ECC 002A0821 */ addu $at, $at, $t2 -/* D3AD0 800D2ED0 902A9670 */ lbu $t2, %lo(__osIntOffTable)($at) -/* D3AD4 800D2ED4 3C01800F */ lui $at, %hi(__osIntTable) -/* D3AD8 800D2ED8 002A0821 */ addu $at, $at, $t2 -/* D3ADC 800D2EDC 8C2A9690 */ lw $t2, %lo(__osIntTable)($at) -/* D3AE0 800D2EE0 01400008 */ jr $t2 -/* D3AE4 800D2EE4 00000000 */ nop -glabel .L800D2EE8 -/* D3AE8 800D2EE8 2401DFFF */ addiu $at, $zero, -0x2001 -/* D3AEC 800D2EEC 1000FFF0 */ b .L800D2EB0 -/* D3AF0 800D2EF0 02018024 */ and $s0, $s0, $at -glabel .L800D2EF4 -/* D3AF4 800D2EF4 2401BFFF */ addiu $at, $zero, -0x4001 -/* D3AF8 800D2EF8 1000FFED */ b .L800D2EB0 -/* D3AFC 800D2EFC 02018024 */ and $s0, $s0, $at -glabel .L800D2F00 -/* D3B00 800D2F00 40095800 */ mfc0 $t1, $11 /* handwritten instruction */ -/* D3B04 800D2F04 40895800 */ mtc0 $t1, $11 /* handwritten instruction */ -/* D3B08 800D2F08 0C034C79 */ jal send_mesg -/* D3B0C 800D2F0C 24040018 */ addiu $a0, $zero, 0x18 -/* D3B10 800D2F10 3C01FFFF */ lui $at, (0xFFFF7FFF >> 16) -/* D3B14 800D2F14 34217FFF */ ori $at, $at, (0xFFFF7FFF & 0xFFFF) -/* D3B18 800D2F18 1000FFE5 */ b .L800D2EB0 -/* D3B1C 800D2F1C 02018024 */ and $s0, $s0, $at -glabel .L800D2F20 -/* D3B20 800D2F20 2401F7FF */ addiu $at, $zero, -0x801 -/* D3B24 800D2F24 02018024 */ and $s0, $s0, $at -/* D3B28 800D2F28 240A0004 */ addiu $t2, $zero, 0x4 -/* D3B2C 800D2F2C 3C01800E */ lui $at, %hi(__osHwIntTable) -/* D3B30 800D2F30 002A0821 */ addu $at, $at, $t2 -/* D3B34 800D2F34 8C2A48A0 */ lw $t2, %lo(__osHwIntTable)($at) -/* D3B38 800D2F38 3C1D8013 */ lui $sp, %hi(leoDiskStack) -/* D3B3C 800D2F3C 27BDAAE0 */ addiu $sp, $sp, %lo(leoDiskStack) -/* D3B40 800D2F40 24040010 */ addiu $a0, $zero, 0x10 -/* D3B44 800D2F44 11400007 */ beqz $t2, .L800D2F64 -/* D3B48 800D2F48 27BD0FF0 */ addiu $sp, $sp, 0xFF0 -/* D3B4C 800D2F4C 0140F809 */ jalr $t2 -/* D3B50 800D2F50 00000000 */ nop -/* D3B54 800D2F54 10400003 */ beqz $v0, .L800D2F64 -/* D3B58 800D2F58 00000000 */ nop -/* D3B5C 800D2F5C 10000082 */ b .L800D3168 -/* D3B60 800D2F60 00000000 */ nop -.L800D2F64: -/* D3B64 800D2F64 0C034C79 */ jal send_mesg -/* D3B68 800D2F68 00000000 */ nop -/* D3B6C 800D2F6C 1000FFD0 */ b .L800D2EB0 -/* D3B70 800D2F70 00000000 */ nop -glabel .L800D2F74 -/* D3B74 800D2F74 3C08800E */ lui $t0, %hi(__OSGlobalIntMask) -/* D3B78 800D2F78 250838AC */ addiu $t0, $t0, %lo(__OSGlobalIntMask) -/* D3B7C 800D2F7C 8D080000 */ lw $t0, 0x0($t0) -/* D3B80 800D2F80 3C11A430 */ lui $s1, %hi(MI_INTR_REG) -/* D3B84 800D2F84 8E310008 */ lw $s1, %lo(MI_INTR_REG)($s1) -/* D3B88 800D2F88 00084402 */ srl $t0, $t0, 16 -/* D3B8C 800D2F8C 02288824 */ and $s1, $s1, $t0 -/* D3B90 800D2F90 32290001 */ andi $t1, $s1, 0x1 -/* D3B94 800D2F94 11200013 */ beqz $t1, .L800D2FE4 -/* D3B98 800D2F98 00000000 */ nop -/* D3B9C 800D2F9C 3C0CA404 */ lui $t4, %hi(SP_STATUS_REG) -/* D3BA0 800D2FA0 8D8C0010 */ lw $t4, %lo(SP_STATUS_REG)($t4) -/* D3BA4 800D2FA4 24090008 */ addiu $t1, $zero, 0x8 -/* D3BA8 800D2FA8 3C01A404 */ lui $at, %hi(SP_STATUS_REG) -/* D3BAC 800D2FAC 318C0300 */ andi $t4, $t4, 0x300 -/* D3BB0 800D2FB0 3231003E */ andi $s1, $s1, 0x3E -/* D3BB4 800D2FB4 11800007 */ beqz $t4, .L800D2FD4 -/* D3BB8 800D2FB8 AC290010 */ sw $t1, %lo(SP_STATUS_REG)($at) -/* D3BBC 800D2FBC 0C034C79 */ jal send_mesg -/* D3BC0 800D2FC0 24040020 */ addiu $a0, $zero, 0x20 -/* D3BC4 800D2FC4 12200038 */ beqz $s1, .L800D30A8 -/* D3BC8 800D2FC8 00000000 */ nop -/* D3BCC 800D2FCC 10000005 */ b .L800D2FE4 -/* D3BD0 800D2FD0 00000000 */ nop -.L800D2FD4: -/* D3BD4 800D2FD4 0C034C79 */ jal send_mesg -/* D3BD8 800D2FD8 24040058 */ addiu $a0, $zero, 0x58 -/* D3BDC 800D2FDC 12200032 */ beqz $s1, .L800D30A8 -/* D3BE0 800D2FE0 00000000 */ nop -.L800D2FE4: -/* D3BE4 800D2FE4 32290008 */ andi $t1, $s1, 0x8 -/* D3BE8 800D2FE8 11200007 */ beqz $t1, .L800D3008 -/* D3BEC 800D2FEC 3C01A440 */ lui $at, %hi(VI_V_CURRENT_LINE_REG) -/* D3BF0 800D2FF0 32310037 */ andi $s1, $s1, 0x37 -/* D3BF4 800D2FF4 AC200010 */ sw $zero, %lo(VI_V_CURRENT_LINE_REG)($at) -/* D3BF8 800D2FF8 0C034C79 */ jal send_mesg -/* D3BFC 800D2FFC 24040038 */ addiu $a0, $zero, 0x38 -/* D3C00 800D3000 12200029 */ beqz $s1, .L800D30A8 -/* D3C04 800D3004 00000000 */ nop -.L800D3008: -/* D3C08 800D3008 32290004 */ andi $t1, $s1, 0x4 -/* D3C0C 800D300C 11200009 */ beqz $t1, .L800D3034 -/* D3C10 800D3010 00000000 */ nop -/* D3C14 800D3014 24090001 */ addiu $t1, $zero, 0x1 -/* D3C18 800D3018 3C01A450 */ lui $at, %hi(AI_STATUS_REG) -/* D3C1C 800D301C 3231003B */ andi $s1, $s1, 0x3B -/* D3C20 800D3020 AC29000C */ sw $t1, %lo(AI_STATUS_REG)($at) -/* D3C24 800D3024 0C034C79 */ jal send_mesg -/* D3C28 800D3028 24040030 */ addiu $a0, $zero, 0x30 -/* D3C2C 800D302C 1220001E */ beqz $s1, .L800D30A8 -/* D3C30 800D3030 00000000 */ nop -.L800D3034: -/* D3C34 800D3034 32290002 */ andi $t1, $s1, 0x2 -/* D3C38 800D3038 11200007 */ beqz $t1, .L800D3058 -/* D3C3C 800D303C 3C01A480 */ lui $at, %hi(SI_STATUS_REG) -/* D3C40 800D3040 3231003D */ andi $s1, $s1, 0x3D -/* D3C44 800D3044 AC200018 */ sw $zero, %lo(SI_STATUS_REG)($at) -/* D3C48 800D3048 0C034C79 */ jal send_mesg -/* D3C4C 800D304C 24040028 */ addiu $a0, $zero, 0x28 -/* D3C50 800D3050 12200015 */ beqz $s1, .L800D30A8 -/* D3C54 800D3054 00000000 */ nop -.L800D3058: -/* D3C58 800D3058 32290010 */ andi $t1, $s1, 0x10 -/* D3C5C 800D305C 11200009 */ beqz $t1, .L800D3084 -/* D3C60 800D3060 00000000 */ nop -/* D3C64 800D3064 24090002 */ addiu $t1, $zero, 0x2 -/* D3C68 800D3068 3C01A460 */ lui $at, %hi(PI_STATUS_REG) -/* D3C6C 800D306C 3231002F */ andi $s1, $s1, 0x2F -/* D3C70 800D3070 AC290010 */ sw $t1, %lo(PI_STATUS_REG)($at) -/* D3C74 800D3074 0C034C79 */ jal send_mesg -/* D3C78 800D3078 24040040 */ addiu $a0, $zero, 0x40 -/* D3C7C 800D307C 1220000A */ beqz $s1, .L800D30A8 -/* D3C80 800D3080 00000000 */ nop -.L800D3084: -/* D3C84 800D3084 32290020 */ andi $t1, $s1, 0x20 -/* D3C88 800D3088 11200007 */ beqz $t1, .L800D30A8 -/* D3C8C 800D308C 00000000 */ nop -/* D3C90 800D3090 24090800 */ addiu $t1, $zero, 0x800 -/* D3C94 800D3094 3C01A430 */ lui $at, %hi(MI_MODE_REG) -/* D3C98 800D3098 3231001F */ andi $s1, $s1, 0x1F -/* D3C9C 800D309C AC290000 */ sw $t1, %lo(MI_MODE_REG)($at) -/* D3CA0 800D30A0 0C034C79 */ jal send_mesg -/* D3CA4 800D30A4 24040048 */ addiu $a0, $zero, 0x48 -.L800D30A8: -/* D3CA8 800D30A8 2401FBFF */ addiu $at, $zero, -0x401 -/* D3CAC 800D30AC 1000FF80 */ b .L800D2EB0 -/* D3CB0 800D30B0 02018024 */ and $s0, $s0, $at -glabel .L800D30B4 -/* D3CB4 800D30B4 8F5B0118 */ lw $k1, 0x118($k0) /* handwritten instruction */ -/* D3CB8 800D30B8 2401EFFF */ addiu $at, $zero, -0x1001 -/* D3CBC 800D30BC 3C09800E */ lui $t1, %hi(__osShutdown) -/* D3CC0 800D30C0 0361D824 */ and $k1, $k1, $at -/* D3CC4 800D30C4 AF5B0118 */ sw $k1, 0x118($k0) /* handwritten instruction */ -/* D3CC8 800D30C8 252938A8 */ addiu $t1, $t1, %lo(__osShutdown) -/* D3CCC 800D30CC 8D2A0000 */ lw $t2, 0x0($t1) -/* D3CD0 800D30D0 11400003 */ beqz $t2, .L800D30E0 -/* D3CD4 800D30D4 2401EFFF */ addiu $at, $zero, -0x1001 -/* D3CD8 800D30D8 10000023 */ b .L800D3168 -/* D3CDC 800D30DC 02018024 */ and $s0, $s0, $at -.L800D30E0: -/* D3CE0 800D30E0 240A0001 */ addiu $t2, $zero, 0x1 -/* D3CE4 800D30E4 AD2A0000 */ sw $t2, 0x0($t1) -/* D3CE8 800D30E8 0C034C79 */ jal send_mesg -/* D3CEC 800D30EC 24040070 */ addiu $a0, $zero, 0x70 -/* D3CF0 800D30F0 3C0A800E */ lui $t2, %hi(__osRunQueue) -/* D3CF4 800D30F4 8D4A4888 */ lw $t2, %lo(__osRunQueue)($t2) -/* D3CF8 800D30F8 2401EFFF */ addiu $at, $zero, -0x1001 -/* D3CFC 800D30FC 02018024 */ and $s0, $s0, $at -/* D3D00 800D3100 8D5B0118 */ lw $k1, 0x118($t2) /* handwritten instruction */ -/* D3D04 800D3104 0361D824 */ and $k1, $k1, $at -/* D3D08 800D3108 10000017 */ b .L800D3168 -/* D3D0C 800D310C AD5B0118 */ sw $k1, 0x118($t2) /* handwritten instruction */ -glabel .L800D3110 -/* D3D10 800D3110 2401FDFF */ addiu $at, $zero, -0x201 -/* D3D14 800D3114 01014024 */ and $t0, $t0, $at -/* D3D18 800D3118 40886800 */ mtc0 $t0, $13 /* handwritten instruction */ -/* D3D1C 800D311C 0C034C79 */ jal send_mesg -/* D3D20 800D3120 24040008 */ addiu $a0, $zero, 0x8 -/* D3D24 800D3124 2401FDFF */ addiu $at, $zero, -0x201 -/* D3D28 800D3128 1000FF61 */ b .L800D2EB0 -/* D3D2C 800D312C 02018024 */ and $s0, $s0, $at -glabel .L800D3130 -/* D3D30 800D3130 2401FEFF */ addiu $at, $zero, -0x101 -/* D3D34 800D3134 01014024 */ and $t0, $t0, $at -/* D3D38 800D3138 40886800 */ mtc0 $t0, $13 /* handwritten instruction */ -/* D3D3C 800D313C 0C034C79 */ jal send_mesg -/* D3D40 800D3140 24040000 */ addiu $a0, $zero, 0x0 -/* D3D44 800D3144 2401FEFF */ addiu $at, $zero, -0x101 -/* D3D48 800D3148 1000FF59 */ b .L800D2EB0 -/* D3D4C 800D314C 02018024 */ and $s0, $s0, $at -.L800D3150: -/* D3D50 800D3150 24090001 */ addiu $t1, $zero, 0x1 -/* D3D54 800D3154 A7490012 */ sh $t1, 0x12($k0) /* handwritten instruction */ -/* D3D58 800D3158 0C034C79 */ jal send_mesg -/* D3D5C 800D315C 24040050 */ addiu $a0, $zero, 0x50 -/* D3D60 800D3160 10000001 */ b .L800D3168 -/* D3D64 800D3164 00000000 */ nop -glabel .L800D3168 -/* D3D68 800D3168 3C0A800E */ lui $t2, %hi(__osRunQueue) -/* D3D6C 800D316C 8D4A4888 */ lw $t2, %lo(__osRunQueue)($t2) -/* D3D70 800D3170 8F490004 */ lw $t1, 0x4($k0) /* handwritten instruction */ -/* D3D74 800D3174 8D4B0004 */ lw $t3, 0x4($t2) -/* D3D78 800D3178 012B082A */ slt $at, $t1, $t3 -/* D3D7C 800D317C 10200007 */ beqz $at, .L800D319C -/* D3D80 800D3180 00000000 */ nop -/* D3D84 800D3184 3C04800E */ lui $a0, %hi(__osRunQueue) -/* D3D88 800D3188 03402825 */ or $a1, $k0, $zero -/* D3D8C 800D318C 0C034CF3 */ jal __osEnqueueThread -/* D3D90 800D3190 24844888 */ addiu $a0, $a0, %lo(__osRunQueue) -/* D3D94 800D3194 08034D09 */ j __osDispatchThread -/* D3D98 800D3198 00000000 */ nop -.L800D319C: -/* D3D9C 800D319C 3C09800E */ lui $t1, %hi(__osRunQueue) -/* D3DA0 800D31A0 25294888 */ addiu $t1, $t1, %lo(__osRunQueue) -/* D3DA4 800D31A4 8D2A0000 */ lw $t2, 0x0($t1) -/* D3DA8 800D31A8 AF4A0000 */ sw $t2, 0x0($k0) /* handwritten instruction */ -/* D3DAC 800D31AC 08034D09 */ j __osDispatchThread -/* D3DB0 800D31B0 AD3A0000 */ sw $k0, 0x0($t1) /* handwritten instruction */ -.L800D31B4: -/* D3DB4 800D31B4 3C01800E */ lui $at, %hi(__osFaultedThread) -/* D3DB8 800D31B8 AC3A4894 */ sw $k0, %lo(__osFaultedThread)($at) /* handwritten instruction */ -/* D3DBC 800D31BC 24090001 */ addiu $t1, $zero, 0x1 -/* D3DC0 800D31C0 A7490010 */ sh $t1, 0x10($k0) /* handwritten instruction */ -/* D3DC4 800D31C4 24090002 */ addiu $t1, $zero, 0x2 -/* D3DC8 800D31C8 A7490012 */ sh $t1, 0x12($k0) /* handwritten instruction */ -/* D3DCC 800D31CC 400A4000 */ mfc0 $t2, $8 /* handwritten instruction */ -/* D3DD0 800D31D0 AF4A0124 */ sw $t2, 0x124($k0) /* handwritten instruction */ -/* D3DD4 800D31D4 0C034C79 */ jal send_mesg -/* D3DD8 800D31D8 24040060 */ addiu $a0, $zero, 0x60 -/* D3DDC 800D31DC 08034D09 */ j __osDispatchThread -/* D3DE0 800D31E0 00000000 */ nop -.end __osException +__osRdb_Mesg: + .word 0 -leaf send_mesg -/* D3DE4 800D31E4 3C0A8013 */ lui $t2, %hi(__osEventStateTab) -/* D3DE8 800D31E8 254ACCD0 */ addiu $t2, $t2, %lo(__osEventStateTab) -/* D3DEC 800D31EC 01445021 */ addu $t2, $t2, $a0 -/* D3DF0 800D31F0 8D490000 */ lw $t1, 0x0($t2) -/* D3DF4 800D31F4 03E09025 */ or $s2, $ra, $zero -/* D3DF8 800D31F8 11200025 */ beqz $t1, .L800D3290 -/* D3DFC 800D31FC 00000000 */ nop -/* D3E00 800D3200 8D2B0008 */ lw $t3, 0x8($t1) -/* D3E04 800D3204 8D2C0010 */ lw $t4, 0x10($t1) -/* D3E08 800D3208 016C082A */ slt $at, $t3, $t4 -/* D3E0C 800D320C 10200020 */ beqz $at, .L800D3290 -/* D3E10 800D3210 00000000 */ nop -/* D3E14 800D3214 8D2D000C */ lw $t5, 0xC($t1) -/* D3E18 800D3218 01AB6821 */ addu $t5, $t5, $t3 -/* D3E1C 800D321C 01AC001A */ div $zero, $t5, $t4 -/* D3E20 800D3220 15800002 */ bnez $t4, .L800D322C -/* D3E24 800D3224 00000000 */ nop -/* D3E28 800D3228 0007000D */ break 7 -.L800D322C: -/* D3E2C 800D322C 2401FFFF */ addiu $at, $zero, -0x1 -/* D3E30 800D3230 15810004 */ bne $t4, $at, .L800D3244 -/* D3E34 800D3234 3C018000 */ lui $at, (0x80000000 >> 16) -/* D3E38 800D3238 15A10002 */ bne $t5, $at, .L800D3244 -/* D3E3C 800D323C 00000000 */ nop -/* D3E40 800D3240 0006000D */ break 6 -.L800D3244: -/* D3E44 800D3244 8D2C0014 */ lw $t4, 0x14($t1) -/* D3E48 800D3248 00006810 */ mfhi $t5 -/* D3E4C 800D324C 000D6880 */ sll $t5, $t5, 2 -/* D3E50 800D3250 018D6021 */ addu $t4, $t4, $t5 -/* D3E54 800D3254 8D4D0004 */ lw $t5, 0x4($t2) -/* D3E58 800D3258 256A0001 */ addiu $t2, $t3, 0x1 -/* D3E5C 800D325C AD8D0000 */ sw $t5, 0x0($t4) -/* D3E60 800D3260 AD2A0008 */ sw $t2, 0x8($t1) -/* D3E64 800D3264 8D2A0000 */ lw $t2, 0x0($t1) -/* D3E68 800D3268 8D4B0000 */ lw $t3, 0x0($t2) -/* D3E6C 800D326C 11600008 */ beqz $t3, .L800D3290 -/* D3E70 800D3270 00000000 */ nop -/* D3E74 800D3274 0C034D05 */ jal __osPopThread -/* D3E78 800D3278 01202025 */ or $a0, $t1, $zero -/* D3E7C 800D327C 00405025 */ or $t2, $v0, $zero -/* D3E80 800D3280 3C04800E */ lui $a0, %hi(__osRunQueue) -/* D3E84 800D3284 01402825 */ or $a1, $t2, $zero -/* D3E88 800D3288 0C034CF3 */ jal __osEnqueueThread -/* D3E8C 800D328C 24844888 */ addiu $a0, $a0, %lo(__osRunQueue) -.L800D3290: -/* D3E90 800D3290 02400008 */ jr $s2 -/* D3E94 800D3294 00000000 */ nop -.end send_mesg +__os_Kdebug_Pkt: + .word 0 -leaf handle_CpU -/* D3E98 800D3298 3C013000 */ lui $at, (0x30000000 >> 16) -/* D3E9C 800D329C 01014824 */ and $t1, $t0, $at -/* D3EA0 800D32A0 00094F02 */ srl $t1, $t1, 28 -/* D3EA4 800D32A4 240A0001 */ addiu $t2, $zero, 0x1 -/* D3EA8 800D32A8 152AFFC2 */ bne $t1, $t2, .L800D31B4 -/* D3EAC 800D32AC 00000000 */ nop -/* D3EB0 800D32B0 8F5B0118 */ lw $k1, 0x118($k0) /* handwritten instruction */ -/* D3EB4 800D32B4 3C012000 */ lui $at, (0x20000000 >> 16) -/* D3EB8 800D32B8 24090001 */ addiu $t1, $zero, 0x1 -/* D3EBC 800D32BC 0361D825 */ or $k1, $k1, $at -/* D3EC0 800D32C0 AF490018 */ sw $t1, 0x18($k0) /* handwritten instruction */ -/* D3EC4 800D32C4 1000FFB5 */ b .L800D319C -/* D3EC8 800D32C8 AF5B0118 */ sw $k1, 0x118($k0) /* handwritten instruction */ -.end handle_CpU +#if BUILD_VERSION >= VERSION_K +__osPreviousThread: + .word 0 +#endif +#endif -leaf __osEnqueueAndYield -/* D3ECC 800D32CC 3C05800E */ lui $a1, %hi(__osRunningThread) -/* D3ED0 800D32D0 8CA54890 */ lw $a1, %lo(__osRunningThread)($a1) -/* D3ED4 800D32D4 40086000 */ mfc0 $t0, $12 /* handwritten instruction */ -/* D3ED8 800D32D8 8CBB0018 */ lw $k1, 0x18($a1) /* handwritten instruction */ -/* D3EDC 800D32DC 35080002 */ ori $t0, $t0, 0x2 -/* D3EE0 800D32E0 ACA80118 */ sw $t0, 0x118($a1) -/* D3EE4 800D32E4 FCB00098 */ sd $s0, 0x98($a1) -/* D3EE8 800D32E8 FCB100A0 */ sd $s1, 0xA0($a1) -/* D3EEC 800D32EC FCB200A8 */ sd $s2, 0xA8($a1) -/* D3EF0 800D32F0 FCB300B0 */ sd $s3, 0xB0($a1) -/* D3EF4 800D32F4 FCB400B8 */ sd $s4, 0xB8($a1) -/* D3EF8 800D32F8 FCB500C0 */ sd $s5, 0xC0($a1) -/* D3EFC 800D32FC FCB600C8 */ sd $s6, 0xC8($a1) -/* D3F00 800D3300 FCB700D0 */ sd $s7, 0xD0($a1) -/* D3F04 800D3304 FCBC00E8 */ sd $gp, 0xE8($a1) -/* D3F08 800D3308 FCBD00F0 */ sd $sp, 0xF0($a1) -/* D3F0C 800D330C FCBE00F8 */ sd $fp, 0xF8($a1) -/* D3F10 800D3310 FCBF0100 */ sd $ra, 0x100($a1) -/* D3F14 800D3314 13600009 */ beqz $k1, .L800D333C /* handwritten instruction */ -/* D3F18 800D3318 ACBF011C */ sw $ra, 0x11C($a1) -/* D3F1C 800D331C 445BF800 */ cfc1 $k1, $31 -/* D3F20 800D3320 F4B40180 */ sdc1 $f20, 0x180($a1) -/* D3F24 800D3324 F4B60188 */ sdc1 $f22, 0x188($a1) -/* D3F28 800D3328 F4B80190 */ sdc1 $f24, 0x190($a1) -/* D3F2C 800D332C F4BA0198 */ sdc1 $f26, 0x198($a1) -/* D3F30 800D3330 F4BC01A0 */ sdc1 $f28, 0x1A0($a1) -/* D3F34 800D3334 F4BE01A8 */ sdc1 $f30, 0x1A8($a1) -/* D3F38 800D3338 ACBB012C */ sw $k1, 0x12C($a1) /* handwritten instruction */ -.L800D333C: -/* D3F3C 800D333C 8CBB0118 */ lw $k1, 0x118($a1) /* handwritten instruction */ -/* D3F40 800D3340 3369FF00 */ andi $t1, $k1, 0xFF00 /* handwritten instruction */ -/* D3F44 800D3344 1120000D */ beqz $t1, .L800D337C -/* D3F48 800D3348 00000000 */ nop -/* D3F4C 800D334C 3C08800E */ lui $t0, %hi(__OSGlobalIntMask) -/* D3F50 800D3350 250838AC */ addiu $t0, $t0, %lo(__OSGlobalIntMask) -/* D3F54 800D3354 8D080000 */ lw $t0, 0x0($t0) -/* D3F58 800D3358 2401FFFF */ addiu $at, $zero, -0x1 -/* D3F5C 800D335C 01014026 */ xor $t0, $t0, $at -/* D3F60 800D3360 3C01FFFF */ lui $at, (0xFFFF00FF >> 16) -/* D3F64 800D3364 3108FF00 */ andi $t0, $t0, 0xFF00 -/* D3F68 800D3368 342100FF */ ori $at, $at, (0xFFFF00FF & 0xFFFF) -/* D3F6C 800D336C 01284825 */ or $t1, $t1, $t0 -/* D3F70 800D3370 0361D824 */ and $k1, $k1, $at -/* D3F74 800D3374 0369D825 */ or $k1, $k1, $t1 -/* D3F78 800D3378 ACBB0118 */ sw $k1, 0x118($a1) /* handwritten instruction */ -.L800D337C: -/* D3F7C 800D337C 3C1BA430 */ lui $k1, %hi(MI_INTR_MASK_REG) /* handwritten instruction */ -/* D3F80 800D3380 8F7B000C */ lw $k1, %lo(MI_INTR_MASK_REG)($k1) /* handwritten instruction */ -/* D3F84 800D3384 1360000B */ beqz $k1, .L800D33B4 /* handwritten instruction */ -/* D3F88 800D3388 00000000 */ nop -/* D3F8C 800D338C 3C1A800E */ lui $k0, %hi(__OSGlobalIntMask) /* handwritten instruction */ -/* D3F90 800D3390 275A38AC */ addiu $k0, $k0, %lo(__OSGlobalIntMask) /* handwritten instruction */ -/* D3F94 800D3394 8F5A0000 */ lw $k0, 0x0($k0) /* handwritten instruction */ -/* D3F98 800D3398 8CA80128 */ lw $t0, 0x128($a1) -/* D3F9C 800D339C 2401FFFF */ addiu $at, $zero, -0x1 -/* D3FA0 800D33A0 001AD402 */ srl $k0, $k0, 16 -/* D3FA4 800D33A4 0341D026 */ xor $k0, $k0, $at -/* D3FA8 800D33A8 335A003F */ andi $k0, $k0, 0x3F /* handwritten instruction */ -/* D3FAC 800D33AC 0348D024 */ and $k0, $k0, $t0 -/* D3FB0 800D33B0 037AD825 */ or $k1, $k1, $k0 -.L800D33B4: -/* D3FB4 800D33B4 10800003 */ beqz $a0, .L800D33C4 -/* D3FB8 800D33B8 ACBB0128 */ sw $k1, 0x128($a1) /* handwritten instruction */ -/* D3FBC 800D33BC 0C034CF3 */ jal __osEnqueueThread -/* D3FC0 800D33C0 00000000 */ nop -.L800D33C4: -/* D3FC4 800D33C4 08034D09 */ j __osDispatchThread -/* D3FC8 800D33C8 00000000 */ nop -.end __osEnqueueAndYield +.text -leaf __osEnqueueThread -/* D3FCC 800D33CC 8C980000 */ lw $t8, 0x0($a0) -/* D3FD0 800D33D0 8CAF0004 */ lw $t7, 0x4($a1) -/* D3FD4 800D33D4 0080C825 */ or $t9, $a0, $zero -/* D3FD8 800D33D8 8F0E0004 */ lw $t6, 0x4($t8) -/* D3FDC 800D33DC 01CF082A */ slt $at, $t6, $t7 -/* D3FE0 800D33E0 14200007 */ bnez $at, .L800D3400 -/* D3FE4 800D33E4 00000000 */ nop -.L800D33E8: -/* D3FE8 800D33E8 0300C825 */ or $t9, $t8, $zero -/* D3FEC 800D33EC 8F180000 */ lw $t8, 0x0($t8) -/* D3FF0 800D33F0 8F0E0004 */ lw $t6, 0x4($t8) -/* D3FF4 800D33F4 01CF082A */ slt $at, $t6, $t7 -/* D3FF8 800D33F8 1020FFFB */ beqz $at, .L800D33E8 -/* D3FFC 800D33FC 00000000 */ nop -.L800D3400: -/* D4000 800D3400 8F380000 */ lw $t8, 0x0($t9) -/* D4004 800D3404 ACB80000 */ sw $t8, 0x0($a1) -/* D4008 800D3408 AF250000 */ sw $a1, 0x0($t9) -/* D400C 800D340C 03E00008 */ jr $ra -/* D4010 800D3410 ACA40008 */ sw $a0, 0x8($a1) -.end __osEnqueueThread +/** + * The exception preamble is copied to the exception vectors at + * UT_VEC, XUT_VEC, ECC_VEC, E_VEC, to direct execution to __osException + */ +LEAF(__osExceptionPreamble) + la k0, __osException + jr k0 +END(__osExceptionPreamble) -leaf __osPopThread -/* D4014 800D3414 8C820000 */ lw $v0, 0x0($a0) -/* D4018 800D3418 8C590000 */ lw $t9, 0x0($v0) -/* D401C 800D341C 03E00008 */ jr $ra -/* D4020 800D3420 AC990000 */ sw $t9, 0x0($a0) -.end __osPopThread +#ifndef _FINALROM +LEAF(__ptExceptionPreamble) +.set noreorder + sw k0, -0x10(sp) + b pt_next + lui k0, %hi(__ptException) + nop + nop +pt_next: + addiu k0, k0, %lo(__ptException) + jr k0 + nop +.set reorder +END(__ptExceptionPreamble) -leaf __osDispatchThread -/* D4024 800D3424 3C04800E */ lui $a0, %hi(__osRunQueue) -/* D4028 800D3428 0C034D05 */ jal __osPopThread -/* D402C 800D342C 24844888 */ addiu $a0, $a0, %lo(__osRunQueue) -/* D4030 800D3430 3C01800E */ lui $at, %hi(__osRunningThread) -/* D4034 800D3434 AC224890 */ sw $v0, %lo(__osRunningThread)($at) -/* D4038 800D3438 24080004 */ addiu $t0, $zero, 0x4 -/* D403C 800D343C A4480010 */ sh $t0, 0x10($v0) -/* D4040 800D3440 0040D025 */ or $k0, $v0, $zero -/* D4044 800D3444 3C08800E */ lui $t0, %hi(__OSGlobalIntMask) -/* D4048 800D3448 8F5B0118 */ lw $k1, 0x118($k0) /* handwritten instruction */ -/* D404C 800D344C 250838AC */ addiu $t0, $t0, %lo(__OSGlobalIntMask) -/* D4050 800D3450 8D080000 */ lw $t0, 0x0($t0) -/* D4054 800D3454 3C01FFFF */ lui $at, (0xFFFF00FF >> 16) -/* D4058 800D3458 3369FF00 */ andi $t1, $k1, 0xFF00 /* handwritten instruction */ -/* D405C 800D345C 342100FF */ ori $at, $at, (0xFFFF00FF & 0xFFFF) -/* D4060 800D3460 3108FF00 */ andi $t0, $t0, 0xFF00 -/* D4064 800D3464 01284824 */ and $t1, $t1, $t0 -/* D4068 800D3468 0361D824 */ and $k1, $k1, $at -/* D406C 800D346C 0369D825 */ or $k1, $k1, $t1 -/* D4070 800D3470 409B6000 */ mtc0 $k1, $12 /* handwritten instruction */ -/* D4074 800D3474 DF5B0108 */ ld $k1, 0x108($k0) /* handwritten instruction */ -/* D4078 800D3478 DF410020 */ ld $at, 0x20($k0) /* handwritten instruction */ -/* D407C 800D347C DF420028 */ ld $v0, 0x28($k0) /* handwritten instruction */ -/* D4080 800D3480 03600013 */ mtlo $k1 -/* D4084 800D3484 DF5B0110 */ ld $k1, 0x110($k0) /* handwritten instruction */ -/* D4088 800D3488 DF430030 */ ld $v1, 0x30($k0) /* handwritten instruction */ -/* D408C 800D348C DF440038 */ ld $a0, 0x38($k0) /* handwritten instruction */ -/* D4090 800D3490 DF450040 */ ld $a1, 0x40($k0) /* handwritten instruction */ -/* D4094 800D3494 DF460048 */ ld $a2, 0x48($k0) /* handwritten instruction */ -/* D4098 800D3498 DF470050 */ ld $a3, 0x50($k0) /* handwritten instruction */ -/* D409C 800D349C DF480058 */ ld $t0, 0x58($k0) /* handwritten instruction */ -/* D40A0 800D34A0 DF490060 */ ld $t1, 0x60($k0) /* handwritten instruction */ -/* D40A4 800D34A4 DF4A0068 */ ld $t2, 0x68($k0) /* handwritten instruction */ -/* D40A8 800D34A8 DF4B0070 */ ld $t3, 0x70($k0) /* handwritten instruction */ -/* D40AC 800D34AC DF4C0078 */ ld $t4, 0x78($k0) /* handwritten instruction */ -/* D40B0 800D34B0 DF4D0080 */ ld $t5, 0x80($k0) /* handwritten instruction */ -/* D40B4 800D34B4 DF4E0088 */ ld $t6, 0x88($k0) /* handwritten instruction */ -/* D40B8 800D34B8 DF4F0090 */ ld $t7, 0x90($k0) /* handwritten instruction */ -/* D40BC 800D34BC DF500098 */ ld $s0, 0x98($k0) /* handwritten instruction */ -/* D40C0 800D34C0 DF5100A0 */ ld $s1, 0xA0($k0) /* handwritten instruction */ -/* D40C4 800D34C4 DF5200A8 */ ld $s2, 0xA8($k0) /* handwritten instruction */ -/* D40C8 800D34C8 DF5300B0 */ ld $s3, 0xB0($k0) /* handwritten instruction */ -/* D40CC 800D34CC DF5400B8 */ ld $s4, 0xB8($k0) /* handwritten instruction */ -/* D40D0 800D34D0 DF5500C0 */ ld $s5, 0xC0($k0) /* handwritten instruction */ -/* D40D4 800D34D4 DF5600C8 */ ld $s6, 0xC8($k0) /* handwritten instruction */ -/* D40D8 800D34D8 DF5700D0 */ ld $s7, 0xD0($k0) /* handwritten instruction */ -/* D40DC 800D34DC DF5800D8 */ ld $t8, 0xD8($k0) /* handwritten instruction */ -/* D40E0 800D34E0 DF5900E0 */ ld $t9, 0xE0($k0) /* handwritten instruction */ -/* D40E4 800D34E4 DF5C00E8 */ ld $gp, 0xE8($k0) /* handwritten instruction */ -/* D40E8 800D34E8 03600011 */ mthi $k1 -/* D40EC 800D34EC DF5D00F0 */ ld $sp, 0xF0($k0) /* handwritten instruction */ -/* D40F0 800D34F0 DF5E00F8 */ ld $fp, 0xF8($k0) /* handwritten instruction */ -/* D40F4 800D34F4 DF5F0100 */ ld $ra, 0x100($k0) /* handwritten instruction */ -/* D40F8 800D34F8 8F5B011C */ lw $k1, 0x11C($k0) /* handwritten instruction */ -/* D40FC 800D34FC 409B7000 */ mtc0 $k1, $14 /* handwritten instruction */ -/* D4100 800D3500 8F5B0018 */ lw $k1, 0x18($k0) /* handwritten instruction */ -/* D4104 800D3504 13600013 */ beqz $k1, .L800D3554 /* handwritten instruction */ -/* D4108 800D3508 00000000 */ nop -/* D410C 800D350C 8F5B012C */ lw $k1, 0x12C($k0) /* handwritten instruction */ -/* D4110 800D3510 44DBF800 */ ctc1 $k1, $31 -/* D4114 800D3514 D7400130 */ ldc1 $f0, 0x130($k0) -/* D4118 800D3518 D7420138 */ ldc1 $f2, 0x138($k0) -/* D411C 800D351C D7440140 */ ldc1 $f4, 0x140($k0) -/* D4120 800D3520 D7460148 */ ldc1 $f6, 0x148($k0) -/* D4124 800D3524 D7480150 */ ldc1 $f8, 0x150($k0) -/* D4128 800D3528 D74A0158 */ ldc1 $f10, 0x158($k0) -/* D412C 800D352C D74C0160 */ ldc1 $f12, 0x160($k0) -/* D4130 800D3530 D74E0168 */ ldc1 $f14, 0x168($k0) -/* D4134 800D3534 D7500170 */ ldc1 $f16, 0x170($k0) -/* D4138 800D3538 D7520178 */ ldc1 $f18, 0x178($k0) -/* D413C 800D353C D7540180 */ ldc1 $f20, 0x180($k0) -/* D4140 800D3540 D7560188 */ ldc1 $f22, 0x188($k0) -/* D4144 800D3544 D7580190 */ ldc1 $f24, 0x190($k0) -/* D4148 800D3548 D75A0198 */ ldc1 $f26, 0x198($k0) -/* D414C 800D354C D75C01A0 */ ldc1 $f28, 0x1A0($k0) -/* D4150 800D3550 D75E01A8 */ ldc1 $f30, 0x1A8($k0) -.L800D3554: -/* D4154 800D3554 8F5B0128 */ lw $k1, 0x128($k0) /* handwritten instruction */ -/* D4158 800D3558 3C1A800E */ lui $k0, %hi(__OSGlobalIntMask) /* handwritten instruction */ -/* D415C 800D355C 275A38AC */ addiu $k0, $k0, %lo(__OSGlobalIntMask) /* handwritten instruction */ -/* D4160 800D3560 8F5A0000 */ lw $k0, 0x0($k0) /* handwritten instruction */ -/* D4164 800D3564 001AD402 */ srl $k0, $k0, 16 -/* D4168 800D3568 037AD824 */ and $k1, $k1, $k0 -/* D416C 800D356C 001BD840 */ sll $k1, $k1, 1 -/* D4170 800D3570 3C1A800F */ lui $k0, %hi(__osRcpImTable) /* handwritten instruction */ -/* D4174 800D3574 275A94D0 */ addiu $k0, $k0, %lo(__osRcpImTable) /* handwritten instruction */ -/* D4178 800D3578 037AD821 */ addu $k1, $k1, $k0 -/* D417C 800D357C 977B0000 */ lhu $k1, 0x0($k1) /* handwritten instruction */ -/* D4180 800D3580 3C1AA430 */ lui $k0, %hi(MI_INTR_MASK_REG) /* handwritten instruction */ -/* D4184 800D3584 275A000C */ addiu $k0, $k0, %lo(MI_INTR_MASK_REG) /* handwritten instruction */ -/* D4188 800D3588 AF5B0000 */ sw $k1, 0x0($k0) /* handwritten instruction */ -/* D418C 800D358C 00000000 */ nop -/* D4190 800D3590 00000000 */ nop -/* D4194 800D3594 00000000 */ nop -/* D4198 800D3598 00000000 */ nop -/* D419C 800D359C 42000018 */ eret /* handwritten instruction */ -.end __osDispatchThread +LEAF(__ptException) +.set noreorder + mfc0 k0, C0_CAUSE + andi k0, k0, 0x7c + bnez k0, pt_not_Int + srl k0, k0, 2 + mfc0 k0, C0_CAUSE + nop + andi k0, k0, CAUSE_IP7 + beqz k0, __osException + nop + j pt_break + nop +pt_not_Int: + sw k1, -8(sp) + /* determine if the pt exception handler should deal with this cause */ + la k1, __osCauseTable_pt + add k1, k1, k0 + lbu k0, (k1) + beqz k0, __osException + nop +pt_break: +pi_ok_loop: + lw k0, PHYS_TO_K1(PI_STATUS_REG) + nop + andi k0, k0, (PI_STATUS_DMA_BUSY | PI_STATUS_IO_BUSY) + bnez k0, pi_ok_loop + nop + lw k0, KMC_STAT + nop + andi k0, k0, 8 + bnez k0, pt_prof + li k0, KMC_CODE_ENTRY + lw k1, -8(sp) + jr k0 + addiu sp, sp, -0x60 +pt_prof: + mfc0 k0, C0_EPC + /* the following two ways is a (necessarily) messy way to write "sw k0, KMC_WPORT" without using at */ + lui k1, (KMC_WPORT >> 16 + 1) + sw k0, -(KMC_WPORT & 0xFFFF)(k1) + lw k1, -8(sp) + lw k0, -0x10(sp) + eret + nop +.set reorder +END(__ptException) +#endif -leaf __osCleanupThread -/* D41A0 800D35A0 0C035980 */ jal osDestroyThread -/* D41A4 800D35A4 00002025 */ or $a0, $zero, $zero -.end __osCleanupThread +LEAF(__osException) + /* Load scratch space for thread saving */ + la k0, __osThreadSave + /* Save AT */ +.set noat + sd $1, THREAD_GP1(k0); +.set at + /* Save SR */ + MFC0( k1, C0_SR) + sw k1, THREAD_SR(k0) + /* Disable interrupts */ + and k1, k1, ~(SR_IE | SR_EXL) + MTC0( k1, C0_SR) + /* Save some temp registers for use in the following */ + sd $8, THREAD_GP8(k0) + sd $9, THREAD_GP9(k0) + sd $10, THREAD_GP10(k0) + /* Mark FPU as unused */ + sw zero, THREAD_FP(k0) + /* This instruction is useless, leftover because of bad placement of an ifdef for the debug version */ + MFC0( t0, C0_CAUSE) +#ifndef _FINALROM + lw t2, __kmc_pt_mode + bnez t2, skip_kmc_mode + andi t1, t0, 0x7c + li t2, 0 + bne t1, t2, savecontext + and t1, k1, t0 + andi t2, t1, CAUSE_IP7 + beqz t2, notIP7 + /* clear rdb write interrupt */ + la t1, RDB_WRITE_INTR_REG + sw zero, (t1) +IP7check: + MFC0( t0, C0_CAUSE) + andi t0, t0, CAUSE_IP7 + bne zero, t0, IP7check + la t2, RDB_BASE_REG + lw t0, (t2) + srl t1, t0, 0x1a + andi t1, t1, 0x3f + li t2, RDB_TYPE_HtoG_DATA + beq t1, t2, HandData + li t2, RDB_TYPE_HtoG_DEBUG + beq t1, t2, HandDbg + li t2, RDB_TYPE_HtoG_KDEBUG + beq t1, t2, HandKDebug + li t2, RDB_TYPE_HtoG_DEBUG_CT + beq t1, t2, DbgCnt + li t2, RDB_TYPE_HtoG_DATA_DONE + beq t1, t2, DataRead + li t2, RDB_TYPE_HtoG_LOG_DONE + beq t1, t2, LogRead + li t2, RDB_TYPE_HtoG_REQ_RAMROM + beq t1, t2, ReqRamrom + li t2, RDB_TYPE_HtoG_FREE_RAMROM + beq t1, t2, FreeRamrom + li t2, RDB_TYPE_HtoG_PROF_SIGNAL + beq t1, t2, SignalProf + b rdbout +SignalProf: + li t2, 1 + srl t1, t0, 0x10 + andi t1, t1, 0xff + beq t1, t2, AckProf + li t2, 0xa8 + sw t2, __osRdb_Mesg + b savecontext +AckProf: + li t2, 0xb0 + sw t2, __osRdb_Mesg + b savecontext +HandKDebug: + sw t0, __os_Kdebug_Pkt + b savecontext +DbgCnt: + li t2, 0xffffff + and t1, t0, t2 + sw t1, __osRdb_DbgRead_Ct + b rdbout +DataRead: + li t2, 0x88 + sw t2, __osRdb_Mesg + b savecontext +LogRead: + li t2, 0x80 + sw t2, __osRdb_Mesg + b savecontext +ReqRamrom: + li t2, 0x90 + sw t2, __osRdb_Mesg + b savecontext +FreeRamrom: + li t2, 0x98 + sw t2, __osRdb_Mesg + b savecontext +HandData: + srl t1, t0, 0x18 + andi t1, t1, 3 + beq zero, t1, rdbout + lw t2, __osRdb_Read_Data_Ct + subu t2, t2, t1 + sw t2, __osRdb_Read_Data_Ct + sd t3, THREAD_GP11(k0) + lw t3, __osRdb_Read_Data_Buf + srl t2, t0, 0x10 + andi t2, t2, 0xff + sb t2, (t3) + addi t3, t3, 1 + addi t1, t1, -1 + beq zero, t1, doneData + srl t2, t0, 8 + andi t2, t2, 0xff + sb t2, (t3) + addi t3, t3, 1 + addi t1, t1, -1 + beq zero, t1, doneData + andi t0, t0, 0xff + sb t0, (t3) + addi t3, t3, 1 +doneData: + sw t3, __osRdb_Read_Data_Buf + ld t3, THREAD_GP11(k0) + lw t2, __osRdb_Read_Data_Ct + bne zero, t2, rdbout + li t2, 0x78 + sw t2, __osRdb_Mesg + b savecontext +HandDbg: + srl t1, t0, 0x18 + andi t1, t1, 3 + beq zero, t1, rdbout + lw t2, __osRdb_DbgRead_Ct + subu t2, t2, t1 + sw t2, __osRdb_DbgRead_Ct + sd t3, THREAD_GP11(k0) + lw t3, __osRdb_DbgRead_Buf + bne zero, t3, 1f + ld t3, THREAD_GP11(k0) + b rdbout +1: + srl t2, t0, 0x10 + andi t2, t2, 0xff + sb t2, (t3) + addi t3, t3, 1 + addi t1, t1, -1 + beq zero, t1, doneDbg + srl t2, t0, 8 + andi t2, t2, 0xff + sb t2, (t3) + addi t3, t3, 1 + addi t1, t1, -1 + beq zero, t1, doneDbg + andi t0, t0, 0xff + sb t0, (t3) + addi t3, t3, 1 +doneDbg: + sw t3, __osRdb_DbgRead_Buf + ld t3, THREAD_GP11(k0) + lw t2, __osRdb_DbgRead_Ct + bne zero, t2, rdbout + li t2, 0xa0 + sw t2, __osRdb_Mesg + b savecontext +notIP7: + andi t2, t1, CAUSE_IP6 + beqz t2, savecontext + /* clear rdb read interrupt */ + la t1, RDB_READ_INTR_REG + sw zero, (t1) + lw t2, __osRdb_IP6_Ct + bnez t2, 2f + li t2, 1 + sw t2, __osRdb_IP6_Empty + b rdbout +2: + addi t2, t2, -1 + sw t2, __osRdb_IP6_Ct + lw t0, __osRdb_IP6_Data + lw t1, __osRdb_IP6_CurSend + sll t2, t1, 2 + add t0, t2, t0 + lw t2, (t0) + addi t1, t1, 1 + lw t0, __osRdb_IP6_Size + sub t0, t0, t1 + bgtz t0, 5f + li t1, 0 +5: + sw t1, __osRdb_IP6_CurSend +checkIP6: + MFC0( t0, C0_CAUSE) + andi t0, t0, CAUSE_IP6 + bne zero, t0, checkIP6 + la t0, RDB_BASE_REG + sw t2, (t0) +rdbout: + ld t0, THREAD_GP8(k0) + ld t1, THREAD_GP9(k0) + ld t2, THREAD_GP10(k0) +.set noat + ld $1, THREAD_GP1(k0) +.set at + lw k1, THREAD_SR(k0) + MTC0( k1, C0_SR) +.set noreorder + nop + nop + nop + nop + eret +.set reorder + +skip_kmc_mode: +#endif + +savecontext: + /* Save the context of the previously running thread to be restored when it resumes */ + move t0, k0 + lw k0, __osRunningThread +#if !defined(_FINALROM) && BUILD_VERSION >= VERSION_K + sw k0, __osPreviousThread +#endif + ld t1, THREAD_GP1(t0) + sd t1, THREAD_GP1(k0) + ld t1, THREAD_SR(t0) + sd t1, THREAD_SR(k0) + ld t1, THREAD_GP8(t0) + sd t1, THREAD_GP8(k0) + ld t1, THREAD_GP9(t0) + sd t1, THREAD_GP9(k0) + ld t1, THREAD_GP10(t0) + sd t1, THREAD_GP10(k0) +3: + sd $2, THREAD_GP2(k0) + sd $3, THREAD_GP3(k0) + sd $4, THREAD_GP4(k0) + sd $5, THREAD_GP5(k0) + sd $6, THREAD_GP6(k0) + sd $7, THREAD_GP7(k0) + sd $11, THREAD_GP11(k0) + sd $12, THREAD_GP12(k0) + sd $13, THREAD_GP13(k0) + sd $14, THREAD_GP14(k0) + sd $15, THREAD_GP15(k0) + sd $16, THREAD_GP16(k0) + sd $17, THREAD_GP17(k0) + sd $18, THREAD_GP18(k0) + sd $19, THREAD_GP19(k0) + sd $20, THREAD_GP20(k0) + sd $21, THREAD_GP21(k0) + sd $22, THREAD_GP22(k0) + sd $23, THREAD_GP23(k0) + sd $24, THREAD_GP24(k0) + sd $25, THREAD_GP25(k0) + sd $28, THREAD_GP28(k0) + sd $29, THREAD_GP29(k0) + sd $30, THREAD_GP30(k0) + sd $31, THREAD_GP31(k0) + + mflo t0 + sd t0, THREAD_LO(k0) + mfhi t0 + sd t0, THREAD_HI(k0) + + lw k1, THREAD_SR(k0) + andi t1, k1, SR_IMASK + beqz t1, savercp + + /* + * If any CPU interrupts are enabled in the SR of the previous thread, bitwise-OR in the + * disabled CPU interrupts from the global interrupt mask. + * This is an attempt at reverting the effect of masking the SR of the thread with the + * global interrupt mask. This is however broken, see comments for osSetIntMask. + */ + la t0, __OSGlobalIntMask + lw t0, 0(t0) +#if BUILD_VERSION >= VERSION_H + xor t2, t0, ~0 /* not except not using not */ + andi t2, t2, SR_IMASK + or ta0, t1, t2 + and t3, k1, ~SR_IMASK + or t3, t3, ta0 + sw t3, THREAD_SR(k0) + andi t0, t0, SR_IMASK + and t1, t1, t0 + and k1, k1, ~SR_IMASK + or k1, k1, t1 +#else + xor t0, t0, ~0 /* not except not using not */ + andi t0, t0, SR_IMASK + or t1, t1, t0 + and k1, k1, ~SR_IMASK + or k1, k1, t1 + sw k1, THREAD_SR(k0) +#endif +savercp: + + /* Save the currently masked RCP interrupts. */ + lw t1, PHYS_TO_K1(MI_INTR_MASK_REG) + beqz t1, endrcp + + /* + * Similar to the above comment, but for RCP interrupt enable bits rather than CPU. + * This suffers from the same problem as above. + */ + la t0, __OSGlobalIntMask + lw t0, 0(t0) + + srl t0, t0, 0x10 + xor t0, t0, ~0 + andi t0, t0, 0x3f + lw ta0, THREAD_RCP(k0) + and t0, t0, ta0 + or t1, t1, t0 +endrcp: + sw t1, THREAD_RCP(k0) + MFC0( t0, C0_EPC) + sw t0, THREAD_PC(k0) + lw t0, THREAD_FP(k0) + beqz t0, 1f + /* Save FP Registers if FPU was used by the thread */ + CFC1( t0, fcr31) + NOP + sw t0, THREAD_FPCSR(k0) + sdc1 $f0, THREAD_FP0(k0) + sdc1 $f2, THREAD_FP2(k0) + sdc1 $f4, THREAD_FP4(k0) + sdc1 $f6, THREAD_FP6(k0) + sdc1 $f8, THREAD_FP8(k0) + sdc1 $f10, THREAD_FP10(k0) + sdc1 $f12, THREAD_FP12(k0) + sdc1 $f14, THREAD_FP14(k0) + sdc1 $f16, THREAD_FP16(k0) + sdc1 $f18, THREAD_FP18(k0) + sdc1 $f20, THREAD_FP20(k0) + sdc1 $f22, THREAD_FP22(k0) + sdc1 $f24, THREAD_FP24(k0) + sdc1 $f26, THREAD_FP26(k0) + sdc1 $f28, THREAD_FP28(k0) + sdc1 $f30, THREAD_FP30(k0) +1: + /* + * Determine the cause of the exception or interrupt and + * enter appropriate handling routine + */ + MFC0( t0, C0_CAUSE) + sw t0, THREAD_CAUSE(k0) + +.set noreorder + li t1, OS_STATE_RUNNABLE + sh t1, THREAD_STATE(k0) +.set reorder + +#ifndef _FINALROM + lw a0, __os_Kdebug_Pkt + beqz a0, no_kdebug + sw zero, __os_Kdebug_Pkt + jal kdebugserver + b __osDispatchThreadSave +no_kdebug: + lw a0, __osRdb_Mesg + beqz a0, no_rdb_mesg + sw zero, __osRdb_Mesg + jal send_mesg + lw t0, 0x120(k0) +no_rdb_mesg: +#endif + + andi t1, t0, CAUSE_EXCMASK + /* Test for break exception */ + li t2, EXC_BREAK + beq t1, t2, handle_break + + /* Test for CpU (coprocessor unusable) exception */ + li t2, EXC_CPU + beq t1, t2, handle_CpU + + /* Test for interrupt, if it is not an interrupt, panic */ + li t2, EXC_INT + bne t1, t2, panic +handle_interrupt: + and s0, k1, t0 +next_interrupt: + /* + * Handle external interrupt causes, using a jump table + * to enter into the appropriate handler + */ + andi t1, s0, SR_IMASK + srl t2, t1, 0xc + bnez t2, 1f + + srl t2, t1, SR_IMASKSHIFT + addi t2, t2, 16 +1: + + lbu t2, __osIntOffTable(t2) + + lw t2, __osIntTable(t2) + jr t2 + +/** + * IP6 Interrupt + * Only signalled by development hardware + */ +IP6_Hdlr: + /* Mask out interrupt and continue */ + and s0, s0, ~CAUSE_IP6 + b next_interrupt + +/** + * IP7 Interrupt + * Only signalled by development hardware + */ +IP7_Hdlr: + /* Mask out interrupt and continue */ + and s0, s0, ~CAUSE_IP7 + b next_interrupt + +/** + * IP8/Counter Interrupt + * Once the cop0 count register reaches the value of the + * cop0 compare register, this interrupt is triggered + */ +counter: + MFC0( t1, C0_COMPARE) + MTC0( t1, C0_COMPARE) + li a0, MESG(OS_EVENT_COUNTER) + /* Post counter message */ + jal send_mesg + /* Mask out interrupt and continue */ + and s0, s0, ~CAUSE_IP8 + b next_interrupt + +/** + * IP4/Cartridge Interrupt + * Signalled by the N64 Disk Drive + */ +cart: +#if BUILD_VERSION >= VERSION_J + /* Mask out interrupt */ + and s0, s0, ~CAUSE_IP4 + /* Load cart callback set by __osSetHWIntrRoutine */ + la t1, __osHwIntTable + add t1, HWINTR_SIZE + lw t2, HWINTR_CALLBACK(t1) + + /* If the callback is NULL, handling is done */ + beqz t2, 1f + + /* Set up a stack and run the callback */ + lw sp, HWINTR_SP(t1) + jalr t2 + + beqz v0, 1f + /* Redispatch immediately if the callback returned nonzero */ + b redispatch + +1: + /* Post a cart event message */ + li a0, MESG(OS_EVENT_CART) + jal send_mesg + /* Continue */ + b next_interrupt +#else + li a0, MESG(OS_EVENT_CART) + /* Mask out interrupt */ + and s0, s0, ~CAUSE_IP4 + la sp, leoDiskStack + addiu sp, 0x1000 - 0x10 # Stack size minus initial frame + /* Load cart callback set by __osSetHWIntrRoutine */ + li t2, HWINTR_SIZE + lw t2, __osHwIntTable(t2) + + /* If the callback is NULL, handling is done */ + beqz t2, 1f + + /* Set up a stack and run the callback */ + jalr t2 +#if BUILD_VERSION >= VERSION_H + li a0, MESG(OS_EVENT_CART) +#endif + + beqz v0, 1f + /* Redispatch immediately if the callback returned nonzero */ + b redispatch + +1: + /* Post a cart event message */ + jal send_mesg + /* Continue */ + b next_interrupt +#endif + +/** + * IP3/RCP Interrupt + * Signalled by the RCP for various reasons, described below + */ +rcp: + /* + * Load the MI interrupts and mask with the RCP bits in the global interrupt mask + * + * @bug this clobbers the t0 register which is expected to hold the value of the + * C0_CAUSE register in the sw1 and sw2 handlers. If the sw1 or sw2 handler runs + * after this, the interrupt will not be cleared properly. + */ + lw s1, PHYS_TO_K1(MI_INTR_REG) + la t0, __OSGlobalIntMask + lw t0, (t0) + + srl t0, t0, 0x10 + and s1, s1, t0 + +/** + * Signal Processor (SP) Interrupt + */ + /* Test for sp interrupt */ + andi t1, s1, MI_INTR_SP + beqz t1, vi + + /* Test for yielded or done signals in particular */ + + /* Mask out SP interrupt */ + andi s1, s1, (MI_INTR_SI | MI_INTR_AI | MI_INTR_VI | MI_INTR_PI | MI_INTR_DP) + lw ta0, PHYS_TO_K1(SP_STATUS_REG) +#if BUILD_VERSION >= VERSION_H + li t1, (SP_CLR_INTR | SP_CLR_SIG3) +#else + li t1, SP_CLR_INTR +#endif + + /* Clear interrupt and signal 3 */ + sw t1, PHYS_TO_K1(SP_STATUS_REG) + andi ta0, ta0, (SP_STATUS_YIELDED | SP_STATUS_TASKDONE) + beqz ta0, sp_other_break + + /* Post an SP event message */ + li a0, MESG(OS_EVENT_SP) + jal send_mesg + + beqz s1, NoMoreRcpInts + + /* Step over sp_other_break handler */ + b vi + +sp_other_break: + /* + * An sp signal that is not due to yielding or task completion, such as + * an sp breakpoint. Post a different event message + */ + li a0, MESG(OS_EVENT_SP_BREAK) + jal send_mesg + + beqz s1, NoMoreRcpInts + +/** + * Video Interface (VI) Interrupt + */ +vi: + /* Test for vi interrupt */ + andi t1, s1, MI_INTR_VI + beqz t1, ai + + /* Mask out vi interrupt */ + andi s1, s1, (MI_INTR_SP | MI_INTR_SI | MI_INTR_AI | MI_INTR_PI | MI_INTR_DP) + + /* Clear interrupt */ + sw zero, PHYS_TO_K1(VI_CURRENT_REG) + + /* Post vi event message */ + li a0, MESG(OS_EVENT_VI) + jal send_mesg + beqz s1, NoMoreRcpInts + +/** + * Audio Interface (AI) Interrupt + */ +ai: + /* Test for ai interrupt */ + andi t1, s1, MI_INTR_AI + beqz t1, si + + /* Mask out ai interrupt */ + andi s1, s1, (MI_INTR_SP | MI_INTR_SI | MI_INTR_VI | MI_INTR_PI | MI_INTR_DP) + + li t1, 1 + /* Clear interrupt */ + sw t1, PHYS_TO_K1(AI_STATUS_REG) + + /* Post ai event message */ + li a0, MESG(OS_EVENT_AI) + jal send_mesg + beqz s1, NoMoreRcpInts + +/** + * Serial Interface (SI) Interrupt + */ +si: + /* Test for si interrupt */ + andi t1, s1, MI_INTR_SI + beqz t1, pi + + /* Mask out si interrupt */ + andi s1, s1, (MI_INTR_SP | MI_INTR_AI | MI_INTR_VI | MI_INTR_PI | MI_INTR_DP) + /* Clear interrupt */ + sw zero, PHYS_TO_K1(SI_STATUS_REG) + + /* Post si event message */ + li a0, MESG(OS_EVENT_SI) + jal send_mesg + beqz s1, NoMoreRcpInts + +/** + * Parallel Interface (PI) Interrupt + */ +pi: + /* Test for pi interrupt */ + andi t1, s1, MI_INTR_PI + beqz t1, dp + + /* Mask out pi interrupt */ + andi s1, s1, (MI_INTR_SP | MI_INTR_SI | MI_INTR_AI | MI_INTR_VI | MI_INTR_DP) + + /* Clear interrupt */ + li t1, PI_STATUS_CLR_INTR + sw t1, PHYS_TO_K1(PI_STATUS_REG) + +#if BUILD_VERSION >= VERSION_J + /* Load pi callback */ + la t1, __osPiIntTable + lw t2, (t1) + /* Skip callback if NULL */ + beqz t2, 1f + + /* Set up a stack and run the callback */ + lw sp, 4(t1) + move a0, v0 + jalr t2 + + /* If the callback returns non-zero, do not post a pi event message */ + bnez v0, 2f +1: +#endif + /* Post pi event message */ + li a0, MESG(OS_EVENT_PI) + jal send_mesg +#if BUILD_VERSION >= VERSION_J +2: +#endif + beqz s1, NoMoreRcpInts + +/** + * Display Processor (DP) Interrupt + */ +dp: + /* Test for dp interrupt */ + andi t1, s1, MI_INTR_DP + beqz t1, NoMoreRcpInts + + /* Mask out dp interrupt */ + andi s1, s1, (MI_INTR_SP | MI_INTR_SI | MI_INTR_AI | MI_INTR_VI | MI_INTR_PI) + + /* Clear dp interrupt */ + li t1, MI_CLR_DP_INTR + sw t1, PHYS_TO_K1(MI_INIT_MODE_REG) + + /* Post dp event message */ + li a0, MESG(OS_EVENT_DP) + jal send_mesg + +NoMoreRcpInts: + /* Mask out interrupt and continue */ + and s0, s0, ~CAUSE_IP3 + b next_interrupt + +/** + * IP5/PreNMI Interrupt + * Reset button has been pressed + */ +prenmi: + /* Disable IP5/PreNMI interrupt for the previously running thread */ + lw k1, THREAD_SR(k0) + + and k1, k1, ~CAUSE_IP5 + sw k1, THREAD_SR(k0) + /* Test __osShutdown for first PreNMI event */ + la t1, __osShutdown + lw t2, 0(t1) + beqz t2, firstnmi + + /* Mask out interrupt and redispatch immediately */ + and s0, s0, ~CAUSE_IP5 + b redispatch + +firstnmi: + /* Set __osShutdown */ + li t2, 1 + sw t2, (t1) + /* Post a PreNMI event message */ + li a0, MESG(OS_EVENT_PRENMI) + jal send_mesg + + /* Mask out and disable IP5/PreNMI interrupt for the highest priority thread */ + and s0, s0, ~CAUSE_IP5 + lw t2, __osRunQueue + lw k1, THREAD_SR(t2) + and k1, k1, ~CAUSE_IP5 + sw k1, THREAD_SR(t2) + /* Redispatch immediately */ + b redispatch + +sw2: + /* Mask out interrupt */ + and t0, t0, ~CAUSE_SW2 + MTC0( t0, C0_CAUSE) + + /* Post sw2 event message */ + li a0, MESG(OS_EVENT_SW2) + jal send_mesg + + /* Mask out interrupt and continue */ + and s0, s0, ~CAUSE_SW2 + b next_interrupt + +sw1: + /* Mask out interrupt */ + and t0, t0, ~CAUSE_SW1 + MTC0( t0, C0_CAUSE) + + /* Post sw1 event message */ + li a0, MESG(OS_EVENT_SW1) + jal send_mesg + + /* Mask out interrupt and continue */ + and s0, s0, ~CAUSE_SW1 + b next_interrupt + +handle_break: + /* Set last thread as having hit a break exception */ + li t1, OS_FLAG_CPU_BREAK + sh t1, THREAD_FLAGS(k0) + /* Post a cpu break event message */ + li a0, MESG(OS_EVENT_CPU_BREAK) + jal send_mesg + + /* Redispatch */ + b redispatch + +redispatch: + /* Get priority of previously running thread */ + lw t1, THREAD_PRI(k0) + lw t2, __osRunQueue + /* Get highest priority from waiting threads */ + lw t3, THREAD_PRI(t2) + + bge t1, t3, enqueueRunning + + /* + * The previously running thread is no longer the highest priority, + * enqueue it to the run queue to wait its turn again + */ + move a1, k0 + la a0, __osRunQueue + + jal __osEnqueueThread + + j __osDispatchThread + +/** + * Resume the previously running thread by placing it at the top of + * the run queue and dispatching it + */ +enqueueRunning: + la t1, __osRunQueue + lw t2, MQ_MTQUEUE(t1) + sw t2, THREAD_NEXT(k0) + sw k0, MQ_MTQUEUE(t1) + j __osDispatchThread + +/** + * Unhandled exceptions & interrupts end up here, + * trap to software by posting a fault message + */ +panic: + /* Mark the thread as having faulted */ + sw k0, __osFaultedThread + li t1, OS_STATE_STOPPED + sh t1, THREAD_STATE(k0) + li t1, OS_FLAG_FAULT + sh t1, THREAD_FLAGS(k0) + + /* Save C0_BADVADDR */ + MFC0( t2, C0_BADVADDR) + + sw t2, THREAD_BADVADDR(k0) + + /* Post the fault message */ + li a0, MESG(OS_EVENT_FAULT) + jal send_mesg + + /* Dispatch next thread */ + j __osDispatchThread +END(__osException) + +/** + * Handles posting event messages to the listening message queue, if there is one + */ +LEAF(send_mesg) + /* Save return address */ + move s2, ra + + /* Load pointer to listening message queue */ + la t2, __osEventStateTab + addu t2, t2, a0 + lw t1, OS_EVENTSTATE_MESSAGE_QUEUE(t2) + + /* If there is no listening message queue, done */ + beqz t1, send_done + + /* Test if the message queue is full, if so do not post the message */ + lw t3, MQ_VALIDCOUNT(t1) + lw ta0, MQ_MSGCOUNT(t1) + + bge t3, ta0, send_done + + /* Add validcount to first and modulo with msgcount */ + lw ta1, MQ_FIRST(t1) + addu ta1, ta1, t3 + + rem ta1, ta1, ta0 + lw ta0, MQ_MSG(t1) + mul ta1, ta1, 4 + addu ta0, ta0, ta1 + + /* Fetch the message to post */ + lw ta1, OS_EVENTSTATE_MESSAGE(t2) + /* Post the message to the message queue */ + sw ta1, 0(ta0) + /* Increment the validCount */ + addiu t2, t3, 1 + sw t2, MQ_VALIDCOUNT(t1) + /* + * If there was a thread blocked on this message queue, + * wake it up + */ + lw t2, MQ_MTQUEUE(t1) + lw t3, THREAD_NEXT(t2) + beqz t3, send_done + + move a0, t1 + jal __osPopThread + + move t2, v0 + + move a1, t2 + la a0, __osRunQueue + jal __osEnqueueThread +send_done: + jr s2 +END(send_mesg) + +/** + * Handle coprocessor unusable exception + */ +LEAF(handle_CpU) + and t1, t0, CAUSE_CEMASK + srl t1, t1, CAUSE_CESHIFT + /* if not coprocessor 1, panic */ + li t2, 1 + bne t1, t2, panic + + /* Mark cop1 as usable for previous thread */ + li t1, 1 + sw t1, THREAD_FP(k0) + lw k1, THREAD_SR(k0) + or k1, k1, SR_CU1 + sw k1, THREAD_SR(k0) + b enqueueRunning +END(handle_CpU) + +/** + * void __osEnqueueAndYield(OSThread** threadQueue); + * + * Voluntary thread yielding. + * Enqueues the currently running thread to the top of the + * thread queue `threadQueue` and yields to the highest priority + * unblocked runnable thread. + */ +LEAF(__osEnqueueAndYield) + lw a1, __osRunningThread +#if !defined(_FINALROM) && BUILD_VERSION >= VERSION_K + sw a1, __osPreviousThread +#endif + /* Save SR */ + MFC0( t0, C0_SR) + ori t0, t0, SR_EXL + sw t0, THREAD_SR(a1) + + /* Save callee-saved registers */ + sd s0, THREAD_GP16(a1) + sd s1, THREAD_GP17(a1) + sd s2, THREAD_GP18(a1) + sd s3, THREAD_GP19(a1) + sd s4, THREAD_GP20(a1) + sd s5, THREAD_GP21(a1) + sd s6, THREAD_GP22(a1) + sd s7, THREAD_GP23(a1) + sd gp, THREAD_GP28(a1) + sd sp, THREAD_GP29(a1) + sd s8, THREAD_GP30(a1) + sd ra, THREAD_GP31(a1) + sw ra, THREAD_PC(a1) + + /* Save FPU callee-saved registers if the current thread has used the FPU */ + lw k1, THREAD_FP(a1) + beqz k1, 1f + cfc1 k1, fcr31 + sw k1, THREAD_FPCSR(a1) + sdc1 $f20, THREAD_FP20(a1) + sdc1 $f22, THREAD_FP22(a1) + sdc1 $f24, THREAD_FP24(a1) + sdc1 $f26, THREAD_FP26(a1) + sdc1 $f28, THREAD_FP28(a1) + sdc1 $f30, THREAD_FP30(a1) +1: + lw k1, THREAD_SR(a1) + andi t1, k1, SR_IMASK + beqz t1, 2f + + /* + * This code does the same thing as the block just above the `savercp` label. + * See the comment there for more about this. + */ + la t0, __OSGlobalIntMask + lw t0, 0(t0) + xor t0, t0, ~0 + andi t0, t0, SR_IMASK + or t1, t1, t0 + and k1, k1, ~SR_IMASK + or k1, k1, t1 + sw k1, THREAD_SR(a1) +2: + lw k1, PHYS_TO_K1(MI_INTR_MASK_REG) + beqz k1, 3f + + /* + * This code does the same thing as the block just below the `savercp` label. + * See the comment there for more about this. + */ + la k0, __OSGlobalIntMask + lw k0, 0(k0) + + srl k0, k0, RCP_IMASKSHIFT + xor k0, k0, ~0 + andi k0, k0, (RCP_IMASK >> RCP_IMASKSHIFT) + lw t0, THREAD_RCP(a1) + and k0, k0, t0 + or k1, k1, k0 +3: + /* + * If the specified thread queue is null, skip + * straight to dispatching + */ + sw k1, THREAD_RCP(a1) + beqz a0, noEnqueue + jal __osEnqueueThread +noEnqueue: + j __osDispatchThread +END(__osEnqueueAndYield) + +/** + * void __osEnqueueThread(OSThread** threadQueue, OSThread* thread); + * + * Enqueues `thread` to the thread queue `threadQueue`, inserted by priority + */ +LEAF(__osEnqueueThread) + move t9, a0 + lw t8, 0(a0) + lw ta3, THREAD_PRI(a1) + lw ta2, THREAD_PRI(t8) + /* + * If the current highest priority thread is a lower priority than + * the new thread, skip searching the queue + */ + blt ta2, ta3, 2f +1: + /* + * Search the queue for the position to insert the thread to maintain + * ordering by priority + */ + move t9, t8 + lw t8, THREAD_NEXT(t8) + lw ta2, THREAD_PRI(t8) + bge ta2, ta3, 1b +2: + /* Insert the thread into the queue */ + lw t8, THREAD_NEXT(t9) + sw t8, THREAD_NEXT(a1) + sw a1, THREAD_NEXT(t9) + sw a0, THREAD_QUEUE(a1) + jr ra +END(__osEnqueueThread) + +/** + * OSThread* __osPopThread(OSThread** threadQueue); + * + * Pops the highest priority thread from the top of the + * thread queue `threadQueue` and returns it + */ +LEAF(__osPopThread) + lw v0, 0(a0) /* a0 is OSThread** */ + lw t9, THREAD_NEXT(v0) + sw t9, 0(a0) + jr ra +END(__osPopThread) + +#if BUILD_VERSION >= VERSION_K +LEAF(__osNop) + jr ra +END(__osNop) +#endif + +/** + * void __osDispatchThread(void); + * + * Dispatches the next thread to run after restoring the context + */ +LEAF(__osDispatchThread) + /* Obtain highest priority thread from the active run queue */ + la a0, __osRunQueue + jal __osPopThread + /* Set thread as running */ + sw v0, __osRunningThread + li t0, OS_STATE_RUNNING + sh t0, THREAD_STATE(v0) + /* + * Restore SR, masking out any interrupts that are not also + * enabled in the global interrupt mask + */ + move k0, v0 + +#if !defined(_FINALROM) && BUILD_VERSION >= VERSION_K + la t0, __osThprofFunc + lw t0, (t0) + beqz t0, __osDispatchThreadSave +1: + lw a0, __osPreviousThread + lw sp, __osThprofStack + jalr t0 +#endif + +/* There is another 1: label somewhere around here in version J and below */ +#if BUILD_VERSION < VERSION_K +1: +#endif + +__osDispatchThreadSave: + lw k1, THREAD_SR(k0) + la t0, __OSGlobalIntMask + lw t0, 0(t0) + andi t0, t0, SR_IMASK + andi t1, k1, SR_IMASK + and t1, t1, t0 + and k1, k1, ~SR_IMASK + or k1, k1, t1 + MTC0( k1, C0_SR) +/* Restore GPRs */ +.set noat + ld $1, THREAD_GP1(k0) +.set at + ld $2, THREAD_GP2(k0) + ld $3, THREAD_GP3(k0) + ld $4, THREAD_GP4(k0) + ld $5, THREAD_GP5(k0) + ld $6, THREAD_GP6(k0) + ld $7, THREAD_GP7(k0) + ld $8, THREAD_GP8(k0) + ld $9, THREAD_GP9(k0) + ld $10, THREAD_GP10(k0) + ld $11, THREAD_GP11(k0) + ld $12, THREAD_GP12(k0) + ld $13, THREAD_GP13(k0) + ld $14, THREAD_GP14(k0) + ld $15, THREAD_GP15(k0) + ld $16, THREAD_GP16(k0) + ld $17, THREAD_GP17(k0) + ld $18, THREAD_GP18(k0) + ld $19, THREAD_GP19(k0) + ld $20, THREAD_GP20(k0) + ld $21, THREAD_GP21(k0) + ld $22, THREAD_GP22(k0) + ld $23, THREAD_GP23(k0) + ld $24, THREAD_GP24(k0) + ld $25, THREAD_GP25(k0) + ld $28, THREAD_GP28(k0) + ld $29, THREAD_GP29(k0) + ld $30, THREAD_GP30(k0) + ld $31, THREAD_GP31(k0) + ld k1, THREAD_LO(k0) + mtlo k1 + ld k1, THREAD_HI(k0) + mthi k1 + /* Move thread pc to EPC so that eret will return execution to where the thread left off */ + lw k1, THREAD_PC(k0) + MTC0( k1, C0_EPC) + + /* Check if the FPU was used by this thread and if so also restore the FPU registers */ + lw k1, THREAD_FP(k0) + beqz k1, 1f + + lw k1, THREAD_FPCSR(k0) + CTC1( k1, fcr31) + ldc1 $f0, THREAD_FP0(k0) + ldc1 $f2, THREAD_FP2(k0) + ldc1 $f4, THREAD_FP4(k0) + ldc1 $f6, THREAD_FP6(k0) + ldc1 $f8, THREAD_FP8(k0) + ldc1 $f10, THREAD_FP10(k0) + ldc1 $f12, THREAD_FP12(k0) + ldc1 $f14, THREAD_FP14(k0) + ldc1 $f16, THREAD_FP16(k0) + ldc1 $f18, THREAD_FP18(k0) + ldc1 $f20, THREAD_FP20(k0) + ldc1 $f22, THREAD_FP22(k0) + ldc1 $f24, THREAD_FP24(k0) + ldc1 $f26, THREAD_FP26(k0) + ldc1 $f28, THREAD_FP28(k0) + ldc1 $f30, THREAD_FP30(k0) + +1: + /* + * Restore RCP interrupt mask, masking out any RCP interrupts that + * are not also enabled in the global interrupt mask + */ +.set noreorder + lw k1, THREAD_RCP(k0) + la k0, __OSGlobalIntMask + lw k0, 0(k0) + srl k0, k0, 0x10 + and k1, k1, k0 + sll k1, k1, 0x1 + la k0, __osRcpImTable + addu k1, k1, k0 + lhu k1, 0(k1) + la k0, PHYS_TO_K1(MI_INTR_MASK_REG) + sw k1, 0(k0) + + /* Empty pipeline */ + nop + nop + nop + nop + + /* Resume thread execution */ + eret +.set reorder +END(__osDispatchThread) + +/** + * void __osCleanupThread(void); + * + * When a thread entrypoint function returns, it returns to this function. + * This function is responsible for cleaning up the thread, signalling for the + * current thread to be destroyed. + */ +LEAF(__osCleanupThread) + move a0, zero +#if !defined(BBPLAYER) && !defined(__sgi) + nop +#endif + /* Despite being a jal, this function does not return as the thread will have been destroyed */ + jal osDestroyThread +END(__osCleanupThread) diff --git a/libultra/src/os/getcount.s b/libultra/src/os/getcount.s index 480b088f..9ce72c65 100644 --- a/libultra/src/os/getcount.s +++ b/libultra/src/os/getcount.s @@ -1,14 +1,9 @@ -.include "macro.inc" +#include "PR/R4300.h" +#include "sys/asm.h" +#include "sys/regdef.h" -/* assembler directives */ -.set noat /* allow manual use of $at */ -.set noreorder /* don't insert nops after branches */ -.set gp=64 /* allow use of 64-bit general purpose registers */ - -.section .text, "ax" - -leaf osGetCount -mfc0 $v0, $9 /* C0_COUNT */ -jr $ra -nop -.end osGetCount +.text +LEAF(osGetCount) + MFC0( v0, C0_COUNT) + jr ra +END(osGetCount) diff --git a/libultra/src/os/getsr.s b/libultra/src/os/getsr.s index 9eaff16b..2db98999 100644 --- a/libultra/src/os/getsr.s +++ b/libultra/src/os/getsr.s @@ -1,15 +1,9 @@ -.include "macro.inc" +#include "PR/R4300.h" +#include "sys/asm.h" +#include "sys/regdef.h" -/* assembler directives */ -.set noat /* allow manual use of $at */ -.set noreorder /* don't insert nops after branches */ -.set gp=64 /* allow use of 64-bit general purpose registers */ - -.section .text, "ax" - -leaf __osGetSR -mfc0 $v0, $12 /* C0_SR */ -jr $ra - nop -nop -.end __osGetSR +.text +LEAF(__osGetSR) + MFC0( v0, C0_SR) + jr ra +END(__osGetSR) diff --git a/libultra/src/os/interrupt.s b/libultra/src/os/interrupt.s index c0a78f81..1f4305b1 100644 --- a/libultra/src/os/interrupt.s +++ b/libultra/src/os/interrupt.s @@ -1,29 +1,55 @@ -.include "macro.inc" +#include "PR/R4300.h" +#include "sys/asm.h" +#include "sys/regdef.h" +#include "PR/os_version.h" +#include "threadasm.h" -/* assembler directives */ -.set noat /* allow manual use of $at */ -.set noreorder /* don't insert nops after branches */ -.set gp=64 /* allow use of 64-bit general purpose registers */ +.text +.set noreorder +LEAF(__osDisableInt) +#if BUILD_VERSION >= VERSION_J + la t2, __OSGlobalIntMask + lw t3, (t2) + andi t3, SR_IMASK + mfc0 t0, C0_SR + and t1, t0, ~SR_IE + mtc0 t1, C0_SR + andi v0, t0, SR_IE + lw t0, (t2) + andi t0, SR_IMASK + beq t0, t3, No_Change_Global_Int + # @bug this la should be lw, it may never come up in practice as to reach this code + # the CPU bits of __OSGlobalIntMask must have changed while this function is running. + la t2, __osRunningThread # this is intentionally a macro in the branch delay slot + lw t1, THREAD_SR(t2) + andi t2, t1, SR_IMASK + and t2, t0 + and t1, ~SR_IMASK + or t1, t2 + and t1, ~SR_IE + mtc0 t1, C0_SR + nop + nop +No_Change_Global_Int: + jr ra + nop +#else + mfc0 t0, C0_SR + and t1, t0, ~SR_IE + mtc0 t1, C0_SR + andi v0, t0, SR_IE + nop + jr ra + nop +#endif +END(__osDisableInt) -.section .text, "ax" - -leaf __osDisableInt -mfc0 $t0, $12 -addiu $at, $zero, -0x2 -and $t1, $t0, $at -mtc0 $t1, $12 -andi $v0, $t0, 0x1 -nop -jr $ra -nop -.end __osDisableInt - -leaf __osRestoreInt -mfc0 $t0, $12 -or $t0, $t0, $a0 -mtc0 $t0, $12 -nop -nop -jr $ra - nop -.end __osRestoreInt +LEAF(__osRestoreInt) + mfc0 t0, C0_SR + or t0, t0, a0 + mtc0 t0, C0_SR + nop + nop + jr ra + nop +END(__osRestoreInt) diff --git a/libultra/src/os/invaldcache.s b/libultra/src/os/invaldcache.s index b40fc8a5..43671d0c 100644 --- a/libultra/src/os/invaldcache.s +++ b/libultra/src/os/invaldcache.s @@ -1,62 +1,91 @@ -.include "macro.inc" +#include "PR/R4300.h" +#include "sys/asm.h" +#include "sys/regdef.h" -/* assembler directives */ -.set noat /* allow manual use of $at */ -.set noreorder /* don't insert nops after branches */ -.set gp=64 /* allow use of 64-bit general purpose registers */ +.text +/** + * void osInvalDCache(void* vaddr, s32 nbytes); + * + * Invalidates the CPU Data Cache for `nbytes` at `vaddr`. + * The cache is not automatically synced with physical memory, so cache + * lines must be invalidated to ensure old data is not used in place of + * newly available data supplied by an external agent in a DMA operation. + * + * If `vaddr` is not aligned to a cache line boundary, or nbytes is not a + * multiple of the data cache line size (16 bytes) a larger region is + * invalidated. + * + * If the amount to invalidate is at least the data cache size (DCACHE_SIZE), + * the entire data cache is invalidated. + */ +LEAF(osInvalDCache) + /* If the amount to invalidate is less than or equal to 0, return immediately */ + blez a1, 3f + /* + * If the amount to invalidate is as large as or larger than + * the data cache size, invalidate all + */ + li t3, DCACHE_SIZE + bgeu a1, t3, 4f -.section .text, "ax" + /* + * Ensure end address does not wrap around and end up smaller + * than the start address + */ + move t0, a0 + addu t1, a0, a1 + bgeu t0, t1, 3f -/* Generated by spimdisasm 1.30.0 */ + /* Mask start with cache line */ + addiu t1, t1, -DCACHE_LINESIZE + andi t2, t0, DCACHE_LINEMASK + /* If mask is not zero, the start is not cache aligned */ + beqz t2, 1f -/* Handwritten function */ -leaf osInvalDCache -/* D23F0 800D17F0 18A0001F */ blez $a1, .L800D1870 -/* D23F4 800D17F4 00000000 */ nop -/* D23F8 800D17F8 240B2000 */ addiu $t3, $zero, 0x2000 -/* D23FC 800D17FC 00AB082B */ sltu $at, $a1, $t3 -/* D2400 800D1800 1020001D */ beqz $at, .L800D1878 -/* D2404 800D1804 00000000 */ nop -/* D2408 800D1808 00804025 */ or $t0, $a0, $zero -/* D240C 800D180C 00854821 */ addu $t1, $a0, $a1 -/* D2410 800D1810 0109082B */ sltu $at, $t0, $t1 -/* D2414 800D1814 10200016 */ beqz $at, .L800D1870 -/* D2418 800D1818 00000000 */ nop -/* D241C 800D181C 310A000F */ andi $t2, $t0, 0xF -/* D2420 800D1820 11400007 */ beqz $t2, .L800D1840 -/* D2424 800D1824 2529FFF0 */ addiu $t1, $t1, -0x10 -/* D2428 800D1828 010A4023 */ subu $t0, $t0, $t2 -/* D242C 800D182C BD150000 */ cache 0x15, 0x0($t0) /* handwritten instruction */ -/* D2430 800D1830 0109082B */ sltu $at, $t0, $t1 -/* D2434 800D1834 1020000E */ beqz $at, .L800D1870 -/* D2438 800D1838 00000000 */ nop -/* D243C 800D183C 25080010 */ addiu $t0, $t0, 0x10 -.L800D1840: -/* D2440 800D1840 312A000F */ andi $t2, $t1, 0xF -/* D2444 800D1844 11400006 */ beqz $t2, .L800D1860 -/* D2448 800D1848 00000000 */ nop -/* D244C 800D184C 012A4823 */ subu $t1, $t1, $t2 -/* D2450 800D1850 BD350010 */ cache 0x15, 0x10($t1) /* handwritten instruction */ -/* D2454 800D1854 0128082B */ sltu $at, $t1, $t0 -/* D2458 800D1858 14200005 */ bnez $at, .L800D1870 -/* D245C 800D185C 00000000 */ nop -.L800D1860: -/* D2460 800D1860 BD110000 */ cache 0x11, 0x0($t0) /* handwritten instruction */ -/* D2464 800D1864 0109082B */ sltu $at, $t0, $t1 -/* D2468 800D1868 1420FFFD */ bnez $at, .L800D1860 -/* D246C 800D186C 25080010 */ addiu $t0, $t0, 0x10 -.L800D1870: -/* D2470 800D1870 03E00008 */ jr $ra -/* D2474 800D1874 00000000 */ nop -.L800D1878: -/* D2478 800D1878 3C088000 */ lui $t0, 0x8000 -/* D247C 800D187C 010B4821 */ addu $t1, $t0, $t3 -/* D2480 800D1880 2529FFF0 */ addiu $t1, $t1, -0x10 -.L800D1884: -/* D2484 800D1884 BD010000 */ cache 0x01, 0x0($t0) /* handwritten instruction */ -/* D2488 800D1888 0109082B */ sltu $at, $t0, $t1 -/* D248C 800D188C 1420FFFD */ bnez $at, .L800D1884 -/* D2490 800D1890 25080010 */ addiu $t0, $t0, (0x80000010 & 0xFFFF) -/* D2494 800D1894 03E00008 */ jr $ra -/* D2498 800D1898 00000000 */ nop -.end osInvalDCache + /* Subtract mask result to align to cache line */ + subu t0, t0, t2 + /* Hit-Writeback-Invalidate unaligned part */ + CACHE( (C_HWBINV | CACH_PD), (t0)) + /* If that is all there is to do, return early */ + bgeu t0, t1, 3f + + + addiu t0, t0, DCACHE_LINESIZE +1: + /* Mask end with cache line */ + andi t2, t1, DCACHE_LINEMASK + /* If mask is not zero, the end is not cache aligned */ + beqz t2, 2f + + /* Subtract mask result to align to cache line */ + subu t1, t1, t2 + + /* Hit-Writeback-Invalidate unaligned part */ + CACHE( (C_HWBINV | CACH_PD), DCACHE_LINESIZE(t1)) + bltu t1, t0, 3f + +2: + /* Hit-Invalidate */ + CACHE( (C_HINV | CACH_PD), (t0)) + .set noreorder + bltu t0, t1, 2b + addiu t0, t0, DCACHE_LINESIZE + .set reorder +3: + jr ra + +4: + li t0, K0BASE + addu t1, t0, t3 + addiu t1, t1, -DCACHE_LINESIZE +5: + /* Index-Writeback-Invalidate */ + CACHE( (C_IINV | CACH_PD), (t0)) + .set noreorder + bltu t0, t1, 5b + addiu t0, t0, DCACHE_LINESIZE + .set reorder + + jr ra + +END(osInvalDCache) diff --git a/libultra/src/os/invalicache.s b/libultra/src/os/invalicache.s index e2299a75..541b3872 100644 --- a/libultra/src/os/invalicache.s +++ b/libultra/src/os/invalicache.s @@ -1,47 +1,51 @@ -.include "macro.inc" +#include "PR/R4300.h" +#include "sys/asm.h" +#include "sys/regdef.h" -/* assembler directives */ -.set noat /* allow manual use of $at */ -.set noreorder /* don't insert nops after branches */ -.set gp=64 /* allow use of 64-bit general purpose registers */ +.text +LEAF(osInvalICache) + /* If the amount to invalidate is less than or equal to 0, return immediately */ + blez a1, 2f -.section .text, "ax" + /* + * If the amount to invalidate is as large as or larger than + * the instruction cache size, invalidate all + */ + li t3, ICACHE_SIZE + bgeu a1, t3, 3f -/* Generated by spimdisasm 1.30.0 */ + /* + * ensure end address does not wrap around and end up smaller + * than the start address + */ + move t0, a0 + addu t1, a0, a1 + bgeu t0, t1, 2f -/* Handwritten function */ -leaf osInvalICache -/* D52B0 800D46B0 18A00011 */ blez $a1, .L800D46F8 -/* D52B4 800D46B4 00000000 */ nop -/* D52B8 800D46B8 240B4000 */ addiu $t3, $zero, 0x4000 -/* D52BC 800D46BC 00AB082B */ sltu $at, $a1, $t3 -/* D52C0 800D46C0 1020000F */ beqz $at, .L800D4700 -/* D52C4 800D46C4 00000000 */ nop -/* D52C8 800D46C8 00804025 */ or $t0, $a0, $zero -/* D52CC 800D46CC 00854821 */ addu $t1, $a0, $a1 -/* D52D0 800D46D0 0109082B */ sltu $at, $t0, $t1 -/* D52D4 800D46D4 10200008 */ beqz $at, .L800D46F8 -/* D52D8 800D46D8 00000000 */ nop -/* D52DC 800D46DC 310A001F */ andi $t2, $t0, 0x1F -/* D52E0 800D46E0 2529FFE0 */ addiu $t1, $t1, -0x20 -/* D52E4 800D46E4 010A4023 */ subu $t0, $t0, $t2 -.L800D46E8: -/* D52E8 800D46E8 BD100000 */ cache 0x10, 0x0($t0) /* handwritten instruction */ -/* D52EC 800D46EC 0109082B */ sltu $at, $t0, $t1 -/* D52F0 800D46F0 1420FFFD */ bnez $at, .L800D46E8 -/* D52F4 800D46F4 25080020 */ addiu $t0, $t0, 0x20 -.L800D46F8: -/* D52F8 800D46F8 03E00008 */ jr $ra -/* D52FC 800D46FC 00000000 */ nop -.L800D4700: -/* D5300 800D4700 3C088000 */ lui $t0, 0x8000 -/* D5304 800D4704 010B4821 */ addu $t1, $t0, $t3 -/* D5308 800D4708 2529FFE0 */ addiu $t1, $t1, -0x20 -.L800D470C: -/* D530C 800D470C BD000000 */ cache 0x00, 0x0($t0) /* handwritten instruction */ -/* D5310 800D4710 0109082B */ sltu $at, $t0, $t1 -/* D5314 800D4714 1420FFFD */ bnez $at, .L800D470C -/* D5318 800D4718 25080020 */ addiu $t0, $t0, (0x80000020 & 0xFFFF) -/* D531C 800D471C 03E00008 */ jr $ra -/* D5320 800D4720 00000000 */ nop -.end osInvalICache + /* Mask and subtract to align to cache line */ + addiu t1, t1, -ICACHE_LINESIZE + andi t2, t0, ICACHE_LINEMASK + subu t0, t0, t2 +1: + CACHE( (C_HINV | CACH_PI), (t0)) + .set noreorder + bltu t0, t1, 1b + addiu t0, t0, ICACHE_LINESIZE + .set reorder +2: + jr ra + +3: + li t0, K0BASE + addu t1, t0, t3 + addiu t1, t1, -ICACHE_LINESIZE +4: + CACHE( (C_IINV | CACH_PI), (t0)) + .set noreorder + bltu t0, t1, 4b + addiu t0, t0, ICACHE_LINESIZE + .set reorder + + jr ra + +END(osInvalICache) diff --git a/libultra/src/os/maptlbrdb.s b/libultra/src/os/maptlbrdb.s index 6e443232..1714304d 100644 --- a/libultra/src/os/maptlbrdb.s +++ b/libultra/src/os/maptlbrdb.s @@ -1,36 +1,31 @@ -.include "macro.inc" +#include "PR/R4300.h" +#include "PR/rdb.h" +#include "sys/asm.h" +#include "sys/regdef.h" -/* assembler directives */ -.set noat /* allow manual use of $at */ -.set noreorder /* don't insert nops after branches */ -.set gp=64 /* allow use of 64-bit general purpose registers */ - -.section .text, "ax" - -/* Generated by spimdisasm 1.30.0 */ - -/* Handwritten function */ -leaf osMapTLBRdb -/* D5330 800D4730 40085000 */ mfc0 $t0, $10 /* handwritten instruction */ -/* D5334 800D4734 2409001F */ addiu $t1, $zero, 0x1F -/* D5338 800D4738 40890000 */ mtc0 $t1, $0 /* handwritten instruction */ -/* D533C 800D473C 40802800 */ mtc0 $zero, $5 /* handwritten instruction */ -/* D5340 800D4740 240A0017 */ addiu $t2, $zero, 0x17 -/* D5344 800D4744 3C09C000 */ lui $t1, (0xC0000000 >> 16) -/* D5348 800D4748 40895000 */ mtc0 $t1, $10 /* handwritten instruction */ -/* D534C 800D474C 3C098000 */ lui $t1, (0x80000000 >> 16) -/* D5350 800D4750 00095982 */ srl $t3, $t1, 6 -/* D5354 800D4754 016A5825 */ or $t3, $t3, $t2 -/* D5358 800D4758 408B1000 */ mtc0 $t3, $2 /* handwritten instruction */ -/* D535C 800D475C 24090001 */ addiu $t1, $zero, 0x1 -/* D5360 800D4760 40891800 */ mtc0 $t1, $3 /* handwritten instruction */ -/* D5364 800D4764 00000000 */ nop -/* D5368 800D4768 42000002 */ tlbwi /* handwritten instruction */ -/* D536C 800D476C 00000000 */ nop -/* D5370 800D4770 00000000 */ nop -/* D5374 800D4774 00000000 */ nop -/* D5378 800D4778 00000000 */ nop -/* D537C 800D477C 40885000 */ mtc0 $t0, $10 /* handwritten instruction */ -/* D5380 800D4780 03E00008 */ jr $ra -/* D5384 800D4784 00000000 */ nop -.end osMapTLBRdb +.text +.set noreorder +LEAF(osMapTLBRdb) + mfc0 t0, C0_ENTRYHI + li t1, NTLBENTRIES + mtc0 t1, C0_INX + mtc0 zero, C0_PAGEMASK /* 4k */ + li t2, (TLBLO_UNCACHED | TLBLO_D | TLBLO_V | TLBLO_G) + li t1, K2BASE + mtc0 t1, C0_ENTRYHI + li t1, RDB_BASE_VIRTUAL_ADDR + srl t3, t1, TLBLO_PFNSHIFT + or t3, t3, t2 + mtc0 t3, C0_ENTRYLO0 + li t1, TLBLO_G + mtc0 t1, C0_ENTRYLO1 + nop + tlbwi + nop + nop + nop + nop + mtc0 t0, C0_ENTRYHI + jr ra + nop +END(osMapTLBRdb) diff --git a/libultra/src/os/probetlb.s b/libultra/src/os/probetlb.s index 1d3eb9da..5bd4981d 100644 --- a/libultra/src/os/probetlb.s +++ b/libultra/src/os/probetlb.s @@ -1,64 +1,85 @@ -.include "macro.inc" +#include "PR/R4300.h" +#include "sys/asm.h" +#include "sys/regdef.h" -/* assembler directives */ -.set noat /* allow manual use of $at */ -.set noreorder /* don't insert nops after branches */ -.set gp=64 /* allow use of 64-bit general purpose registers */ - -.section .text, "ax" - -/* Generated by spimdisasm 1.30.0 */ - -/* Handwritten function */ -leaf __osProbeTLB -/* D41B0 800D35B0 40085000 */ mfc0 $t0, $10 /* handwritten instruction */ -/* D41B4 800D35B4 310900FF */ andi $t1, $t0, 0xFF -/* D41B8 800D35B8 2401E000 */ addiu $at, $zero, -0x2000 -/* D41BC 800D35BC 00815024 */ and $t2, $a0, $at -/* D41C0 800D35C0 012A4825 */ or $t1, $t1, $t2 -/* D41C4 800D35C4 40895000 */ mtc0 $t1, $10 /* handwritten instruction */ -/* D41C8 800D35C8 00000000 */ nop -/* D41CC 800D35CC 00000000 */ nop -/* D41D0 800D35D0 00000000 */ nop -/* D41D4 800D35D4 42000008 */ tlbp /* handwritten instruction */ -/* D41D8 800D35D8 00000000 */ nop -/* D41DC 800D35DC 00000000 */ nop -/* D41E0 800D35E0 400B0000 */ mfc0 $t3, $0 /* handwritten instruction */ -/* D41E4 800D35E4 3C018000 */ lui $at, (0x80000000 >> 16) -/* D41E8 800D35E8 01615824 */ and $t3, $t3, $at -/* D41EC 800D35EC 1560001A */ bnez $t3, .L800D3658 -/* D41F0 800D35F0 00000000 */ nop -/* D41F4 800D35F4 42000001 */ tlbr /* handwritten instruction */ -/* D41F8 800D35F8 00000000 */ nop -/* D41FC 800D35FC 00000000 */ nop -/* D4200 800D3600 00000000 */ nop -/* D4204 800D3604 400B2800 */ mfc0 $t3, $5 /* handwritten instruction */ -/* D4208 800D3608 216B2000 */ addi $t3, $t3, 0x2000 /* handwritten instruction */ -/* D420C 800D360C 000B5842 */ srl $t3, $t3, 1 -/* D4210 800D3610 01646024 */ and $t4, $t3, $a0 -/* D4214 800D3614 15800004 */ bnez $t4, .L800D3628 -/* D4218 800D3618 216BFFFF */ addi $t3, $t3, -0x1 /* handwritten instruction */ -/* D421C 800D361C 40021000 */ mfc0 $v0, $2 /* handwritten instruction */ -/* D4220 800D3620 10000002 */ b .L800D362C -/* D4224 800D3624 00000000 */ nop -.L800D3628: -/* D4228 800D3628 40021800 */ mfc0 $v0, $3 /* handwritten instruction */ -.L800D362C: -/* D422C 800D362C 304D0002 */ andi $t5, $v0, 0x2 -/* D4230 800D3630 11A00009 */ beqz $t5, .L800D3658 -/* D4234 800D3634 00000000 */ nop -/* D4238 800D3638 3C013FFF */ lui $at, (0x3FFFFFC0 >> 16) -/* D423C 800D363C 3421FFC0 */ ori $at, $at, (0x3FFFFFC0 & 0xFFFF) -/* D4240 800D3640 00411024 */ and $v0, $v0, $at -/* D4244 800D3644 00021180 */ sll $v0, $v0, 6 -/* D4248 800D3648 008B6824 */ and $t5, $a0, $t3 -/* D424C 800D364C 004D1020 */ add $v0, $v0, $t5 /* handwritten instruction */ -/* D4250 800D3650 10000002 */ b .L800D365C -/* D4254 800D3654 00000000 */ nop -.L800D3658: -/* D4258 800D3658 2402FFFF */ addiu $v0, $zero, -0x1 -.L800D365C: -/* D425C 800D365C 40885000 */ mtc0 $t0, $10 /* handwritten instruction */ -/* D4260 800D3660 03E00008 */ jr $ra -/* D4264 800D3664 00000000 */ nop -.end __osProbeTLB +.text +.set noreorder +/** + * u32 __osProbeTLB(void* vaddr); + * + * Searches the TLB for the physical address associated with + * the virtual address `vaddr`. + * + * Returns the physical address if found, or -1 if not found. + */ +LEAF(__osProbeTLB) + /* Set C0_ENTRYHI based on supplied vaddr */ + mfc0 t0, C0_ENTRYHI + andi t1, t0, TLBHI_PIDMASK + and t2, a0, (TLBHI_VPN2MASK << 32) >> 32 + or t1, t1, t2 + mtc0 t1, C0_ENTRYHI + nop + nop + nop + /* + * TLB probe, sets C0_INX to a value matching C0_ENTRYHI. + * If no match is found the TLBINX_PROBE bit is set to indicate this. + */ + tlbp + nop + nop + /* Read result */ + mfc0 t3, C0_INX + and t3, t3, TLBINX_PROBE + /* Branch if no match was found */ + bnez t3, 3f + nop + /* + * Read TLB, sets C0_ENTRYHI, C0_ENTRYLO0, C0_ENTRYLO1 and C0_PAGEMASK for the TLB + * entry indicated by C0_INX + */ + tlbr + nop + nop + nop + /* Calculate page size = (page mask + 0x2000) >> 1 */ + mfc0 t3, C0_PAGEMASK + addi t3, t3, 0x2000 + srl t3, t3, 0x1 + /* & with vaddr */ + and ta0, t3, a0 + /* Select C0_ENTRYLO0 or C0_ENTRYLO1 */ + bnez ta0, 1f + /* make bitmask out of page size */ + addi t3, t3, -1 + mfc0 v0, C0_ENTRYLO0 + b 2f + nop +1: + mfc0 v0, C0_ENTRYLO1 +2: + /* Check valid bit and branch if not valid */ + andi ta1, v0, TLBLO_V + beqz ta1, 3f + nop + /* Extract the Page Frame Number from the entry */ + and v0, v0, TLBLO_PFNMASK + sll v0, v0, TLBLO_PFNSHIFT + /* Mask vaddr with page size mask */ + and ta1, a0, t3 + /* Add masked vaddr to pfn to obtain the physical address */ + add v0, v0, ta1 + b 4f + nop +3: + /* + * No physical address for the supplied virtual address was found, + * return -1 + */ + li v0, -1 +4: + mtc0 t0, C0_ENTRYHI + jr ra + nop +END(__osProbeTLB) diff --git a/libultra/src/os/setcompare.s b/libultra/src/os/setcompare.s index 379162b5..7f8969c7 100644 --- a/libultra/src/os/setcompare.s +++ b/libultra/src/os/setcompare.s @@ -1,17 +1,9 @@ -.include "macro.inc" +#include "PR/R4300.h" +#include "sys/asm.h" +#include "sys/regdef.h" -/* assembler directives */ -.set noat /* allow manual use of $at */ -.set noreorder /* don't insert nops after branches */ -.set gp=64 /* allow use of 64-bit general purpose registers */ - -.section .text, "ax" - -/* Generated by spimdisasm 1.30.0 */ - -/* Handwritten function */ -leaf __osSetCompare -/* D8060 800D7460 40845800 */ mtc0 $a0, $11 /* handwritten instruction */ -/* D8064 800D7464 03E00008 */ jr $ra -/* D8068 800D7468 00000000 */ nop -.end __osSetCompare +.text +LEAF(__osSetCompare) + MTC0( a0, C0_COMPARE) + jr ra +END(__osSetCompare) diff --git a/libultra/src/os/setfpccsr.s b/libultra/src/os/setfpccsr.s index 2bf34ccb..f36e5b8c 100644 --- a/libultra/src/os/setfpccsr.s +++ b/libultra/src/os/setfpccsr.s @@ -1,17 +1,14 @@ -.include "macro.inc" +#include "PR/R4300.h" +#include "sys/asm.h" +#include "sys/regdef.h" -/* assembler directives */ -.set noat /* allow manual use of $at */ -.set noreorder /* don't insert nops after branches */ -.set gp=64 /* allow use of 64-bit general purpose registers */ - -.section .text, "ax" - -/* Generated by spimdisasm 1.30.0 */ - -leaf __osSetFpcCsr -cfc1 $v0, $31 -ctc1 $a0, $31 -jr $ra -nop -.end __osSetFpcCsr +.text +LEAF(__osSetFpcCsr) + CFC1( v0, fcr31) + CTC1( a0, fcr31) + jr ra +#ifndef MODERN_CC +END(__osSetSR) # @bug: Should be __osSetFpcCsr +#else +END(__osSetFpcCsr) +#endif diff --git a/libultra/src/os/setintmask.s b/libultra/src/os/setintmask.s index 4a378695..b9f93b0a 100644 --- a/libultra/src/os/setintmask.s +++ b/libultra/src/os/setintmask.s @@ -1,70 +1,162 @@ -.include "macro.inc" +#include "PR/R4300.h" +#include "PR/rcp.h" +#include "PR/os.h" +#include "sys/asm.h" +#include "sys/regdef.h" -/* assembler directives */ -.set noat /* allow manual use of $at */ -.set noreorder /* don't insert nops after branches */ -.set gp=64 /* allow use of 64-bit general purpose registers */ +#define MI_INTR_MASK ((1 << 6) - 1) -.section .rodata +.globl __osRcpImTable -glabel __osRcpImTable +.text +.set noreorder +/** + * OSIntMask osSetIntMask(OSIntMask); + * + * Sets the interrupt enable mask for the current thread. External interrupts + * originating either in the CPU or the RCP may be "masked out" so that they + * are not handled. This is sometimes important for critical code sections + * that must not be interrupted. + * Interrupts that are not enabled in the global interrupt mask __OSGlobalIntMask + * cannot be set here. The global interrupt mask is OS-internal and is not + * expected to change during runtime. + * The returned value is the previous interrupt enable mask so that it can be + * restored later. + * + * @bug Some usage of the global interrupt mask is broken both in here and in the + * exception handler routines. + * While a thread is running, the C0_SR interrupt enable bits contain the + * interrupt enable bits for the current thread masked by the global + * interrupt mask. There is an attempt to recover only the original interrupt + * enable bits belonging to the thread itself using the operation + * (SR | ~__OSGlobalIntMask). + * However, this does not work as intended and can cause interrupts to end + * up enabled when not intended to be. The same issue is present for the + * RCP interrupt enable bits in MI_INTR_MASK_REG. + * This does not cause issues in practice as __OSGlobalIntMask is almost always + * OS_IM_ALL, so the operation is usually simply (SR | 0). + */ +LEAF(osSetIntMask) + /* Extract interrupt enable bits from current SR */ + mfc0 ta0, C0_SR + + andi v0, ta0, OS_IM_CPU + + /* Get value of __OSGlobalIntMask */ + la t0, __OSGlobalIntMask + lw t3, 0(t0) + + /* Bitwise-OR in the disabled CPU bits of __OSGlobalIntMask */ + xor t0, t3, ~0 + andi t0, t0, SR_IMASK + or v0, v0, t0 + + /* Fetch MI_INTR_MASK_REG */ + lw t2, PHYS_TO_K1(MI_INTR_MASK_REG) + /* If there are RCP interrupts masked */ + beqz t2, 1f + srl t1, t3, 0x10 + + /* Bitwise-OR in the disabled RCP bits of __OSGlobalIntMask */ + xor t1, t1, ~0 + andi t1, t1, (RCP_IMASK >> RCP_IMASKSHIFT) + or t2, t2, t1 +1: + /* Shift the RCP bits to not conflict with the CPU bits */ + sll t2, t2, RCP_IMASKSHIFT + /* OR the CPU and RCP bits together */ + or v0, v0, t2 + + /* Extract RCP interrupt enable bits from requested mask and mask with __OSGlobalIntMask */ + and t0, a0, RCP_IMASK + and t0, t0, t3 + /* Convert to a value for MI_INTR_MASK_REG and set it */ + srl t0, t0, (RCP_IMASKSHIFT - 1) + lhu t2, __osRcpImTable(t0) + sw t2, PHYS_TO_K1(MI_INTR_MASK_REG) + + /* Extract CPU interrupt enable bits from requested mask and mask with __OSGlobalIntMask */ + andi t0, a0, OS_IM_CPU + andi t1, t3, SR_IMASK + and t0, t0, t1 + + and ta0, ta0, ~SR_IMASK + /* Bitwise OR in the remaining bits of SR and set new SR */ + or ta0, ta0, t0 + + mtc0 ta0, C0_SR + nop + nop + jr ra + nop +END(osSetIntMask) + +.rdata +EXPORT(__osRcpImTable) /* LUT to convert between MI_INTR and MI_INTR_MASK */ /* MI_INTR is status for each interrupt whereas */ /* MI_INTR_MASK has seperate bits for set/clr */ -.half 0x0555, 0x0556, 0x0559, 0x055A, 0x0565, 0x0566, 0x0569, 0x056A -.half 0x0595, 0x0596, 0x0599, 0x059A, 0x05A5, 0x05A6, 0x05A9, 0x05AA -.half 0x0655, 0x0656, 0x0659, 0x065A, 0x0665, 0x0666, 0x0669, 0x066A -.half 0x0695, 0x0696, 0x0699, 0x069A, 0x06A5, 0x06A6, 0x06A9, 0x06AA -.half 0x0955, 0x0956, 0x0959, 0x095A, 0x0965, 0x0966, 0x0969, 0x096A -.half 0x0995, 0x0996, 0x0999, 0x099A, 0x09A5, 0x09A6, 0x09A9, 0x09AA -.half 0x0A55, 0x0A56, 0x0A59, 0x0A5A, 0x0A65, 0x0A66, 0x0A69, 0x0A6A -.half 0x0A95, 0x0A96, 0x0A99, 0x0A9A, 0x0AA5, 0x0AA6, 0x0AA9, 0x0AAA - -.section .text, "ax" - -/* Generated by spimdisasm 1.30.0 */ - -/* Handwritten function */ -leaf osSetIntMask -/* CA630 800C9A30 400C6000 */ mfc0 $t4, $12 /* handwritten instruction */ -/* CA634 800C9A34 3182FF01 */ andi $v0, $t4, 0xFF01 -/* CA638 800C9A38 3C08800E */ lui $t0, %hi(__OSGlobalIntMask) -/* CA63C 800C9A3C 250838AC */ addiu $t0, $t0, %lo(__OSGlobalIntMask) -/* CA640 800C9A40 8D0B0000 */ lw $t3, 0x0($t0) -/* CA644 800C9A44 2401FFFF */ addiu $at, $zero, -0x1 -/* CA648 800C9A48 01614026 */ xor $t0, $t3, $at -/* CA64C 800C9A4C 3108FF00 */ andi $t0, $t0, 0xFF00 -/* CA650 800C9A50 00481025 */ or $v0, $v0, $t0 -/* CA654 800C9A54 3C0AA430 */ lui $t2, %hi(MI_INTR_MASK_REG) -/* CA658 800C9A58 8D4A000C */ lw $t2, %lo(MI_INTR_MASK_REG)($t2) -/* CA65C 800C9A5C 11400005 */ beqz $t2, .L800C9A74 -/* CA660 800C9A60 000B4C02 */ srl $t1, $t3, 16 -/* CA664 800C9A64 2401FFFF */ addiu $at, $zero, -0x1 -/* CA668 800C9A68 01214826 */ xor $t1, $t1, $at -/* CA66C 800C9A6C 3129003F */ andi $t1, $t1, 0x3F -/* CA670 800C9A70 01495025 */ or $t2, $t2, $t1 -.L800C9A74: -/* CA674 800C9A74 000A5400 */ sll $t2, $t2, 16 -/* CA678 800C9A78 004A1025 */ or $v0, $v0, $t2 -/* CA67C 800C9A7C 3C01003F */ lui $at, (0x3F0000 >> 16) -/* CA680 800C9A80 00814024 */ and $t0, $a0, $at -/* CA684 800C9A84 010B4024 */ and $t0, $t0, $t3 -/* CA688 800C9A88 000843C2 */ srl $t0, $t0, 15 -/* CA68C 800C9A8C 3C0A800F */ lui $t2, %hi(__osRcpImTable) -/* CA690 800C9A90 01485021 */ addu $t2, $t2, $t0 -/* CA694 800C9A94 954A94D0 */ lhu $t2, %lo(__osRcpImTable)($t2) -/* CA698 800C9A98 3C01A430 */ lui $at, %hi(MI_INTR_MASK_REG) -/* CA69C 800C9A9C AC2A000C */ sw $t2, %lo(MI_INTR_MASK_REG)($at) -/* CA6A0 800C9AA0 3088FF01 */ andi $t0, $a0, 0xFF01 -/* CA6A4 800C9AA4 3169FF00 */ andi $t1, $t3, 0xFF00 -/* CA6A8 800C9AA8 01094024 */ and $t0, $t0, $t1 -/* CA6AC 800C9AAC 3C01FFFF */ lui $at, (0xFFFF00FF >> 16) -/* CA6B0 800C9AB0 342100FF */ ori $at, $at, (0xFFFF00FF & 0xFFFF) -/* CA6B4 800C9AB4 01816024 */ and $t4, $t4, $at -/* CA6B8 800C9AB8 01886025 */ or $t4, $t4, $t0 -/* CA6BC 800C9ABC 408C6000 */ mtc0 $t4, $12 /* handwritten instruction */ -/* CA6C0 800C9AC0 00000000 */ nop -/* CA6C4 800C9AC4 00000000 */ nop -/* CA6C8 800C9AC8 03E00008 */ jr $ra -/* CA6CC 800C9ACC 00000000 */ nop -.end osSetIntMask +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP +.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP diff --git a/libultra/src/os/setsr.s b/libultra/src/os/setsr.s index d46decf7..37540fcb 100644 --- a/libultra/src/os/setsr.s +++ b/libultra/src/os/setsr.s @@ -1,18 +1,10 @@ -.include "macro.inc" +#include "PR/R4300.h" +#include "sys/asm.h" +#include "sys/regdef.h" -/* assembler directives */ -.set noat /* allow manual use of $at */ -.set noreorder /* don't insert nops after branches */ -.set gp=64 /* allow use of 64-bit general purpose registers */ - -.section .text, "ax" - -/* Generated by spimdisasm 1.30.0 */ - -/* Handwritten function */ -leaf __osSetSR -mtc0 $a0, $12 /* handwritten instruction */ -nop -jr $ra -nop -.end __osSetSR +.text +LEAF(__osSetSR) + MTC0( a0, C0_SR) + NOP + jr ra +END(__osSetSR) diff --git a/libultra/src/os/writebackdcache.s b/libultra/src/os/writebackdcache.s index d323bd73..95d7c6fc 100644 --- a/libultra/src/os/writebackdcache.s +++ b/libultra/src/os/writebackdcache.s @@ -1,47 +1,54 @@ -.include "macro.inc" +#include "PR/R4300.h" +#include "sys/asm.h" +#include "sys/regdef.h" -/* assembler directives */ -.set noat /* allow manual use of $at */ -.set noreorder /* don't insert nops after branches */ -.set gp=64 /* allow use of 64-bit general purpose registers */ +.text +/** + * void osWritebackDCache(void* vaddr, s32 nbytes); + * + * Writes back the contents of the data cache to main memory for `nbytes` at `vaddr`. + * If `nbytes` is as large as or larger than the data cache size, the entire cache is + * written back. + */ +LEAF(osWritebackDCache) + /* If the amount to write back is less than or equal to 0, return immediately */ + blez a1, 2f + /* + * If the amount to write back is as large as or larger than + * the data cache size, write back all + */ + li t3, DCACHE_SIZE + bgeu a1, t3, 3f + /* + * ensure end address does not wrap around and end up smaller + * than the start address + */ + move t0, a0 + addu t1, a0, a1 + bgeu t0, t1, 2f + /* Mask and subtract to align to cache line */ + addiu t1, t1, -DCACHE_LINESIZE + andi t2, t0, DCACHE_LINEMASK + subu t0, t0, t2 +1: + .set noreorder + cache (C_HWB | CACH_PD), (t0) + bltu t0, t1, 1b + addiu t0, t0, DCACHE_LINESIZE + .set reorder +2: + jr ra -.section .text, "ax" - -/* Generated by spimdisasm 1.30.0 */ - -/* Handwritten function */ -leaf osWritebackDCache -/* D5230 800D4630 18A00011 */ blez $a1, .L800D4678 -/* D5234 800D4634 00000000 */ nop -/* D5238 800D4638 240B2000 */ addiu $t3, $zero, 0x2000 -/* D523C 800D463C 00AB082B */ sltu $at, $a1, $t3 -/* D5240 800D4640 1020000F */ beqz $at, .L800D4680 -/* D5244 800D4644 00000000 */ nop -/* D5248 800D4648 00804025 */ or $t0, $a0, $zero -/* D524C 800D464C 00854821 */ addu $t1, $a0, $a1 -/* D5250 800D4650 0109082B */ sltu $at, $t0, $t1 -/* D5254 800D4654 10200008 */ beqz $at, .L800D4678 -/* D5258 800D4658 00000000 */ nop -/* D525C 800D465C 310A000F */ andi $t2, $t0, 0xF -/* D5260 800D4660 2529FFF0 */ addiu $t1, $t1, -0x10 -/* D5264 800D4664 010A4023 */ subu $t0, $t0, $t2 -.L800D4668: -/* D5268 800D4668 BD190000 */ cache 0x19, 0x0($t0) /* handwritten instruction */ -/* D526C 800D466C 0109082B */ sltu $at, $t0, $t1 -/* D5270 800D4670 1420FFFD */ bnez $at, .L800D4668 -/* D5274 800D4674 25080010 */ addiu $t0, $t0, 0x10 -.L800D4678: -/* D5278 800D4678 03E00008 */ jr $ra -/* D527C 800D467C 00000000 */ nop -.L800D4680: -/* D5280 800D4680 3C088000 */ lui $t0, 0x8000 -/* D5284 800D4684 010B4821 */ addu $t1, $t0, $t3 -/* D5288 800D4688 2529FFF0 */ addiu $t1, $t1, -0x10 -.L800D468C: -/* D528C 800D468C BD010000 */ cache 0x01, 0x0($t0) /* handwritten instruction */ -/* D5290 800D4690 0109082B */ sltu $at, $t0, $t1 -/* D5294 800D4694 1420FFFD */ bnez $at, .L800D468C -/* D5298 800D4698 25080010 */ addiu $t0, $t0, (0x80000010 & 0xFFFF) -/* D529C 800D469C 03E00008 */ jr $ra -/* D52A0 800D46A0 00000000 */ nop -.end osWritebackDCache +/* same as osWritebackDCacheAll in operation */ +3: + li t0, K0BASE + addu t1, t0, t3 + addiu t1, t1, -DCACHE_LINESIZE +4: + .set noreorder + cache (C_IWBINV | CACH_PD), (t0) + bltu t0, t1, 4b + addiu t0, t0, DCACHE_LINESIZE + .set reorder + jr ra +END(osWritebackDCache) diff --git a/libultra/src/os/writebackdcacheall.s b/libultra/src/os/writebackdcacheall.s index efed022a..d792be87 100644 --- a/libultra/src/os/writebackdcacheall.s +++ b/libultra/src/os/writebackdcacheall.s @@ -1,25 +1,18 @@ -.include "macro.inc" +#include "PR/R4300.h" +#include "sys/asm.h" +#include "sys/regdef.h" -/* assembler directives */ -.set noat /* allow manual use of $at */ -.set noreorder /* don't insert nops after branches */ -.set gp=64 /* allow use of 64-bit general purpose registers */ - -.section .text, "ax" - -/* Generated by spimdisasm 1.30.0 */ - -/* Handwritten function */ -leaf osWritebackDCacheAll -/* D24A0 800D18A0 3C088000 */ lui $t0, 0x8000 -/* D24A4 800D18A4 240A2000 */ addiu $t2, $zero, 0x2000 -/* D24A8 800D18A8 010A4821 */ addu $t1, $t0, $t2 -/* D24AC 800D18AC 2529FFF0 */ addiu $t1, $t1, -0x10 -.L800D18B0: -/* D24B0 800D18B0 BD010000 */ cache 0x01, 0x0($t0) /* handwritten instruction */ -/* D24B4 800D18B4 0109082B */ sltu $at, $t0, $t1 -/* D24B8 800D18B8 1420FFFD */ bnez $at, .L800D18B0 -/* D24BC 800D18BC 25080010 */ addiu $t0, $t0, (0x80000010 & 0xFFFF) -/* D24C0 800D18C0 03E00008 */ jr $ra -/* D24C4 800D18C4 00000000 */ nop -.end osWritebackDCacheAll +.text +LEAF(osWritebackDCacheAll) + li t0, K0BASE + li t2, DCACHE_SIZE + addu t1, t0, t2 + addiu t1, t1, -DCACHE_LINESIZE +1: + .set noreorder + cache (C_IWBINV | CACH_PD), (t0) + bltu t0, t1, 1b + addiu t0, t0, DCACHE_LINESIZE + .set reorder + jr ra +END(osWritebackDCacheAll) diff --git a/mods/dkr.custom.ld b/mods/dkr.custom.ld index 603a89e1..e050dd60 100644 --- a/mods/dkr.custom.ld +++ b/mods/dkr.custom.ld @@ -39,11 +39,11 @@ SECTIONS build/src/hasm/entrypoint.s.o(.text); build/src*.o(.text); build/libultra/src*.o(.text); - build/asm/data/ucode_audio.s.o(.text); - build/asm/data/ucode_boot.s.o(.text); - build/asm/data/ucode_f3ddkr_dram.s.o(.text); - build/asm/data/ucode_f3ddkr_fifo.s.o(.text); - build/asm/data/ucode_f3ddkr_xbus.s.o(.text); + build/asm/data/aspMain.s.o(.text); + build/asm/data/rspboot.s.o(.text); + build/asm/data/f3ddkr_dram.s.o(.text); + build/asm/data/f3ddkr_fifo.s.o(.text); + build/asm/data/f3ddkr_xbus.s.o(.text); build/asm/data/ucode_unknown_2.s.o(.text); /* Data */ main_TEXT_END = .; @@ -51,11 +51,11 @@ SECTIONS main_DATA_START = .; build/src*.o(.data*); build/libultra/src*.o(.data); - build/asm/data/data_audio.s.o(.data); - build/asm/data/data_f3ddkr_dram.s.o(.data); - build/asm/data/data_f3ddkr_fifo.s.o(.data); - build/asm/data/data_f3ddkr_xbus.s.o(.data); - build/asm/data/data_unknown_2.s.o(.data); + build/asm/data/aspMain.s.o(.data); + build/asm/data/f3ddkr_dram.s.o(.data); + build/asm/data/f3ddkr_fifo.s.o(.data); + build/asm/data/f3ddkr_xbus.s.o(.data); + build/asm/data/ucode_unknown_2.s.o(.data); /* Rodata */ main_DATA_END = .; main_DATA_SIZE = ABSOLUTE(main_DATA_END - main_DATA_START); diff --git a/src/audiomgr.c b/src/audiomgr.c index 93166eab..3a44e36e 100644 --- a/src/audiomgr.c +++ b/src/audiomgr.c @@ -325,8 +325,8 @@ static u32 __amHandleFrameMsg(AudioInfo *info, AudioInfo *lastInfo) { t->list.t.data_ptr = (u64 *) __am.ACMDList[curAcmdList]; t->list.t.data_size = (cmdp - __am.ACMDList[curAcmdList]) * sizeof(Acmd); t->list.t.type = M_AUDTASK; - t->list.t.ucode_boot = (u64 *) rspF3DDKRBootStart; - t->list.t.ucode_boot_size = ((int) rspF3DDKRDramStart - (int) rspF3DDKRBootStart); + t->list.t.ucode_boot = (u64 *) rspbootTextStart; + t->list.t.ucode_boot_size = (s32) ((s32) rspbootTextEnd - (s32) rspbootTextStart); t->list.t.flags = OS_TASK_DP_WAIT; t->list.t.ucode = (u64 *) aspMainTextStart; t->list.t.ucode_data = (u64 *) aspMainDataStart; diff --git a/src/hasm/collision.s b/src/hasm/collision.s index 9bec8464..54e405d6 100644 --- a/src/hasm/collision.s +++ b/src/hasm/collision.s @@ -7,15 +7,15 @@ .section .rodata -glabel D_800E5F60 +dlabel D_800E5F60 .float -0.1 -glabel D_800E5F64 +dlabel D_800E5F64 .float -0.1 -glabel D_800E5F68 +dlabel D_800E5F68 .float 0.707 -glabel D_800E5F6C +dlabel D_800E5F6C .float 0.45 -glabel D_800E5F70 +dlabel D_800E5F70 .float -0.1 .section .text, "ax" diff --git a/src/hasm/entrypoint.s b/src/hasm/entrypoint.s index b3d6d066..0837386b 100644 --- a/src/hasm/entrypoint.s +++ b/src/hasm/entrypoint.s @@ -8,7 +8,7 @@ .section .bss .equ entrypointThreadStackSize, 0x1000 -glabel entrypointThreadStack +dlabel entrypointThreadStack .space entrypointThreadStackSize .size entrypointThreadStack, entrypointThreadStackSize diff --git a/src/hasm/gzip_asm.s b/src/hasm/gzip_asm.s index f08dee5c..269bf096 100644 --- a/src/hasm/gzip_asm.s +++ b/src/hasm/gzip_asm.s @@ -7,22 +7,22 @@ .section .rodata -glabel gzip_border +dlabel gzip_border .byte 16, 17, 18, 0, 8, 7, 9, 6, 10, 5, 11, 4, 12, 3, 13, 2, 14, 1, 15 -glabel gzip_cplens +dlabel gzip_cplens .half 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 17, 19, 23, 27, 31, 35, 43, 51, 59, 67, 83, 99, 115, 131, 163, 195, 227, 258, 0, 0 -glabel gzip_cplext +dlabel gzip_cplext .byte 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 0, 99, 99 -glabel gzip_cpdist +dlabel gzip_cpdist .half 1, 2, 3, 4, 5, 7, 9, 13, 17, 25, 33, 49, 65, 97, 129, 193, 257, 385, 513, 769, 1025, 1537, 2049, 3073, 4097, 6145, 8193, 12289, 16385, 24577 -glabel gzip_cpdext +dlabel gzip_cpdext .byte 0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13 -glabel gzip_mask_bits +dlabel gzip_mask_bits .half 0x0000, 0x0001, 0x0003, 0x0007, 0x000f, 0x001f, 0x003f, 0x007f, 0x00ff, 0x01ff, 0x03ff, 0x07ff, 0x0fff, 0x1fff, 0x3fff, 0x7fff, 0xffff .section .text, "ax" diff --git a/src/hasm/llmuldiv_gcc.s b/src/hasm/llmuldiv_gcc.s index 00be7317..d0fc973d 100644 --- a/src/hasm/llmuldiv_gcc.s +++ b/src/hasm/llmuldiv_gcc.s @@ -8,9 +8,9 @@ .set gp=64 /* allow use of 64-bit general purpose registers */ .section .rodata -glabel D_800E9550 +dlabel D_800E9550 .double -0.0 -glabel D_800E9558 +dlabel D_800E9558 .double -0.0 .section .text, "ax" diff --git a/src/hasm/math_util.s b/src/hasm/math_util.s index 3b7776c3..ce89eadc 100644 --- a/src/hasm/math_util.s +++ b/src/hasm/math_util.s @@ -7,17 +7,17 @@ .section .data -glabel gIntDisFlag +dlabel gIntDisFlag .word 0x00000000 -glabel gCurrentRNGSeed +dlabel gCurrentRNGSeed .word 0x5141564D /* 'QAVM' */ -glabel gPrevRNGSeed +dlabel gPrevRNGSeed .word 0x5141564D /* 'QAVM' */ /* 1025 unsigned 16 bit integer values 0-1024 */ -glabel gSineTable +dlabel gSineTable .half 0x0000, 0x0032, 0x0065, 0x0097, 0x00C9, 0x00FB, 0x012E, 0x0160, 0x0192, 0x01C4, 0x01F7, 0x0229, 0x025B, 0x028D, 0x02C0 .half 0x02F2, 0x0324, 0x0356, 0x0389, 0x03BB, 0x03ED, 0x041F, 0x0452, 0x0484, 0x04B6, 0x04E8, 0x051B, 0x054D, 0x057F, 0x05B1 .half 0x05E3, 0x0616, 0x0648, 0x067A, 0x06AC, 0x06DE, 0x0711, 0x0743, 0x0775, 0x07A7, 0x07D9, 0x080C, 0x083E, 0x0870, 0x08A2 @@ -89,7 +89,7 @@ glabel gSineTable .half 0x7FFF, 0x8000, 0x8000, 0x8000, 0x8000 /* 1025 unsigned 16 bit integer values 0-1024 */ -glabel gArcTanTable +dlabel gArcTanTable .half 0x0000, 0x000A, 0x0014, 0x001F, 0x0029, 0x0033, 0x003D, 0x0047, 0x0051, 0x005C, 0x0066, 0x0070, 0x007A, 0x0084, 0x008F .half 0x0099, 0x00A3, 0x00AD, 0x00B7, 0x00C2, 0x00CC, 0x00D6, 0x00E0, 0x00EA, 0x00F4, 0x00FF, 0x0109, 0x0113, 0x011D, 0x0127 .half 0x0131, 0x013C, 0x0146, 0x0150, 0x015A, 0x0164, 0x016F, 0x0179, 0x0183, 0x018D, 0x0197, 0x01A1, 0x01AC, 0x01B6, 0x01C0 diff --git a/src/menu.c b/src/menu.c index 21e8e07e..b36cda4a 100644 --- a/src/menu.c +++ b/src/menu.c @@ -8808,17 +8808,17 @@ void trackmenu_render_2D(s32 x, s32 y, char *hubName, char *trackName, s32 rectO rendermode_reset(&sMenuCurrDisplayList); } -// https://decomp.me/scratch/L6qKV +// https://decomp.me/scratch/bQDRA #ifdef NON_MATCHING // trackmenu_render_names void func_8008FF1C(UNUSED s32 updateRate) { s32 i; // sp7C - UNUSED s32 pad1; + char *trackName; char *hubName; - s16 temp4; + s32 selectedTrack; s32 trackSelectX; - UNUSED s32 pad2; - s32 temp; + s32 trackSelectY; + char *levelName; s32 maxTrackY; s8 *trackMenuIds; Settings *settings; // sp58 @@ -8827,112 +8827,109 @@ void func_8008FF1C(UNUSED s32 updateRate) { s32 trackY; s32 j; s32 startIndex; + s16 temp; settings = get_settings(); trackMenuIds = (s8 *) get_misc_asset(ASSET_MISC_TRACKS_MENU_IDS); - if (gMenuDelay > -23 && gMenuDelay < 23) { - if (gFFLUnlocked == -1) { - maxTrackY = 3; - } else { - maxTrackY = 4; - } - trackSelectX = (gTrackSelectX / 320); - temp = (gTrackSelectY / -gTrackSelectViewportY); - trackY = temp - 1; - startIndex = -1; - for (i = startIndex, cur = gTrackSelectRenderDetails; i < 2; i++) { - for (j = startIndex; j < 2; j++) { - trackX = trackSelectX + j; - if ((trackY < 0) || (maxTrackY < trackY) || (trackX < 0) || (trackX >= 6)) { - cur->visible = 0; - } else { - cur->visible = 1; - hubName = level_name(level_world_id(trackY + 1)); - temp4 = gTrackSelectIDs[trackY][trackX]; - cur->hubName = hubName; - if ((temp4) != -1) { - cur->trackName = level_name(trackMenuIds[(trackY * 6) + trackX]); - if (trackX == 4) { - if (((settings->trophies >> (trackY * 2)) & 3) == 3) { - cur->visible = 2; - } - } else if ((settings->courseFlagsPtr[trackMenuIds[(trackY * 6) + trackX]] & 2)) { + if (gMenuDelay <= -23 || gMenuDelay >= 23) { + return; + } + + if (gFFLUnlocked == -1) { + maxTrackY = 3; + } else { + maxTrackY = 4; + } + trackSelectX = (gTrackSelectX / 320); + trackY = (gTrackSelectY / -gTrackSelectViewportY); + trackSelectY = trackY - 1; + startIndex = -1; + for (i = startIndex, cur = gTrackSelectRenderDetails; i < 2; i++) { + for (j = startIndex; j < 2; j++, cur++) { + trackX = trackSelectX + j; + trackY = trackSelectY; + if (trackY < 0 || maxTrackY < trackY || trackX < 0 || trackX >= 6) { + cur->visible = 0; + } else { + cur->visible = 1; + levelName = level_name(level_world_id(trackY + 1)); + temp = (temp = gTrackSelectIDs[trackY][trackX]); // ???? + selectedTrack = gTrackSelectIDs[trackY][trackX]; + cur->hubName = levelName; + if (selectedTrack != -1) { + cur->trackName = level_name(trackMenuIds[((trackY * 6) + trackX)]); + if (trackX == 4) { + if ((((settings->trophies) >> (trackY * 2)) & 3) == 3) { cur->visible = 2; } - } else { - cur->trackName = (char *) gQMarkPtr; + } else if ((settings->courseFlagsPtr[trackMenuIds[((trackY * 6) + trackX)]] & 2)) { + cur->visible = 2; } - cur->xOff = ((trackX * 320) - gTrackSelectX); - if (1) {} // Fakematch - cur->yOff = ((-trackY * gTrackSelectViewportY) - gTrackSelectY); - cur->opacity = 0xFF; - if ((trackX == gSelectedTrackX) && (trackY == gSelectedTrackY)) { - cur->copyViewPort = (cur->copyViewPort & 0xFF) | 0x80; - if (gOpacityDecayTimer < 32) { - cur->opacity = gOpacityDecayTimer * 8; - } - } else { - cur->copyViewPort = cur->copyViewPort & 0xFF7F; + } else { + cur->trackName = gQMarkPtr; + } + cur->xOff = ((trackX * 320) - gTrackSelectX); + cur->yOff = ((-trackY * gTrackSelectViewportY) - gTrackSelectY); + cur->opacity = 0xFF; + if ((trackX == gSelectedTrackX) && (trackY == gSelectedTrackY)) { + cur->copyViewPort = (cur->copyViewPort & 0xFF) | 0x80; + if (gOpacityDecayTimer < 32) { + cur->opacity = gOpacityDecayTimer * 8; } - cur->copyViewPort = cur->copyViewPort & 0xFF80; - if (gMenuDelay == 0) { - if (trackY > 0) { - cur->copyViewPort = - (((cur->copyViewPort & 0xFF) | 1) & 0x7F) | (cur->copyViewPort & 0xFF80); - } - if (trackX < 5) { - cur->copyViewPort = - (((cur->copyViewPort & 0xFF) | 2) & 0x7F) | (cur->copyViewPort & 0xFF80); - } - if (trackY < maxTrackY) { - cur->copyViewPort = - (((cur->copyViewPort & 0xFF) | 4) & 0x7F) | (cur->copyViewPort & 0xFF80); - } - if (trackX > 0) { - cur->copyViewPort = - (((cur->copyViewPort & 0xFF) | 8) & 0x7F) | (cur->copyViewPort & 0xFF80); - } - if (trackX == 4 && trackY == 4) { - cur->copyViewPort = - ((cur->copyViewPort & 0xFF & 0xFF) & 0x7D) | (cur->copyViewPort & 0xFF80); - } - if (trackX == 5 && trackY == 3) { - cur->copyViewPort = - ((cur->copyViewPort & 0xFF & 0xFF) & 0x7B) | (cur->copyViewPort & 0xFF80); - } + } else { + cur->copyViewPort = cur->copyViewPort & 0xFF7F; + } + cur->copyViewPort = cur->copyViewPort & 0xFF80; + if (gMenuDelay == 0) { + if (trackY > 0) { + cur->copyViewPort = (((cur->copyViewPort & 0xFF) | 1) & 0x7F) | (cur->copyViewPort & 0xFF80); } - if (trackX == 4) { - cur->border = 6; - } else if (trackX == 5) { - cur->border = 5; - } else { - cur->border = 4; + if (trackX < 5) { + cur->copyViewPort = (((cur->copyViewPort & 0xFF) | 2) & 0x7F) | (cur->copyViewPort & 0xFF80); + } + if (trackY < maxTrackY) { + cur->copyViewPort = (((cur->copyViewPort & 0xFF) | 4) & 0x7F) | (cur->copyViewPort & 0xFF80); + } + if (trackX > 0) { + cur->copyViewPort = (((cur->copyViewPort & 0xFF) | 8) & 0x7F) | (cur->copyViewPort & 0xFF80); + } + if (trackX == 4 && trackY == 4) { + cur->copyViewPort = ((cur->copyViewPort & 0xFF & 0xFF) & 0x7D) | (cur->copyViewPort & 0xFF80); + } + if (trackX == 5 && trackY == 3) { + cur->copyViewPort = ((cur->copyViewPort & 0xFF & 0xFF) & 0x7B) | (cur->copyViewPort & 0xFF80); } } - cur++; - } - trackY++; - } - camDisableUserView(0, TRUE); - menu_camera_centre(); - mtx_ortho(&sMenuCurrDisplayList, &sMenuCurrHudMat); - rendermode_reset(&sMenuCurrDisplayList); - gDPPipeSync(sMenuCurrDisplayList++); - D_80126928 = 64; - D_8012692C = 32; - gTrackMenuHubName = NULL; - for (i = 0; i < ARRAY_COUNT(gTrackSelectRenderDetails); i++) { - if (gTrackSelectRenderDetails[i].visible != 0) { - trackmenu_render_2D(gTrackSelectRenderDetails[i].xOff, gTrackSelectRenderDetails[i].yOff, - gTrackSelectRenderDetails[i].hubName, gTrackSelectRenderDetails[i].trackName, - gTrackSelectRenderDetails[i].opacity, gTrackSelectRenderDetails[i].border, - ((u32) gTrackSelectRenderDetails[i].viewPort) >> 0xF, - (gTrackSelectRenderDetails[i].visible == 1) ? D_800E05D4 : D_800E05F4, - gTrackSelectRenderDetails[i].copyViewPort & 0x7F); + if (trackX == 4) { + cur->border = 6; + } else if (trackX == 5) { + cur->border = 5; + } else { + cur->border = 4; + } } } - gTrackSelectVertsFlip = 1 - gTrackSelectVertsFlip; + trackSelectY++; } + camDisableUserView(0, TRUE); + menu_camera_centre(); + mtx_ortho(&sMenuCurrDisplayList, &sMenuCurrHudMat); + rendermode_reset(&sMenuCurrDisplayList); + gDPPipeSync(sMenuCurrDisplayList++); + D_80126928 = 64; + D_8012692C = 32; + gTrackMenuHubName = NULL; + for (i = 0; i < ARRAY_COUNT(gTrackSelectRenderDetails); i++) { + if (gTrackSelectRenderDetails[i].visible != 0) { + trackmenu_render_2D(gTrackSelectRenderDetails[i].xOff, gTrackSelectRenderDetails[i].yOff, + gTrackSelectRenderDetails[i].hubName, gTrackSelectRenderDetails[i].trackName, + gTrackSelectRenderDetails[i].opacity, gTrackSelectRenderDetails[i].border, + ((u32) gTrackSelectRenderDetails[i].viewPort) >> 0xF, + (gTrackSelectRenderDetails[i].visible == 1) ? D_800E05D4 : D_800E05F4, + gTrackSelectRenderDetails[i].copyViewPort & 0x7F); + } + } + gTrackSelectVertsFlip = 1 - gTrackSelectVertsFlip; } #else #pragma GLOBAL_ASM("asm/nonmatchings/menu/func_8008FF1C.s") diff --git a/src/rcp_dkr.c b/src/rcp_dkr.c index ea112080..ba9254b8 100644 --- a/src/rcp_dkr.c +++ b/src/rcp_dkr.c @@ -180,8 +180,8 @@ s32 gfxtask_run_xbus(Gfx *dlBegin, Gfx *dlEnd, UNUSED s32 recvMesg) { dkrtask->task.data_size = dlEnd - dlBegin; dkrtask->task.type = M_GFXTASK; dkrtask->task.flags = OS_TASK_DP_WAIT; - dkrtask->task.ucode_boot = (u64 *) rspF3DDKRBootStart; - dkrtask->task.ucode_boot_size = (s32) (rspF3DDKRDramStart - rspF3DDKRBootStart); + dkrtask->task.ucode_boot = (u64 *) rspbootTextStart; + dkrtask->task.ucode_boot_size = (s32) ((s32) rspbootTextEnd - (s32) rspbootTextStart); dkrtask->task.ucode = (u64 *) rspF3DDKRXbusStart; dkrtask->task.ucode_data = (u64 *) rspF3DDKRDataXbusStart; dkrtask->task.ucode_data_size = SP_UCODE_DATA_SIZE; @@ -220,8 +220,8 @@ UNUSED void gfxtask_run_xbus2(Gfx *dlBegin, Gfx *dlEnd, s32 recvMesg) { dkrtask->task.data_size = (s32) (dlEnd - dlBegin) * sizeof(Gfx); dkrtask->task.type = M_GFXTASK; dkrtask->task.flags = OS_TASK_DP_WAIT; - dkrtask->task.ucode_boot = (u64 *) rspF3DDKRBootStart; - dkrtask->task.ucode_boot_size = (s32) (rspF3DDKRDramStart - rspF3DDKRBootStart); + dkrtask->task.ucode_boot = (u64 *) rspbootTextStart; + dkrtask->task.ucode_boot_size = (s32) ((s32) rspbootTextEnd - (s32) rspbootTextStart); dkrtask->task.ucode = (u64 *) rspF3DDKRXbusStart; dkrtask->task.ucode_data = (u64 *) rspF3DDKRDataXbusStart; dkrtask->task.ucode_data_size = SP_UCODE_DATA_SIZE; @@ -270,11 +270,11 @@ UNUSED void gfxtask_run_fifo(Gfx *dlBegin, Gfx *dlEnd, s32 recvMesg) { } dkrtask->task.data_ptr = (u64 *) dlBegin; - dkrtask->task.ucode_boot = (u64 *) rspF3DDKRBootStart; + dkrtask->task.ucode_boot = (u64 *) rspbootTextStart; dkrtask->task.data_size = (s32) (dlEnd - dlBegin) * sizeof(Gfx); dkrtask->task.type = M_GFXTASK; dkrtask->task.flags = OS_TASK_DP_WAIT; - dkrtask->task.ucode_boot_size = (s32) (rspF3DDKRDramStart - rspF3DDKRBootStart); + dkrtask->task.ucode_boot_size = (s32) ((s32) rspbootTextEnd - (s32) rspbootTextStart); dkrtask->task.ucode = (u64 *) rspF3DDKRFifoStart; dkrtask->task.ucode_data = (u64 *) rspF3DDKRDataFifoStart; dkrtask->task.ucode_data_size = SP_UCODE_DATA_SIZE; @@ -326,8 +326,8 @@ UNUSED void gfxtask_run_fifo2(Gfx *dlBegin, Gfx *dlEnd, s32 recvMesg) { dkrtask->task.data_ptr = (u64 *) dlBegin; dkrtask->task.type = M_GFXTASK; dkrtask->task.flags = OS_TASK_DP_WAIT; - dkrtask->task.ucode_boot = (u64 *) rspF3DDKRBootStart; - dkrtask->task.ucode_boot_size = (s32) (rspF3DDKRDramStart - rspF3DDKRBootStart); + dkrtask->task.ucode_boot = (u64 *) rspbootTextStart; + dkrtask->task.ucode_boot_size = (s32) ((s32) rspbootTextEnd - (s32) rspbootTextStart); dkrtask->task.ucode = (u64 *) rspF3DDKRFifoStart; dkrtask->task.ucode_data = (u64 *) rspF3DDKRDataFifoStart; dkrtask->task.ucode_data_size = SP_UCODE_DATA_SIZE; diff --git a/src/rcp_dkr.h b/src/rcp_dkr.h index ac0a6b67..a81f4613 100644 --- a/src/rcp_dkr.h +++ b/src/rcp_dkr.h @@ -46,13 +46,11 @@ extern s32 gGfxBufCounter; extern s32 gGfxBufCounter2; extern s32 gGfxTaskIsRunning; -// Defined in dkr.ld -extern s8 rspF3DDKRDramStart[]; -extern s8 rspF3DDKRBootStart[]; -extern s8 rspF3DDKRXbusStart[]; -extern s8 rspF3DDKRDataXbusStart[]; -extern s8 rspF3DDKRFifoStart[]; -extern s8 rspF3DDKRDataFifoStart[]; +extern long long int rspF3DDKRDramStart[], rspF3DDKRDramEnd[]; +extern long long int rspF3DDKRXbusStart[], rspF3DDKRXbusEnd[]; +extern long long int rspF3DDKRDataXbusStart[], rspF3DDKRDataXbusEnd[]; +extern long long int rspF3DDKRFifoStart[], rspF3DDKRFifoEnd[]; +extern long long int rspF3DDKRDataFifoStart[], rspF3DDKRDataFifoEnd[]; s32 gfxtask_wait(void); void bgdraw_primcolour(u8 red, u8 green, u8 blue); diff --git a/tools/m2c b/tools/m2c index 7b0af9cd..6983af41 160000 --- a/tools/m2c +++ b/tools/m2c @@ -1 +1 @@ -Subproject commit 7b0af9cd8775b26e6fe92a3d8a045a012ccd6cf4 +Subproject commit 6983af41fd78e3e025a07ab0c2bb069be57e6ccc diff --git a/ver/splat/dkr.jpn.v79.yaml b/ver/splat/dkr.jpn.v79.yaml index a9319261..ecbb34f3 100644 --- a/ver/splat/dkr.jpn.v79.yaml +++ b/ver/splat/dkr.jpn.v79.yaml @@ -17,6 +17,10 @@ options: src_path: src build_path: build asset_path: assets + asm_function_macro: glabel + asm_jtbl_label_macro: jlabel + asm_data_macro: dlabel + asm_emit_size_directive: True section_order: [".text", ".data", ".rodata", ".bss"] migrate_rodata_to_functions: True hasm_in_src_path: True @@ -254,11 +258,11 @@ segments: - [0xD8F30, c, ../libultra/src/libc/xldtob] - [0xD99F0, hasm, ../libultra/src/os/setcompare] - [0xD9A00, c, ../libultra/src/libc/ldiv] - - [0xD9B90, textbin, ucode_audio] - - [0xDAA50, textbin, ucode_boot] - - [0xDAB20, textbin, ucode_f3ddkr_dram] - - [0xDBD20, textbin, ucode_f3ddkr_fifo] - - [0xDCF00, textbin, ucode_f3ddkr_xbus] + - [0xD9B90, textbin, aspMain] + - [0xDAA50, textbin, rspboot] + - [0xDAB20, textbin, f3ddkr_dram] + - [0xDBD20, textbin, f3ddkr_fifo] + - [0xDCF00, textbin, f3ddkr_xbus] - [0xDE100, textbin, ucode_unknown_2] - [0xDEBC0, .data, audio] - [0xDEC10, .data, audiomgr] @@ -378,11 +382,11 @@ segments: - [0xEBE80, .rodata, ../libultra/src/gu/sinf] - [0xEBED0, .rodata, ../libultra/src/libc/xldtob] - [0xEBF30, hasm, ../libultra/src/gu/libm_vals] - - { start: 0xEBF40, type: databin, name: data_audio, linker_section_order: .rodata } - - { start: 0xEC210, type: databin, name: data_f3ddkr_dram, linker_section_order: .rodata } - - { start: 0xECA10, type: databin, name: data_f3ddkr_fifo, linker_section_order: .rodata } - - { start: 0xED210, type: databin, name: data_f3ddkr_xbus, linker_section_order: .rodata } - - { start: 0xEDA10, type: databin, name: data_unknown_2, linker_section_order: .rodata } + - { start: 0xEBF40, type: databin, name: aspMain, linker_section_order: .rodata } + - { start: 0xEC210, type: databin, name: f3ddkr_dram, linker_section_order: .rodata } + - { start: 0xECA10, type: databin, name: f3ddkr_fifo, linker_section_order: .rodata } + - { start: 0xED210, type: databin, name: f3ddkr_xbus, linker_section_order: .rodata } + - { start: 0xEDA10, type: databin, name: ucode_unknown_2, linker_section_order: .rodata } - { type: .bss, vram: 0x800ED9D0, name: audio } - { type: .bss, vram: 0x80117A00, name: audiomgr } - { type: .bss, vram: 0x8011B640, name: audiosfx } @@ -439,7 +443,7 @@ segments: - { type: .bss, vram: 0x8012EC80, name: ../libultra/src/io/sptask } - { type: .bss, vram: 0x8012ECC0, name: ../libultra/src/io/piacs } - { type: .bss, vram: 0x8012ECE0, name: ../libultra/src/os/timerintr } - - { type: .bss, vram: 0x8012ED20, name: ../libultra/src/os/exceptasm } + - { type: .bss, vram: 0x8012ED20, name: ../libultra/src/debug/kdebugserver } - name: assets type: bin diff --git a/ver/splat/dkr.pal.v77.yaml b/ver/splat/dkr.pal.v77.yaml index 266b1c6a..0a2dfe81 100644 --- a/ver/splat/dkr.pal.v77.yaml +++ b/ver/splat/dkr.pal.v77.yaml @@ -17,6 +17,10 @@ options: src_path: src build_path: build asset_path: assets + asm_function_macro: glabel + asm_jtbl_label_macro: jlabel + asm_data_macro: dlabel + asm_emit_size_directive: True section_order: [".text", ".data", ".rodata", ".bss"] migrate_rodata_to_functions: True hasm_in_src_path: True @@ -254,11 +258,11 @@ segments: - [0xD7630, c, ../libultra/src/libc/xldtob] - [0xD80F0, hasm, ../libultra/src/os/setcompare] - [0xD8100, c, ../libultra/src/libc/ldiv] - - [0xD8290, textbin, ucode_audio] - - [0xD9150, textbin, ucode_boot] - - [0xD9220, textbin, ucode_f3ddkr_dram] - - [0xDA420, textbin, ucode_f3ddkr_fifo] - - [0xDB600, textbin, ucode_f3ddkr_xbus] + - [0xD8290, textbin, aspMain] + - [0xD9150, textbin, rspboot] + - [0xD9220, textbin, f3ddkr_dram] + - [0xDA420, textbin, f3ddkr_fifo] + - [0xDB600, textbin, f3ddkr_xbus] - [0xDC800, textbin, ucode_unknown_2] - [0xDD2C0, .data, audio] - [0xDD310, .data, audiomgr] @@ -378,11 +382,11 @@ segments: - [0xEA4A0, .rodata, ../libultra/src/gu/sinf] - [0xEA4F0, .rodata, ../libultra/src/libc/xldtob] - [0xEA550, hasm, ../libultra/src/gu/libm_vals] - - { start: 0xEA560, type: databin, name: data_audio, linker_section_order: .rodata } - - { start: 0xEA830, type: databin, name: data_f3ddkr_dram, linker_section_order: .rodata } - - { start: 0xEB030, type: databin, name: data_f3ddkr_fifo, linker_section_order: .rodata } - - { start: 0xEB830, type: databin, name: data_f3ddkr_xbus, linker_section_order: .rodata } - - { start: 0xEC030, type: databin, name: data_unknown_2, linker_section_order: .rodata } + - { start: 0xEA560, type: databin, name: aspMain, linker_section_order: .rodata } + - { start: 0xEA830, type: databin, name: f3ddkr_dram, linker_section_order: .rodata } + - { start: 0xEB030, type: databin, name: f3ddkr_fifo, linker_section_order: .rodata } + - { start: 0xEB830, type: databin, name: f3ddkr_xbus, linker_section_order: .rodata } + - { start: 0xEC030, type: databin, name: ucode_unknown_2, linker_section_order: .rodata } - { type: .bss, vram: 0x800EBFF0, name: audio } - { type: .bss, vram: 0x80116020, name: audiomgr } - { type: .bss, vram: 0x80119C60, name: audiosfx } @@ -439,7 +443,7 @@ segments: - { type: .bss, vram: 0x8012D230, name: ../libultra/src/io/sptask } - { type: .bss, vram: 0x8012D270, name: ../libultra/src/io/piacs } - { type: .bss, vram: 0x8012D290, name: ../libultra/src/os/timerintr } - - { type: .bss, vram: 0x8012D2D0, name: ../libultra/src/os/exceptasm } + - { type: .bss, vram: 0x8012D2D0, name: ../libultra/src/debug/kdebugserver } - name: assets type: bin diff --git a/ver/splat/dkr.pal.v80.yaml b/ver/splat/dkr.pal.v80.yaml index 3a2d9903..9e5ec589 100644 --- a/ver/splat/dkr.pal.v80.yaml +++ b/ver/splat/dkr.pal.v80.yaml @@ -17,6 +17,10 @@ options: src_path: src build_path: build asset_path: assets + asm_function_macro: glabel + asm_jtbl_label_macro: jlabel + asm_data_macro: dlabel + asm_emit_size_directive: True section_order: [".text", ".data", ".rodata", ".bss"] migrate_rodata_to_functions: True hasm_in_src_path: True @@ -254,11 +258,11 @@ segments: - [0xD7B90, c, ../libultra/src/libc/xldtob] - [0xD8650, hasm, ../libultra/src/os/setcompare] - [0xD8660, c, ../libultra/src/libc/ldiv] - - [0xD87F0, textbin, ucode_audio] - - [0xD96B0, textbin, ucode_boot] - - [0xD9780, textbin, ucode_f3ddkr_dram] - - [0xDA980, textbin, ucode_f3ddkr_fifo] - - [0xDBB70, textbin, ucode_f3ddkr_xbus] + - [0xD87F0, textbin, aspMain] + - [0xD96B0, textbin, rspboot] + - [0xD9780, textbin, f3ddkr_dram] + - [0xDA980, textbin, f3ddkr_fifo] + - [0xDBB70, textbin, f3ddkr_xbus] - [0xDCD60, textbin, ucode_unknown_2] - [0xDD830, .data, audio] - [0xDD880, .data, audiomgr] @@ -378,11 +382,11 @@ segments: - [0xEAA20, .rodata, ../libultra/src/gu/sinf] - [0xEAA70, .rodata, ../libultra/src/libc/xldtob] - [0xEAAD0, hasm, ../libultra/src/gu/libm_vals] - - { start: 0xEAAE0, type: databin, name: data_audio, linker_section_order: .rodata } - - { start: 0xEADB0, type: databin, name: data_f3ddkr_dram, linker_section_order: .rodata } - - { start: 0xEB5B0, type: databin, name: data_f3ddkr_fifo, linker_section_order: .rodata } - - { start: 0xEBDB0, type: databin, name: data_f3ddkr_xbus, linker_section_order: .rodata } - - { start: 0xEC5B0, type: databin, name: data_unknown_2, linker_section_order: .rodata } + - { start: 0xEAAE0, type: databin, name: aspMain, linker_section_order: .rodata } + - { start: 0xEADB0, type: databin, name: f3ddkr_dram, linker_section_order: .rodata } + - { start: 0xEB5B0, type: databin, name: f3ddkr_fifo, linker_section_order: .rodata } + - { start: 0xEBDB0, type: databin, name: f3ddkr_xbus, linker_section_order: .rodata } + - { start: 0xEC5B0, type: databin, name: ucode_unknown_2, linker_section_order: .rodata } - { type: .bss, vram: 0x800EC570, name: audio } - { type: .bss, vram: 0x801165A0, name: audiomgr } - { type: .bss, vram: 0x8011A1E0, name: audiosfx } @@ -439,7 +443,7 @@ segments: - { type: .bss, vram: 0x8012D7F0, name: ../libultra/src/io/sptask } - { type: .bss, vram: 0x8012D830, name: ../libultra/src/io/piacs } - { type: .bss, vram: 0x8012D850, name: ../libultra/src/os/timerintr } - - { type: .bss, vram: 0x8012D890, name: ../libultra/src/os/exceptasm } + - { type: .bss, vram: 0x8012D890, name: ../libultra/src/debug/kdebugserver } - name: assets type: bin diff --git a/ver/splat/dkr.us.v77.yaml b/ver/splat/dkr.us.v77.yaml index 82ace25e..92601a5a 100644 --- a/ver/splat/dkr.us.v77.yaml +++ b/ver/splat/dkr.us.v77.yaml @@ -17,6 +17,10 @@ options: src_path: src build_path: build asset_path: assets + asm_function_macro: glabel + asm_jtbl_label_macro: jlabel + asm_data_macro: dlabel + asm_emit_size_directive: True section_order: [".text", ".data", ".rodata", ".bss"] migrate_rodata_to_functions: True hasm_in_src_path: True @@ -254,11 +258,11 @@ segments: - [0xD75A0, c, ../libultra/src/libc/xldtob] - [0xD8060, hasm, ../libultra/src/os/setcompare] - [0xD8070, c, ../libultra/src/libc/ldiv] - - [0xD8200, textbin, ucode_audio] - - [0xD90C0, textbin, ucode_boot] - - [0xD9190, textbin, ucode_f3ddkr_dram] - - [0xDA390, textbin, ucode_f3ddkr_fifo] - - [0xDB570, textbin, ucode_f3ddkr_xbus] + - [0xD8200, textbin, aspMain] + - [0xD90C0, textbin, rspboot] + - [0xD9190, textbin, f3ddkr_dram] + - [0xDA390, textbin, f3ddkr_fifo] + - [0xDB570, textbin, f3ddkr_xbus] - [0xDC770, textbin, ucode_unknown_2] - [0xDD230, .data, audio] - [0xDD280, .data, audiomgr] @@ -378,11 +382,11 @@ segments: - [0xEA410, .rodata, ../libultra/src/gu/sinf] - [0xEA460, .rodata, ../libultra/src/libc/xldtob] - [0xEA4C0, hasm, ../libultra/src/gu/libm_vals] - - { start: 0xEA4D0, type: databin, name: data_audio, linker_section_order: .rodata } - - { start: 0xEA7A0, type: databin, name: data_f3ddkr_dram, linker_section_order: .rodata } - - { start: 0xEAFA0, type: databin, name: data_f3ddkr_fifo, linker_section_order: .rodata } - - { start: 0xEB7A0, type: databin, name: data_f3ddkr_xbus, linker_section_order: .rodata } - - { start: 0xEBFA0, type: databin, name: data_unknown_2, linker_section_order: .rodata } + - { start: 0xEA4D0, type: databin, name: aspMain, linker_section_order: .rodata } + - { start: 0xEA7A0, type: databin, name: f3ddkr_dram, linker_section_order: .rodata } + - { start: 0xEAFA0, type: databin, name: f3ddkr_fifo, linker_section_order: .rodata } + - { start: 0xEB7A0, type: databin, name: f3ddkr_xbus, linker_section_order: .rodata } + - { start: 0xEBFA0, type: databin, name: ucode_unknown_2, linker_section_order: .rodata } - { type: .bss, vram: 0x800EBF60, name: audio } - { type: .bss, vram: 0x80115F90, name: audiomgr } - { type: .bss, vram: 0x80119BD0, name: audiosfx } @@ -439,7 +443,7 @@ segments: - { type: .bss, vram: 0x8012D1A0, name: ../libultra/src/io/sptask } - { type: .bss, vram: 0x8012D1E0, name: ../libultra/src/io/piacs } - { type: .bss, vram: 0x8012D200, name: ../libultra/src/os/timerintr } - - { type: .bss, vram: 0x8012D240, name: ../libultra/src/os/exceptasm } + - { type: .bss, vram: 0x8012D240, name: ../libultra/src/debug/kdebugserver } # TODO: If we can split up the assets bin file to these two files, we can properly # define the symbol for __ASSETS_LUT_END even if it changes with custom assets diff --git a/ver/splat/dkr.us.v80.yaml b/ver/splat/dkr.us.v80.yaml index e08c340b..bfa299fc 100644 --- a/ver/splat/dkr.us.v80.yaml +++ b/ver/splat/dkr.us.v80.yaml @@ -17,6 +17,10 @@ options: src_path: src build_path: build asset_path: assets + asm_function_macro: glabel + asm_jtbl_label_macro: jlabel + asm_data_macro: dlabel + asm_emit_size_directive: True section_order: [".text", ".data", ".rodata", ".bss"] migrate_rodata_to_functions: True hasm_in_src_path: True @@ -254,11 +258,11 @@ segments: - [0xD7B00, c, ../libultra/src/libc/xldtob] - [0xD85C0, hasm, ../libultra/src/os/setcompare] - [0xD85D0, c, ../libultra/src/libc/ldiv] - - [0xD8760, textbin, ucode_audio] - - [0xD9620, textbin, ucode_boot] - - [0xD96F0, textbin, ucode_f3ddkr_dram] - - [0xDA8F0, textbin, ucode_f3ddkr_fifo] - - [0xDBAE0, textbin, ucode_f3ddkr_xbus] + - [0xD8760, textbin, aspMain] + - [0xD9620, textbin, rspboot] + - [0xD96F0, textbin, f3ddkr_dram] + - [0xDA8F0, textbin, f3ddkr_fifo] + - [0xDBAE0, textbin, f3ddkr_xbus] - [0xDCCD0, textbin, ucode_unknown_2] - [0xDD7A0, .data, audio] - [0xDD7F0, .data, audiomgr] @@ -378,11 +382,11 @@ segments: - [0xEA990, .rodata, ../libultra/src/gu/sinf] - [0xEA9E0, .rodata, ../libultra/src/libc/xldtob] - [0xEAA40, hasm, ../libultra/src/gu/libm_vals] - - { start: 0xEAA50, type: databin, name: data_audio, linker_section_order: .rodata } - - { start: 0xEAD20, type: databin, name: data_f3ddkr_dram, linker_section_order: .rodata } - - { start: 0xEB520, type: databin, name: data_f3ddkr_fifo, linker_section_order: .rodata } - - { start: 0xEBD20, type: databin, name: data_f3ddkr_xbus, linker_section_order: .rodata } - - { start: 0xEC520, type: databin, name: data_unknown_2, linker_section_order: .rodata } + - { start: 0xEAA50, type: databin, name: aspMain, linker_section_order: .rodata } + - { start: 0xEAD20, type: databin, name: f3ddkr_dram, linker_section_order: .rodata } + - { start: 0xEB520, type: databin, name: f3ddkr_fifo, linker_section_order: .rodata } + - { start: 0xEBD20, type: databin, name: f3ddkr_xbus, linker_section_order: .rodata } + - { start: 0xEC520, type: databin, name: ucode_unknown_2, linker_section_order: .rodata } - { type: .bss, vram: 0x800EC4E0, name: audio } - { type: .bss, vram: 0x80116510, name: audiomgr } - { type: .bss, vram: 0x8011A150, name: audiosfx } @@ -439,7 +443,7 @@ segments: - { type: .bss, vram: 0x8012D760, name: ../libultra/src/io/sptask } - { type: .bss, vram: 0x8012D7A0, name: ../libultra/src/io/piacs } - { type: .bss, vram: 0x8012D7C0, name: ../libultra/src/os/timerintr } - - { type: .bss, vram: 0x8012D800, name: ../libultra/src/os/exceptasm } + - { type: .bss, vram: 0x8012D800, name: ../libultra/src/debug/kdebugserver } - name: assets type: bin diff --git a/ver/symbols/symbol_addrs.jpn.v79.txt b/ver/symbols/symbol_addrs.jpn.v79.txt index 1fe58e36..aabc92b2 100644 --- a/ver/symbols/symbol_addrs.jpn.v79.txt +++ b/ver/symbols/symbol_addrs.jpn.v79.txt @@ -2151,12 +2151,12 @@ lldiv = 0x800D8E00; ldiv = 0x800D8F00; // ucode_text jpn v79 -aspMainTextStart = 0x800D8F90; // size:0xEC0 -rspF3DDKRBootStart = 0x800D9E50; // size:0xD0 -rspF3DDKRDramStart = 0x800D9F20; // size:0x1200 -rspF3DDKRFifoStart = 0x800DB120; // size:0x11E0 -rspF3DDKRXbusStart = 0x800DC300; // size:0x1200 -rspUnknown2Start = 0x800DD500; // size:0xAC0 +aspMainTextStart = 0x800D8F90; // size:0xEC0 name_end:aspMainTextEnd +rspbootTextStart = 0x800D9E50; // size:0xD0 name_end:rspbootTextEnd +rspF3DDKRDramStart = 0x800D9F20; // size:0x1200 name_end:rspF3DDKRDramEnd +rspF3DDKRFifoStart = 0x800DB120; // size:0x11E0 name_end:rspF3DDKRFifoEnd +rspF3DDKRXbusStart = 0x800DC300; // size:0x1200 name_end:rspF3DDKRXbusEnd +rspUnknown2Start = 0x800DD500; // size:0xAC0 name_end:rspUnknown2End // audio.c .data gMusicPlayer = 0x800DDFC0; @@ -3502,11 +3502,11 @@ _Ldtob_1e8 = 0x800EB328; // type:f64 __libm_qnan_f = 0x800EB330; // type:f64 // ucode_data -aspMainDataStart = 0x800EB340; // size:0x2D0 -rspF3DDKRDataDramStart = 0x800EB610; // size:0x800 -rspF3DDKRDataFifoStart = 0x800EBE10; // size:0x800 -rspF3DDKRDataXbusStart = 0x800EC610; // size:0x800 -rspUnknown2DataStart = 0x800ECE10; // size:0xBC0 +aspMainDataStart = 0x800EB340; // size:0x2D0 name_end:aspMainDataEnd +rspF3DDKRDataDramStart = 0x800EB610; // size:0x800 name_end:rspF3DDKRDataDramEnd +rspF3DDKRDataFifoStart = 0x800EBE10; // size:0x800 name_end:rspF3DDKRDataFifoEnd +rspF3DDKRDataXbusStart = 0x800EC610; // size:0x800 name_end:rspF3DDKRDataXbusEnd +rspUnknown2DataStart = 0x800ECE10; // size:0xBC0 name_end:rspUnknown2DataEnd // Start of BSS gAudioHeapStack = 0x800ED9D0; // size:0x29D88 diff --git a/ver/symbols/symbol_addrs.pal.v77.txt b/ver/symbols/symbol_addrs.pal.v77.txt index 90630246..bf04b5db 100644 --- a/ver/symbols/symbol_addrs.pal.v77.txt +++ b/ver/symbols/symbol_addrs.pal.v77.txt @@ -2062,12 +2062,12 @@ lldiv = 0x800D7500; ldiv = 0x800D7600; // ucode_text pal v77 -aspMainTextStart = 0x800D7690; // size:0xEC0 -rspF3DDKRBootStart = 0x800D8550; // size:0xD0 -rspF3DDKRDramStart = 0x800D8620; // size:0x1200 -rspF3DDKRFifoStart = 0x800D9820; // size:0x11E0 -rspF3DDKRXbusStart = 0x800DAA00; // size:0x1200 -rspUnknown2Start = 0x800DBC00; // size:0xAC0 +aspMainTextStart = 0x800D7690; // size:0xEC0 name_end:aspMainTextEnd +rspbootTextStart = 0x800D8550; // size:0xD0 name_end:rspbootTextEnd +rspF3DDKRDramStart = 0x800D8620; // size:0x1200 name_end:rspF3DDKRDramEnd +rspF3DDKRFifoStart = 0x800D9820; // size:0x11E0 name_end:rspF3DDKRFifoEnd +rspF3DDKRXbusStart = 0x800DAA00; // size:0x1200 name_end:rspF3DDKRXbusEnd +rspUnknown2Start = 0x800DBC00; // size:0xAC0 name_end:rspUnknown2End gMusicPlayer = 0x800DC6C0; gJinglePlayer = 0x800DC6C4; @@ -3250,11 +3250,11 @@ Ldtob_Inf = 0x800E993C; // type:asciz force_not_migration:true defined:true _Genld_0_string = 0x800E9940; // type:asciz force_not_migration:true defined:true _Ldtob_1e8 = 0x800E9948; // type:f64 __libm_qnan_f = 0x800E9950; // type:f64 -aspMainDataStart = 0x800E9960; // size:0x2D0 -rspF3DDKRDataDramStart = 0x800E9C30; // size:0x800 -rspF3DDKRDataFifoStart = 0x800EA430; // size:0x800 -rspF3DDKRDataXbusStart = 0x800EAC30; // size:0x800 -rspUnknown2DataStart = 0x800EB430; // size:0xBC0 +aspMainDataStart = 0x800E9960; // size:0x2D0 name_end:aspMainDataEnd +rspF3DDKRDataDramStart = 0x800E9C30; // size:0x800 name_end:rspF3DDKRDataDramEnd +rspF3DDKRDataFifoStart = 0x800EA430; // size:0x800 name_end:rspF3DDKRDataFifoEnd +rspF3DDKRDataXbusStart = 0x800EAC30; // size:0x800 name_end:rspF3DDKRDataXbusEnd +rspUnknown2DataStart = 0x800EB430; // size:0xBC0 name_end:rspUnknown2DataEnd gAudioHeapStack = 0x800EBFF0; // size:0x29D88 gALHeap = 0x80115D78; gSequenceTable = 0x80115D88; diff --git a/ver/symbols/symbol_addrs.pal.v80.txt b/ver/symbols/symbol_addrs.pal.v80.txt index 46166f1c..999bfcfe 100644 --- a/ver/symbols/symbol_addrs.pal.v80.txt +++ b/ver/symbols/symbol_addrs.pal.v80.txt @@ -1983,12 +1983,12 @@ lldiv = 0x800D7A60; ldiv = 0x800D7B60; // ucode_text pal v80 -aspMainTextStart = 0x800D7BF0; // size:0xEC0 -rspF3DDKRBootStart = 0x800D8AB0; // size:0xD0 -rspF3DDKRDramStart = 0x800D8B80; // size:0x1200 -rspF3DDKRFifoStart = 0x800D9D80; // size:0x11F0 -rspF3DDKRXbusStart = 0x800DAF70; // size:0x11F0 -rspUnknown2Start = 0x800DC160; // size:0xAD0 +aspMainTextStart = 0x800D7BF0; // size:0xEC0 name_end:aspMainTextEnd +rspbootTextStart = 0x800D8AB0; // size:0xD0 name_end:rspbootTextEnd +rspF3DDKRDramStart = 0x800D8B80; // size:0x1200 name_end:rspF3DDKRDramEnd +rspF3DDKRFifoStart = 0x800D9D80; // size:0x11F0 name_end:rspF3DDKRFifoEnd +rspF3DDKRXbusStart = 0x800DAF70; // size:0x11F0 name_end:rspF3DDKRXbusEnd +rspUnknown2Start = 0x800DC160; // size:0xAD0 name_end:rspUnknown2End sDebugVersionInfoString = 0x800E7730; // type:asciz @@ -3180,11 +3180,11 @@ Ldtob_Inf = 0x800E9EBC; // type:asciz force_not_migration:true defined:true _Genld_0_string = 0x800E9EC0; // type:asciz force_not_migration:true defined:true _Ldtob_1e8 = 0x800E9EC8; // type:f64 __libm_qnan_f = 0x800E9ED0; // type:f64 -aspMainDataStart = 0x800E9EE0; // size:0x2D0 -rspF3DDKRDataDramStart = 0x800EA1B0; // size:0x800 -rspF3DDKRDataFifoStart = 0x800EA9B0; // size:0x800 -rspF3DDKRDataXbusStart = 0x800EB1B0; // size:0x800 -rspUnknown2DataStart = 0x800EB9B0; // size:0xBC0 +aspMainDataStart = 0x800E9EE0; // size:0x2D0 name_end:aspMainDataEnd +rspF3DDKRDataDramStart = 0x800EA1B0; // size:0x800 name_end:rspF3DDKRDataDramEnd +rspF3DDKRDataFifoStart = 0x800EA9B0; // size:0x800 name_end:rspF3DDKRDataFifoEnd +rspF3DDKRDataXbusStart = 0x800EB1B0; // size:0x800 name_end:rspF3DDKRDataXbusEnd +rspUnknown2DataStart = 0x800EB9B0; // size:0xBC0 name_end:rspUnknown2DataEnd gAudioHeapStack = 0x800EC570; // size:0x29D88 gALHeap = 0x801162F8; gSequenceTable = 0x80116308; diff --git a/ver/symbols/symbol_addrs.us.v77.txt b/ver/symbols/symbol_addrs.us.v77.txt index 0dffb00b..636e9b08 100644 --- a/ver/symbols/symbol_addrs.us.v77.txt +++ b/ver/symbols/symbol_addrs.us.v77.txt @@ -2146,12 +2146,12 @@ lldiv = 0x800D7470; ldiv = 0x800D7570; // ucode_text us v77 -aspMainTextStart = 0x800D7600; // size:0xEC0 -rspF3DDKRBootStart = 0x800D84C0; // size:0xD0 -rspF3DDKRDramStart = 0x800D8590; // size:0x1200 -rspF3DDKRFifoStart = 0x800D9790; // size:0x11E0 -rspF3DDKRXbusStart = 0x800DA970; // size:0x1200 -rspUnknown2Start = 0x800DBB70; // size:0xAC0 +aspMainTextStart = 0x800D7600; // size:0xEC0 name_end:aspMainTextEnd +rspbootTextStart = 0x800D84C0; // size:0xD0 name_end:rspbootTextEnd +rspF3DDKRDramStart = 0x800D8590; // size:0x1200 name_end:rspF3DDKRDramEnd +rspF3DDKRFifoStart = 0x800D9790; // size:0x11E0 name_end:rspF3DDKRFifoEnd +rspF3DDKRXbusStart = 0x800DA970; // size:0x1200 name_end:rspF3DDKRXbusEnd +rspUnknown2Start = 0x800DBB70; // size:0xAC0 name_end:rspUnknown2End // audio.c .data gMusicPlayer = 0x800DC630; @@ -3615,11 +3615,11 @@ _Ldtob_1e8 = 0x800E98B8; // type:f64 __libm_qnan_f = 0x800E98C0; // type:f64 // ucode_data -aspMainDataStart = 0x800E98D0; // size:0x2D0 -rspF3DDKRDataDramStart = 0x800E9BA0; // size:0x800 -rspF3DDKRDataFifoStart = 0x800EA3A0; // size:0x800 -rspF3DDKRDataXbusStart = 0x800EABA0; // size:0x800 -rspUnknown2DataStart = 0x800EB3A0; // size:0xBC0 +aspMainDataStart = 0x800E98D0; // size:0x2D0 name_end:aspMainDataEnd +rspF3DDKRDataDramStart = 0x800E9BA0; // size:0x800 name_end:rspF3DDKRDataDramEnd +rspF3DDKRDataFifoStart = 0x800EA3A0; // size:0x800 name_end:rspF3DDKRDataFifoEnd +rspF3DDKRDataXbusStart = 0x800EABA0; // size:0x800 name_end:rspF3DDKRDataXbusEnd +rspUnknown2DataStart = 0x800EB3A0; // size:0xBC0 name_end:rspUnknown2DataEnd // audio.c .bss gAudioHeapStack = 0x800EBF60; // size:0x29D88 diff --git a/ver/symbols/symbol_addrs.us.v80.txt b/ver/symbols/symbol_addrs.us.v80.txt index c163aca2..5a2b5b6d 100644 --- a/ver/symbols/symbol_addrs.us.v80.txt +++ b/ver/symbols/symbol_addrs.us.v80.txt @@ -1982,12 +1982,12 @@ lldiv = 0x800D79D0; ldiv = 0x800D7AD0; // ucode_text us v80 -aspMainTextStart = 0x800D7B60; // size:0xEC0 -rspF3DDKRBootStart = 0x800D8A20; // size:0xD0 -rspF3DDKRDramStart = 0x800D8AF0; // size:0x1200 -rspF3DDKRFifoStart = 0x800D9CF0; // size:0x11F0 -rspF3DDKRXbusStart = 0x800DAEE0; // size:0x11F0 -rspUnknown2Start = 0x800DC0D0; // size:0xAD0 +aspMainTextStart = 0x800D7B60; // size:0xEC0 name_end:aspMainTextEnd +rspbootTextStart = 0x800D8A20; // size:0xD0 name_end:rspbootTextEnd +rspF3DDKRDramStart = 0x800D8AF0; // size:0x1200 name_end:rspF3DDKRDramEnd +rspF3DDKRFifoStart = 0x800D9CF0; // size:0x11F0 name_end:rspF3DDKRFifoEnd +rspF3DDKRXbusStart = 0x800DAEE0; // size:0x11F0 name_end:rspF3DDKRXbusEnd +rspUnknown2Start = 0x800DC0D0; // size:0xAD0 name_end:rspUnknown2End sDebugVersionInfoString = 0x800E76A0; // type:asciz sDebugBuildDateString = 0x800E76A8; // type:asciz @@ -3176,11 +3176,11 @@ Ldtob_Inf = 0x800E9E2C; // type:asciz force_not_migration:true defined:true _Genld_0_string = 0x800E9E30; // type:asciz force_not_migration:true defined:true _Ldtob_1e8 = 0x800E9E38; // type:f64 __libm_qnan_f = 0x800E9E40; // type:f64 -aspMainDataStart = 0x800E9E50; // size:0x2D0 -rspF3DDKRDataDramStart = 0x800EA120; // size:0x800 -rspF3DDKRDataFifoStart = 0x800EA920; // size:0x800 -rspF3DDKRDataXbusStart = 0x800EB120; // size:0x800 -rspUnknown2DataStart = 0x800EB920; // size:0xBC0 +aspMainDataStart = 0x800E9E50; // size:0x2D0 name_end:aspMainDataEnd +rspF3DDKRDataDramStart = 0x800EA120; // size:0x800 name_end:rspF3DDKRDataDramEnd +rspF3DDKRDataFifoStart = 0x800EA920; // size:0x800 name_end:rspF3DDKRDataFifoEnd +rspF3DDKRDataXbusStart = 0x800EB120; // size:0x800 name_end:rspF3DDKRDataXbusEnd +rspUnknown2DataStart = 0x800EB920; // size:0xBC0 name_end:rspUnknown2DataEnd gAudioHeapStack = 0x800EC4E0; // size:0x29D88 gALHeap = 0x80116268; gSequenceTable = 0x80116278;