Make the GpioV2Lib not depend on platform and provide required APIs
Late this library could be used to replace the common GpioV2Lib.
This library could support multiple GPIO controller and the interface
is transparent to caller.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This tool does data convert between [.yaml, .dlt] and [.h].
e.g.: Generate GPIO DLT from GPIO .h file
> python Platform\CommonBoardPkg\Tools\GpioV2DataConvert.py
-w Platform\ArrowlakeBoardPkg;Platform\ArrowlakeBoardPkg\CfgData;
Silicon\ArrowlakePkg
-if GpioTableArlSPostMem.h
-of arls.dlt
NOTE: This tool will search all the paths specified by "-w" to find GPIO
related definitions.
Signed-off-by: Guo Dong <guo.dong@intel.com>
When OsLoader shell "fs load" tried to free memory, the
assertion happened with the message "CR has Bad Signature".
It's caused when FreePool() tried to free the memory allocated
by AllocatePages(), and the memory signature is not as expected.
So modify the free memory function to FreePages()
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
- Add support for MBL CRB board.
- Add HD Audio I2S codecs.
- PCM3168A codec for MBL RVP boards.
- Configure GPIO pins to be used as display HPD in the ACPI DSDT table.
Signed-off-by: costel-ignat <costel.ignat@intel.com>
- Added new CPU Id and Plaform ID (MBL RVP).
- Add PreMem GPIO table.
- Add DDI configuration table.
- Add new SPD entry to accommodate the new memory configuration.
- Add support for PCM3168A Audio Codec.
- Implement board detection over I2c.
Signed-off-by: costel-ignat <costel.ignat@intel.com>
When checking whether to update the RTD3 SSDT table for ADL RVP/CRB
SKUs, the GetPlatformId() return values are compared against the board
id that was probed from the hardware (instead of the platform id to
which the board id was mapped; cf. EcSupport.c).
Signed-off-by: Bruno Achauer <bruno.achauer@intel.com>
BIOS version is NEX RPL-S MR4/RPL-S Refresh MR2 Hotfix (5134_05) FSP
FSP version is 0C00DE40
platform version is 1.4
Microcode Files are: ['m_07_90672_00000036.pdb', 'm_32_b0671_00000129.pdb']
Signed-off-by: Randy <randy.lin@intel.com>
This commit adds support for PCIe resizable BARsupport.
The feature can be enabled by setting PcdResizableBarSupport
for the board build script and its disabled by default.
Signed-off-by: pastorcx <mariano-paulx.pastorcici@intel.com>
Removed the source code related to TCC tools
including DSO switch, SWSRAM switch, TCC subregions
TCC Error Log switch, RTCM, RTCT
The code change applies on TGL/EHL/ADL/RPL/MTL
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
DebugAgentLib was using its own IDT Entry structure definition that
didn't adjust for x64. Removed this definition and switched to built
in definition from ProcessorBind.h which does adjust for architecture
correctly.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
* fix: [ADLN] Prevent to enumerate RP25 and above
PCIe RP25 and above are supported only when PCH seriese is PCH S.
Prevent to enumerate RP25 and above to address resource conflict with eMMC.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
* fix: [ADLN] Update eMMC driver strength
Update eMMC driver strength 40Ohm for CRB.
Improve performance benchmark result.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
---------
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
Guo Dong
Vincent Chen
costel-ignat
Bruno Achauer
Randy
Antara Borwankar
Pastorcici, Mariano-paulX
Biswas Arghya
bejeanmo
tsaikevin
Stanley Chang