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ARL: clean up the code

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Remove unused file, definitions or libraries.

Signed-off-by: Guo Dong <guo.dong@intel.com>
This commit is contained in:
Guo Dong
2024-09-29 16:26:50 -07:00
committed by Guo Dong
parent 76ee9f23c6
commit 69e9996e56
20 changed files with 36 additions and 5243 deletions
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Silicon/ArrowlakePkg/Include/GpioPinsVer2Lp.h
-35
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@@ -1,35 +0,0 @@
/** @file
GPIO pins for TGL-PCH-LP,
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _GPIO_PINS_VER2_LP_H_
#define _GPIO_PINS_VER2_LP_H_
///
/// Unique ID used in GpioPad defines
///
#define GPIO_VER2_LP_CHIPSET_ID 0x9
///
/// TGL LP GPIO Groups
/// Use below for functions from PCH GPIO Lib which
/// require GpioGroup as argument
///
#define GPIO_VER2_LP_GROUP_GPP_B 0x0900
#define GPIO_VER2_LP_GROUP_GPP_T 0x0901
#define GPIO_VER2_LP_GROUP_GPP_A 0x0902
#define GPIO_VER2_LP_GROUP_GPP_R 0x0903
#define GPIO_VER2_LP_GROUP_GPD 0x0905
#define GPIO_VER2_LP_GROUP_GPP_S 0x0906
#define GPIO_VER2_LP_GROUP_GPP_H 0x0907
#define GPIO_VER2_LP_GROUP_GPP_D 0x0908
#define GPIO_VER2_LP_GROUP_GPP_U 0x0909
#define GPIO_VER2_LP_GROUP_VGPIO 0x090A
#define GPIO_VER2_LP_GROUP_GPP_C 0x090B
#define GPIO_VER2_LP_GROUP_GPP_F 0x090C
#define GPIO_VER2_LP_GROUP_GPP_E 0x090E
#endif // _GPIO_PINS_VER2_LP_H_
Silicon/ArrowlakePkg/Include/GpioPinsVer4S.h
-473
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@@ -1,473 +0,0 @@
/** @file
GPIO pins for ADL-PCH-S,
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _GPIO_PINS_VER4_S_H_
#define _GPIO_PINS_VER4_S_H_
///
/// Unique ID used in GpioPad defines
///
#define GPIO_VER4_S_CHIPSET_ID 0x8
///
/// ADL S GPIO Groups
/// Use below for functions from PCH GPIO Lib which
/// require GpioGroup as argument
///
#define GPIO_VER4_S_GROUP_GPD 0x0808
///
/// Unique ID used in GpioPad defines
///
#define GPIO_VER6_SOC_S_CHIPSET_ID 0xA
///
/// MTL SoC-S GPIO Groups
/// Use below for functions from PCH GPIO Lib which
/// require GpioGroup as argument
///
// COM0
#define GPIO_VER6_SOC_S_GROUP_GPP_A ((GPIO_VER6_SOC_S_CHIPSET_ID << 8) | 0x00)
#define GPIO_VER6_SOC_S_GROUP_VGPIO_0 ((GPIO_VER6_SOC_S_CHIPSET_ID << 8) | 0x01)
#define GPIO_VER6_SOC_S_GROUP_GPP_C ((GPIO_VER6_SOC_S_CHIPSET_ID << 8) | 0x02)
// COM1
#define GPIO_VER6_SOC_S_GROUP_GPP_B ((GPIO_VER6_SOC_S_CHIPSET_ID << 8) | 0x03)
#define GPIO_VER6_SOC_S_GROUP_VGPIO_3 ((GPIO_VER6_SOC_S_CHIPSET_ID << 8) | 0x04)
#define GPIO_VER6_SOC_S_GROUP_GPP_D ((GPIO_VER6_SOC_S_CHIPSET_ID << 8) | 0x05)
// COM2
// COM3
#define GPIO_VER6_SOC_S_GROUP_JTAG ((GPIO_VER6_SOC_S_CHIPSET_ID << 8) | 0x06)
#define GPIO_VER6_SOC_S_GROUP_VGPIO_4 ((GPIO_VER6_SOC_S_CHIPSET_ID << 8) | 0x07)
///
/// Unique ID used in GpioPad defines
///
#define GPIO_VER6_SOC_M_CHIPSET_ID 0xA
///
/// MTL SoC-M GPIO Groups
/// Use below for functions from PCH GPIO Lib which
/// require GpioGroup as argument
///
// COM0
#define GPIO_VER6_SOC_M_GROUP_CPU ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x00)
#define GPIO_VER6_SOC_M_GROUP_GPP_V ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x01)
#define GPIO_VER6_SOC_M_GROUP_GPP_C ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x02)
// COM1
#define GPIO_VER6_SOC_M_GROUP_GPP_A ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x03)
#define GPIO_VER6_SOC_M_GROUP_GPP_E ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x04)
// COM2
// COM3
#define GPIO_VER6_SOC_M_GROUP_GPP_H ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x05)
#define GPIO_VER6_SOC_M_GROUP_GPP_F ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x06)
#define GPIO_VER6_SOC_M_GROUP_SPI_SYS ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x07)
#define GPIO_VER6_SOC_M_GROUP_USB_THC ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x08)
// COM4
#define GPIO_VER6_SOC_M_GROUP_GPP_S ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x09)
#define GPIO_VER6_SOC_M_GROUP_JTAG ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x0A)
// COM5
#define GPIO_VER6_SOC_M_GROUP_GPP_B ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x0B)
#define GPIO_VER6_SOC_M_GROUP_GPP_D ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x0C)
#define GPIO_VER6_SOC_M_GROUP_VGPIO ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x0D)
///
/// MTL SOC GPIO pins
/// Use below for functions from PCH GPIO Lib which
/// require GpioPad as argument. Encoding used here
/// has all information required by library functions
///
// COM0
#define GPIO_VER6_SOC_M_CPU_PECI ((GPIO_VER6_SOC_M_GROUP_CPU << 16 ) | 0x00)
#define GPIO_VER6_SOC_M_CPU_RESET_B ((GPIO_VER6_SOC_M_GROUP_CPU << 16 ) | 0x01)
#define GPIO_VER6_SOC_M_CPU_SOUT ((GPIO_VER6_SOC_M_GROUP_CPU << 16 ) | 0x02)
#define GPIO_VER6_SOC_M_CPU_SCK ((GPIO_VER6_SOC_M_GROUP_CPU << 16 ) | 0x03)
#define GPIO_VER6_SOC_M_CPU_ALERT_B ((GPIO_VER6_SOC_M_GROUP_CPU << 16 ) | 0x04)
#define GPIO_VER6_SOC_M_GPP_V0 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x00)
#define GPIO_VER6_SOC_M_GPP_V1 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x01)
#define GPIO_VER6_SOC_M_GPP_V2 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x02)
#define GPIO_VER6_SOC_M_GPP_V3 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x03)
#define GPIO_VER6_SOC_M_GPP_V4 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x04)
#define GPIO_VER6_SOC_M_GPP_V5 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x05)
#define GPIO_VER6_SOC_M_GPP_V6 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x06)
#define GPIO_VER6_SOC_M_GPP_V7 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x07)
#define GPIO_VER6_SOC_M_GPP_V8 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x08)
#define GPIO_VER6_SOC_M_GPP_V9 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x09)
#define GPIO_VER6_SOC_M_GPP_V10 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x0A)
#define GPIO_VER6_SOC_M_GPP_V11 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x0B)
#define GPIO_VER6_SOC_M_GPP_V12 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x0C)
#define GPIO_VER6_SOC_M_GPP_V13 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x0D)
#define GPIO_VER6_SOC_M_GPP_V14 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x0E)
#define GPIO_VER6_SOC_M_GPP_V15 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x0F)
#define GPIO_VER6_SOC_M_GPP_V16 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x10)
#define GPIO_VER6_SOC_M_GPP_V17 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x11)
#define GPIO_VER6_SOC_M_GPP_V18 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x12)
#define GPIO_VER6_SOC_M_GPP_V19 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x13)
#define GPIO_VER6_SOC_M_GPP_V20 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x14)
#define GPIO_VER6_SOC_M_GPP_V21 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x15)
#define GPIO_VER6_SOC_M_GPP_V22 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x16)
#define GPIO_VER6_SOC_M_GPP_V23 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x17)
#define GPIO_VER6_SOC_M_GPP_C0 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x00)
#define GPIO_VER6_SOC_M_GPP_C1 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x01)
#define GPIO_VER6_SOC_M_GPP_C2 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x02)
#define GPIO_VER6_SOC_M_GPP_C3 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x03)
#define GPIO_VER6_SOC_M_GPP_C4 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x04)
#define GPIO_VER6_SOC_M_GPP_C5 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x05)
#define GPIO_VER6_SOC_M_GPP_C6 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x06)
#define GPIO_VER6_SOC_M_GPP_C7 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x07)
#define GPIO_VER6_SOC_M_GPP_C8 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x08)
#define GPIO_VER6_SOC_M_GPP_C9 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x09)
#define GPIO_VER6_SOC_M_GPP_C10 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x0A)
#define GPIO_VER6_SOC_M_GPP_C11 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x0B)
#define GPIO_VER6_SOC_M_GPP_C12 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x0C)
#define GPIO_VER6_SOC_M_GPP_C13 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x0D)
#define GPIO_VER6_SOC_M_GPP_C14 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x0E)
#define GPIO_VER6_SOC_M_GPP_C15 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x0F)
#define GPIO_VER6_SOC_M_GPP_C16 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x10)
#define GPIO_VER6_SOC_M_GPP_C17 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x11)
#define GPIO_VER6_SOC_M_GPP_C18 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x12)
#define GPIO_VER6_SOC_M_GPP_C19 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x13)
#define GPIO_VER6_SOC_M_GPP_C20 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x14)
#define GPIO_VER6_SOC_M_GPP_C21 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x15)
#define GPIO_VER6_SOC_M_GPP_C22 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x16)
#define GPIO_VER6_SOC_M_GPP_C23 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x17)
// COM1
#define GPIO_VER6_SOC_M_GPP_A0 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x00)
#define GPIO_VER6_SOC_M_GPP_A1 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x01)
#define GPIO_VER6_SOC_M_GPP_A2 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x02)
#define GPIO_VER6_SOC_M_GPP_A3 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x03)
#define GPIO_VER6_SOC_M_GPP_A4 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x04)
#define GPIO_VER6_SOC_M_GPP_A5 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x05)
#define GPIO_VER6_SOC_M_GPP_A6 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x06)
#define GPIO_VER6_SOC_M_GPP_A7 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x07)
#define GPIO_VER6_SOC_M_GPP_A8 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x08)
#define GPIO_VER6_SOC_M_GPP_A9 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x09)
#define GPIO_VER6_SOC_M_GPP_A10 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x0A)
#define GPIO_VER6_SOC_M_GPP_A11 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x0B)
#define GPIO_VER6_SOC_M_GPP_A12 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x0C)
#define GPIO_VER6_SOC_M_GPP_A13 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x0D)
#define GPIO_VER6_SOC_M_GPP_A14 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x0E)
#define GPIO_VER6_SOC_M_GPP_A15 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x0F)
#define GPIO_VER6_SOC_M_GPP_A16 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x10)
#define GPIO_VER6_SOC_M_GPP_A17 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x11)
#define GPIO_VER6_SOC_M_GPP_A18 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x12)
#define GPIO_VER6_SOC_M_GPP_A19 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x13)
#define GPIO_VER6_SOC_M_GPP_A20 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x14)
#define GPIO_VER6_SOC_M_GPP_A21 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x15)
#define GPIO_VER6_SOC_M_GPP_A22 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x16)
#define GPIO_VER6_SOC_M_GPP_A23 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x17)
#define GPIO_VER6_SOC_M_ESPI_CLK_LOOPBK ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x18)
#define GPIO_VER6_SOC_M_GPP_E0 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x00)
#define GPIO_VER6_SOC_M_GPP_E1 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x01)
#define GPIO_VER6_SOC_M_GPP_E2 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x02)
#define GPIO_VER6_SOC_M_GPP_E3 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x03)
#define GPIO_VER6_SOC_M_GPP_E4 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x04)
#define GPIO_VER6_SOC_M_GPP_E5 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x05)
#define GPIO_VER6_SOC_M_GPP_E6 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x06)
#define GPIO_VER6_SOC_M_GPP_E7 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x07)
#define GPIO_VER6_SOC_M_GPP_E8 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x08)
#define GPIO_VER6_SOC_M_GPP_E9 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x09)
#define GPIO_VER6_SOC_M_GPP_E10 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x0A)
#define GPIO_VER6_SOC_M_GPP_E11 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x0B)
#define GPIO_VER6_SOC_M_GPP_E12 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x0C)
#define GPIO_VER6_SOC_M_GPP_E13 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x0D)
#define GPIO_VER6_SOC_M_GPP_E14 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x0E)
#define GPIO_VER6_SOC_M_GPP_E15 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x0F)
#define GPIO_VER6_SOC_M_GPP_E16 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x10)
#define GPIO_VER6_SOC_M_GPP_E17 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x11)
#define GPIO_VER6_SOC_M_GPP_E18 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x12)
#define GPIO_VER6_SOC_M_GPP_E19 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x13)
#define GPIO_VER6_SOC_M_GPP_E20 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x14)
#define GPIO_VER6_SOC_M_GPP_E21 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x15)
#define GPIO_VER6_SOC_M_GPP_E22 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x16)
#define GPIO_VER6_SOC_M_GPP_E23 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x17)
#define GPIO_VER6_SOC_M_THC0_GPSI0_CLK_LOOPBK ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x18)
// COM2
// COM3
#define GPIO_VER6_SOC_M_GPP_H0 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x00)
#define GPIO_VER6_SOC_M_GPP_H1 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x01)
#define GPIO_VER6_SOC_M_GPP_H2 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x02)
#define GPIO_VER6_SOC_M_GPP_H3 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x03)
#define GPIO_VER6_SOC_M_GPP_H4 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x04)
#define GPIO_VER6_SOC_M_GPP_H5 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x05)
#define GPIO_VER6_SOC_M_GPP_H6 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x06)
#define GPIO_VER6_SOC_M_GPP_H7 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x07)
#define GPIO_VER6_SOC_M_GPP_H8 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x08)
#define GPIO_VER6_SOC_M_GPP_H9 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x09)
#define GPIO_VER6_SOC_M_GPP_H10 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x0A)
#define GPIO_VER6_SOC_M_GPP_H11 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x0B)
#define GPIO_VER6_SOC_M_GPP_H12 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x0C)
#define GPIO_VER6_SOC_M_GPP_H13 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x0D)
#define GPIO_VER6_SOC_M_GPP_H14 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x0E)
#define GPIO_VER6_SOC_M_GPP_H15 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x0F)
#define GPIO_VER6_SOC_M_GPP_H16 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x10)
#define GPIO_VER6_SOC_M_GPP_H17 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x11)
#define GPIO_VER6_SOC_M_GPP_H18 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x12)
#define GPIO_VER6_SOC_M_GPP_H19 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x13)
#define GPIO_VER6_SOC_M_GPP_H20 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x14)
#define GPIO_VER6_SOC_M_GPP_H21 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x15)
#define GPIO_VER6_SOC_M_GPP_H22 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x16)
#define GPIO_VER6_SOC_M_GPP_H23 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x17)
#define GPIO_VER6_SOC_M_LPI3C1_CLK_LOOPBK ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x18)
#define GPIO_VER6_SOC_M_LPI3C0_CLK_LOOPBK ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x19)
#define GPIO_VER6_SOC_M_GPP_F0 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x00)
#define GPIO_VER6_SOC_M_GPP_F1 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x01)
#define GPIO_VER6_SOC_M_GPP_F2 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x02)
#define GPIO_VER6_SOC_M_GPP_F3 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x03)
#define GPIO_VER6_SOC_M_GPP_F4 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x04)
#define GPIO_VER6_SOC_M_GPP_F5 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x05)
#define GPIO_VER6_SOC_M_GPP_F6 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x06)
#define GPIO_VER6_SOC_M_GPP_F7 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x07)
#define GPIO_VER6_SOC_M_GPP_F8 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x08)
#define GPIO_VER6_SOC_M_GPP_F9 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x09)
#define GPIO_VER6_SOC_M_GPP_F10 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x0A)
#define GPIO_VER6_SOC_M_GPP_F11 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x0B)
#define GPIO_VER6_SOC_M_GPP_F12 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x0C)
#define GPIO_VER6_SOC_M_GPP_F13 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x0D)
#define GPIO_VER6_SOC_M_GPP_F14 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x0E)
#define GPIO_VER6_SOC_M_GPP_F15 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x0F)
#define GPIO_VER6_SOC_M_GPP_F16 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x10)
#define GPIO_VER6_SOC_M_GPP_F17 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x11)
#define GPIO_VER6_SOC_M_GPP_F18 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x12)
#define GPIO_VER6_SOC_M_GPP_F19 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x13)
#define GPIO_VER6_SOC_M_GPP_F20 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x14)
#define GPIO_VER6_SOC_M_GPP_F21 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x15)
#define GPIO_VER6_SOC_M_GPP_F22 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x16)
#define GPIO_VER6_SOC_M_GPP_F23 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x17)
#define GPIO_VER6_SOC_M_THC1_GSPI1_CLK_LOOPBK ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x18)
#define GPIO_VER6_SOC_M_GSPI0A_CLK_LOOPBK ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x19)
#define GPIO_VER6_SOC_M_SPI0_IO2 ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x00)
#define GPIO_VER6_SOC_M_SPI0_IO3 ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x01)
#define GPIO_VER6_SOC_M_SPI0_MOSI_IO_0 ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x02)
#define GPIO_VER6_SOC_M_SPI0_MISO_IO_0 ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x03)
#define GPIO_VER6_SOC_M_SPI0_TPM_CS_B ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x04)
#define GPIO_VER6_SOC_M_SPI0_FLASH_0_CS_B ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x05)
#define GPIO_VER6_SOC_M_SPI0_FLASH_1_CS_B ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x06)
#define GPIO_VER6_SOC_M_SPI0_CLK ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x07)
#define GPIO_VER6_SOC_M_BKLTEN ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x08)
#define GPIO_VER6_SOC_M_BKLTCTL ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x09)
#define GPIO_VER6_SOC_M_VDDEN ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x0A)
#define GPIO_VER6_SOC_M_SYS_PWROK ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x0B)
#define GPIO_VER6_SOC_M_SYS_RESET_B ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x0C)
#define GPIO_VER6_SOC_M_MLK_RST_B ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x0D)
#define GPIO_VER6_SOC_M_SPI0_CLK_LOOPBK ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x0E)
#define GPIO_VER6_SOC_M_USB_0 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x00)
#define GPIO_VER6_SOC_M_USB_1 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x01)
#define GPIO_VER6_SOC_M_USB_2 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x02)
#define GPIO_VER6_SOC_M_USB_3 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x03)
#define GPIO_VER6_SOC_M_USB_4 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x04)
#define GPIO_VER6_SOC_M_USB_5 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x05)
#define GPIO_VER6_SOC_M_USB_6 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x06)
#define GPIO_VER6_SOC_M_USB_7 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x07)
#define GPIO_VER6_SOC_M_TS_0 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x08)
#define GPIO_VER6_SOC_M_TS_1 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x09)
#define GPIO_VER6_SOC_M_THC_0 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x0A)
#define GPIO_VER6_SOC_M_THC_1 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x0B)
#define GPIO_VER6_SOC_M_THC_2 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x0C)
#define GPIO_VER6_SOC_M_THC_3 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x0D)
// COM4
#define GPIO_VER6_SOC_M_GPP_S0 ((GPIO_VER6_SOC_M_GROUP_GPP_S << 16) | 0x00)
#define GPIO_VER6_SOC_M_GPP_S1 ((GPIO_VER6_SOC_M_GROUP_GPP_S << 16) | 0x01)
#define GPIO_VER6_SOC_M_GPP_S2 ((GPIO_VER6_SOC_M_GROUP_GPP_S << 16) | 0x02)
#define GPIO_VER6_SOC_M_GPP_S3 ((GPIO_VER6_SOC_M_GROUP_GPP_S << 16) | 0x03)
#define GPIO_VER6_SOC_M_GPP_S4 ((GPIO_VER6_SOC_M_GROUP_GPP_S << 16) | 0x04)
#define GPIO_VER6_SOC_M_GPP_S5 ((GPIO_VER6_SOC_M_GROUP_GPP_S << 16) | 0x05)
#define GPIO_VER6_SOC_M_GPP_S6 ((GPIO_VER6_SOC_M_GROUP_GPP_S << 16) | 0x06)
#define GPIO_VER6_SOC_M_GPP_S7 ((GPIO_VER6_SOC_M_GROUP_GPP_S << 16) | 0x07)
#define GPIO_VER6_SOC_M_MBPB0 ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x00)
#define GPIO_VER6_SOC_M_MBPB1 ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x01)
#define GPIO_VER6_SOC_M_MBPB2 ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x02)
#define GPIO_VER6_SOC_M_MBPB3 ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x03)
#define GPIO_VER6_SOC_M_JTAG_TDO ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x04)
#define GPIO_VER6_SOC_M_PRDY_B ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x05)
#define GPIO_VER6_SOC_M_PREQ_B ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x06)
#define GPIO_VER6_SOC_M_JTAG_TDI ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x07)
#define GPIO_VER6_SOC_M_JTAG_TMS ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x08)
#define GPIO_VER6_SOC_M_JTAG_TCK ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x09)
#define GPIO_VER6_SOC_M_DBG_PMODE ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x0A)
#define GPIO_VER6_SOC_M_JTAG_TRST_B ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x0B)
// COM5
#define GPIO_VER6_SOC_M_GPP_B0 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x00)
#define GPIO_VER6_SOC_M_GPP_B1 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x01)
#define GPIO_VER6_SOC_M_GPP_B2 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x02)
#define GPIO_VER6_SOC_M_GPP_B3 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x03)
#define GPIO_VER6_SOC_M_GPP_B4 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x04)
#define GPIO_VER6_SOC_M_GPP_B5 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x05)
#define GPIO_VER6_SOC_M_GPP_B6 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x06)
#define GPIO_VER6_SOC_M_GPP_B7 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x07)
#define GPIO_VER6_SOC_M_GPP_B8 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x08)
#define GPIO_VER6_SOC_M_GPP_B9 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x09)
#define GPIO_VER6_SOC_M_GPP_B10 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x0A)
#define GPIO_VER6_SOC_M_GPP_B11 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x0B)
#define GPIO_VER6_SOC_M_GPP_B12 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x0C)
#define GPIO_VER6_SOC_M_GPP_B13 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x0D)
#define GPIO_VER6_SOC_M_GPP_B14 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x0E)
#define GPIO_VER6_SOC_M_GPP_B15 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x0F)
#define GPIO_VER6_SOC_M_GPP_B16 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x10)
#define GPIO_VER6_SOC_M_GPP_B17 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x11)
#define GPIO_VER6_SOC_M_GPP_B18 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x12)
#define GPIO_VER6_SOC_M_GPP_B19 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x13)
#define GPIO_VER6_SOC_M_GPP_B20 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x14)
#define GPIO_VER6_SOC_M_GPP_B21 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x15)
#define GPIO_VER6_SOC_M_GPP_B22 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x16)
#define GPIO_VER6_SOC_M_GPP_B23 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x17)
#define GPIO_VER6_SOC_M_ISHI3C0_CLK_LOOPBK ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x18)
#define GPIO_VER6_SOC_M_GPP_D0 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x00)
#define GPIO_VER6_SOC_M_GPP_D1 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x01)
#define GPIO_VER6_SOC_M_GPP_D2 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x02)
#define GPIO_VER6_SOC_M_GPP_D3 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x03)
#define GPIO_VER6_SOC_M_GPP_D4 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x04)
#define GPIO_VER6_SOC_M_GPP_D5 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x05)
#define GPIO_VER6_SOC_M_GPP_D6 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x06)
#define GPIO_VER6_SOC_M_GPP_D7 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x07)
#define GPIO_VER6_SOC_M_GPP_D8 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x08)
#define GPIO_VER6_SOC_M_GPP_D9 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x09)
#define GPIO_VER6_SOC_M_GPP_D10 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x0A)
#define GPIO_VER6_SOC_M_GPP_D11 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x0B)
#define GPIO_VER6_SOC_M_GPP_D12 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x0C)
#define GPIO_VER6_SOC_M_GPP_D13 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x0D)
#define GPIO_VER6_SOC_M_GPP_D14 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x0E)
#define GPIO_VER6_SOC_M_GPP_D15 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x0F)
#define GPIO_VER6_SOC_M_GPP_D16 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x10)
#define GPIO_VER6_SOC_M_GPP_D17 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x11)
#define GPIO_VER6_SOC_M_GPP_D18 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x12)
#define GPIO_VER6_SOC_M_GPP_D19 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x13)
#define GPIO_VER6_SOC_M_GPP_D20 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x14)
#define GPIO_VER6_SOC_M_GPP_D21 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x15)
#define GPIO_VER6_SOC_M_GPP_D22 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x16)
#define GPIO_VER6_SOC_M_GPP_D23 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x17)
#define GPIO_VER6_SOC_M_BOOTHALT_B ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x18)
#define GPIO_VER6_SOC_M_VGPIO0 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x00)
#define GPIO_VER6_SOC_M_VGPIO4 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x01)
#define GPIO_VER6_SOC_M_VGPIO5 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x02)
#define GPIO_VER6_SOC_M_VGPIO6 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x03)
#define GPIO_VER6_SOC_M_VGPIO7 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x04)
#define GPIO_VER6_SOC_M_VGPIO8 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x05)
#define GPIO_VER6_SOC_M_VGPIO9 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x06)
#define GPIO_VER6_SOC_M_VGPIO10 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x07)
#define GPIO_VER6_SOC_M_VGPIO11 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x08)
#define GPIO_VER6_SOC_M_VGPIO12 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x09)
#define GPIO_VER6_SOC_M_VGPIO13 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x0A)
#define GPIO_VER6_SOC_M_VGPIO18 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x0B)
#define GPIO_VER6_SOC_M_VGPIO19 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x0C)
#define GPIO_VER6_SOC_M_VGPIO20 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x0D)
#define GPIO_VER6_SOC_M_VGPIO21 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x0E)
#define GPIO_VER6_SOC_M_VGPIO22 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x0F)
#define GPIO_VER6_SOC_M_VGPIO23 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x10)
#define GPIO_VER6_SOC_M_VGPIO24 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x11)
#define GPIO_VER6_SOC_M_VGPIO25 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x12)
#define GPIO_VER6_SOC_M_VGPIO30 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x13)
#define GPIO_VER6_SOC_M_VGPIO31 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x14)
#define GPIO_VER6_SOC_M_VGPIO32 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x15)
#define GPIO_VER6_SOC_M_VGPIO33 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x16)
#define GPIO_VER6_SOC_M_VGPIO34 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x17)
#define GPIO_VER6_SOC_M_VGPIO35 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x18)
#define GPIO_VER6_SOC_M_VGPIO36 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x19)
#define GPIO_VER6_SOC_M_VGPIO37 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x1A)
#define GPIO_VER6_SOC_M_VGPIO40 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x1B)
#define GPIO_VER6_SOC_M_VGPIO41 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x1C)
#define GPIO_VER6_SOC_M_VGPIO42 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x1D)
#define GPIO_VER6_SOC_M_VGPIO43 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x1E)
#define GPIO_VER6_SOC_M_VGPIO44 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x1F)
#define GPIO_VER6_SOC_M_VGPIO45 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x20)
#define GPIO_VER6_SOC_M_VGPIO46 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x21)
#define GPIO_VER6_SOC_M_VGPIO47 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x22)
//
// GPIO Pin Muxing
// Determines a selection of physical pad for a given signal.
// Please refer to GPIO_NATIVE_PAD type.
// If certain signal is not listed below it means that it can be enabled
// only on a single pad and muxing setting is not needed.
//
#define GPIO_VER6_SOC_M_MUXING_ISH_SPI0_CS_GPP_D5 0x3A2CA005 // Native Function 3
#define GPIO_VER6_SOC_M_MUXING_ISH_SPI0_CS_GPP_F17 0x4A26A011 // Native Function 4
#define GPIO_VER6_SOC_M_MUXING_ISH_SPI0_CLK_GPP_D6 0x3A2C9006 // Native Function 3
#define GPIO_VER6_SOC_M_MUXING_ISH_SPI0_CLK_GPP_F11 0x4A26900B // Native Function 4
#define GPIO_VER6_SOC_M_MUXING_ISH_SPI0_MISO_GPP_D7 0x3A2C8007 // Native Function 3
#define GPIO_VER6_SOC_M_MUXING_ISH_SPI0_MISO_GPP_F12 0x4A26800C // Native Function 4
#define GPIO_VER6_SOC_M_MUXING_ISH_SPI0_MOSI_GPP_D8 0x3A2C7008 // Native Function 3
#define GPIO_VER6_SOC_M_MUXING_ISH_SPI0_MOSI_GPP_F13 0x4A26700D // Native Function 4
#define GPIO_VER6_SOC_M_MUXING_ISH_UART1_RXD_GPP_H14 0x1A25220E // Native Function 1
#define GPIO_VER6_SOC_M_MUXING_ISH_UART1_RXD_GPP_H6 0x3A252206 // Native Function 3
#define GPIO_VER6_SOC_M_MUXING_ISH_UART1_TXD_GPP_H15 0x1A25320F // Native Function 1
#define GPIO_VER6_SOC_M_MUXING_ISH_UART1_TXD_GPP_H7 0x3A253207 // Native Function 3
#define GPIO_VER6_SOC_M_MUXING_ISH_I2C2_SDA_GPP_B18 0x1A2BE412 // Native Function 1
#define GPIO_VER6_SOC_M_MUXING_ISH_I2C2_SDA_GPP_D1 0x3A2CE401 // Native Function 3
#define GPIO_VER6_SOC_M_MUXING_ISH_I2C2_SCL_GPP_B19 0x1A2BD413 // Native Function 1
#define GPIO_VER6_SOC_M_MUXING_ISH_I2C2_SCL_GPP_D2 0x3A2CD402 // Native Function 3
#define GPIO_VER6_SOC_M_MUXING_ISH_GP5_GPP_B22 0x4A0BAA16 // Native Function 4
#define GPIO_VER6_SOC_M_MUXING_ISH_GP5_GPP_E15 0x8A04AA0F // Native Function 8
#define GPIO_VER6_SOC_M_MUXING_ISH_GP6_GPP_B23 0x4A0BAC17 // Native Function 4
#define GPIO_VER6_SOC_M_MUXING_ISH_GP6_GPP_F10 0x8A06AC0A // Native Function 8
#define GPIO_VER6_SOC_M_MUXING_ISH_GP8_GPP_B20 0x4A0BB014 // Native Function 4
#define GPIO_VER6_SOC_M_MUXING_ISH_GP8_GPP_F22 0x8A06B016 // Native Function 8
#define GPIO_VER6_SOC_M_MUXING_ISH_GP9_GPP_B21 0x4A0BB215 // Native Function 4
#define GPIO_VER6_SOC_M_MUXING_ISH_GP9_GPP_F23 0x8A06B217 // Native Function 8
#define GPIO_VER6_SOC_M_MUXING_ISH_GP10_GPP_E16 0x8A04B410 // Native Function 8
#define GPIO_VER6_SOC_M_MUXING_ISH_GP10_GPP_H10 0x8A05B40A // Native Function 8
#define GPIO_VER6_SOC_M_MUXING_ISH_GP11_GPP_F9 0x8A06B609 // Native Function 8
#define GPIO_VER6_SOC_M_MUXING_ISH_GP11_GPP_H11 0x8A05B60B // Native Function 8
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_SPI0_CS_GPP_E10 0x5A04700A // Native Function 5
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_SPI0_CS_GPP_F18 0x8A067012 // Native Function 8
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_SPI0_CLK_GPP_E11 0x5A04600B // Native Function 5
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_SPI0_CLK_GPP_F16 0x8A066010 // Native Function 8
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_SPI0_MISO_GPP_E12 0x5A04500C // Native Function 5
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_SPI0_MISO_GPP_F15 0x8A06500F // Native Function 8
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_SPI0_MOSI_GPP_E13 0x5A04400D // Native Function 5
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_SPI0_MOSI_GPP_F14 0x8A06400E // Native Function 8
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C2_SDA_GPP_H4 0x1A45C804 // Native Function 1
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C2_SDA_GPP_B2 0x8A4BC802 // Native Function 8
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C2_SCL_GPP_H5 0x1A45A805 // Native Function 1
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C2_SCL_GPP_B3 0x8A4BA803 // Native Function 8
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C3_SDA_GPP_H6 0x1A45CA06 // Native Function 1
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C3_SDA_GPP_D1 0x1A4CCA01 // Native Function 1
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C3_SCL_GPP_H7 0x1A45AA07 // Native Function 1
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C3_SCL_GPP_D2 0x1A4CAA02 // Native Function 1
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C4_SDA_GPP_E12 0x8A44CC0C // Native Function 8
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C4_SDA_GPP_B18 0x2A4BCC12 // Native Function 2
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C4_SCL_GPP_E13 0x8A44AC0D // Native Function 8
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C4_SCL_GPP_B19 0x2A4BAC13 // Native Function 2
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C5_SDA_GPP_F13 0x8A46CE0D // Native Function 8
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C5_SDA_GPP_B20 0x2A4BCE14 // Native Function 2
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C5_SCL_GPP_F12 0x8A46AE0C // Native Function 8
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C5_SCL_GPP_B21 0x2A4BAE15 // Native Function 2
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I3C1_SDA_GPP_H21 0x2A652015 // Native Function 2
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I3C1_SDA_GPP_H10 0x2A65200A // Native Function 2
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I3C1_SCL_GPP_H22 0x2A651C16 // Native Function 2
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I3C1_SCL_GPP_H11 0x2A651C0B // Native Function 2
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I3C1_SCL_FB 0x2A65C018 // Native Function 2
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I3C1_SCL_FB_A 0x3A65C018 // Native Function 3
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_UART1_RXD_GPP_H6 0x2A050406 // Native Function 2
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_UART1_RXD_GPP_H14 0x2A05040E // Native Function 2
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_UART1_TXD_GPP_H7 0x2A051407 // Native Function 2
#define GPIO_VER6_SOC_M_MUXING_SERIALIO_UART1_TXD_GPP_H15 0x2A05140F // Native Function 2
#endif // _GPIO_PINS_VER4_S_H_
Silicon/ArrowlakePkg/Include/GpioV2PinsMtlPchS.h
+20 -2416
View File
File diff suppressed because it is too large Load Diff
Silicon/ArrowlakePkg/Include/GpioV2PinsMtlSoc.h
+11 -210
View File
@@ -19,7 +19,6 @@
// GPIO community indexes in controller
//
// Com 0
#define MTL_M_GPIO_PAD_COM_IDX_CPU 0
#define MTL_M_GPIO_PAD_COM_IDX_GPP_V 0
#define MTL_M_GPIO_PAD_COM_IDX_GPP_C 0
// Com 1
@@ -28,44 +27,36 @@
// Com 3
#define MTL_M_GPIO_PAD_COM_IDX_GPP_H 2
#define MTL_M_GPIO_PAD_COM_IDX_GPP_F 2
#define MTL_M_GPIO_PAD_COM_IDX_SPI_SYS 2
#define MTL_M_GPIO_PAD_COM_IDX_USB_THC 2
// Com 4
#define MTL_M_GPIO_PAD_COM_IDX_GPP_S 3
#define MTL_M_GPIO_PAD_COM_IDX_JTAG 3
// Com 5
#define MTL_M_GPIO_PAD_COM_IDX_GPP_B 4
#define MTL_M_GPIO_PAD_COM_IDX_GPP_D 4
#define MTL_M_GPIO_PAD_COM_IDX_VGPIO 4
//
// GPIO group indexes in communities
//
// Com 0
#define MTL_M_GPIO_PAD_GRP_IDX_CPU 0
#define MTL_M_GPIO_PAD_GRP_IDX_GPP_V 1
#define MTL_M_GPIO_PAD_GRP_IDX_GPP_C 2
#define MTL_M_GPIO_PAD_GRP_IDX_GPP_V 0
#define MTL_M_GPIO_PAD_GRP_IDX_GPP_C 1
// Com 1
#define MTL_M_GPIO_PAD_GRP_IDX_GPP_A 0
#define MTL_M_GPIO_PAD_GRP_IDX_GPP_E 1
// Com 3
#define MTL_M_GPIO_PAD_GRP_IDX_GPP_H 0
#define MTL_M_GPIO_PAD_GRP_IDX_GPP_F 1
#define MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS 2
#define MTL_M_GPIO_PAD_GRP_IDX_USB_THC 3
// Com 4
#define MTL_M_GPIO_PAD_GRP_IDX_GPP_S 0
#define MTL_M_GPIO_PAD_GRP_IDX_JTAG 1
// Com 5
#define MTL_M_GPIO_PAD_GRP_IDX_GPP_B 0
#define MTL_M_GPIO_PAD_GRP_IDX_GPP_D 1
#define MTL_M_GPIO_PAD_GRP_IDX_VGPIO 2
//
// GPIO Group defines
//
// Com 0
#define GPIOV2_MTL_SOC_M_GROUP_CPU GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_CPU, MTL_M_GPIO_PAD_GRP_IDX_CPU, 0xFF)
#define GPIOV2_MTL_SOC_M_GROUP_V GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_V, MTL_M_GPIO_PAD_GRP_IDX_GPP_V, 0xFF)
#define GPIOV2_MTL_SOC_M_GROUP_C GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_C, MTL_M_GPIO_PAD_GRP_IDX_GPP_C, 0xFF)
// Com 1
@@ -74,26 +65,16 @@
// Com 3
#define GPIOV2_MTL_SOC_M_GROUP_H GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_H, MTL_M_GPIO_PAD_GRP_IDX_GPP_H, 0xFF)
#define GPIOV2_MTL_SOC_M_GROUP_F GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_F, MTL_M_GPIO_PAD_GRP_IDX_GPP_F, 0xFF)
#define GPIOV2_MTL_SOC_M_GROUP_SPI GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 0xFF)
#define GPIOV2_MTL_SOC_M_GROUP_USB GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 0xFF)
// Com 4
#define GPIOV2_MTL_SOC_M_GROUP_S GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_S, MTL_M_GPIO_PAD_GRP_IDX_GPP_S, 0xFF)
#define GPIOV2_MTL_SOC_M_GROUP_MBPB GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 0xFF)
// Com 5
#define GPIOV2_MTL_SOC_M_GROUP_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_B, MTL_M_GPIO_PAD_GRP_IDX_GPP_B, 0xFF)
#define GPIOV2_MTL_SOC_M_GROUP_D GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_D, MTL_M_GPIO_PAD_GRP_IDX_GPP_D, 0xFF)
#define GPIOV2_MTL_SOC_M_GROUP_VGPIO GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0xFF)
//
// GPIO PAD defines
//
// Com 0
#define GPIOV2_MTL_SOC_M_CPU_PECI GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_CPU, MTL_M_GPIO_PAD_GRP_IDX_CPU, 0)
#define GPIOV2_MTL_SOC_M_CPU_RESET_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_CPU, MTL_M_GPIO_PAD_GRP_IDX_CPU, 1)
#define GPIOV2_MTL_SOC_M_CPU_SOUT GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_CPU, MTL_M_GPIO_PAD_GRP_IDX_CPU, 2)
#define GPIOV2_MTL_SOC_M_CPU_SCK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_CPU, MTL_M_GPIO_PAD_GRP_IDX_CPU, 3)
#define GPIOV2_MTL_SOC_M_CPU_ALERT_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_CPU, MTL_M_GPIO_PAD_GRP_IDX_CPU, 4)
#define GPIOV2_MTL_SOC_M_GPP_V0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_V, MTL_M_GPIO_PAD_GRP_IDX_GPP_V, 0)
#define GPIOV2_MTL_SOC_M_GPP_V1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_V, MTL_M_GPIO_PAD_GRP_IDX_GPP_V, 1)
#define GPIOV2_MTL_SOC_M_GPP_V2 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_V, MTL_M_GPIO_PAD_GRP_IDX_GPP_V, 2)
@@ -169,7 +150,6 @@
#define GPIOV2_MTL_SOC_M_GPP_A21 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_A, MTL_M_GPIO_PAD_GRP_IDX_GPP_A, 21)
#define GPIOV2_MTL_SOC_M_GPP_A22 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_A, MTL_M_GPIO_PAD_GRP_IDX_GPP_A, 22)
#define GPIOV2_MTL_SOC_M_GPP_A23 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_A, MTL_M_GPIO_PAD_GRP_IDX_GPP_A, 23)
#define GPIOV2_MTL_SOC_M_ESPI_CLK_LOOPBK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_A, MTL_M_GPIO_PAD_GRP_IDX_GPP_A, 24)
#define GPIOV2_MTL_SOC_M_GPP_E0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_E, MTL_M_GPIO_PAD_GRP_IDX_GPP_E, 0)
#define GPIOV2_MTL_SOC_M_GPP_E1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_E, MTL_M_GPIO_PAD_GRP_IDX_GPP_E, 1)
@@ -195,7 +175,6 @@
#define GPIOV2_MTL_SOC_M_GPP_E21 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_E, MTL_M_GPIO_PAD_GRP_IDX_GPP_E, 21)
#define GPIOV2_MTL_SOC_M_GPP_E22 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_E, MTL_M_GPIO_PAD_GRP_IDX_GPP_E, 22)
#define GPIOV2_MTL_SOC_M_GPP_E23 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_E, MTL_M_GPIO_PAD_GRP_IDX_GPP_E, 23)
#define GPIOV2_MTL_SOC_M_THC0_GPSI0_CLK_LOOPBK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_E, MTL_M_GPIO_PAD_GRP_IDX_GPP_E, 24)
// Com 3
#define GPIOV2_MTL_SOC_M_GPP_H0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_H, MTL_M_GPIO_PAD_GRP_IDX_GPP_H, 0)
@@ -221,9 +200,6 @@
#define GPIOV2_MTL_SOC_M_GPP_H20 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_H, MTL_M_GPIO_PAD_GRP_IDX_GPP_H, 20)
#define GPIOV2_MTL_SOC_M_GPP_H21 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_H, MTL_M_GPIO_PAD_GRP_IDX_GPP_H, 21)
#define GPIOV2_MTL_SOC_M_GPP_H22 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_H, MTL_M_GPIO_PAD_GRP_IDX_GPP_H, 22)
#define GPIOV2_MTL_SOC_M_GPP_H23 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_H, MTL_M_GPIO_PAD_GRP_IDX_GPP_H, 23)
#define GPIOV2_MTL_SOC_M_LPI3C1_CLK_LOOPBK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_H, MTL_M_GPIO_PAD_GRP_IDX_GPP_H, 24)
#define GPIOV2_MTL_SOC_M_LPI3C0_CLK_LOOPBK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_H, MTL_M_GPIO_PAD_GRP_IDX_GPP_H, 25)
#define GPIOV2_MTL_SOC_M_GPP_F0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_F, MTL_M_GPIO_PAD_GRP_IDX_GPP_F, 0)
#define GPIOV2_MTL_SOC_M_GPP_F1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_F, MTL_M_GPIO_PAD_GRP_IDX_GPP_F, 1)
@@ -249,39 +225,6 @@
#define GPIOV2_MTL_SOC_M_GPP_F21 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_F, MTL_M_GPIO_PAD_GRP_IDX_GPP_F, 21)
#define GPIOV2_MTL_SOC_M_GPP_F22 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_F, MTL_M_GPIO_PAD_GRP_IDX_GPP_F, 22)
#define GPIOV2_MTL_SOC_M_GPP_F23 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_F, MTL_M_GPIO_PAD_GRP_IDX_GPP_F, 23)
#define GPIOV2_MTL_SOC_M_THC1_GSPI1_CLK_LOOPBK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_F, MTL_M_GPIO_PAD_GRP_IDX_GPP_F, 24)
#define GPIOV2_MTL_SOC_M_GSPI0A_CLK_LOOPBK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_F, MTL_M_GPIO_PAD_GRP_IDX_GPP_F, 25)
#define GPIOV2_MTL_SOC_M_SPI0_IO2 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 0)
#define GPIOV2_MTL_SOC_M_SPI0_IO3 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 1)
#define GPIOV2_MTL_SOC_M_SPI0_MOSI_IO_0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 2)
#define GPIOV2_MTL_SOC_M_SPI0_MISO_IO_0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 3)
#define GPIOV2_MTL_SOC_M_SPI0_TPM_CS_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 4)
#define GPIOV2_MTL_SOC_M_SPI0_FLASH_0_CS_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 5)
#define GPIOV2_MTL_SOC_M_SPI0_FLASH_1_CS_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 6)
#define GPIOV2_MTL_SOC_M_SPI0_CLK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 7)
#define GPIOV2_MTL_SOC_M_BKLTEN GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 8)
#define GPIOV2_MTL_SOC_M_BKLTCTL GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 9)
#define GPIOV2_MTL_SOC_M_VDDEN GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 10)
#define GPIOV2_MTL_SOC_M_SYS_PWROK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 11)
#define GPIOV2_MTL_SOC_M_SYS_RESET_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 12)
#define GPIOV2_MTL_SOC_M_MLK_RST_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 13)
#define GPIOV2_MTL_SOC_M_SPI0_CLK_LOOPBK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 14)
#define GPIOV2_MTL_SOC_M_USB_0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 0)
#define GPIOV2_MTL_SOC_M_USB_1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 1)
#define GPIOV2_MTL_SOC_M_USB_2 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 2)
#define GPIOV2_MTL_SOC_M_USB_3 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 3)
#define GPIOV2_MTL_SOC_M_USB_4 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 4)
#define GPIOV2_MTL_SOC_M_USB_5 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 5)
#define GPIOV2_MTL_SOC_M_USB_6 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 6)
#define GPIOV2_MTL_SOC_M_USB_7 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 7)
#define GPIOV2_MTL_SOC_M_TS_0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 8)
#define GPIOV2_MTL_SOC_M_TS_1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 9)
#define GPIOV2_MTL_SOC_M_THC_0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 10)
#define GPIOV2_MTL_SOC_M_THC_1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 11)
#define GPIOV2_MTL_SOC_M_THC_2 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 12)
#define GPIOV2_MTL_SOC_M_THC_3 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 13)
// Com 4
#define GPIOV2_MTL_SOC_M_GPP_S0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_S, MTL_M_GPIO_PAD_GRP_IDX_GPP_S, 0)
@@ -293,19 +236,6 @@
#define GPIOV2_MTL_SOC_M_GPP_S6 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_S, MTL_M_GPIO_PAD_GRP_IDX_GPP_S, 6)
#define GPIOV2_MTL_SOC_M_GPP_S7 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_S, MTL_M_GPIO_PAD_GRP_IDX_GPP_S, 7)
#define GPIOV2_MTL_SOC_M_MBPB0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 0)
#define GPIOV2_MTL_SOC_M_MBPB1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 1)
#define GPIOV2_MTL_SOC_M_MBPB2 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 2)
#define GPIOV2_MTL_SOC_M_MBPB3 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 3)
#define GPIOV2_MTL_SOC_M_JTAG_TDO GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 4)
#define GPIOV2_MTL_SOC_M_PRDY_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 5)
#define GPIOV2_MTL_SOC_M_PREQ_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 6)
#define GPIOV2_MTL_SOC_M_JTAG_TDI GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 7)
#define GPIOV2_MTL_SOC_M_JTAG_TMS GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 8)
#define GPIOV2_MTL_SOC_M_JTAG_TCK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 9)
#define GPIOV2_MTL_SOC_M_DBG_PMODE GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 10)
#define GPIOV2_MTL_SOC_M_JTAG_TRST_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 11)
// Com 5
#define GPIOV2_MTL_SOC_M_GPP_B0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_B, MTL_M_GPIO_PAD_GRP_IDX_GPP_B, 0)
#define GPIOV2_MTL_SOC_M_GPP_B1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_B, MTL_M_GPIO_PAD_GRP_IDX_GPP_B, 1)
@@ -331,7 +261,6 @@
#define GPIOV2_MTL_SOC_M_GPP_B21 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_B, MTL_M_GPIO_PAD_GRP_IDX_GPP_B, 21)
#define GPIOV2_MTL_SOC_M_GPP_B22 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_B, MTL_M_GPIO_PAD_GRP_IDX_GPP_B, 22)
#define GPIOV2_MTL_SOC_M_GPP_B23 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_B, MTL_M_GPIO_PAD_GRP_IDX_GPP_B, 23)
#define GPIOV2_MTL_SOC_M_ISHI3C0_CLK_LOOPBK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_B, MTL_M_GPIO_PAD_GRP_IDX_GPP_B, 24)
#define GPIOV2_MTL_SOC_M_GPP_D0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_D, MTL_M_GPIO_PAD_GRP_IDX_GPP_D, 0)
#define GPIOV2_MTL_SOC_M_GPP_D1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_D, MTL_M_GPIO_PAD_GRP_IDX_GPP_D, 1)
@@ -357,86 +286,28 @@
#define GPIOV2_MTL_SOC_M_GPP_D21 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_D, MTL_M_GPIO_PAD_GRP_IDX_GPP_D, 21)
#define GPIOV2_MTL_SOC_M_GPP_D22 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_D, MTL_M_GPIO_PAD_GRP_IDX_GPP_D, 22)
#define GPIOV2_MTL_SOC_M_GPP_D23 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_D, MTL_M_GPIO_PAD_GRP_IDX_GPP_D, 23)
#define GPIOV2_MTL_SOC_M_BOOTHALT_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_D, MTL_M_GPIO_PAD_GRP_IDX_GPP_D, 24)
#define GPIOV2_MTL_SOC_M_VGPIO0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x00)
#define GPIOV2_MTL_SOC_M_VGPIO4 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x01)
#define GPIOV2_MTL_SOC_M_VGPIO5 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x02)
#define GPIOV2_MTL_SOC_M_VGPIO6 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x03)
#define GPIOV2_MTL_SOC_M_VGPIO7 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x04)
#define GPIOV2_MTL_SOC_M_VGPIO8 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x05)
#define GPIOV2_MTL_SOC_M_VGPIO9 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x06)
#define GPIOV2_MTL_SOC_M_VGPIO10 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x07)
#define GPIOV2_MTL_SOC_M_VGPIO11 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x08)
#define GPIOV2_MTL_SOC_M_VGPIO12 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x09)
#define GPIOV2_MTL_SOC_M_VGPIO13 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x0A)
#define GPIOV2_MTL_SOC_M_VGPIO18 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x0B)
#define GPIOV2_MTL_SOC_M_VGPIO19 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x0C)
#define GPIOV2_MTL_SOC_M_VGPIO20 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x0D)
#define GPIOV2_MTL_SOC_M_VGPIO21 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x0E)
#define GPIOV2_MTL_SOC_M_VGPIO22 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x0F)
#define GPIOV2_MTL_SOC_M_VGPIO23 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x10)
#define GPIOV2_MTL_SOC_M_VGPIO24 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x11)
#define GPIOV2_MTL_SOC_M_VGPIO25 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x12)
#define GPIOV2_MTL_SOC_M_VGPIO30 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x13)
#define GPIOV2_MTL_SOC_M_VGPIO31 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x14)
#define GPIOV2_MTL_SOC_M_VGPIO32 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x15)
#define GPIOV2_MTL_SOC_M_VGPIO33 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x16)
#define GPIOV2_MTL_SOC_M_VGPIO34 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x17)
#define GPIOV2_MTL_SOC_M_VGPIO35 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x18)
#define GPIOV2_MTL_SOC_M_VGPIO36 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x19)
#define GPIOV2_MTL_SOC_M_VGPIO37 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x1A)
#define GPIOV2_MTL_SOC_M_VGPIO40 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x1B)
#define GPIOV2_MTL_SOC_M_VGPIO41 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x1C)
#define GPIOV2_MTL_SOC_M_VGPIO42 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x1D)
#define GPIOV2_MTL_SOC_M_VGPIO43 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x1E)
#define GPIOV2_MTL_SOC_M_VGPIO44 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x1F)
#define GPIOV2_MTL_SOC_M_VGPIO45 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x20)
#define GPIOV2_MTL_SOC_M_VGPIO46 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x21)
#define GPIOV2_MTL_SOC_M_VGPIO47 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x22)
// Com 0
#define MTL_S_GPIO_PAD_COM_IDX_GPP_A 0
#define MTL_S_GPIO_PAD_COM_IDX_VGPIO_0 0
#define MTL_S_GPIO_PAD_COM_IDX_GPP_C 0
// Com 1
#define MTL_S_GPIO_PAD_COM_IDX_GPP_B 1
#define MTL_S_GPIO_PAD_COM_IDX_VGPIO_3 1
#define MTL_S_GPIO_PAD_COM_IDX_GPP_D 1
// Com 2
// Com 3
#define MTL_S_GPIO_PAD_COM_IDX_JTAG 2
#define MTL_S_GPIO_PAD_COM_IDX_VGPIO_4 2
#define MTL_S_GPIO_PAD_COM_IDX_GPP_A 0
#define MTL_S_GPIO_PAD_GRP_IDX_GPP_A 0
// Com 0
#define MTL_S_GPIO_PAD_GRP_IDX_GPP_A 0
#define MTL_S_GPIO_PAD_GRP_IDX_VGPIO_0 1
#define MTL_S_GPIO_PAD_GRP_IDX_GPP_C 2
// Com 1
#define MTL_S_GPIO_PAD_GRP_IDX_GPP_B 0
#define MTL_S_GPIO_PAD_GRP_IDX_VGPIO_3 1
#define MTL_S_GPIO_PAD_GRP_IDX_GPP_D 2
// Com 2
// Com 3
#define MTL_S_GPIO_PAD_GRP_IDX_JTAG 0
#define MTL_S_GPIO_PAD_GRP_IDX_VGPIO_4 1
#define MTL_S_GPIO_PAD_COM_IDX_GPP_B 1
#define MTL_S_GPIO_PAD_GRP_IDX_GPP_B 0
#define MTL_S_GPIO_PAD_COM_IDX_GPP_D 1
#define MTL_S_GPIO_PAD_GRP_IDX_GPP_D 1
//
// GPIO Group defines
//
// Com 0
#define GPIOV2_MTL_SOC_S_GROUP_A GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_A, MTL_S_GPIO_PAD_GRP_IDX_GPP_A, 0xFF)
#define GPIOV2_MTL_SOC_S_GROUP_VGPIO0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_0, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_0, 0xFF)
#define GPIOV2_MTL_SOC_S_GROUP_C GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 0xFF)
// Com 1
#define GPIOV2_MTL_SOC_S_GROUP_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_B, MTL_S_GPIO_PAD_GRP_IDX_GPP_B, 0xFF)
#define GPIOV2_MTL_SOC_S_GROUP_VGPIO3 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_3, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_3, 0xFF)
#define GPIOV2_MTL_SOC_S_GROUP_D GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_D, MTL_S_GPIO_PAD_GRP_IDX_GPP_D, 0xFF)
// Com 3
#define GPIOV2_MTL_SOC_S_GROUP_JTAG GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 0xFF)
#define GPIOV2_MTL_SOC_S_GROUP_VGPIO4 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_4, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_4, 0xFF)
//
// MTL SoC-S GPIO pins
@@ -466,46 +337,6 @@
#define GPIOV2_MTL_SOC_S_GPP_A21 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_A, MTL_S_GPIO_PAD_GRP_IDX_GPP_A, 21)
#define GPIOV2_MTL_SOC_S_GPP_A22 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_A, MTL_S_GPIO_PAD_GRP_IDX_GPP_A, 22)
#define GPIOV2_MTL_SOC_S_GPP_A23 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_A, MTL_S_GPIO_PAD_GRP_IDX_GPP_A, 23)
#define GPIOV2_MTL_SOC_S_RTCCLKIN GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_A, MTL_S_GPIO_PAD_GRP_IDX_GPP_A, 24)
#define GPIOV2_MTL_SOC_S_RESET_SYNC_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_A, MTL_S_GPIO_PAD_GRP_IDX_GPP_A, 25)
#define GPIOV2_MTL_SOC_S_PCH_PWROK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_A, MTL_S_GPIO_PAD_GRP_IDX_GPP_A, 26)
#define GPIOV2_MTL_SOC_S_ESPI_CLK_LOOPBACK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_A, MTL_S_GPIO_PAD_GRP_IDX_GPP_A, 27)
#define GPIOV2_MTL_SOC_S_VGPIO_LPC_0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_0, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_0, 0)
#define GPIOV2_MTL_SOC_S_VGPIO_LPC_1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_0, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_0, 1)
#define GPIOV2_MTL_SOC_S_VGPIO_LPC_2 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_0, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_0, 2)
#define GPIOV2_MTL_SOC_S_VGPIO_LPC_3 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_0, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_0, 3)
#define GPIOV2_MTL_SOC_S_VGPIO_LPC_4 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_0, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_0, 4)
#define GPIOV2_MTL_SOC_S_VGPIO_EC_SCI GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_0, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_0, 5)
#define GPIOV2_MTL_SOC_S_VGPIO_EC_SCI1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_0, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_0, 6)
#define GPIOV2_MTL_SOC_S_GPP_C0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 0)
#define GPIOV2_MTL_SOC_S_GPP_C1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 1)
#define GPIOV2_MTL_SOC_S_GPP_C2 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 2)
#define GPIOV2_MTL_SOC_S_GPP_C3 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 3)
#define GPIOV2_MTL_SOC_S_GPP_C4 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 4)
#define GPIOV2_MTL_SOC_S_GPP_C5 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 5)
#define GPIOV2_MTL_SOC_S_GPP_C6 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 6)
#define GPIOV2_MTL_SOC_S_GPP_C7 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 7)
#define GPIOV2_MTL_SOC_S_GPP_C8 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 8)
#define GPIOV2_MTL_SOC_S_GPP_C9 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 9)
#define GPIOV2_MTL_SOC_S_GPP_C10 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 10)
#define GPIOV2_MTL_SOC_S_GPP_C11 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 11)
#define GPIOV2_MTL_SOC_S_GPP_C12 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 12)
#define GPIOV2_MTL_SOC_S_GPP_C13 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 13)
#define GPIOV2_MTL_SOC_S_GPP_C14 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 14)
#define GPIOV2_MTL_SOC_S_GPP_C15 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 15)
#define GPIOV2_MTL_SOC_S_GPP_C16 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 16)
#define GPIOV2_MTL_SOC_S_GPP_C17 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 17)
#define GPIOV2_MTL_SOC_S_GPP_C18 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 18)
#define GPIOV2_MTL_SOC_S_GPP_C19 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 19)
#define GPIOV2_MTL_SOC_S_GPP_C20 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 20)
#define GPIOV2_MTL_SOC_S_GPP_C21 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 21)
#define GPIOV2_MTL_SOC_S_GPP_C22 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 22)
#define GPIOV2_MTL_SOC_S_GPP_C23 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 23)
#define GPIOV2_MTL_SOC_S_GPP_C24 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 24)
#define GPIOV2_MTL_SOC_S_GPP_C25 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 25)
#define GPIOV2_MTL_SOC_S_GPP_C26 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 26)
// COM1
#define GPIOV2_MTL_SOC_S_GPP_B0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_B, MTL_S_GPIO_PAD_GRP_IDX_GPP_B, 0)
@@ -529,14 +360,6 @@
#define GPIOV2_MTL_SOC_S_GPP_B18 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_B, MTL_S_GPIO_PAD_GRP_IDX_GPP_B, 18)
#define GPIOV2_MTL_SOC_S_GPP_B19 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_B, MTL_S_GPIO_PAD_GRP_IDX_GPP_B, 19)
#define GPIOV2_MTL_SOC_S_VGPIO_USB_0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_3, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_3, 0)
#define GPIOV2_MTL_SOC_S_VGPIO_USB_1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_3, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_3, 1)
#define GPIOV2_MTL_SOC_S_VGPIO_USB_2 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_3, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_3, 2)
#define GPIOV2_MTL_SOC_S_VGPIO_USB_3 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_3, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_3, 3)
#define GPIOV2_MTL_SOC_S_VGPIO_PCIE_80 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_3, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_3, 4)
#define GPIOV2_MTL_SOC_S_VGPIO_TS_0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_3, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_3, 5)
#define GPIOV2_MTL_SOC_S_VGPIO_TS_1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_3, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_3, 6)
#define GPIOV2_MTL_SOC_S_GPP_D0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_D, MTL_S_GPIO_PAD_GRP_IDX_GPP_D, 0)
#define GPIOV2_MTL_SOC_S_GPP_D1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_D, MTL_S_GPIO_PAD_GRP_IDX_GPP_D, 1)
#define GPIOV2_MTL_SOC_S_GPP_D2 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_D, MTL_S_GPIO_PAD_GRP_IDX_GPP_D, 2)
@@ -562,28 +385,6 @@
#define GPIOV2_MTL_SOC_S_GPP_D22 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_D, MTL_S_GPIO_PAD_GRP_IDX_GPP_D, 22)
#define GPIOV2_MTL_SOC_S_GPP_D23 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_D, MTL_S_GPIO_PAD_GRP_IDX_GPP_D, 23)
// COM2
// COM3
#define GPIOV2_MTL_SOC_S_PECI GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 0)
#define GPIOV2_MTL_SOC_S_VIDSOUT GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 1)
#define GPIOV2_MTL_SOC_S_VIDSCK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 2)
#define GPIOV2_MTL_SOC_S_VIDALERT_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 3)
#define GPIOV2_MTL_SOC_S_JTAG_MBPB_0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 4)
#define GPIOV2_MTL_SOC_S_JTAG_MBPB_1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 5)
#define GPIOV2_MTL_SOC_S_JTAG_MBPB_2 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 6)
#define GPIOV2_MTL_SOC_S_JTAG_MBPB_3 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 7)
#define GPIOV2_MTL_SOC_S_JTAG_TDO GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 8)
#define GPIOV2_MTL_SOC_S_PRDY_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 9)
#define GPIOV2_MTL_SOC_S_PREQ_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 10)
#define GPIOV2_MTL_SOC_S_JTAG_TDI GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 11)
#define GPIOV2_MTL_SOC_S_JTAG_TMS GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 12)
#define GPIOV2_MTL_SOC_S_JTAG_TCK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 13)
#define GPIOV2_MTL_SOC_S_JTAG_PMODE GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 14)
#define GPIOV2_MTL_SOC_S_JTAG_TRST_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 15)
#define GPIOV2_MTL_SOC_S_VGPIO_ISCLK0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_4, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_4, 0)
#define GPIOV2_MTL_SOC_S_VGPIO_ISCLK1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_4, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_4, 1)
//*********************************************************************
// MTL-SOC-S Pins End *
Silicon/ArrowlakePkg/Include/Library/MtlPchGpioTopologyLib.h
-86
View File
@@ -1,86 +0,0 @@
/** @file
Header file for common part for Gpio V2 Controller PEI and DXE modules
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _GPIOV2_TOPOLOGY_MTL_PCH_H_
#define _GPIOV2_TOPOLOGY_MTL_PCH_H_
//#include <Library/GpioV2AccessLib.h>
#include <GpioV2ControllerInterface.h>
#include <Include/GpioV2Pad.h>
/**
This procedure retrieves number of communities for PCH with index 'PchIndex'
@param[in] PchIndex MTL SOC/PCH index
@retval Number of communities on requested PCH
**/
UINT32
MtlPchGpioGetCommunitiesNum (
IN UINT32 PchIndex
);
/**
This procedure retrieves pointer to array of communities for PCH with index 'PchIndex'
@param[in] PchIndex MTL SOC/PCH index
@retval pointer to array of communities on requested PCH
**/
GPIOV2_COMMUNITY*
MtlPchGpioGetCommunities (
IN UINT32 PchIndex
);
GPIOV2_GROUP
MtlPchGpioGetGroups (
IN UINT32 CommunityIndex,
IN UINT32 GroupIndex
);
/**
This procedure retrieves number of native signals for LNL SOC
@retval Number of native signals on LNL SOC
**/
UINT32
MtlPchGpioGetNativeSignalsNum (
VOID
);
/**
This procedure retrieves pointer to array of native signals for LNL SOC
@retval pointer to array of native signals on LNL SOC
**/
GPIOV2_NATIVE_SIGNAL_DATA *
MtlPchGpioGetNativeSignals (
VOID
);
/**
This procedure retrieves register offset for given Gpio Pad
@param[in] GpioPad Gpio Pad. Please refer to GpioPinsYYY.h - where YYY name of the platform (eg. MTL, EBG, ...)
@param[in] Register Register for which user want to retrieve offset. Please refer to GpioV2Pad.h
@param[out] RegisterOffset Pointer to a buffer for register offset
@retval EFI_SUCCESS The function completed successfully
@retval EFI_INVALID_PARAMETER Invalid group or pad number
**/
EFI_STATUS
MtlPchGpioGetRegOffset (
IN GPIOV2_PAD GpioPad,
IN GPIOV2_REGISTER Register,
OUT UINT32 *RegisterOffset
);
EFI_STATUS
MtlPchInstallCommunityAccess (
OUT P2SB_SIDEBAND_REGISTER_ACCESS *CommunityAccess
);
#endif //_GPIOV2_TOPOLOGY_MTL_PCH_H_
Silicon/ArrowlakePkg/Include/Library/MtlPchPcieRpLib.h
+1 -49
View File
@@ -9,32 +9,6 @@
#ifndef _MTL_PCH_PCIE_RP_LIB_
#define _MTL_PCH_PCIE_RP_LIB_
#include <Library/P2SbSidebandAccessLib.h>
/**
Translate RpIndex to controller index.
@param[in] RpIndex Root port index
@return ControllerIndex
@retval 0xFF Failed to lookup controller index.
**/
UINT32
MtlPchRpIndexToControllerIndex (
IN UINT32 RpIndex
);
/**
Get the FID number of the PCIe root port.
@param[in] RpIndex Index of the root port
@return FID number to use when sending SBI msg
**/
UINT16
MtlPchPcieRpGetSbiFid (
IN UINT32 RpIndex
);
/**
Get MTL SoC Pcie Root Port Device and Function Number by Root Port physical Number
@@ -47,34 +21,12 @@ MtlPchPcieRpGetSbiFid (
@retval EFI_INVALID_PARAMETER RpNumber is invalid
**/
EFI_STATUS
EFIAPI
MtlPchGetPcieRpDevFun (
IN UINT32 RpNumber,
OUT UINT16 *RpDev,
OUT UINT16 *RpFun
);
/**
This function returns PID according to PCIe controller index
@param[in] ControllerIndex PCIe controller index
@retval P2SB_PID Returns PID for SBI Access
**/
P2SB_PID
MtlPchGetPcieControllerSbiPid (
IN UINT32 ControllerIndex
);
/**
This function returns PID according to Root Port Number
@param[in] RpIndex Root Port Index (0-based)
@retval P2SB_PID Returns PID for SBI Access
**/
P2SB_PID
MtlPchGetRpSbiPid (
IN UINT32 RpIndex
);
#endif
Silicon/ArrowlakePkg/Include/Library/MtlSocGpioTopologyLib.h
-93
View File
@@ -1,93 +0,0 @@
/** @file
Header file for common part for Gpio V2 Controller PEI and DXE modules
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
**/
#ifndef _GPIOV2_CONTROLLER_INIT_MTL_H_
#define _GPIOV2_CONTROLLER_INIT_MTL_H_
#include <Include/GpioV2ControllerInterface.h>
#include <Include/GpioV2Pad.h>
#include <Uefi/UefiBaseType.h>
#include <Include/P2SbController.h>
#include <Include/P2SbSidebandAccessLib.h>
/**
This procedure retrieves number of communities for PCH with index 'PchIndex'
@param[in] PchIndex MTL SOC/PCH index
@retval Number of communities on requested PCH
**/
UINT32
MtlSocGpioGetCommunitiesNum(
IN UINT32 PchIndex
);
/**
This procedure retrieves pointer to array of communities for PCH with index 'PchIndex'
@param[in] PchIndex MTL SOC/PCH index
@retval pointer to array of communities on requested PCH
**/
GPIOV2_COMMUNITY*
MtlSocGpioGetCommunities(
IN UINT32 PchIndex
);
GPIOV2_COMMUNITY*
MtlSocGpioGetCommunity (
IN UINT32 CommunityIndex
);
GPIOV2_GROUP
MtlSocGpioGetGroups (
IN UINT32 CommunityIndex,
IN UINT32 GroupIndex
);
EFI_STATUS
MtlSocGetP2SbController (
IN OUT P2SB_CONTROLLER *P2SbController
);
EFI_STATUS
MtlSocInstallCommunityAccess (
//IN UINT32 CommunityIndex,
OUT P2SB_SIDEBAND_REGISTER_ACCESS *CommunityAccess
);
/* GPIOV2_UNLOCK_GROUP_DATA*
MtlSocGpioUnlockData (
IN UINT32 CommunityIndex
); */
/* P2SB_SIDEBAND_REGISTER_ACCESS
MtlSocGetCommunityAccess (
IN UINT32 CommunityIndex
); */
/**
This procedure retrieves register offset for given Gpio Pad
@param[in] GpioPad Gpio Pad. Please refer to GpioPinsYYY.h - where YYY name of the platform (eg. MTL, EBG, ...)
@param[in] Register Register for which user want to retrieve offset. Please refer to GpioV2Pad.h
@param[out] RegisterOffset Pointer to a buffer for register offset
@retval EFI_SUCCESS The function completed successfully
@retval EFI_INVALID_PARAMETER Invalid group or pad number
**/
EFI_STATUS
MtlSocGpioGetRegOffset (
IN GPIOV2_PAD GpioPad,
IN GPIOV2_REGISTER Register,
OUT UINT32 *RegisterOffset
);
#endif //_GPIOV2_CONTROLLER_INIT_MTL_H_
Silicon/ArrowlakePkg/Include/Library/MtlSocPcieRpLib.h
+1 -76
View File
@@ -9,34 +9,6 @@
#ifndef _MTL_SOC_PCIE_RP_LIB_H_
#define _MTL_SOC_PCIE_RP_LIB_H_
//#include <Library/P2SbSidebandAccessLib.h>
#include <Include/PcrDefine.h>
/**
Translate RpIndex to controller index.
@param[in] RpIndex Root port index
@return ControllerIndex
@retval 0xFF Failed to lookup controller index.
**/
UINT32
MtlSocRpIndexToControllerIndex (
IN UINTN RpIndex
);
/**
Get the FID number of the PCIe root port.
@param[in] RpIndex Index of the root port
@return FID number to use when sending SBI msg
**/
UINT16
MtlSocPcieRpGetSbiFid (
IN UINTN RpIndex
);
/**
Get MTL SoC Pcie Root Port Device and Function Number by Root Port physical Number
@@ -48,58 +20,11 @@ MtlSocPcieRpGetSbiFid (
@retval EFI_INVALID_PARAMETER RpNumber is invalid
**/
EFI_STATUS
EFIAPI
MtlSocGetPcieRpDevFun (
IN UINTN RpNumber,
OUT UINT16 *RpDev,
OUT UINT16 *RpFun
);
/**
This function returns PID according to PCIe controller index
@param[in] ControllerIndex PCIe controller index
@retval P2SB_PID Returns PID for SBI Access
**/
P2SB_PID
MtlSocGetPcieControllerSbiPid (
IN UINT32 ControllerIndex
);
/**
This function returns PID according to Root Port Number
@param[in] RpIndex Root Port Index (0-based)
@retval P2SB_PID Returns PID for SBI Access
**/
P2SB_PID
MtlSocGetRpSbiPid (
IN UINTN RpIndex
);
/**
Checks whether RpIndex is located on IOE die.
@param[in] RpIndex Root port index.
@return TRUE if root port is located on IOE die.
**/
BOOLEAN
MtlSocIsRpOnIoeDie (
IN UINT32 RpIndex
);
/**
Checks if root port is decoded by IOC.
@param[in] RpIndex Root port index.
@return TRUE if root port is IOC decoded.
**/
BOOLEAN
MtlSocIsRpIocDecoded (
IN UINT32 RpIndex
);
#endif
Silicon/ArrowlakePkg/Include/P2SbSidebandAccessLib.h
-359
View File
@@ -1,359 +0,0 @@
/** @file
Header for P2SbSidebandAccessLib
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _P2SB_SIDEBAND_ACCESS_LIB_H_
#define _P2SB_SIDEBAND_ACCESS_LIB_H_
#include "RegisterAccess.h"
#include "P2SbController.h"
#include "PcrDefine.h"
#include <Uefi/UefiBaseType.h>
#define P2SB_REGISTER_ACCESS_INIT {P2SbSidebandRead8, P2SbSidebandWrite8, P2SbSidebandOr8, P2SbSidebandAnd8, P2SbSidebandAndThenOr8, \
P2SbSidebandRead16, P2SbSidebandWrite16, P2SbSidebandOr16, P2SbSidebandAnd16, P2SbSidebandAndThenOr16,\
P2SbSidebandRead32, P2SbSidebandWrite32, P2SbSidebandOr32, P2SbSidebandAnd32, P2SbSidebandAndThenOr32}
typedef enum {
P2SbMemory = 0,
P2SbPciConfig,
P2SbPrivateConfig
} P2SB_REGISTER_SPACE;
typedef enum {
P2SbMmioAccess = 0,
P2SbMsgAccess
} P2SB_SIDEBAND_ACCESS_METHOD;
/**
REGISTER_ACCESS for P2SB device to support access to sideband registers.
Be sure to keep first member of this structure as REGISTER_ACCESS to allow
for correct casting between caller who sees this structure as REGISTER_ACCESS
and calle who will cast it to P2SB_SIDEBAND_REGISTER_ACCESS.
**/
typedef struct {
REGISTER_ACCESS Access;
P2SB_SIDEBAND_ACCESS_METHOD AccessMethod;
P2SB_PID P2SbPid;
UINT16 Fid;
P2SB_REGISTER_SPACE RegisterSpace;
BOOLEAN PostedWrites;
P2SB_CONTROLLER *P2SbCtrl;
UINT32 Offset;
} P2SB_SIDEBAND_REGISTER_ACCESS;
/**
Reads an 8-bit register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@return The 8-bit register value specified by Offset
**/
UINT8
P2SbSidebandRead8 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset
);
/**
Writes an 8-bit register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] Value Value to write to register
@return The 8-bit register value written to register
**/
UINT8
P2SbSidebandWrite8 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT8 Value
);
/**
Performs an 8-bit or on the register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] OrData Data with which register should be OR-ed
@return The 8-bit register value written to register
**/
UINT8
P2SbSidebandOr8 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT8 OrData
);
/**
Performs an 8-bit and on the register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] AndData Data with which register should be AND-ed
@return The 8-bit register value written to register
**/
UINT8
P2SbSidebandAnd8 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT8 AndData
);
/**
Performs an 8-bit and then or on the register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] AndData Data with which register should be AND-ed
@param[in] OrData Data with which register should be OR-ed
@return The 8-bit register value written to register
**/
UINT8
P2SbSidebandAndThenOr8 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT8 AndData,
IN UINT8 OrData
);
/**
Reads a 16-bit register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@return The 16-bit register value specified by Offset
**/
UINT16
P2SbSidebandRead16 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset
);
/**
Writes a 16-bit register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] Value Value to write to register
@return The 16-bit register value written to register
**/
UINT16
P2SbSidebandWrite16 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT16 Value
);
/**
Performs a 16-bit or on the register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] OrData Data with which register should be OR-ed
@return The 16-bit register value written to register
**/
UINT16
P2SbSidebandOr16 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT16 OrData
);
/**
Performs a 16-bit and on the register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] AndData Data with which register should be AND-ed
@return The 16-bit register value written to register
**/
UINT16
P2SbSidebandAnd16 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT16 AndData
);
/**
Performs a 16-bit and then or on the register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] AndData Data with which register should be AND-ed
@param[in] OrData Data with which register should be OR-ed
@return The 16-bit register value written to register
**/
UINT16
P2SbSidebandAndThenOr16 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT16 AndData,
IN UINT16 OrData
);
/**
Reads a 32-bit register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@return The 32-bit register value specified by Offset
**/
UINT32
P2SbSidebandRead32 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset
);
/**
Writes a 32-bit register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] Value Value to write to register
@return The 32-bit register value written to register
**/
UINT32
P2SbSidebandWrite32 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT32 Value
);
/**
Performs a 32-bit or on the register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] OrData Data with which register should be OR-ed
@return The 32-bit register value written to register
**/
UINT32
P2SbSidebandOr32 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT32 OrData
);
/**
Performs a 32-bit and on the register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] AndData Data with which register should be AND-ed
@return The 32-bit register value written to register
**/
UINT32
P2SbSidebandAnd32 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT32 AndData
);
/**
Performs a 32-bit and then or on the register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] AndData Data with which register should be AND-ed
@param[in] OrData Data with which register should be OR-ed
@return The 32-bit register value written to register
**/
UINT32
P2SbSidebandAndThenOr32 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT32 AndData,
IN UINT32 OrData
);
/**
Builds P2SB sideband access.
@param[in] P2SbController Pointer to P2SB controller implementing the sideband
@param[in] P2SbPid Port id
@param[in] Fid Function id
@param[in] RegisterSpace Target register space
@param[in] AccessMethod Access method
@param[in] PostedWrites If TRUE writes sent through sideband msg will be posted
@param[out] P2SbSidebandAccess On output an initialized sideband access descriptor
@retval TRUE Access initialized successfuly
@retval FALSE Failed to initialize access
**/
BOOLEAN
BuildP2SbSidebandAccess (
IN P2SB_CONTROLLER *P2sbController,
IN P2SB_PID P2SbPid,
IN UINT16 Fid,
IN P2SB_REGISTER_SPACE RegisterSpace,
IN P2SB_SIDEBAND_ACCESS_METHOD AccessMethod,
IN BOOLEAN PostedWrites,
OUT P2SB_SIDEBAND_REGISTER_ACCESS *P2SbSidebandAccess
);
/**
Builds P2SB sideband access using offset to config space.
This offset will be added to every register offset, when access callbacks are used.
Some IPs, like for example DMI, implement multiple register banks in the same register space.
For instance sideband register space can contain both PCR registers,
starting from the beginning of the register space,
and PCI config registers starting from the offset in the same register space.
@param[in] P2SbController Pointer to P2SB controller implementing the sideband
@param[in] P2SbPid Port id
@param[in] Fid Function id
@param[in] RegisterSpace Target register space
@param[in] AccessMethod Access method
@param[in] PostedWrites If TRUE writes sent through sideband msg will be posted
@param[in] Offset Register space offset that will be added to register offset
@param[out] P2SbSidebandAccess An initialized sideband access descriptor containing register space offset
@retval TRUE Access initialized successfuly
@retval FALSE Failed to initialize access
**/
BOOLEAN
BuildP2SbSidebandAccessEx (
IN P2SB_CONTROLLER *P2SbController,
IN P2SB_PID P2SbPid,
IN UINT16 Fid,
IN P2SB_REGISTER_SPACE RegisterSpace,
IN P2SB_SIDEBAND_ACCESS_METHOD AccessMethod,
IN BOOLEAN PostedWrites,
IN UINT32 Offset,
OUT P2SB_SIDEBAND_REGISTER_ACCESS *P2SbSidebandAccess
);
/**
Get P2SB instance for MTL PCH
@param[in, out] P2SbController P2SB controller pointer
@retval EFI_SUCCESS - Completed successfully
EFI_INVALID_PARAMETER - P2SbController NULL
**/
EFI_STATUS
MtlPchGetP2SbController (
IN OUT P2SB_CONTROLLER *P2SbController
);
#endif
Silicon/ArrowlakePkg/Include/PchReservedResources.h
-3
View File
@@ -59,9 +59,6 @@
#define PCH_TRACE_HUB_MTB_MMIO_SIZE 0x00100000 ///< 1MB
#define PCH_TRACE_HUB_FW_BASE_ADDRESS 0xFE200000 ///< TraceHub FW MMIO base address
#define PCH_PCR_BASE_ADDRESS 0xE0000000 ///< SBREG MMIO base address
#define PCH_PCR_MMIO_SIZE 0x01000000 ///< 16MB
#define IOE_PCR_ABOVE_4G_BASE_ADDRESS 0x3FFF0000000 ///< IOE P2SB above 4G base address (PhysicalAddressBits - SIZE_256M
#endif
Silicon/ArrowlakePkg/Include/PcrDefine.h
-60
View File
@@ -1,60 +0,0 @@
/** @file
Private Control Register definitions
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _PCR_DEFINE_H_
#define _PCR_DEFINE_H_
#include "PchReservedResources.h"
/**
Definition for PCR address
The PCR address is used to the PCR MMIO programming
SBREG_BAR_20BITADDRESS is configured by SoC
SBREG_BAR_20BITADDRESS=1, the format has included 16b addressing.
+---------------------------------------------------------------------------------------------+
| Addr[63:28] | Addr[27:24] | Addr[23:16] | Addr[15:2] | Addr[1:0] |
+----------------+-----------------------+-----------------+----------------------------------+
| REG_BAR[63:28] | TargetRegister[19:16] | TargetPort[7:0] | TargetRegister[15:2] |
+---------------------------------------------------------------------------------------------+
SBREG_BAR_20BITADDRESS=0
+---------------------------------------------------------------------------------------------+
| Addr[63:24] | Addr[27:24] | Addr[23:16] | Addr[15:2] | Addr[1:0] |
+----------------+-----------------------+-----------------+----------------------------------+
| REG_BAR[63:24] | REG_BAR[27:24] | TargetPort[7:0] | TargetRegister[15:2] |
+---------------------------------------------------------------------------------------------+
**/
#define PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_ADDRESS | (UINT32) (((Offset) & 0x0F0000) << 8) | ((UINT8)(Pid) << 16) | (UINT16) ((Offset) & 0xFFFF))
/**
PCH PCR boot script accessing macro
Those macros are only available for DXE phase.
**/
#define PCH_PCR_BOOT_SCRIPT_WRITE(Width, Pid, Offset, Count, Buffer) \
S3BootScriptSaveMemWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), Count, Buffer); \
#define PCH_PCR_BOOT_SCRIPT_READ_WRITE(Width, Pid, Offset, DataOr, DataAnd) \
S3BootScriptSaveMemReadWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), DataOr, DataAnd); \
#define PCH_PCR_BOOT_SCRIPT_READ(Width, Pid, Offset, BitMask, BitValue) \
S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), BitMask, BitValue, 1, 1);
typedef UINT8 P2SB_PID;
typedef union {
UINT16 Pid16bit;
struct {
P2SB_PID LocalPid;
UINT8 SegmentId;
} PortId;
} P2SB_PORT_16_ID;
#define GET_P2SB_LOCAL_PID(id) ((id) & 0xFF)
#endif // _PCR_DEFINE_H_
Silicon/ArrowlakePkg/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf
-1
View File
@@ -28,4 +28,3 @@
IoLib
DebugLib
PcieRpSocLib
P2SbSocLib
Silicon/ArrowlakePkg/Library/FirmwareUpdateLib/FirmwareUpdateLib.c
-1
View File
@@ -18,7 +18,6 @@
#include <Library/FirmwareUpdateLib.h>
#include <Library/BootloaderCommonLib.h>
#include <Library/PchSbiAccessLib.h>
#include <Library/PchPcrLib.h>
#include <Library/HeciInitLib.h>
#include <Register/PchRegsPcr.h>
#include <Register/PchRegsLpc.h>
Silicon/ArrowlakePkg/Library/PchP2sbLib/PchP2sbLib.c
-976
View File
File diff suppressed because it is too large Load Diff
Silicon/ArrowlakePkg/Library/PciExpressHelpersLibrary/PciExpressHelpersLibrary.inf
+3 -6
View File
@@ -24,13 +24,10 @@
[LibraryClasses]
IoLib
DebugLib
PchPcrLib
PchInfoLib
GpioLib
TimerLib
BasePchPciBdfLib
BasePcieHelperLib
PcieRpLib
PchInfoLib
TimerLib
BasePcieHelperLib
[Packages]
Silicon/ArrowlakePkg/ArrowlakePkg.dec
Silicon/ArrowlakePkg/Library/PcieRpLib/PcieRpLib.inf
-3
View File
@@ -25,12 +25,9 @@
[LibraryClasses]
IoLib
DebugLib
PchPcrLib
PchInfoLib
GpioLib
TimerLib
BasePcieHelperLib
PchPciBdfLib
[Packages]
MdePkg/MdePkg.dec
Silicon/ArrowlakePkg/Library/PlatformHookLib/PlatformHookLib.c
-2
View File
@@ -10,14 +10,12 @@
#include <Library/IoLib.h>
#include <Library/PciLib.h>
#include <Library/PchInfoLib.h>
#include <Library/PchPcrLib.h>
#include <Library/BootloaderCommonLib.h>
#include <Library/BootloaderCoreLib.h>
#include <PchReservedResources.h>
#include <PchAccess.h>
#include <IndustryStandard/Pci.h>
#include <Register/SerialIoUartRegs.h>
#include <Include/PcrDefine.h>
#include <Library/PciSegmentLib.h>
#include <Register/SaRegsHostBridge.h>
#include <Register/PchRegsLpc.h>
Silicon/ArrowlakePkg/Library/PlatformHookLib/PlatformHookLibArlp.c
-2
View File
@@ -10,14 +10,12 @@
#include <Library/IoLib.h>
#include <Library/PciLib.h>
#include <Library/PchInfoLib.h>
#include <Library/PchPcrLib.h>
#include <Library/BootloaderCommonLib.h>
#include <Library/BootloaderCoreLib.h>
#include <PchReservedResources.h>
#include <PchAccess.h>
#include <IndustryStandard/Pci.h>
#include <Register/SerialIoUartRegs.h>
#include <Include/PcrDefine.h>
#include <Library/PciSegmentLib.h>
#include <Register/SaRegsHostBridge.h>
#include <Register/PchRegsLpc.h>
Silicon/CommonSocPkg/Include/Library/P2SbSidebandAccessLib.h
-391
View File
@@ -1,391 +0,0 @@
/** @file
Header for P2SbSidebandAccessLib
Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _P2SB_SIDEBAND_ACCESS_LIB_H_
#define _P2SB_SIDEBAND_ACCESS_LIB_H_
#include "Library/RegisterAccess.h"
#include <Library/PchSbiAccessLib.h>
#include "Library/P2SbController.h"
#include "Library/PcrDefine.h"
#include <Uefi/UefiBaseType.h>
//#include "PchSbiAccessV2Lib.h"
#define P2SB_REGISTER_ACCESS_INIT {P2SbSidebandRead8, P2SbSidebandWrite8, P2SbSidebandOr8, P2SbSidebandAnd8, P2SbSidebandAndThenOr8, \
P2SbSidebandRead16, P2SbSidebandWrite16, P2SbSidebandOr16, P2SbSidebandAnd16, P2SbSidebandAndThenOr16,\
P2SbSidebandRead32, P2SbSidebandWrite32, P2SbSidebandOr32, P2SbSidebandAnd32, P2SbSidebandAndThenOr32}
typedef enum {
P2SbMemory = 0,
P2SbPciConfig,
P2SbPrivateConfig
} P2SB_REGISTER_SPACE;
typedef enum {
P2SbMmioAccess = 0,
P2SbMsgAccess
} P2SB_SIDEBAND_ACCESS_METHOD;
/**
REGISTER_ACCESS for P2SB device to support access to sideband registers.
Be sure to keep first member of this structure as REGISTER_ACCESS to allow
for correct casting between caller who sees this structure as REGISTER_ACCESS
and calle who will cast it to P2SB_SIDEBAND_REGISTER_ACCESS.
**/
typedef struct {
REGISTER_ACCESS Access;
P2SB_SIDEBAND_ACCESS_METHOD AccessMethod;
P2SB_PID P2SbPid;
UINT16 Fid;
P2SB_REGISTER_SPACE RegisterSpace;
BOOLEAN PostedWrites;
P2SB_CONTROLLER P2SbCtrl;
UINT32 Offset;
} P2SB_SIDEBAND_REGISTER_ACCESS;
/**
Reads an 8-bit register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@return The 8-bit register value specified by Offset
**/
UINT8
P2SbSidebandRead8 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset
);
/**
Writes an 8-bit register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] Value Value to write to register
@return The 8-bit register value written to register
**/
UINT8
P2SbSidebandWrite8 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT8 Value
);
/**
Performs an 8-bit or on the register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] OrData Data with which register should be OR-ed
@return The 8-bit register value written to register
**/
UINT8
P2SbSidebandOr8 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT8 OrData
);
/**
Performs an 8-bit and on the register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] AndData Data with which register should be AND-ed
@return The 8-bit register value written to register
**/
UINT8
P2SbSidebandAnd8 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT8 AndData
);
/**
Performs an 8-bit and then or on the register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] AndData Data with which register should be AND-ed
@param[in] OrData Data with which register should be OR-ed
@return The 8-bit register value written to register
**/
UINT8
P2SbSidebandAndThenOr8 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT8 AndData,
IN UINT8 OrData
);
/**
Reads a 16-bit register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@return The 16-bit register value specified by Offset
**/
UINT16
P2SbSidebandRead16 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset
);
/**
Writes a 16-bit register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] Value Value to write to register
@return The 16-bit register value written to register
**/
UINT16
P2SbSidebandWrite16 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT16 Value
);
/**
Performs a 16-bit or on the register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] OrData Data with which register should be OR-ed
@return The 16-bit register value written to register
**/
UINT16
P2SbSidebandOr16 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT16 OrData
);
/**
Performs a 16-bit and on the register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] AndData Data with which register should be AND-ed
@return The 16-bit register value written to register
**/
UINT16
P2SbSidebandAnd16 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT16 AndData
);
/**
Performs a 16-bit and then or on the register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] AndData Data with which register should be AND-ed
@param[in] OrData Data with which register should be OR-ed
@return The 16-bit register value written to register
**/
UINT16
P2SbSidebandAndThenOr16 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT16 AndData,
IN UINT16 OrData
);
/**
Reads a 32-bit register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@return The 32-bit register value specified by Offset
**/
UINT32
P2SbSidebandRead32 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset
);
/**
Writes a 32-bit register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] Value Value to write to register
@return The 32-bit register value written to register
**/
UINT32
P2SbSidebandWrite32 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT32 Value
);
/**
Performs a 32-bit or on the register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] OrData Data with which register should be OR-ed
@return The 32-bit register value written to register
**/
UINT32
P2SbSidebandOr32 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT32 OrData
);
/**
Performs a 32-bit and on the register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] AndData Data with which register should be AND-ed
@return The 32-bit register value written to register
**/
UINT32
P2SbSidebandAnd32 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT32 AndData
);
/**
Performs a 32-bit and then or on the register
@param[in] This Pointer to REGISTER_ACCESS
@param[in] Offset Offset of the register in the register bank
@param[in] AndData Data with which register should be AND-ed
@param[in] OrData Data with which register should be OR-ed
@return The 32-bit register value written to register
**/
UINT32
P2SbSidebandAndThenOr32 (
IN REGISTER_ACCESS *This,
IN UINT32 Offset,
IN UINT32 AndData,
IN UINT32 OrData
);
/**
Full function for executing P2SB SBI message
Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
It will clash with POST time SBI programming when SMI happen.
Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI
to prevent from racing condition.
This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access
needed, it's better to unhide the P2SB before calling and hide it back after done.
When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been
SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information
when needed.
@param[in] P2sbBase P2SB PCI config base
@param[in] Pid Port ID of the SBI message
@param[in] Offset Offset of the SBI message
@param[in] Opcode Opcode
@param[in] Posted Posted message
@param[in] Fbe First byte enable
@param[in] Bar Bar
@param[in] Fid Function ID
@param[in, out] Data32 Read/Write data
@param[out] Response Response
@retval EFI_SUCCESS Successfully completed.
@retval EFI_DEVICE_ERROR Transaction fail
@retval EFI_INVALID_PARAMETER Invalid parameter
@retval EFI_TIMEOUT Timeout while waiting for response
**/
EFI_STATUS
P2SbSbiExecutionEx (
IN UINT64 P2sbBase,
IN P2SB_PID Pid,
IN UINT64 Offset,
IN PCH_SBI_OPCODE Opcode,
IN BOOLEAN Posted,
IN UINT16 Fbe,
IN UINT16 Bar,
IN UINT16 Fid,
IN OUT UINT32 *Data32,
OUT UINT8 *Response
);
/**
Builds P2SB sideband access.
@param[in] P2SbController Pointer to P2SB controller implementing the sideband
@param[in] P2SbPid Port id
@param[in] Fid Function id
@param[in] RegisterSpace Target register space
@param[in] AccessMethod Access method
@param[in] PostedWrites If TRUE writes sent through sideband msg will be posted
@param[out] P2SbSidebandAccess On output an initialized sideband access descriptor
@retval TRUE Access initialized successfuly
@retval FALSE Failed to initialize access
**/
BOOLEAN
BuildP2SbSidebandAccess (
IN P2SB_PID P2SbPid,
IN UINT16 Fid,
IN P2SB_REGISTER_SPACE RegisterSpace,
IN P2SB_SIDEBAND_ACCESS_METHOD AccessMethod,
IN BOOLEAN PostedWrites,
OUT P2SB_SIDEBAND_REGISTER_ACCESS *P2SbSidebandAccess
);
/**
Builds P2SB sideband access using offset to config space.
This offset will be added to every register offset, when access callbacks are used.
Some IPs, like for example DMI, implement multiple register banks in the same register space.
For instance sideband register space can contain both PCR registers,
starting from the beginning of the register space,
and PCI config registers starting from the offset in the same register space.
@param[in] P2SbController Pointer to P2SB controller implementing the sideband
@param[in] P2SbPid Port id
@param[in] Fid Function id
@param[in] RegisterSpace Target register space
@param[in] AccessMethod Access method
@param[in] PostedWrites If TRUE writes sent through sideband msg will be posted
@param[in] Offset Register space offset that will be added to register offset
@param[out] P2SbSidebandAccess An initialized sideband access descriptor containing register space offset
@retval TRUE Access initialized successfuly
@retval FALSE Failed to initialize access
**/
BOOLEAN
BuildP2SbSidebandAccessEx (
IN P2SB_CONTROLLER *P2SbController,
IN P2SB_PID P2SbPid,
IN UINT16 Fid,
IN P2SB_REGISTER_SPACE RegisterSpace,
IN P2SB_SIDEBAND_ACCESS_METHOD AccessMethod,
IN BOOLEAN PostedWrites,
IN UINT32 Offset,
OUT P2SB_SIDEBAND_REGISTER_ACCESS *P2SbSidebandAccess
);
#endif
Silicon/CommonSocPkg/Library/PchPcrLib/PchPcrLib.inf
-1
View File
@@ -32,6 +32,5 @@
IoLib
DebugLib
PchInfoLib
GpioSiLib
[Pcd]