mirror of
https://github.com/Dasharo/slimbootloader.git
synced 2026-06-14 04:16:15 -07:00
feat: [AZB] Add Arizona Beach platform support
This patch adds platform and silicon for Arizona Beach (AZB) platform. TEST=LPDDR5 AZB CRB board is able to boot to Yocto. Signed-off-by: Aakash Panwar <aakash.panwar@intel.com> Signed-off-by: Akshatha Thekkade <akshatha.thekkade@intel.com> Signed-off-by: Biswas Arghya <arghya.biswas@intel.com> Signed-off-by: Chirag Vijay Kolhe <chirag.vijay.kolhe@intel.com> Signed-off-by: M Karuppasamy <karuppasamy.m@intel.com> Signed-off-by: Sachin Kamat <sachin.kamat@intel.com>
This commit is contained in:
Sachin Kamat
Guo Dong
@@ -109,6 +109,14 @@ jobs:
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Build.Name: "rpls"
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Build.Arch: ""
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Build.Target: ""
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AZB_X86_DEBUG:
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Build.Name: "azb"
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Build.Arch: ""
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Build.Target: ""
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AZB_X86_RELEASE:
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Build.Name: "azb"
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Build.Arch: ""
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Build.Target: "-r"
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pool:
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@@ -228,6 +236,14 @@ jobs:
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Build.Name: "rpls"
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Build.Arch: "-a x64"
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Build.Target: ""
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AZB_X86_DEBUG:
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Build.Name: "azb"
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Build.Arch: ""
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Build.Target: ""
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AZB_X86_RELEASE:
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Build.Name: "azb"
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Build.Arch: ""
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Build.Target: "-r"
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pool:
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vmImage: 'windows-2019'
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@@ -4,3 +4,4 @@ VerInfo.txt
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!CoffeelakeBoardPkg/VbtBin/
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!AlderlakeBoardPkg/VbtBin/
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!ApollolakeBoardPkg/VbtBin/Vbt_*.*
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*.json
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@@ -38,6 +38,7 @@ class Board(BaseBoard):
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self.MICROCODE_INF_FILE = ''
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self._LP_SUPPORT = False
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self._N_SUPPORT = False
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self._AZB_SUPPORT = False
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self.PCI_EXPRESS_BASE = 0xC0000000
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self.PCI_IO_BASE = 0x00002000
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@@ -0,0 +1,417 @@
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## @file
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# This file is used to provide board specific image information.
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#
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# Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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# Import Modules
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#
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import os
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import sys
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import time
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sys.dont_write_bytecode = True
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sys.path.append (os.path.join('..', '..'))
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from BuildLoader import BaseBoard, STITCH_OPS, FLASH_REGION_TYPE, HASH_USAGE
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from BuildLoader import IPP_CRYPTO_OPTIMIZATION_MASK, IPP_CRYPTO_ALG_MASK, HASH_TYPE_VALUE
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class Board(BaseBoard):
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def __init__(self, *args, **kwargs):
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super(Board, self).__init__(*args, **kwargs)
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self.VERINFO_IMAGE_ID = 'SB_AZB'
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self.VERINFO_PROJ_MAJOR_VER = 1
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self.VERINFO_PROJ_MINOR_VER = 2
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self.VERINFO_CORE_MAJOR_VER = 1
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self.VERINFO_CORE_MINOR_VER = 0
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self.VERINFO_SVN = 1
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self.VERINFO_BUILD_DATE = time.strftime("%m/%d/%Y")
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self.BOARD_NAME = 'azb'
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self.BOARD_PKG_NAME = 'AlderlakeBoardPkg'
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self.SILICON_PKG_NAME = 'AlderlakePkg'
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self._CFGDATA_DEF_FILE = 'CfgDataDefAzb.yaml'
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self.FSP_IMAGE_ID = '$ADLFSP$'
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self._EXTRA_INC_PATH = ['Silicon/AlderlakePkg/Azb/Include']
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self._FSP_PATH_NAME = 'Silicon/AlderlakePkg/Azb/FspBin'
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self.MICROCODE_INF_FILE = 'Silicon/AlderlakePkg/Microcode/MicrocodeAzb.inf'
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self._LP_SUPPORT = False
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self._N_SUPPORT = False
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self._AZB_SUPPORT = True
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# _AZB_WWAN_SUPPORT enable WWAN with ~600ms delay in Stage1B for GPIO init.
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# If WWAN is not needed then change the flag as False to save ~600ms boot time.
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self._AZB_WWAN_SUPPORT = True
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self.SUPPORT_SR_IOV = 0
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self.PCI_EXPRESS_BASE = 0xC0000000
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self.PCI_IO_BASE = 0x00002000
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self.PCI_MEM32_BASE = 0x80000000
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self.ACPI_PM_TIMER_BASE = 0x1808
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self.FLASH_LAYOUT_START = 0x100000000 # 4GB Top
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self.FLASH_BASE_SIZE = 0x02000000 # 32MB
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self.FLASH_BASE_ADDRESS = (self.FLASH_LAYOUT_START - self.FLASH_BASE_SIZE)
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self.LOADER_ACPI_RECLAIM_MEM_SIZE = 0x000090000
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self.HAVE_FIT_TABLE = 1
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self.HAVE_VBT_BIN = 0
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self.HAVE_VERIFIED_BOOT = 1
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self.HAVE_MEASURED_BOOT = 1
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self.HAVE_FLASH_MAP = 1
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self.HAVE_ACPI_TABLE = 1
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self.HAVE_PSD_TABLE = 1
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self.ENABLE_SPLASH = 0
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self.ENABLE_FRAMEBUFFER_INIT = 0
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self.ENABLE_VTD = 0
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# To enable source debug, set 1 to self.ENABLE_SOURCE_DEBUG
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self.ENABLE_SOURCE_DEBUG = 0
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# If ENABLE_SOURCE_DEBUG is disabled, SKIP_STAGE1A_SOURCE_DEBUG will be ignored
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self.SKIP_STAGE1A_SOURCE_DEBUG = 1
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self.ENABLE_PCIE_PM = 1
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# 0: Disable 1: Enable 2: Auto (disable for UEFI payload, enable for others)
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self.ENABLE_SMM_REBASE = 2
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# 0 - PCH UART0, 1 - PCH UART1, 2 - PCH UART2, 0xFF - EC UART 0x3F8
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self.DEBUG_PORT_NUMBER = 0x0
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self.ENABLE_MULTI_USB_BOOT_DEV = 1
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self.CPU_MAX_LOGICAL_PROCESSOR_NUMBER = 24
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if self.HAVE_FIT_TABLE:
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self.FIT_ENTRY_MAX_NUM = 17
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# RSA2048 or RSA3072
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self._RSA_SIGN_TYPE = 'RSA3072'
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# 'SHA2_256' or 'SHA2_384'
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self._SIGN_HASH = 'SHA2_384'
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# 0x01 for SHA2_256 or 0x02 for SHA2_384
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self.SIGN_HASH_TYPE = HASH_TYPE_VALUE[self._SIGN_HASH]
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# 0x0010 for SM3_256 | 0x0008 for SHA2_512 | 0x0004 for SHA2_384 | 0x0002 for SHA2_256 | 0x0001 for SHA1
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self.IPP_HASH_LIB_SUPPORTED_MASK = IPP_CRYPTO_ALG_MASK['SHA2_384'] | IPP_CRYPTO_ALG_MASK['SHA2_256']
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# G9 for 384 | W7 Opt for SHA384| Ni Opt for SHA256| V8 Opt for SHA256
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self.ENABLE_CRYPTO_SHA_OPT = IPP_CRYPTO_OPTIMIZATION_MASK['SHA256_NI'] | IPP_CRYPTO_OPTIMIZATION_MASK['SHA384_W7']
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# Key configuration
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self._MASTER_PRIVATE_KEY = 'KEY_ID_MASTER' + '_' + self._RSA_SIGN_TYPE
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self._CFGDATA_PRIVATE_KEY = 'KEY_ID_CFGDATA' + '_' + self._RSA_SIGN_TYPE
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self._CONTAINER_PRIVATE_KEY = 'KEY_ID_CONTAINER' + '_' + self._RSA_SIGN_TYPE
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self.ENABLE_SMP_INIT = 1
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self.ENABLE_FWU = 1
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self.ENABLE_SMBIOS = 1
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self.ENABLE_CSME_UPDATE = 1
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# CSME update library is required to enable this option and will be available as part of CSME kit
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self.BUILD_CSME_UPDATE_DRIVER = 0
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self.STAGE1A_XIP = 1
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self.STAGE1B_XIP = 1
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self.STAGE2_XIP = 0
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self.STAGE1A_SIZE = 0x0001B000
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self.STAGE1_STACK_SIZE = 0x00002000
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self.STAGE1_DATA_SIZE = 0x00014000
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self.FSP_M_STACK_TOP = 0xFEF7FF00
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self.STAGE1B_SIZE = 0x00200000
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if self.FSPDEBUG_MODE:
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self.STAGE2_SIZE = 0x000CE000
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else:
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self.STAGE2_SIZE = 0x000C3000
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self.STAGE2_FD_BASE = 0x01000000
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self.STAGE2_FD_SIZE = 0x001F0000
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self.PAYLOAD_SIZE = 0x00030000
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self.EPAYLOAD_SIZE = 0x00161000
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self.ENABLE_FAST_BOOT = 0
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if self.ENABLE_FAST_BOOT:
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self.ENABLE_SPLASH = 0
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self.ENABLE_FRAMEBUFFER_INIT = 0
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self.RELEASE_MODE = 1
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self.HAVE_VERIFIED_BOOT = 0
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self.HAVE_MEASURED_BOOT = 0
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self.VERIFIED_BOOT_HASH_MASK = 0
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self.FSPDEBUG_MODE = 0
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self.ENABLE_SOURCE_DEBUG = 0
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if self.RELEASE_MODE and self.ENABLE_FAST_BOOT:
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self.STAGE1A_SIZE = 0x0001A000
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self.STAGE1B_SIZE = 0x000E0000
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self.STAGE2_SIZE = 0x00079000
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self.STAGE2_FD_SIZE = 0x000F0000
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self.PAYLOAD_SIZE = 0x00020000
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if self.ENABLE_SOURCE_DEBUG:
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if self.FSPDEBUG_MODE:
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self.STAGE2_SIZE += 0x2000
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self.UEFI_VARIABLE_SIZE = 0x1000
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if len(self._PAYLOAD_NAME.split(';')) > 1:
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self.UEFI_VARIABLE_SIZE = 0x00040000
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self.UCODE_SIZE = 0x000C3000
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self.MRCDATA_SIZE = 0x00010000
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self.CFGDATA_SIZE = 0x00004000
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self.KEYHASH_SIZE = 0x00001000
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self.VARIABLE_SIZE = 0x00002000
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self.SBLRSVD_SIZE = 0x00001000
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self.FWUPDATE_SIZE = 0x00020000 if self.ENABLE_FWU else 0
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self.TOP_SWAP_SIZE = 0x00080000
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self.REDUNDANT_SIZE = self.UCODE_SIZE + self.STAGE2_SIZE + self.STAGE1B_SIZE + \
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self.FWUPDATE_SIZE + self.CFGDATA_SIZE + self.KEYHASH_SIZE
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self.REDUNDANT_SIZE = ((self.REDUNDANT_SIZE + 0xFFFF) & ~0xFFFF)
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self.SIIPFW_SIZE = 0x1000
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self.OS_LOADER_FD_SIZE = 0x58000
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self.OS_LOADER_FD_NUMBLK = self.OS_LOADER_FD_SIZE // self.FLASH_BLOCK_SIZE
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self.NON_REDUNDANT_SIZE = 0x3BF000 + self.SIIPFW_SIZE
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self.NON_VOLATILE_SIZE = 0x001000
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self.SLIMBOOTLOADER_SIZE = (self.TOP_SWAP_SIZE + self.REDUNDANT_SIZE) * 2 + \
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self.NON_REDUNDANT_SIZE + self.NON_VOLATILE_SIZE
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self.SLIMBOOTLOADER_SIZE = ((self.SLIMBOOTLOADER_SIZE + 0xFFFFF) & ~0xFFFFF)
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self.PLD_HEAP_SIZE = 0x04000000
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self.PLD_STACK_SIZE = 0x00020000
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self.PLD_RSVD_MEM_SIZE = 0x00500000
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self.KM_SIZE = 0x00000400
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self.BPM_SIZE = 0x00000600
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self.ACM_SIZE = 0x00040000 + self.KM_SIZE + self.BPM_SIZE
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# adjust ACM_SIZE to meet 256KB alignment (to align 256KB ACM size)
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if self.ACM_SIZE > 0:
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acm_top = self.FLASH_LAYOUT_START - self.STAGE1A_SIZE
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acm_btm = acm_top - self.ACM_SIZE
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acm_btm = (acm_btm & 0xFFFC0000)
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self.ACM_SIZE = acm_top - acm_btm
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self.LOADER_RSVD_MEM_SIZE = 0x500000
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self.CFG_DATABASE_SIZE = self.CFGDATA_SIZE
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self._generated_cfg_file_prefix = 'Autogen_'
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self._CFGDATA_INT_FILE = []
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self._CFGDATA_EXT_FILE = [self._generated_cfg_file_prefix + 'CfgDataInt_Azb_Crb_Lpddr5.dlt']
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def PlatformBuildHook (self, build, phase):
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if phase == 'pre-build:before':
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# create build folder if not exist
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if not os.path.exists(build._fv_dir):
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os.makedirs(build._fv_dir)
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# Generate the dlt files based on feature
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brd_cfg_src_dir = os.path.join(os.environ['PLT_SOURCE'], 'Platform', self.BOARD_PKG_NAME, 'CfgData')
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brd_cfg2_src_dir = '.'
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if hasattr(self, 'BOARD_PKG_NAME_OVERRIDE'):
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brd_cfg2_src_dir = os.path.join(os.environ['PLT_SOURCE'], 'Platform', self.BOARD_PKG_NAME_OVERRIDE, 'CfgData')
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for dlt_file in self._CFGDATA_EXT_FILE:
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cfg_dlt_file = os.path.join(brd_cfg_src_dir, dlt_file[len (self._generated_cfg_file_prefix):])
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if not os.path.exists(cfg_dlt_file):
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cfg_dlt_file = os.path.join(brd_cfg2_src_dir, dlt_file[len (self._generated_cfg_file_prefix):])
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lines = open (cfg_dlt_file).read()
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# Write to generated final dlt file
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output_cfg_dlt_file = os.path.join(build._fv_dir, dlt_file)
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open(output_cfg_dlt_file, 'w').write(lines)
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def GetPlatformDsc (self, BuildPkgName = "BootLoaderCorePkg"):
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dsc = {}
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# These libraries will be added into the DSC files
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dsc['LibraryClasses.%s' % self.BUILD_ARCH] = [
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'LoaderLib|Platform/CommonBoardPkg/Library/LoaderLib/LoaderLib.inf',
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'SerialPortLib|BootloaderCommonPkg/Library/SerialPortLib/SerialPortLib.inf',
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'PlatformHookLib|Silicon/$(SILICON_PKG_NAME)/Library/PlatformHookLib/PlatformHookLib.inf',
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'ResetSystemLib|Platform/$(BOARD_PKG_NAME)/Library/ResetSystemLib/ResetSystemLib.inf',
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'GpioLib|Silicon/CommonSocPkg/Library/GpioLib/GpioLib.inf',
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'GpioSiLib|Silicon/$(SILICON_PKG_NAME)/Library/GpioSiLib/GpioSiLib.inf',
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'PchSbiAccessLib|Silicon/CommonSocPkg/Library/PchSbiAccessLib/PchSbiAccessLib.inf',
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'TccLib|Silicon/CommonSocPkg/Library/TccLib/TccLib.inf',
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'ShellExtensionLib|Platform/$(BOARD_PKG_NAME)/Library/ShellExtensionLib/ShellExtensionLib.inf',
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'FspmUpdUpdateLib|Platform/$(BOARD_PKG_NAME)/Library/FspmUpdUpdateLib/FspmUpdUpdateLibAzb.inf',
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'FspsUpdUpdateLib|Platform/$(BOARD_PKG_NAME)/Library/FspsUpdUpdateLib/FspsUpdUpdateLibAzb.inf',
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'PchInfoLib|Silicon/$(SILICON_PKG_NAME)/Library/PchInfoLib/PchInfoLib.inf',
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'PchPciBdfLib|Silicon/$(SILICON_PKG_NAME)/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf',
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'PchPcrLib|Silicon/CommonSocPkg/Library/PchPcrLib/PchPcrLib.inf',
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'PchSpiLib|Silicon/CommonSocPkg/Library/PchSpiLib/PchSpiLib.inf',
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'SpiFlashLib|Silicon/CommonSocPkg/Library/SpiFlashLib/SpiFlashLib.inf',
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'BootGuardLib|Silicon/CommonSocPkg/Library/BootGuardLibCBnT/BootGuardLibCBnT.inf',
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'BdatLib|Silicon/CommonSocPkg/Library/BdatLib/BdatLib.inf',
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'SmbusLib|Silicon/CommonSocPkg/Library/SmbusLib/SmbusLib.inf',
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'IgdOpRegionLib|Silicon/CommonSocPkg/Library/IgdOpRegionLib/IgdOpRegionLib.inf',
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'HeciLib|Silicon/CommonSocPkg/Library/HeciLib/HeciLib.inf',
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'MeChipsetLib|Silicon/$(SILICON_PKG_NAME)/Library/MeChipsetLib/MeChipsetLib.inf',
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'VtdLib|Silicon/$(SILICON_PKG_NAME)/Library/VTdLib/VTdLib.inf',
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'PsdLib|Silicon/$(SILICON_PKG_NAME)/Library/PsdLib/PsdLib.inf',
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'HeciMeExtLib|Silicon/$(SILICON_PKG_NAME)/Library/HeciMeExtLib/HeciMeExtLib.inf',
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'MeExtMeasurementLib|Silicon/$(SILICON_PKG_NAME)/Library/MeExtMeasurementLib/MeExtMeasurementLib.inf',
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'CpuPcieHsPhyInitLib|Silicon/$(SILICON_PKG_NAME)/Library/CpuPcieHsPhyInitLib/CpuPcieHsPhyInitLib.inf',
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'WatchDogTimerLib|Silicon/CommonSocPkg/Library/WatchDogTimerLib/WatchDogTimerLib.inf',
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'TcoTimerLib|Silicon/CommonSocPkg/Library/TcoTimerLib/TcoTimerLib.inf',
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'TopSwapLib|Silicon/CommonSocPkg/Library/TopSwapLib/TopSwapLib.inf',
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]
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if self.BUILD_CSME_UPDATE_DRIVER:
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dsc['LibraryClasses.%s' % self.BUILD_ARCH].append ('MeFwUpdateLib|Silicon/$(SILICON_PKG_NAME)/Library/MeFwUpdateLib/MeFwUpdateLib.inf')
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if self.ENABLE_PCIE_PM:
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lib = [
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'PciePm|Silicon/$(SILICON_PKG_NAME)/Library/PciePm/PciePm.inf',
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'PciExpressHelpersLib|Silicon/$(SILICON_PKG_NAME)/Library/PciExpressHelpersLibrary/PciExpressHelpersLibrary.inf',
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'BasePcieHelperLib|Silicon/$(SILICON_PKG_NAME)/Library/BasePcieHelperLib/BasePcieHelperLib.inf',
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'PcieClientRpLib|Silicon/$(SILICON_PKG_NAME)/Library/PcieClientRpLib/PcieClientRpLib.inf',
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'BasePchPciBdfLib|Silicon/$(SILICON_PKG_NAME)/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf',
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]
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dsc['LibraryClasses.%s' % self.BUILD_ARCH].extend (lib)
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else:
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dsc['LibraryClasses.%s' % self.BUILD_ARCH].append ('PciePm|Silicon/CommonSocPkg/Library/PciePmNull/PciePmNull.inf')
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dsc['PcdsFixedAtBuild'] = ['gPlatformModuleTokenSpaceGuid.PcdAcpiTablesMaxEntry | 40']
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if self._LP_SUPPORT:
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dsc['PcdsFixedAtBuild'].append ('gPlatformAlderLakeTokenSpaceGuid.PcdAdlLpSupport | TRUE')
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if self._AZB_SUPPORT:
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dsc['PcdsFixedAtBuild'].append ('gPlatformAlderLakeTokenSpaceGuid.PcdAzbSupport | TRUE')
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if self._AZB_WWAN_SUPPORT:
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dsc['PcdsFixedAtBuild'].append ('gPlatformAlderLakeTokenSpaceGuid.PcdAzbWwanSupport | TRUE')
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return dsc
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def GetKeyHashList (self):
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# Define a set of new key used for different purposes
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# The key is either key id or public key PEM format or private key PEM format
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pub_key_list = [
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(
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# Key for verifying Config data blob
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HASH_USAGE['PUBKEY_CFG_DATA'],
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'KEY_ID_CFGDATA' + '_' + self._RSA_SIGN_TYPE
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),
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(
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# Key for verifying firmware update
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HASH_USAGE['PUBKEY_FWU'],
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'KEY_ID_FIRMWAREUPDATE' + '_' + self._RSA_SIGN_TYPE
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),
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||||
(
|
||||
# Key for verifying container header
|
||||
HASH_USAGE['PUBKEY_CONT_DEF'],
|
||||
'KEY_ID_CONTAINER' + '_' + self._RSA_SIGN_TYPE
|
||||
),
|
||||
(
|
||||
# Use RSA2048 key for verifying OS image signed with RSA2048
|
||||
HASH_USAGE['PUBKEY_OS'],
|
||||
'KEY_ID_OS1_PUBLIC_RSA2048'
|
||||
),
|
||||
(
|
||||
# Use RSA3072 key for verifying OS image signed with RSA3072
|
||||
HASH_USAGE['PUBKEY_OS'],
|
||||
'KEY_ID_OS1_PUBLIC_RSA3072'
|
||||
),
|
||||
]
|
||||
return pub_key_list
|
||||
|
||||
|
||||
def GetContainerList (self):
|
||||
container_list = []
|
||||
container_list_auth_type = self._RSA_SIGN_TYPE + '_'+ self._SIGNING_SCHEME[4:] + '_' + self._SIGN_HASH
|
||||
container_list.append (
|
||||
# Name | Image File | CompressAlg | AuthType | Key File | Region Align | Region Size | Svn Info
|
||||
# ========================================================================================================================================================
|
||||
('IPFW', 'SIIPFW.bin', '', container_list_auth_type, 'KEY_ID_CONTAINER'+'_'+self._RSA_SIGN_TYPE, 0, 0 , 0), # Container Header
|
||||
)
|
||||
|
||||
bins = os.path.join(os.path.dirname(os.path.realpath(__file__)), 'Binaries')
|
||||
|
||||
return [container_list]
|
||||
|
||||
|
||||
def GetOutputImages (self):
|
||||
# define extra images that will be copied to output folder
|
||||
img_list = ['SlimBootloader.txt',
|
||||
'FlashMap.txt',
|
||||
'CfgDataStitch.py',
|
||||
'CfgDataDef.yaml']
|
||||
return img_list
|
||||
|
||||
|
||||
def GetImageLayout (self):
|
||||
img_list = []
|
||||
|
||||
acm_flag = 0 if self.ACM_SIZE > 0 else STITCH_OPS.MODE_FILE_IGNOR
|
||||
fwu_flag = 0 if self.ENABLE_FWU else STITCH_OPS.MODE_FILE_IGNOR
|
||||
cfg_flag = 0 if len(self._CFGDATA_EXT_FILE) > 0 and self.CFGDATA_REGION_TYPE == FLASH_REGION_TYPE.BIOS else STITCH_OPS.MODE_FILE_IGNOR
|
||||
|
||||
if len(self._CFGDATA_EXT_FILE) > 0 and self.CFGDATA_REGION_TYPE == FLASH_REGION_TYPE.PLATFORMDATA:
|
||||
img_list.extend ([
|
||||
('CFGDATA_PDR.bin', [
|
||||
('CFGDATA.bin', '', self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
||||
]
|
||||
),
|
||||
])
|
||||
|
||||
img_list.extend ([
|
||||
('NON_VOLATILE.bin', [
|
||||
('SBLRSVD.bin', '' , self.SBLRSVD_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
|
||||
]
|
||||
),
|
||||
('NON_REDUNDANT.bin', [
|
||||
('SIIPFW.bin' , '' , self.SIIPFW_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
||||
('VARIABLE.bin' , '' , self.VARIABLE_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
|
||||
('MRCDATA.bin' , '' , self.MRCDATA_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
|
||||
('EPAYLOAD.bin', '' , self.EPAYLOAD_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
||||
('PAYLOAD.bin' , 'Lz4' , self.PAYLOAD_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
||||
('UEFIVARIABLE.bin', '' , self.UEFI_VARIABLE_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
|
||||
]
|
||||
),
|
||||
('REDUNDANT_A.bin', [
|
||||
('UCODE.bin' , '' , self.UCODE_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
||||
('STAGE2.fd' , 'Lz4' , self.STAGE2_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
||||
('FWUPDATE.bin' , 'Lzma' , self.FWUPDATE_SIZE, STITCH_OPS.MODE_FILE_PAD | fwu_flag, STITCH_OPS.MODE_POS_TAIL),
|
||||
('CFGDATA.bin' , '' , self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD | cfg_flag, STITCH_OPS.MODE_POS_TAIL),
|
||||
('KEYHASH.bin' , '' , self.KEYHASH_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
||||
('STAGE1B_A.fd' , '' , self.STAGE1B_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
||||
]
|
||||
),
|
||||
('REDUNDANT_B.bin', [
|
||||
('UCODE.bin' , '' , self.UCODE_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
||||
('STAGE2.fd' , 'Lz4' , self.STAGE2_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
||||
('FWUPDATE.bin' , 'Lzma' , self.FWUPDATE_SIZE, STITCH_OPS.MODE_FILE_PAD | fwu_flag, STITCH_OPS.MODE_POS_TAIL),
|
||||
('CFGDATA.bin' , '' , self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD | cfg_flag, STITCH_OPS.MODE_POS_TAIL),
|
||||
('KEYHASH.bin' , '' , self.KEYHASH_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
||||
('STAGE1B_B.fd' , '' , self.STAGE1B_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
||||
]
|
||||
),
|
||||
('TOP_SWAP_A.bin', [
|
||||
('ACM.bin' , '' , self.ACM_SIZE, STITCH_OPS.MODE_FILE_NOP | acm_flag, STITCH_OPS.MODE_POS_TAIL),
|
||||
('STAGE1A_A.fd' , '' , self.STAGE1A_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
|
||||
]
|
||||
),
|
||||
('TOP_SWAP_B.bin', [
|
||||
('ACM.bin' , '' , self.ACM_SIZE, STITCH_OPS.MODE_FILE_NOP | acm_flag, STITCH_OPS.MODE_POS_TAIL),
|
||||
('STAGE1A_B.fd' , '' , self.STAGE1A_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
|
||||
]
|
||||
),
|
||||
('SlimBootloader.bin', [
|
||||
('NON_VOLATILE.bin' , '' , self.NON_VOLATILE_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
|
||||
('NON_REDUNDANT.bin' , '' , self.NON_REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
|
||||
('REDUNDANT_B.bin' , '' , self.REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
|
||||
('REDUNDANT_A.bin' , '' , self.REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
|
||||
('TOP_SWAP_B.bin' , '' , self.TOP_SWAP_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
|
||||
('TOP_SWAP_A.bin' , '' , self.TOP_SWAP_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
|
||||
]
|
||||
),
|
||||
])
|
||||
|
||||
return img_list
|
||||
@@ -0,0 +1,60 @@
|
||||
## @file
|
||||
#
|
||||
# Slim Bootloader CFGDATA Default File.
|
||||
#
|
||||
# Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
|
||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
#
|
||||
##
|
||||
|
||||
variable:
|
||||
COND_S0IX_DIS : ($FEATURES_CFG_DATA.Features.S0ix == 0)
|
||||
COND_PLD_SEL_EN: ($PLDSEL_CFG_DATA.PldSelGpio.Enable == 1)
|
||||
template:
|
||||
|
||||
- !include Template_CfgData.yaml
|
||||
|
||||
configs:
|
||||
- $ACTION :
|
||||
page : PLT::"Platform", MEM::"Memory Settings", SIL::"Silicon Settings", GEN::"General Settings", GIO::"Gpio Settings", OS::"OS Boot Options", SEC::"Security Settings"
|
||||
- Signature :
|
||||
length : 0x04
|
||||
value : {'CFGD'}
|
||||
- HeaderLength :
|
||||
length : 0x01
|
||||
value : 0x10
|
||||
- Reserved :
|
||||
length : 0x03
|
||||
value : {0,0,0}
|
||||
- UsedLength :
|
||||
length : 0x04
|
||||
value : _LENGTH_
|
||||
- TotalLength :
|
||||
length : 0x04
|
||||
value : 0x2000
|
||||
|
||||
- !include CfgData_Features.yaml
|
||||
|
||||
- !include CfgData_Gpio_Azb.yaml
|
||||
|
||||
- !include Platform/CommonBoardPkg/CfgData/CfgData_Platform.yaml
|
||||
|
||||
- !include Platform/CommonBoardPkg/CfgData/CfgData_Common.yaml
|
||||
|
||||
- !include CfgData_BootOption_Azb.yaml
|
||||
|
||||
- !include CfgData_Memory.yaml
|
||||
|
||||
- !include CfgData_MemSpd_Azb.yaml
|
||||
|
||||
- !include CfgData_Dynamic.yaml
|
||||
|
||||
- !include CfgData_Silicon.yaml
|
||||
|
||||
- !include CfgData_Power.yaml
|
||||
|
||||
- !include CfgData_Security.yaml
|
||||
|
||||
- !include CfgData_PepConstraints.yaml
|
||||
|
||||
- !include CfgData_CapsuleInformation.yaml
|
||||
@@ -0,0 +1,125 @@
|
||||
#/** @file
|
||||
#
|
||||
# Platform Configuration Delta File.
|
||||
#
|
||||
# Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
|
||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
#
|
||||
#
|
||||
#**/
|
||||
|
||||
|
||||
#
|
||||
# Delta configuration values for platform ID 0x0009
|
||||
#
|
||||
|
||||
PLATFORMID_CFG_DATA.PlatformId | 0x0009
|
||||
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_H02 | 0x0100E2A1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H02 | 0x07020001
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPD02 | 0x03148DA1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPD02 | 0x05020601
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_A12 | 0x0100E281
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A12 | 0x020C0001
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_C02 | 0x0500E283
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_C02 | 0x0B020001
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_E00 | 0x03148DA1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E00 | 0x0E000601
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_E03 | 0x03148DE1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E03 | 0x0E030619
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_E07 | 0x05128DA1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E07 | 0x0E070601
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_E22 | 0x05008385
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E22 | 0x0E160001
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_E23 | 0x0500E281
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E23 | 0x0E170001
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_F07 | 0x0500E2A1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F07 | 0x0C070001
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_D06 | 0x00008383
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D06 | 0x08060001
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_D12 | 0x0100E281
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D12 | 0x080C0001
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_D13 | 0x03148DA1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D13 | 0x080D0601
|
||||
PLAT_NAME_CFG_DATA.PlatformName | 'AzbCrb'
|
||||
GEN_CFG_DATA.PayloadId | 'LINX'
|
||||
MEMORY_CFG_DATA.SpdAddressTable | { 0xa8, 0x00, 0xa8, 0x00, 0xa8, 0x00, 0xa8, 0x00, 0xa8, 0x00, 0xa8, 0x00, 0xa8, 0x00, 0xa8, 0x00 }
|
||||
MEMORY_CFG_DATA.SpdDataSel000 | 0x0
|
||||
MEMORY_CFG_DATA.SpdDataSel010 | 0x0
|
||||
MEMORY_CFG_DATA.SpdDataSel020 | 0x0
|
||||
MEMORY_CFG_DATA.SpdDataSel030 | 0x0
|
||||
MEMORY_CFG_DATA.SpdDataSel100 | 0x0
|
||||
MEMORY_CFG_DATA.SpdDataSel101 | 0x0
|
||||
MEMORY_CFG_DATA.SpdDataSel110 | 0x0
|
||||
MEMORY_CFG_DATA.SpdDataSel120 | 0x0
|
||||
MEMORY_CFG_DATA.SpdDataSel130 | 0x0
|
||||
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch0 | { 0x04, 0x01, 0x07, 0x06, 0x00, 0x02, 0x05, 0x03, 0x08, 0x0f, 0x0e, 0x09, 0x0a, 0x0d, 0x0c, 0x0b }
|
||||
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch1 | { 0x00, 0x05, 0x02, 0x07, 0x04, 0x03, 0x01, 0x06, 0x0c, 0x0a, 0x0d, 0x08, 0x0f, 0x0b, 0x0e, 0x09 }
|
||||
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch2 | { 0x01, 0x03, 0x02, 0x00, 0x07, 0x04, 0x06, 0x05, 0x0c, 0x09, 0x0a, 0x08, 0x0d, 0x0b, 0x0e, 0x0f }
|
||||
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch3 | { 0x0f, 0x0c, 0x0b, 0x0a, 0x0e, 0x08, 0x09, 0x0d, 0x07, 0x03, 0x06, 0x00, 0x04, 0x01, 0x05, 0x02 }
|
||||
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch0 | { 0x04, 0x01, 0x07, 0x06, 0x00, 0x02, 0x05, 0x03, 0x08, 0x0f, 0x0e, 0x09, 0x0a, 0x0d, 0x0c, 0x0b }
|
||||
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch1 | { 0x00, 0x05, 0x02, 0x07, 0x04, 0x03, 0x01, 0x06, 0x0c, 0x0a, 0x0d, 0x08, 0x0f, 0x0b, 0x0e, 0x09 }
|
||||
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch2 | { 0x01, 0x03, 0x02, 0x00, 0x07, 0x04, 0x06, 0x05, 0x0c, 0x09, 0x0a, 0x08, 0x0d, 0x0b, 0x0e, 0x0f }
|
||||
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch3 | { 0x0f, 0x0c, 0x0b, 0x0a, 0x0e, 0x08, 0x09, 0x0d, 0x07, 0x03, 0x06, 0x00, 0x04, 0x01, 0x05, 0x02 }
|
||||
MEMORY_CFG_DATA.DqsMapCpu2DramMc1Ch3 | { 1, 0}
|
||||
MEMORY_CFG_DATA.DqsMapCpu2DramMc0Ch3 | { 1, 0}
|
||||
MEMORY_CFG_DATA.DqPinsInterleaved | 0x0
|
||||
MEMORY_CFG_DATA.PlatformMemorySize | 0x8391000
|
||||
MEMORY_CFG_DATA.BootFrequency | 0x02
|
||||
MEMORY_CFG_DATA.ActiveCoreCount | 0x00
|
||||
MEMORY_CFG_DATA.SinitMemorySize | 0x0
|
||||
MEMORY_CFG_DATA.TxtHeapMemorySize | 0x0
|
||||
MEMORY_CFG_DATA.BiosAcmBase | 0xFFA40000
|
||||
MEMORY_CFG_DATA.PcieRpEnableMask | 0xFFFFFF
|
||||
MEMORY_CFG_DATA.PcieClkSrcUsage | { 0x04, 0x05, 0x06, 0x07, 0xff, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
|
||||
MEMORY_CFG_DATA.PcieClkSrcClkReq | { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0xff, 0xff }
|
||||
MEMORY_CFG_DATA.CpuPcieRpEnableMask | 0x1
|
||||
MEMORY_CFG_DATA.IpuLaneUsed | { 0x04, 0x01, 0x02, 0x04, 0x04, 0x04, 0x00, 0x00 }
|
||||
MEMORY_CFG_DATA.CsiSpeed | { 0x02, 0x01, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00 }
|
||||
MEMORY_CFG_DATA.CpuDmiHwEqGen3CoeffListCm | { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
||||
MEMORY_CFG_DATA.CpuDmiHwEqGen3CoeffListCp | { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
||||
MEMORY_CFG_DATA.CpuDmiHwEqGen4CoeffListCm | { 0x00, 0x0e, 0x0a, 0x07, 0x07, 0x07, 0x07, 0x07 }
|
||||
MEMORY_CFG_DATA.CpuDmiHwEqGen4CoeffListCp | { 0x00, 0x07, 0x06, 0x07, 0x07, 0x07, 0x07, 0x07 }
|
||||
MEMORY_CFG_DATA.TcssItbtPcie0En | 0x1
|
||||
MEMORY_CFG_DATA.TcssItbtPcie1En | 0x1
|
||||
MEMORY_CFG_DATA.TcssItbtPcie2En | 0x1
|
||||
MEMORY_CFG_DATA.TcssItbtPcie3En | 0x1
|
||||
MEMORY_CFG_DATA.TcssXhciEn | 0x1
|
||||
MEMORY_CFG_DATA.TcssDma0En | 0x1
|
||||
MEMORY_CFG_DATA.TcssDma1En | 0x1
|
||||
MEMORY_CFG_DATA.UsbTcPortEnPreMem | 0x3
|
||||
MEMORY_CFG_DATA.UserBd | 0x0
|
||||
MEMORY_CFG_DATA.EnableC6Dram | 0x00
|
||||
MEMORY_CFG_DATA.BdatEnable | 0x0
|
||||
MEMORY_CFG_DATA.BiosSize | 0x4000
|
||||
SILICON_CFG_DATA.EnableItbm | 0x01
|
||||
SILICON_CFG_DATA.PchDmiAspmCtrl | 0x04
|
||||
SILICON_CFG_DATA.CpuPcieRpAspm | { 0x00, 0x02, 0x02, 0x00 }
|
||||
SILICON_CFG_DATA.CpuPcieRpPtmEnabled | { 0x01, 0x01, 0x01, 0x00 }
|
||||
SILICON_CFG_DATA.SataLedEnable | 0x00
|
||||
SILICON_CFG_DATA.SataPortsDevSlp | { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
||||
SILICON_CFG_DATA.PortUsb30Enable | { 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
||||
SILICON_CFG_DATA.Usb2OverCurrentPin | { 0x04, 0x05, 0xff, 0xff, 0x02, 0x02, 0xff, 0xff, 0xff, 0xff, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07 }
|
||||
SILICON_CFG_DATA.Usb3OverCurrentPin | { 0x02, 0x02, 0xff, 0xff, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04 }
|
||||
SILICON_CFG_DATA.Usb2PhyPetxiset | { 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
||||
SILICON_CFG_DATA.Usb2PhyPredeemp | { 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
||||
SILICON_CFG_DATA.SerialIoUartMode | { 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
||||
SILICON_CFG_DATA.SerialIoUartAutoFlow | { 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 }
|
||||
SILICON_CFG_DATA.SerialIoI2cMode | { 0x01, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00 }
|
||||
SILICON_CFG_DATA.CpuUsb3OverCurrentPin | { 0x04, 0x05, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }
|
||||
SILICON_CFG_DATA.PchIshI2cEnable | { 0x01, 0x01, 0x00 }
|
||||
SILICON_CFG_DATA.PchIshGpEnable | { 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01 }
|
||||
SILICON_CFG_DATA.PcieRpAspm | { 0x04, 0x00, 0x04, 0x00, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x04, 0x04, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 }
|
||||
SILICON_CFG_DATA.PtmEnabled | { 0x01, 0x01, 0x01, 0x01 }
|
||||
SILICON_CFG_DATA.CpuPcieRpMultiVcEnabled | { 0x01, 0x00, 0x00, 0x00 }
|
||||
POWER_CFG_DATA.TccActivationOffset | 0x0A
|
||||
POWER_CFG_DATA.TurboMode | 0x00
|
||||
POWER_CFG_DATA.EnergyEfficientTurbo | 0x01
|
||||
POWER_CFG_DATA.MaxRatio | 0x04
|
||||
POWER_CFG_DATA.PsysPmax | 0x0
|
||||
POWER_CFG_DATA.ImonSlope | { 0x00, 0x00, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
||||
POWER_CFG_DATA.TdcEnable | { 0x01, 0x01, 0x01, 0x00, 0x00 }
|
||||
PEP_CFG_DATA.PepPcieDg | 0x1
|
||||
PEP_CFG_DATA.PepUfs0 | 0x1
|
||||
PEP_CFG_DATA.PepUfs1 | 0x1
|
||||
CAPSULE_INFO_CFG_DATA.DevInstance | 0x1
|
||||
@@ -0,0 +1,20 @@
|
||||
## @file
|
||||
#
|
||||
# Slim Bootloader CFGDATA Option File.
|
||||
#
|
||||
# Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
|
||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
#
|
||||
##
|
||||
|
||||
|
||||
- $ACTION :
|
||||
page : OS
|
||||
# usb
|
||||
- !expand { BOOT_OPTION_TMPL : [ 0 , 0 , 0 , 5 , 0 , 0xFF , 1 , 1 , '/boot/sbl_os' ] }
|
||||
- !expand { BOOT_OPTION_TMPL : [ 1 , 0 , 0 , 5 , 1 , 0xFF , 1 , 1 , '/boot/sbl_os' ] }
|
||||
# nvme
|
||||
- !expand { BOOT_OPTION_TMPL : [ 2 , 0 , 0 , 6 , 0 , 0x0 , 1 , 1 , '/boot/sbl_os' ] }
|
||||
- !expand { BOOT_OPTION_TMPL : [ 3 , 0 , 0 , 6 , 1 , 0x0 , 1 , 1 , '/boot/sbl_os' ] }
|
||||
# ufs
|
||||
- !expand { BOOT_OPTION_TMPL : [ 4 , 0 , 0 , 3 , 1 , 0x0 , 1 , 1 , '/boot/sbl_os' ] }
|
||||
@@ -0,0 +1,270 @@
|
||||
## @file
|
||||
#
|
||||
# Slim Bootloader CFGDATA Option File.
|
||||
#
|
||||
# Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
|
||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
#
|
||||
##
|
||||
|
||||
|
||||
- $ACTION :
|
||||
page : GIO
|
||||
- GPIO_CFG_DATA :
|
||||
- !expand { CFGHDR_TMPL : [ GPIO_CFG_DATA, 0x400, 1, 0 ] }
|
||||
- GPIO_CFG_HDR :
|
||||
- GpioHeaderSize :
|
||||
length : 0x01
|
||||
value : _LENGTH_GPIO_CFG_HDR_
|
||||
- GpioBaseTableId :
|
||||
length : 0x01
|
||||
value : 0xFF
|
||||
- GpioItemSize :
|
||||
length : 0x02
|
||||
value : 8
|
||||
- GpioItemCount :
|
||||
length : 0x02
|
||||
value : (_LENGTH_GPIO_CFG_DATA_ - _LENGTH_GPIO_CFG_HDR_ - 8) / 8
|
||||
# Bit start offset within each GPIO entry array to identify a GPIO pin uniquely. EX: GPIO group id + pad id
|
||||
# Offset is 2nd DWORD BIT16 = 1 * 32 + 16 = 48
|
||||
- GpioItemIdBitOff :
|
||||
length : 0x01
|
||||
value : 48
|
||||
# Bit length within each GPIO entry array to identify a GPIO pin uniquely.
|
||||
# Length is 2nd DWORD BIT16 to BIT28 = 13
|
||||
- GpioItemIdBitLen :
|
||||
length : 0x01
|
||||
value : 13
|
||||
# Bit offset within each GPIO entry array to indicate SKIP a GPIO programming
|
||||
# Offset is 2nd DWORD BIT31 = 63
|
||||
- GpioItemValidBitOff :
|
||||
length : 0x01
|
||||
value : 63
|
||||
- GpioItemUnused :
|
||||
length : 0x01
|
||||
value : 0
|
||||
# Need 1 bit per GPIO. So this mask byte length needs to be at least (GpioNumber + 7) / 8
|
||||
# Padding can be added to let the whole length aligned at DWORD boundary
|
||||
- GpioBaseTableBitMask :
|
||||
length : 38
|
||||
value : {0}
|
||||
- GpioTableData :
|
||||
length : 0
|
||||
value : 0
|
||||
# The GrpIdx of GpioPinConfig1 is based on mPchLpGpioGroupInfo in GpioSiLib.c
|
||||
# Refer to PadGroup options in CfgData_PayloadSelection_Azb.yaml
|
||||
- !expand { GPIO_TMPL : [ GPP_R00, 0x0350A383, 0x83002019 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R01, 0x0350A383, 0x83012019 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R02, 0x0350A383, 0x83022019 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R03, 0x0350A383, 0x83032019 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R04, 0x0350A383, 0x83042019 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R05, 0x0350A383, 0x83052009 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R06, 0x0350A383, 0x83062001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R07, 0x0350A381, 0x83072001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R08, 0x0350A385, 0x83082001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R09, 0x0350A385, 0x83092001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R10, 0x0550A581, 0x830A2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R11, 0x0550E281, 0x830B2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R12, 0x0350A383, 0x830C2019 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R13, 0x0350E281, 0x830D2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R14, 0x0550A281, 0x830E2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R15, 0x0350A381, 0x830F2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R16, 0x0350A383, 0x83102001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R17, 0x0350A381, 0x83112001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R18, 0x0350A383, 0x83122001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R19, 0x0350A381, 0x83132001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R20, 0x0350A381, 0x83142001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_R21, 0x0350A381, 0x83152001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B00, 0x0550E281, 0x80002001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B01, 0x0550E281, 0x80012001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B02, 0x00348DA1, 0x80022601 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B03, 0x000062E1, 0x80032601 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B04, 0x0350A383, 0x80042001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B05, 0x0350A383, 0x80052001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B06, 0x0350A383, 0x80062001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B07, 0x0350A383, 0x80072001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B08, 0x0350A383, 0x80082001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B09, 0x0350A383, 0x80092001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B10, 0x0350A383, 0x800A2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B11, 0x0350A383, 0x800B2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B12, 0x0550E281, 0x800C2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B13, 0x0550E281, 0x800D2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B14, 0x0550E281, 0x800E2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B15, 0x0550E281, 0x800F2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B16, 0x0350A383, 0x80102001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B17, 0x0350A283, 0x80112001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B18, 0x0350A383, 0x80122001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B19, 0x0314AD83, 0x80132601 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B20, 0x0350A383, 0x80142001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B21, 0x0350A383, 0x80152001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B22, 0x0350A383, 0x80162001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_B23, 0x0350A281, 0x80172001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H00, 0x0350A383, 0x87002001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H01, 0x0350A383, 0x87012001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H02, 0x0550E281, 0x87022001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H03, 0x0350A383, 0x87032001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H04, 0x0350A383, 0x87042001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H05, 0x0550E281, 0x87052001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H06, 0x0150A383, 0x87062001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H07, 0x0150A383, 0x87072001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H08, 0x0538AD81, 0x87082001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H09, 0x0350A381, 0x87092001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H10, 0x0150A281, 0x870A2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H11, 0x0150A281, 0x870B2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H12, 0x0518AD81, 0x870C2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H13, 0x0550E281, 0x870D2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H14, 0x0314AD81, 0x870E2601 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H15, 0x0550E281, 0x870F2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H16, 0x0350A383, 0x87102001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H17, 0x0350A383, 0x87112001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H18, 0x0350A383, 0x87122001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H19, 0x0350A383, 0x87132001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H20, 0x0350A381, 0x87142001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H21, 0x0350A381, 0x87152001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H22, 0x0350E281, 0x87162001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_H23, 0x0314AD81, 0x87172601 ] }
|
||||
- !expand { GPIO_TMPL : [ GPD00, 0x0750A383, 0x85002019 ] }
|
||||
- !expand { GPIO_TMPL : [ GPD01, 0x0750A383, 0x8501201F ] }
|
||||
- !expand { GPIO_TMPL : [ GPD02, 0x0750A383, 0x8502201F ] }
|
||||
- !expand { GPIO_TMPL : [ GPD03, 0x0750A383, 0x85032019 ] }
|
||||
- !expand { GPIO_TMPL : [ GPD04, 0x0750A283, 0x85042001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPD05, 0x0750A283, 0x85052001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPD06, 0x0750A283, 0x85062001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPD07, 0x0750E281, 0x85072001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPD08, 0x0750A383, 0x85082001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPD09, 0x0750A283, 0x85092001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPD10, 0x0750A283, 0x850A2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPD11, 0x0750A283, 0x850B2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPD12, 0x0750A283, 0x850C2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A00, 0x0350A383, 0x82002001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A01, 0x0350A383, 0x82012019 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A02, 0x0350A383, 0x82022001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A03, 0x0350A383, 0x82032019 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A04, 0x0350A383, 0x82040000 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A05, 0x0350A383, 0x82052019 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A06, 0x0350A383, 0x82062001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A07, 0x0350A383, 0x82072001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A08, 0x0350A381, 0x82082001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A09, 0x0550E281, 0x82092001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A10, 0x0550E281, 0x820A2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A11, 0x0350A381, 0x820B2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A12, 0x0350A381, 0x820C2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A13, 0x0350A381, 0x820D2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A14, 0x0350A381, 0x820E2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A15, 0x0350A381, 0x820F2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A16, 0x0350A381, 0x82102001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A17, 0x0350A381, 0x82112001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A18, 0x0350A381, 0x82122001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A19, 0x0350A381, 0x82132001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A20, 0x0350A381, 0x82142001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A21, 0x0350A381, 0x82152001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A22, 0x0350A381, 0x82162001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_A23, 0x0350A381, 0x82172001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C00, 0x0350A383, 0x8B002001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C01, 0x0350A383, 0x8B012001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C02, 0x0550E281, 0x8B022001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C03, 0x0350A383, 0x8B032001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C04, 0x0350A383, 0x8B042001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C05, 0x0550E281, 0x8B052001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C06, 0x0150A383, 0x8B062001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C07, 0x0150A383, 0x8B072001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C08, 0x0538AD81, 0x8B082001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C09, 0x0350A381, 0x8B092001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C10, 0x0150A281, 0x8B0A2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C11, 0x0150A281, 0x8B0B2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C12, 0x0518AD81, 0x8B0C2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C13, 0x0550E281, 0x8B0D2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C14, 0x0314AD81, 0x8B0E2601 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C15, 0x0550E281, 0x8B0F2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C16, 0x0350A383, 0x8B102001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C17, 0x0350A383, 0x8B112001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C18, 0x0350A383, 0x8B122001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C19, 0x0350A383, 0x8B132001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C20, 0x0350A381, 0x8B142001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C21, 0x0350A381, 0x8B152001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C22, 0x0350E281, 0x8B162001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_C23, 0x0314AD81, 0x8B172601 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_S00, 0x0350A383, 0x86002001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_S01, 0x0350A383, 0x8601201F ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_S02, 0x0350A283, 0x8602201F ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_S03, 0x0350A383, 0x8603201F ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_S04, 0x0350A383, 0x86042001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_S05, 0x0550A281, 0x86052001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_S06, 0x0550E281, 0x86062001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_S07, 0x0350A381, 0x86072001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E00, 0x0350A381, 0x8E002001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E01, 0x0350A381, 0x8E012001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E02, 0x0350A381, 0x8E022001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E03, 0x0518A581, 0x8E032001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E04, 0x0150A383, 0x8E042001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E05, 0x0150A383, 0x8E052001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E06, 0x0550E281, 0x8E062001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E07, 0x0512AD81, 0x8E072001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E08, 0x0550E281, 0x8E082001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E09, 0x0350A383, 0x8E092001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E10, 0x0350A381, 0x8E0A2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E11, 0x0350A381, 0x8E0B2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E12, 0x0350A381, 0x8E0C2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E13, 0x0350A381, 0x8E0D2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E14, 0x0350A383, 0x8E0E2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E15, 0x0350A383, 0x8E0F2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E16, 0x0350A385, 0x8E102001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E17, 0x0538AD81, 0x8E112001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E18, 0x0350A38B, 0x8E12201F ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E19, 0x0350A28B, 0x8E13201F ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E20, 0x0350A38B, 0x8E14201F ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E21, 0x0350A28B, 0x8E15201F ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E22, 0x0350A28B, 0x8E16201F ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_E23, 0x0350A28B, 0x8E17201F ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F00, 0x0350A383, 0x8C002001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F01, 0x0350A383, 0x8C012019 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F02, 0x0350A383, 0x8C022001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F03, 0x0350A383, 0x8C032019 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F04, 0x0314AD81, 0x8C042601 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F05, 0x0314AD81, 0x8C052601 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F06, 0x0350A381, 0x8C062001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F07, 0x0550E281, 0x8C072001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F08, 0x0550E281, 0x8C082001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F09, 0x0550E281, 0x8C092001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F10, 0x0550E281, 0x8C0A2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F11, 0x0350A381, 0x8C0B2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F12, 0x0350A381, 0x8C0C2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F13, 0x0350A381, 0x8C0D2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F14, 0x0350A381, 0x8C0E2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F15, 0x0350A381, 0x8C0F2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F16, 0x0350A381, 0x8C102001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F17, 0x0550E283, 0x8C112001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F18, 0x05002483, 0x8C122001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F19, 0x0350A383, 0x8C132001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F20, 0x0550A281, 0x8C142001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F21, 0x0550A581, 0x8C152001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F22, 0x0350A381, 0x8C162001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_F23, 0x0350A381, 0x8C172001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D00, 0x0350A383, 0x88002001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D01, 0x0350A383, 0x88012001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D02, 0x0350A383, 0x88022001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D03, 0x0350A383, 0x88032001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D04, 0x0350A383, 0x88042001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D05, 0x0350A383, 0x88052001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D06, 0x0350A383, 0x88062001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D07, 0x0350A383, 0x88072001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D08, 0x0350A383, 0x88082001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D09, 0x0350A38B, 0x8809201F ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D10, 0x0350A28B, 0x880A201F ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D11, 0x0350A38B, 0x880B201F ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D12, 0x0350A28B, 0x880C201F ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D13, 0x0350A381, 0x880D2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D14, 0x0350A381, 0x880E2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D15, 0x0350A381, 0x880F2001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D16, 0x0550E281, 0x88102001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D17, 0x0350A383, 0x88112001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D18, 0x0350A383, 0x88122001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D19, 0x0350A381, 0x88132001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D20, 0x0550E281, 0x88142001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D21, 0x0350A383, 0x88152001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D22, 0x0350A383, 0x88162001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_D23, 0x0350A381, 0x88172001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_T00, 0x0350A387, 0x81002001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_T01, 0x0350A387, 0x81012001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_T02, 0x0350A387, 0x81022001 ] }
|
||||
- !expand { GPIO_TMPL : [ GPP_T03, 0x0350A387, 0x81032001 ] }
|
||||
@@ -0,0 +1,26 @@
|
||||
## @file
|
||||
#
|
||||
# Slim Bootloader CFGDATA Option File.
|
||||
#
|
||||
# Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
|
||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
#
|
||||
##
|
||||
|
||||
|
||||
- $ACTION :
|
||||
page : MEM_SPD:MEM:"MEM SPD"
|
||||
- $ACTION :
|
||||
page : MEM_SPD
|
||||
- MEM_SPD0_CFG_DATA :
|
||||
- !expand { CFGHDR_TMPL : [ MEM_SPD0_CFG_DATA, 0x8F0, 0, 0 ] }
|
||||
- MemorySpdPtr0 :
|
||||
name : Memory SPD Data 0
|
||||
type : Table
|
||||
option : >
|
||||
0:1:HEX, 1:1:HEX, 2:1:HEX, 3:1:HEX, 4:1:HEX, 5:1:HEX, 6:1:HEX, 7:1:HEX,
|
||||
8:1:HEX, 9:1:HEX, A:1:HEX, B:1:HEX, C:1:HEX, D:1:HEX, E:1:HEX, F:1:HEX
|
||||
help : >
|
||||
Pointer to SPD data in Memory
|
||||
length : 0x200
|
||||
value : {FILE: Spd_Data_Azb_LPDDR5_DR.bin}
|
||||
@@ -334,12 +334,12 @@
|
||||
- ActiveSmallCoreCount :
|
||||
name : Number of active small cores
|
||||
type : Combo
|
||||
option : 0x0:Disable all small cores, 0x1:1, 0x2:2, 0x3:3, 0xff:Active all small cores
|
||||
option : 0x0:Disable all small cores, 0x1:1, 0x2:2, 0x3:3, 0x4:4, 0x8:8, 0xff:Active all small cores
|
||||
help : >
|
||||
Number of active small cores(Depends on Number of small cores). Default 0xFF means to active all system supported small cores. <b>0xFF- Active all small cores</b>; 0- Disable all small cores; 1- 1; 2- 2; 3- 3;
|
||||
Number of active small cores(Depends on Number of small cores). Default 0xFF means to active all system supported small cores. <b>0xFF- Active all small cores</b>; 0- Disable all small cores; 1- 1; 2- 2; 3- 3; 4- 4;
|
||||
length : 0x0001
|
||||
value : 0xff
|
||||
- BiosSize :
|
||||
- BiosSize :
|
||||
name : BiosSize
|
||||
type : EditNum, HEX, (0x0, 0xFFFF)
|
||||
help : >
|
||||
@@ -617,7 +617,7 @@
|
||||
value : {0x04, 0x04, 0x04, 0x04, 0x02, 0x01, 0x04, 0x04}
|
||||
- CsiSpeed :
|
||||
name : Speed of each CSI port
|
||||
type : EditNum, HEX, (0x00,0xFFFF)
|
||||
type : EditNum, HEX, (0x0, 0xFFFF)
|
||||
option : 0x0:Sensor default, 0x1:<416Mbps, 0x2:<1.5Gbps, 0x3:<2Gbps, 0x4:<2.5Gbps, 0x5:<4Gbps, 0x6:>4Gbps
|
||||
help : >
|
||||
Speed of each CSI port
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@@ -2,7 +2,7 @@
|
||||
#
|
||||
# Slim Bootloader CFGDATA Template File.
|
||||
#
|
||||
# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
|
||||
# Copyright (c) 2020 - 2023, Intel Corporation. All rights reserved.<BR>
|
||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
#
|
||||
##
|
||||
@@ -12,7 +12,7 @@ SPD_TMPL: >
|
||||
- SpdDataSel$(1)$(2)$(3) :
|
||||
name : Spd Data MC$(1) CH$(2) DIMM$(3)
|
||||
type : Combo
|
||||
option : 0:NONE, 1:SPD0, 2:SPD1, 3:SPD2, 4:SPD3
|
||||
option : 0:NONE, 1:SPD0, 2:SPD1, 3:SPD2, 4:SPD3, 5:SPD4, 6:SPD5, 7:SPD6, 8:SPD7
|
||||
help : >
|
||||
Select which SPD data should be used for MC$(1) CH$(2) DIMM$(3).SPD0 and SPD1 are associated with configurable SPD data block from MEM SPD. SPD data will be used only when SpdAddressTable SPD Address are marked as 00
|
||||
length : 0x01
|
||||
|
||||
@@ -54,6 +54,10 @@ Defines Platform BoardIds
|
||||
#define BoardIdAdlSAdpSDdr5SODimmCrb 0x30
|
||||
#define PLATFORM_ID_ADL_S_ADP_S_DDR5_SODIMM_CRB 0x1C
|
||||
|
||||
// ArizonaBeach Boards
|
||||
#define BoardIdAzbLp5Crb2A 0x22
|
||||
#define PLATFORM_ID_AZB_LP5_CRB2A 0x09
|
||||
|
||||
// Test boards
|
||||
#define BoardIdTestSDdr5UDimm1DRvp 0x39
|
||||
#define PLATFORM_ID_TEST_S_DDR5_UDIMM_RVP 0x19
|
||||
|
||||
@@ -51,4 +51,4 @@
|
||||
|
||||
[FixedPcd]
|
||||
gPlatformCommonLibTokenSpaceGuid.PcdTccEnabled
|
||||
gPlatformModuleTokenSpaceGuid.PcdFusaSupport
|
||||
gPlatformModuleTokenSpaceGuid.PcdFusaSupport
|
||||
|
||||
@@ -0,0 +1,397 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
**/
|
||||
|
||||
#include <PiPei.h>
|
||||
#include <Uefi/UefiBaseType.h>
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <FspmUpd.h>
|
||||
#include <PlatformBoardId.h>
|
||||
#include <Include/PlatformData.h>
|
||||
#include <PlatformBase.h>
|
||||
#include <ConfigDataDefs.h>
|
||||
#include <Library/PchInfoLib.h>
|
||||
#include <Library/WatchDogTimerLib.h>
|
||||
#include <Include/CpuRegs.h>
|
||||
#include <Register/Cpuid.h>
|
||||
#include <Library/ConfigDataLib.h>
|
||||
#include <ConfigDataCommonStruct.h>
|
||||
#include <Library/ContainerLib.h>
|
||||
#include <Library/BaseMemoryLib.h>
|
||||
#include <GpioPinsVer2Lp.h>
|
||||
|
||||
#include "BoardSaConfigPreMem.h"
|
||||
|
||||
typedef enum {
|
||||
DciDbcDisabled = 0x0,
|
||||
DciDbcUsb2 = 0x1,
|
||||
DciDbcUsb3 = 0x2,
|
||||
DciDbcBoth = 0x3,
|
||||
DciDbcNoChange = 0x4,
|
||||
DciDbcMax
|
||||
} DCI_DBC_MODE;
|
||||
|
||||
|
||||
/**
|
||||
Update FSP-M UPD config data.
|
||||
|
||||
@param FspmUpdPtr The pointer to the FSP-M UPD to be updated.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
UpdateFspConfig (
|
||||
IN VOID *FspmUpdPtr
|
||||
)
|
||||
{
|
||||
FSPM_UPD *FspmUpd;
|
||||
FSP_M_CONFIG *Fspmcfg;
|
||||
MEMORY_CFG_DATA *MemCfgData;
|
||||
PLATFORM_DATA *PlatformData;
|
||||
FEATURES_CFG_DATA *FeaturesCfgData;
|
||||
SILICON_CFG_DATA *SiCfgData;
|
||||
UINT16 PlatformId;
|
||||
UINT8 SaDisplayConfigTable[16] = { 0 };
|
||||
UINT8 Index;
|
||||
UINT8 DebugPort;
|
||||
UINT32 SpdData[9];
|
||||
UINT32 CarBase;
|
||||
UINT32 CarSize;
|
||||
EFI_STATUS Status;
|
||||
|
||||
FspmUpd = (FSPM_UPD *)FspmUpdPtr;
|
||||
Fspmcfg = &FspmUpd->FspmConfig;
|
||||
|
||||
Status = GetTempRamInfo (&CarBase, &CarSize);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
FspmUpd->FspmArchUpd.StackBase = CarBase \
|
||||
+ FixedPcdGet32 (PcdStage1StackBaseOffset) \
|
||||
+ FixedPcdGet32 (PcdStage1StackSize) \
|
||||
+ FixedPcdGet32 (PcdStage1DataSize);
|
||||
FspmUpd->FspmArchUpd.StackSize = CarBase + CarSize - FspmUpd->FspmArchUpd.StackBase;
|
||||
DEBUG ((DEBUG_INFO, "CAR Base 0x%X (0x%X)\n", CarBase, CarSize));
|
||||
DEBUG ((DEBUG_INFO, "FSPM Stack Base=0x%X, Size=0x%X\n", FspmUpd->FspmArchUpd.StackBase, FspmUpd->FspmArchUpd.StackSize));
|
||||
|
||||
DEBUG ((DEBUG_INFO, "FSPM CfgData assignment\n"));
|
||||
MemCfgData = (MEMORY_CFG_DATA *)FindConfigDataByTag (CDATA_MEMORY_TAG);
|
||||
if (MemCfgData == NULL) {
|
||||
CpuHalt ("Failed to find memory CFGDATA!");
|
||||
return;
|
||||
}
|
||||
CopyMem (&Fspmcfg->SpdAddressTable, MemCfgData->SpdAddressTable, sizeof(MemCfgData->SpdAddressTable));
|
||||
|
||||
DebugPort = GetDebugPort ();
|
||||
if (DebugPort < GetPchMaxSerialIoUartControllersNum ()) {
|
||||
Fspmcfg->PcdDebugInterfaceFlags = BIT4 | BIT5;
|
||||
Fspmcfg->SerialIoUartDebugControllerNumber = DebugPort;
|
||||
Fspmcfg->SerialIoUartDebugMode = 4;
|
||||
} else {
|
||||
Fspmcfg->PcdDebugInterfaceFlags = BIT1;
|
||||
if (DebugPort == 0xFF) {
|
||||
Fspmcfg->PcdIsaSerialUartBase = 0;
|
||||
} else {
|
||||
Fspmcfg->PcdIsaSerialUartBase = 1;
|
||||
}
|
||||
}
|
||||
Fspmcfg->PcdSerialDebugLevel = 0x5;
|
||||
|
||||
// Memory SPD Data
|
||||
SpdData[0] = 0;
|
||||
SpdData[1] = (UINT32)(UINTN) (((MEM_SPD0_CFG_DATA *)FindConfigDataByTag (CDATA_MEM_SPD0_TAG))->MemorySpdPtr0);
|
||||
|
||||
Fspmcfg->MemorySpdPtr000 = SpdData[MemCfgData->SpdDataSel000];
|
||||
Fspmcfg->MemorySpdPtr001 = SpdData[MemCfgData->SpdDataSel001];
|
||||
Fspmcfg->MemorySpdPtr010 = SpdData[MemCfgData->SpdDataSel010];
|
||||
Fspmcfg->MemorySpdPtr011 = SpdData[MemCfgData->SpdDataSel011];
|
||||
Fspmcfg->MemorySpdPtr020 = SpdData[MemCfgData->SpdDataSel020];
|
||||
Fspmcfg->MemorySpdPtr021 = SpdData[MemCfgData->SpdDataSel021];
|
||||
Fspmcfg->MemorySpdPtr030 = SpdData[MemCfgData->SpdDataSel030];
|
||||
Fspmcfg->MemorySpdPtr031 = SpdData[MemCfgData->SpdDataSel031];
|
||||
Fspmcfg->MemorySpdPtr100 = SpdData[MemCfgData->SpdDataSel100];
|
||||
Fspmcfg->MemorySpdPtr101 = SpdData[MemCfgData->SpdDataSel101];
|
||||
Fspmcfg->MemorySpdPtr110 = SpdData[MemCfgData->SpdDataSel110];
|
||||
Fspmcfg->MemorySpdPtr111 = SpdData[MemCfgData->SpdDataSel111];
|
||||
Fspmcfg->MemorySpdPtr120 = SpdData[MemCfgData->SpdDataSel120];
|
||||
Fspmcfg->MemorySpdPtr121 = SpdData[MemCfgData->SpdDataSel121];
|
||||
Fspmcfg->MemorySpdPtr130 = SpdData[MemCfgData->SpdDataSel130];
|
||||
Fspmcfg->MemorySpdPtr131 = SpdData[MemCfgData->SpdDataSel131];
|
||||
|
||||
//Dq/Dqs Mapping arrays
|
||||
CopyMem (&Fspmcfg->DqsMapCpu2DramMc0Ch0, MemCfgData->DqsMapCpu2DramMc0Ch0, sizeof(MemCfgData->DqsMapCpu2DramMc0Ch0));
|
||||
CopyMem (&Fspmcfg->DqsMapCpu2DramMc0Ch1, MemCfgData->DqsMapCpu2DramMc0Ch1, sizeof(MemCfgData->DqsMapCpu2DramMc0Ch1));
|
||||
CopyMem (&Fspmcfg->DqsMapCpu2DramMc0Ch2, MemCfgData->DqsMapCpu2DramMc0Ch2, sizeof(MemCfgData->DqsMapCpu2DramMc0Ch2));
|
||||
CopyMem (&Fspmcfg->DqsMapCpu2DramMc0Ch3, MemCfgData->DqsMapCpu2DramMc0Ch3, sizeof(MemCfgData->DqsMapCpu2DramMc0Ch3));
|
||||
CopyMem (&Fspmcfg->DqsMapCpu2DramMc1Ch0, MemCfgData->DqsMapCpu2DramMc1Ch0, sizeof(MemCfgData->DqsMapCpu2DramMc1Ch0));
|
||||
CopyMem (&Fspmcfg->DqsMapCpu2DramMc1Ch1, MemCfgData->DqsMapCpu2DramMc1Ch1, sizeof(MemCfgData->DqsMapCpu2DramMc1Ch1));
|
||||
CopyMem (&Fspmcfg->DqsMapCpu2DramMc1Ch2, MemCfgData->DqsMapCpu2DramMc1Ch2, sizeof(MemCfgData->DqsMapCpu2DramMc1Ch2));
|
||||
CopyMem (&Fspmcfg->DqsMapCpu2DramMc1Ch3, MemCfgData->DqsMapCpu2DramMc1Ch3, sizeof(MemCfgData->DqsMapCpu2DramMc1Ch3));
|
||||
|
||||
CopyMem (&Fspmcfg->DqMapCpu2DramMc0Ch0, MemCfgData->DqMapCpu2DramMc0Ch0, sizeof(MemCfgData->DqMapCpu2DramMc0Ch0));
|
||||
CopyMem (&Fspmcfg->DqMapCpu2DramMc0Ch1, MemCfgData->DqMapCpu2DramMc0Ch1, sizeof(MemCfgData->DqMapCpu2DramMc0Ch1));
|
||||
CopyMem (&Fspmcfg->DqMapCpu2DramMc0Ch2, MemCfgData->DqMapCpu2DramMc0Ch2, sizeof(MemCfgData->DqMapCpu2DramMc0Ch2));
|
||||
CopyMem (&Fspmcfg->DqMapCpu2DramMc0Ch3, MemCfgData->DqMapCpu2DramMc0Ch3, sizeof(MemCfgData->DqMapCpu2DramMc0Ch3));
|
||||
CopyMem (&Fspmcfg->DqMapCpu2DramMc1Ch0, MemCfgData->DqMapCpu2DramMc1Ch0, sizeof(MemCfgData->DqMapCpu2DramMc1Ch0));
|
||||
CopyMem (&Fspmcfg->DqMapCpu2DramMc1Ch1, MemCfgData->DqMapCpu2DramMc1Ch1, sizeof(MemCfgData->DqMapCpu2DramMc1Ch1));
|
||||
CopyMem (&Fspmcfg->DqMapCpu2DramMc1Ch2, MemCfgData->DqMapCpu2DramMc1Ch2, sizeof(MemCfgData->DqMapCpu2DramMc1Ch2));
|
||||
CopyMem (&Fspmcfg->DqMapCpu2DramMc1Ch3, MemCfgData->DqMapCpu2DramMc1Ch3, sizeof(MemCfgData->DqMapCpu2DramMc1Ch3));
|
||||
|
||||
Fspmcfg->DqPinsInterleaved = MemCfgData->DqPinsInterleaved;
|
||||
|
||||
//RComp
|
||||
Fspmcfg->RcompResistor = MemCfgData->RcompResistor;
|
||||
CopyMem (&Fspmcfg->RcompTarget, MemCfgData->RcompTarget, sizeof(MemCfgData->RcompTarget));
|
||||
|
||||
// Mem cfg
|
||||
Fspmcfg->RmtPerTask = MemCfgData->RmtPerTask;
|
||||
Fspmcfg->MrcSafeConfig = MemCfgData->MrcSafeConfig;
|
||||
Fspmcfg->ScramblerSupport = MemCfgData->ScramblerSupport;
|
||||
Fspmcfg->EnhancedInterleave = MemCfgData->EnhancedInterleave;
|
||||
Fspmcfg->RankInterleave = MemCfgData->RankInterleave;
|
||||
Fspmcfg->RemapEnable = MemCfgData->RemapEnable;
|
||||
Fspmcfg->ExitOnFailure = MemCfgData->ExitOnFailure;
|
||||
Fspmcfg->ChHashEnable = MemCfgData->ChHashEnable;
|
||||
Fspmcfg->ChHashInterleaveBit = MemCfgData->ChHashInterleaveBit;
|
||||
Fspmcfg->ChHashMask = MemCfgData->ChHashMask;
|
||||
Fspmcfg->MrcFastBoot = MemCfgData->MrcFastBoot;
|
||||
// Maximum amt of memory needed
|
||||
Fspmcfg->PlatformMemorySize = MemCfgData->PlatformMemorySize;
|
||||
Fspmcfg->SafeMode = 0x0;
|
||||
|
||||
// Cpu Cfg
|
||||
Fspmcfg->CpuRatio = MemCfgData->CpuRatio;
|
||||
Fspmcfg->TmeEnable = MemCfgData->TmeEnable;
|
||||
Fspmcfg->BootFrequency = MemCfgData->BootFrequency;
|
||||
Fspmcfg->ActiveCoreCount = MemCfgData->ActiveCoreCount;
|
||||
Fspmcfg->ActiveSmallCoreCount = MemCfgData->ActiveSmallCoreCount;
|
||||
Fspmcfg->FClkFrequency = MemCfgData->FClkFrequency;
|
||||
Fspmcfg->TxtDprMemoryBase = MemCfgData->TxtDprMemoryBase;
|
||||
Fspmcfg->TxtDprMemorySize = MemCfgData->TxtDprMemorySize;
|
||||
Fspmcfg->SinitMemorySize = MemCfgData->SinitMemorySize;
|
||||
Fspmcfg->TxtHeapMemorySize = MemCfgData->TxtHeapMemorySize;
|
||||
Fspmcfg->BiosSize = MemCfgData->BiosSize;
|
||||
Fspmcfg->BiosAcmBase = MemCfgData->BiosAcmBase;
|
||||
Fspmcfg->BiosGuard = 0x0; // Need to disable, else it will fails in FSPS
|
||||
Fspmcfg->BiosGuardToolsInterface = 1;
|
||||
|
||||
// Skip CPU replacement check for embedded design to always enable fast boot
|
||||
Fspmcfg->SkipCpuReplacementCheck = 1;
|
||||
|
||||
// MRC Training algorithms
|
||||
Fspmcfg->RMT = MemCfgData->RMT;
|
||||
Fspmcfg->BdatEnable = MemCfgData->BdatEnable;
|
||||
Fspmcfg->BdatTestType = MemCfgData->BdatTestType;
|
||||
Fspmcfg->RMC = MemCfgData->RMC;
|
||||
Fspmcfg->MEMTST = MemCfgData->MEMTST;
|
||||
Fspmcfg->ECT = MemCfgData->ECT;
|
||||
|
||||
// Pcie
|
||||
Fspmcfg->PcieRpEnableMask = MemCfgData->PcieRpEnableMask;
|
||||
CopyMem (Fspmcfg->PcieClkSrcUsage, MemCfgData->PcieClkSrcUsage, sizeof(MemCfgData->PcieClkSrcUsage));
|
||||
CopyMem (Fspmcfg->PcieClkSrcClkReq, MemCfgData->PcieClkSrcClkReq, sizeof(MemCfgData->PcieClkSrcClkReq));
|
||||
|
||||
// Cpu Pcie
|
||||
Fspmcfg->CpuPcieRpEnableMask = MemCfgData->CpuPcieRpEnableMask;
|
||||
CopyMem (Fspmcfg->CpuPcieRpPcieSpeed, MemCfgData->CpuPcieRpPcieSpeed, sizeof(MemCfgData->CpuPcieRpPcieSpeed));
|
||||
Fspmcfg->CpuPcieRpClockReqMsgEnable[0] = MemCfgData->CpuPcieRpClockReqMsgEnable[0];
|
||||
Fspmcfg->CpuPcieRpClockReqMsgEnable[1] = MemCfgData->CpuPcieRpClockReqMsgEnable[1];
|
||||
Fspmcfg->CpuPcieRpClockReqMsgEnable[2] = MemCfgData->CpuPcieRpClockReqMsgEnable[2];
|
||||
|
||||
Fspmcfg->SkipMbpHob = 0;
|
||||
DEBUG ((DEBUG_INFO, "SkipMbpHob = 0x%x\n", Fspmcfg->SkipMbpHob));
|
||||
|
||||
// IBECC - removed in the latest FSP. Add them later when needed
|
||||
Fspmcfg->Ibecc = MemCfgData->Ibecc;
|
||||
Fspmcfg->IbeccOperationMode = MemCfgData->IbeccOperationMode;
|
||||
for (Index = 0; Index < 8; Index++) {
|
||||
Fspmcfg->IbeccProtectedRangeEnable[Index] = MemCfgData->IbeccProtectedRegionEnable[Index];
|
||||
Fspmcfg->IbeccProtectedRangeBase[Index] = MemCfgData->IbeccProtectedRegionBase[Index];
|
||||
if (MemCfgData->IbeccProtectedRegionMask[Index] > 0x03FFFFFF) {
|
||||
MemCfgData->IbeccProtectedRegionMask[Index] = 0x03FFFFFF;
|
||||
}
|
||||
Fspmcfg->IbeccProtectedRangeMask[Index] = MemCfgData->IbeccProtectedRegionMask[Index];
|
||||
}
|
||||
|
||||
// Vtd
|
||||
PlatformData = (PLATFORM_DATA *)GetPlatformDataPtr ();
|
||||
if (PlatformData != NULL) {
|
||||
PlatformData->PlatformFeatures.VtdEnable = (!MemCfgData->VtdDisable) & FeaturePcdGet (PcdVtdEnabled);
|
||||
Fspmcfg->VtdDisable = (UINT8)(!PlatformData->PlatformFeatures.VtdEnable);
|
||||
if (PlatformData->PlatformFeatures.VtdEnable == 1) {
|
||||
Fspmcfg->VtdIgdEnable = MemCfgData->VtdIgdEnable;
|
||||
Fspmcfg->VtdIpuEnable = 0x1;
|
||||
Fspmcfg->VtdIopEnable = 0x1;
|
||||
|
||||
Fspmcfg->VtdBaseAddress[0] = VTD_BASEADDRESS_0;
|
||||
Fspmcfg->VtdBaseAddress[1] = 0x0;
|
||||
Fspmcfg->VtdBaseAddress[2] = VTD_BASEADDRESS_2;
|
||||
|
||||
Fspmcfg->X2ApicOptOut = MemCfgData->X2ApicOptOut;
|
||||
Fspmcfg->DmaBufferSize = MemCfgData->DmaBufferSize;
|
||||
Fspmcfg->DmaControlGuarantee = MemCfgData->DmaControlGuarantee;
|
||||
Fspmcfg->PreBootDmaMask = 0x1;
|
||||
}
|
||||
}
|
||||
|
||||
// Host Bridge
|
||||
Fspmcfg->MmioSize = MemCfgData->MmioSize;
|
||||
Fspmcfg->MmioSizeAdjustment = MemCfgData->MmioSizeAdjustment;
|
||||
|
||||
// Smbus
|
||||
Fspmcfg->SmbusEnable = MemCfgData->SmbusEnable;
|
||||
Fspmcfg->PchNumRsvdSmbusAddresses = MemCfgData->PchNumRsvdSmbusAddresses;
|
||||
Fspmcfg->RsvdSmbusAddressTablePtr = MemCfgData->RsvdSmbusAddressTablePtr;
|
||||
|
||||
// Overclocking Cfg
|
||||
Fspmcfg->RealtimeMemoryTiming = MemCfgData->RealtimeMemoryTiming;
|
||||
|
||||
// Tcc related settings
|
||||
Fspmcfg->SaGv = MemCfgData->SaGv; // System Agent Geyserville - SAGV dynamically adjusts the system agent
|
||||
// voltage and clock frequencies depending on power and performance requirements
|
||||
Fspmcfg->DisPgCloseIdleTimeout = MemCfgData->DisPgCloseIdleTimeout; // controls Page Close Idle Timeout
|
||||
Fspmcfg->PowerDownMode = MemCfgData->PowerDownMode; // controls command bus tristating during idle periods
|
||||
Fspmcfg->WrcFeatureEnable = MemCfgData->WrcFeatureEnable;
|
||||
Fspmcfg->HyperThreading = MemCfgData->HyperThreading;
|
||||
Fspmcfg->GtClosEnable = MemCfgData->GtClosEnable;
|
||||
Fspmcfg->VmxEnable = MemCfgData->VmxEnable;
|
||||
Fspmcfg->Lp5BankMode = MemCfgData->Lp5BankMode;
|
||||
|
||||
// CSI port
|
||||
CopyMem (Fspmcfg->IpuLaneUsed, MemCfgData->IpuLaneUsed, sizeof(MemCfgData->IpuLaneUsed));
|
||||
CopyMem (Fspmcfg->CsiSpeed, MemCfgData->CsiSpeed, sizeof(MemCfgData->CsiSpeed));
|
||||
|
||||
// DMI cfg
|
||||
Fspmcfg->DmiMaxLinkSpeed = MemCfgData->DmiMaxLinkSpeed;
|
||||
Fspmcfg->DmiAspm = MemCfgData->DmiAspm;
|
||||
Fspmcfg->DmiAspmCtrl = MemCfgData->DmiAspmCtrl;
|
||||
Fspmcfg->DmiHweq = 0x2;
|
||||
CopyMem (Fspmcfg->DmiGen3RootPortPreset, MemCfgData->DmiGen3RootPortPreset, sizeof(MemCfgData->DmiGen3RootPortPreset));
|
||||
CopyMem (Fspmcfg->DmiGen3EndPointPreset, MemCfgData->DmiGen3EndPointPreset, sizeof(MemCfgData->DmiGen3EndPointPreset));
|
||||
CopyMem (Fspmcfg->DmiGen3EndPointHint, MemCfgData->DmiGen3EndPointHint, sizeof(MemCfgData->DmiGen3EndPointHint));
|
||||
Fspmcfg->DmiGen3Ltcpo[7] = 0x2;
|
||||
for (Index = 0; Index < 8; Index++) {
|
||||
Fspmcfg->DmiGen3Ltcpre[Index] = MemCfgData->DmiGen3Ltcpre[Index];
|
||||
Fspmcfg->DmiGen3DsPortRxPreset[Index] = MemCfgData->DmiGen3DsPortRxPreset[Index];
|
||||
Fspmcfg->DmiGen3DsPortTxPreset[Index] = MemCfgData->DmiGen3DsPortTxPreset[Index];
|
||||
}
|
||||
for (Index = 0; Index < 8; Index++) {
|
||||
Fspmcfg->DmiGen4Ltcpo[Index] = 0x7;
|
||||
}
|
||||
CopyMem (Fspmcfg->CpuDmiHwEqGen3CoeffListCm, MemCfgData->CpuDmiHwEqGen3CoeffListCm, sizeof(MemCfgData->CpuDmiHwEqGen3CoeffListCm));
|
||||
CopyMem (Fspmcfg->CpuDmiHwEqGen3CoeffListCp, MemCfgData->CpuDmiHwEqGen3CoeffListCp, sizeof(MemCfgData->CpuDmiHwEqGen3CoeffListCp));
|
||||
CopyMem (Fspmcfg->CpuDmiHwEqGen4CoeffListCm, MemCfgData->CpuDmiHwEqGen4CoeffListCm, sizeof(MemCfgData->CpuDmiHwEqGen4CoeffListCm));
|
||||
CopyMem (Fspmcfg->CpuDmiHwEqGen4CoeffListCp, MemCfgData->CpuDmiHwEqGen4CoeffListCp, sizeof(MemCfgData->CpuDmiHwEqGen4CoeffListCp));
|
||||
CopyMem (Fspmcfg->PchDmiHwEqGen3CoeffListCm, MemCfgData->PchDmiHwEqGen3CoeffListCm, sizeof(MemCfgData->PchDmiHwEqGen3CoeffListCm));
|
||||
CopyMem (Fspmcfg->PchDmiHwEqGen3CoeffListCp, MemCfgData->PchDmiHwEqGen3CoeffListCp, sizeof(MemCfgData->PchDmiHwEqGen3CoeffListCp));
|
||||
Fspmcfg->Gen3EqPhase23Bypass = MemCfgData->Gen3EqPhase23Bypass;
|
||||
Fspmcfg->Gen3EqPhase3Bypass = MemCfgData->Gen3EqPhase3Bypass;
|
||||
Fspmcfg->Gen3LtcoEnable = MemCfgData->Gen3LtcoEnable;
|
||||
|
||||
// Tcss Dev enable bits
|
||||
Fspmcfg->TcssItbtPcie0En = MemCfgData->TcssItbtPcie0En;
|
||||
Fspmcfg->TcssItbtPcie1En = MemCfgData->TcssItbtPcie1En;
|
||||
Fspmcfg->TcssItbtPcie2En = MemCfgData->TcssItbtPcie2En;
|
||||
Fspmcfg->TcssItbtPcie3En = MemCfgData->TcssItbtPcie3En;
|
||||
Fspmcfg->TcssXhciEn = MemCfgData->TcssXhciEn;
|
||||
Fspmcfg->TcssDma0En = MemCfgData->TcssDma0En;
|
||||
Fspmcfg->TcssDma1En = MemCfgData->TcssDma1En;
|
||||
Fspmcfg->UsbTcPortEnPreMem = MemCfgData->UsbTcPortEnPreMem;
|
||||
|
||||
// Misc
|
||||
Fspmcfg->UserBd = MemCfgData->UserBd;
|
||||
Fspmcfg->EnableC6Dram = MemCfgData->EnableC6Dram;
|
||||
Fspmcfg->TsegSize = MemCfgData->TsegSize;
|
||||
Fspmcfg->SkipExtGfxScan = MemCfgData->SkipExtGfxScan;
|
||||
Fspmcfg->LockPTMregs = MemCfgData->LockPTMregs;
|
||||
Fspmcfg->CridEnable = 0x0;
|
||||
Fspmcfg->Lfsr0Mask = 0xb;
|
||||
Fspmcfg->Lfsr1Mask = 0xb;
|
||||
Fspmcfg->RefreshPanicWm = 0x8;
|
||||
Fspmcfg->RefreshHpWm = 0x7;
|
||||
|
||||
Fspmcfg->PlatformDebugConsent = MemCfgData->PlatformDebugConsent;
|
||||
if (Fspmcfg->PlatformDebugConsent != 0) {
|
||||
Fspmcfg->DciModphyPg = 0;
|
||||
Fspmcfg->DciUsb3TypecUfpDbg = 2;
|
||||
Fspmcfg->DebugInterfaceLockEnable = TRUE;
|
||||
Fspmcfg->DciDbcMode = DciDbcNoChange;
|
||||
Fspmcfg->DciEn = MemCfgData->DciEn;
|
||||
Fspmcfg->CpuTraceHubMode = MemCfgData->CpuTraceHubMode;
|
||||
Fspmcfg->PchTraceHubMode = MemCfgData->PchTraceHubMode;
|
||||
Fspmcfg->CpuTraceHubMemReg0Size = MemCfgData->CpuTraceHubMemReg0Size;
|
||||
Fspmcfg->CpuTraceHubMemReg1Size = MemCfgData->CpuTraceHubMemReg1Size;
|
||||
Fspmcfg->PchTraceHubMemReg0Size = MemCfgData->PchTraceHubMemReg0Size;
|
||||
Fspmcfg->PchTraceHubMemReg1Size = MemCfgData->PchTraceHubMemReg1Size;
|
||||
}
|
||||
|
||||
PlatformId = GetPlatformId();
|
||||
DEBUG((DEBUG_INFO, "PLATFORM_ID_AZB_LP5_CRB2A board Id %x .....\n", PlatformId));
|
||||
|
||||
Fspmcfg->DdiPortAConfig = SaDisplayConfigTable[0];
|
||||
Fspmcfg->DdiPortBConfig = SaDisplayConfigTable[1];
|
||||
Fspmcfg->DdiPortAHpd = SaDisplayConfigTable[2];
|
||||
Fspmcfg->DdiPortBHpd = SaDisplayConfigTable[3];
|
||||
Fspmcfg->DdiPortCHpd = SaDisplayConfigTable[4];
|
||||
Fspmcfg->DdiPort1Hpd = SaDisplayConfigTable[5];
|
||||
Fspmcfg->DdiPort2Hpd = SaDisplayConfigTable[6];
|
||||
Fspmcfg->DdiPort3Hpd = SaDisplayConfigTable[7];
|
||||
Fspmcfg->DdiPort4Hpd = SaDisplayConfigTable[8];
|
||||
Fspmcfg->DdiPortADdc = SaDisplayConfigTable[9];
|
||||
Fspmcfg->DdiPortBDdc = SaDisplayConfigTable[10];
|
||||
Fspmcfg->DdiPortCDdc = SaDisplayConfigTable[11];
|
||||
Fspmcfg->DdiPort1Ddc = SaDisplayConfigTable[12];
|
||||
Fspmcfg->DdiPort2Ddc = SaDisplayConfigTable[13];
|
||||
Fspmcfg->DdiPort3Ddc = SaDisplayConfigTable[14];
|
||||
Fspmcfg->DdiPort4Ddc = SaDisplayConfigTable[15];
|
||||
|
||||
if (IsPchLp ()) {
|
||||
switch (GetPlatformId ()) {
|
||||
case PLATFORM_ID_AZB_LP5_CRB2A:
|
||||
Fspmcfg->DdiPortBHpd = 0x1;
|
||||
Fspmcfg->DmiHweq = 0x2;
|
||||
Fspmcfg->PcieClkReqGpioMux[9] = 0x796e9000;
|
||||
Fspmcfg->SkipCpuReplacementCheck = 0x0;
|
||||
Fspmcfg->FirstDimmBitMask = 0;
|
||||
Fspmcfg->FirstDimmBitMaskEcc = 0;
|
||||
Fspmcfg->Lp5CccConfig = 0xFF;
|
||||
Fspmcfg->GearRatio = 4;
|
||||
Fspmcfg->DdrFreqLimit = 5200;
|
||||
Fspmcfg->SaGv = MemCfgData->SaGv;
|
||||
Fspmcfg->DisableMc0Ch0 = 1;
|
||||
Fspmcfg->DisableMc0Ch1 = 1;
|
||||
Fspmcfg->DisableMc0Ch2 = 1;
|
||||
Fspmcfg->DisableMc0Ch3 = 1;
|
||||
break;
|
||||
default:
|
||||
DEBUG ((DEBUG_INFO, "Unknown board for FSP-M UPD settings.\n"));
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (PcdGetBool (PcdFastBootEnabled) && !(IsPchP ())) {
|
||||
Fspmcfg->CpuPcieRpEnableMask = 0;
|
||||
}
|
||||
|
||||
// S0ix is disabled if TSN is enabled.
|
||||
FeaturesCfgData = (FEATURES_CFG_DATA *) FindConfigDataByTag (CDATA_FEATURES_TAG);
|
||||
SiCfgData = (SILICON_CFG_DATA *)FindConfigDataByTag (CDATA_SILICON_TAG);
|
||||
if ((SiCfgData != NULL) && (SiCfgData->PchTsnEnable == 1)) {
|
||||
if (FeaturesCfgData != NULL) {
|
||||
FeaturesCfgData->Features.S0ix = 0;
|
||||
DEBUG ((DEBUG_INFO, "TSN is enabled, turn off S0ix\n"));
|
||||
}
|
||||
}
|
||||
|
||||
if (FeaturesCfgData != NULL) {
|
||||
if (FeaturesCfgData->Features.S0ix == 1) {
|
||||
Fspmcfg->TcssXdciEn = 0;
|
||||
Fspmcfg->PchIshEnable = 1;
|
||||
ZeroMem (Fspmcfg->PchHdaAudioLinkDmicEnable, sizeof (Fspmcfg->PchHdaAudioLinkDmicEnable));
|
||||
DEBUG ((DEBUG_INFO, "Stage 1B S0ix config applied.\n"));
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,48 @@
|
||||
## @file
|
||||
#
|
||||
# Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
|
||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
#
|
||||
##
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = FspmUpdUpdateLib
|
||||
FILE_GUID = 1A29F3A2-9E6F-4E04-B16C-BB6C647308896
|
||||
MODULE_TYPE = BASE
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = FspmUpdUpdateLib
|
||||
|
||||
#
|
||||
# The following information is for reference only and not required by the build tools.
|
||||
#
|
||||
# VALID_ARCHITECTURES = IA32 X64
|
||||
#
|
||||
|
||||
[Sources]
|
||||
FspmUpdUpdateLibAzb.c
|
||||
BoardSaConfigPreMem.h
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
IntelFsp2Pkg/IntelFsp2Pkg.dec
|
||||
BootloaderCorePkg/BootloaderCorePkg.dec
|
||||
BootloaderCommonPkg/BootloaderCommonPkg.dec
|
||||
Silicon/CommonSocPkg/CommonSocPkg.dec
|
||||
Silicon/AlderlakePkg/AlderlakePkg.dec
|
||||
Platform/CommonBoardPkg/CommonBoardPkg.dec
|
||||
Platform/AlderlakeBoardPkg/AlderlakeBoardPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
BaseLib
|
||||
DebugLib
|
||||
ConfigDataLib
|
||||
WatchDogTimerLib
|
||||
|
||||
[Pcd]
|
||||
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
|
||||
gPlatformModuleTokenSpaceGuid.PcdVtdEnabled
|
||||
gPlatformModuleTokenSpaceGuid.PcdFastBootEnabled
|
||||
gPlatformModuleTokenSpaceGuid.PcdStage1StackBaseOffset
|
||||
gPlatformModuleTokenSpaceGuid.PcdStage1StackSize
|
||||
gPlatformModuleTokenSpaceGuid.PcdStage1DataSize
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,46 @@
|
||||
## @file
|
||||
#
|
||||
# Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
|
||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
#
|
||||
##
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = FspsUpdUpdateLib
|
||||
FILE_GUID = F0F0D153-A1A6-4455-89C5-F2BDD02C25459
|
||||
MODULE_TYPE = BASE
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = FspsUpdUpdateLib
|
||||
|
||||
#
|
||||
# The following information is for reference only and not required by the build tools.
|
||||
#
|
||||
# VALID_ARCHITECTURES = IA32 X64
|
||||
#
|
||||
|
||||
[Sources]
|
||||
FspsUpdUpdateLibAzb.c
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
IntelFsp2Pkg/IntelFsp2Pkg.dec
|
||||
BootloaderCorePkg/BootloaderCorePkg.dec
|
||||
BootloaderCommonPkg/BootloaderCommonPkg.dec
|
||||
Silicon/AlderlakePkg/AlderlakePkg.dec
|
||||
Silicon/CommonSocPkg/CommonSocPkg.dec
|
||||
Platform/CommonBoardPkg/CommonBoardPkg.dec
|
||||
Platform/AlderlakeBoardPkg/AlderlakeBoardPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
BaseLib
|
||||
DebugLib
|
||||
ConfigDataLib
|
||||
WatchDogTimerLib
|
||||
TpmLib
|
||||
|
||||
[Pcd]
|
||||
gPlatformModuleTokenSpaceGuid.PcdEnablePciePm
|
||||
gPlatformModuleTokenSpaceGuid.PcdFastBootEnabled
|
||||
gPlatformModuleTokenSpaceGuid.PcdSblResiliencyEnabled
|
||||
gPlatformCommonLibTokenSpaceGuid.PcdMeasuredBootEnabled
|
||||
@@ -395,6 +395,9 @@ GetBoardId (
|
||||
case BoardIdAdlNLp5Rvp:
|
||||
*PlatformId = PLATFORM_ID_ADL_N_LPDDR5_RVP;
|
||||
break;
|
||||
case BoardIdAzbLp5Crb2A:
|
||||
*PlatformId = PLATFORM_ID_AZB_LP5_CRB2A;
|
||||
break;
|
||||
case BoardIdTestSDdr5UDimm1DRvp:
|
||||
*PlatformId = PLATFORM_ID_TEST_S_DDR5_UDIMM_RVP;
|
||||
break;
|
||||
|
||||
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Reference in New Issue
Block a user