diff --git a/.azurepipelines/azure-pipelines.yml b/.azurepipelines/azure-pipelines.yml
index fb16f477..0c6a5cf0 100644
--- a/.azurepipelines/azure-pipelines.yml
+++ b/.azurepipelines/azure-pipelines.yml
@@ -109,6 +109,14 @@ jobs:
Build.Name: "rpls"
Build.Arch: ""
Build.Target: ""
+ AZB_X86_DEBUG:
+ Build.Name: "azb"
+ Build.Arch: ""
+ Build.Target: ""
+ AZB_X86_RELEASE:
+ Build.Name: "azb"
+ Build.Arch: ""
+ Build.Target: "-r"
pool:
@@ -228,6 +236,14 @@ jobs:
Build.Name: "rpls"
Build.Arch: "-a x64"
Build.Target: ""
+ AZB_X86_DEBUG:
+ Build.Name: "azb"
+ Build.Arch: ""
+ Build.Target: ""
+ AZB_X86_RELEASE:
+ Build.Name: "azb"
+ Build.Arch: ""
+ Build.Target: "-r"
pool:
vmImage: 'windows-2019'
diff --git a/Platform/.gitignore b/Platform/.gitignore
index 10249a0f..890ee714 100644
--- a/Platform/.gitignore
+++ b/Platform/.gitignore
@@ -4,3 +4,4 @@ VerInfo.txt
!CoffeelakeBoardPkg/VbtBin/
!AlderlakeBoardPkg/VbtBin/
!ApollolakeBoardPkg/VbtBin/Vbt_*.*
+*.json
diff --git a/Platform/AlderlakeBoardPkg/BoardConfig.py b/Platform/AlderlakeBoardPkg/BoardConfig.py
index 2a348178..4b4f47eb 100644
--- a/Platform/AlderlakeBoardPkg/BoardConfig.py
+++ b/Platform/AlderlakeBoardPkg/BoardConfig.py
@@ -38,6 +38,7 @@ class Board(BaseBoard):
self.MICROCODE_INF_FILE = ''
self._LP_SUPPORT = False
self._N_SUPPORT = False
+ self._AZB_SUPPORT = False
self.PCI_EXPRESS_BASE = 0xC0000000
self.PCI_IO_BASE = 0x00002000
diff --git a/Platform/AlderlakeBoardPkg/BoardConfigAzb.py b/Platform/AlderlakeBoardPkg/BoardConfigAzb.py
new file mode 100644
index 00000000..78dcb248
--- /dev/null
+++ b/Platform/AlderlakeBoardPkg/BoardConfigAzb.py
@@ -0,0 +1,417 @@
+## @file
+# This file is used to provide board specific image information.
+#
+# Copyright (c) 2023, Intel Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+##
+# Import Modules
+#
+
+import os
+import sys
+import time
+
+sys.dont_write_bytecode = True
+sys.path.append (os.path.join('..', '..'))
+from BuildLoader import BaseBoard, STITCH_OPS, FLASH_REGION_TYPE, HASH_USAGE
+from BuildLoader import IPP_CRYPTO_OPTIMIZATION_MASK, IPP_CRYPTO_ALG_MASK, HASH_TYPE_VALUE
+
+class Board(BaseBoard):
+ def __init__(self, *args, **kwargs):
+ super(Board, self).__init__(*args, **kwargs)
+ self.VERINFO_IMAGE_ID = 'SB_AZB'
+ self.VERINFO_PROJ_MAJOR_VER = 1
+ self.VERINFO_PROJ_MINOR_VER = 2
+ self.VERINFO_CORE_MAJOR_VER = 1
+ self.VERINFO_CORE_MINOR_VER = 0
+ self.VERINFO_SVN = 1
+ self.VERINFO_BUILD_DATE = time.strftime("%m/%d/%Y")
+
+ self.BOARD_NAME = 'azb'
+ self.BOARD_PKG_NAME = 'AlderlakeBoardPkg'
+ self.SILICON_PKG_NAME = 'AlderlakePkg'
+ self._CFGDATA_DEF_FILE = 'CfgDataDefAzb.yaml'
+ self.FSP_IMAGE_ID = '$ADLFSP$'
+ self._EXTRA_INC_PATH = ['Silicon/AlderlakePkg/Azb/Include']
+ self._FSP_PATH_NAME = 'Silicon/AlderlakePkg/Azb/FspBin'
+ self.MICROCODE_INF_FILE = 'Silicon/AlderlakePkg/Microcode/MicrocodeAzb.inf'
+ self._LP_SUPPORT = False
+ self._N_SUPPORT = False
+ self._AZB_SUPPORT = True
+
+ # _AZB_WWAN_SUPPORT enable WWAN with ~600ms delay in Stage1B for GPIO init.
+ # If WWAN is not needed then change the flag as False to save ~600ms boot time.
+ self._AZB_WWAN_SUPPORT = True
+ self.SUPPORT_SR_IOV = 0
+
+ self.PCI_EXPRESS_BASE = 0xC0000000
+ self.PCI_IO_BASE = 0x00002000
+ self.PCI_MEM32_BASE = 0x80000000
+ self.ACPI_PM_TIMER_BASE = 0x1808
+
+ self.FLASH_LAYOUT_START = 0x100000000 # 4GB Top
+ self.FLASH_BASE_SIZE = 0x02000000 # 32MB
+ self.FLASH_BASE_ADDRESS = (self.FLASH_LAYOUT_START - self.FLASH_BASE_SIZE)
+ self.LOADER_ACPI_RECLAIM_MEM_SIZE = 0x000090000
+ self.HAVE_FIT_TABLE = 1
+ self.HAVE_VBT_BIN = 0
+ self.HAVE_VERIFIED_BOOT = 1
+ self.HAVE_MEASURED_BOOT = 1
+ self.HAVE_FLASH_MAP = 1
+ self.HAVE_ACPI_TABLE = 1
+ self.HAVE_PSD_TABLE = 1
+ self.ENABLE_SPLASH = 0
+ self.ENABLE_FRAMEBUFFER_INIT = 0
+ self.ENABLE_VTD = 0
+ # To enable source debug, set 1 to self.ENABLE_SOURCE_DEBUG
+ self.ENABLE_SOURCE_DEBUG = 0
+ # If ENABLE_SOURCE_DEBUG is disabled, SKIP_STAGE1A_SOURCE_DEBUG will be ignored
+ self.SKIP_STAGE1A_SOURCE_DEBUG = 1
+ self.ENABLE_PCIE_PM = 1
+ # 0: Disable 1: Enable 2: Auto (disable for UEFI payload, enable for others)
+ self.ENABLE_SMM_REBASE = 2
+
+ # 0 - PCH UART0, 1 - PCH UART1, 2 - PCH UART2, 0xFF - EC UART 0x3F8
+ self.DEBUG_PORT_NUMBER = 0x0
+
+ self.ENABLE_MULTI_USB_BOOT_DEV = 1
+
+ self.CPU_MAX_LOGICAL_PROCESSOR_NUMBER = 24
+
+ if self.HAVE_FIT_TABLE:
+ self.FIT_ENTRY_MAX_NUM = 17
+
+ # RSA2048 or RSA3072
+ self._RSA_SIGN_TYPE = 'RSA3072'
+
+ # 'SHA2_256' or 'SHA2_384'
+ self._SIGN_HASH = 'SHA2_384'
+
+ # 0x01 for SHA2_256 or 0x02 for SHA2_384
+ self.SIGN_HASH_TYPE = HASH_TYPE_VALUE[self._SIGN_HASH]
+
+ # 0x0010 for SM3_256 | 0x0008 for SHA2_512 | 0x0004 for SHA2_384 | 0x0002 for SHA2_256 | 0x0001 for SHA1
+ self.IPP_HASH_LIB_SUPPORTED_MASK = IPP_CRYPTO_ALG_MASK['SHA2_384'] | IPP_CRYPTO_ALG_MASK['SHA2_256']
+ # G9 for 384 | W7 Opt for SHA384| Ni Opt for SHA256| V8 Opt for SHA256
+ self.ENABLE_CRYPTO_SHA_OPT = IPP_CRYPTO_OPTIMIZATION_MASK['SHA256_NI'] | IPP_CRYPTO_OPTIMIZATION_MASK['SHA384_W7']
+
+ # Key configuration
+ self._MASTER_PRIVATE_KEY = 'KEY_ID_MASTER' + '_' + self._RSA_SIGN_TYPE
+ self._CFGDATA_PRIVATE_KEY = 'KEY_ID_CFGDATA' + '_' + self._RSA_SIGN_TYPE
+ self._CONTAINER_PRIVATE_KEY = 'KEY_ID_CONTAINER' + '_' + self._RSA_SIGN_TYPE
+ self.ENABLE_SMP_INIT = 1
+ self.ENABLE_FWU = 1
+ self.ENABLE_SMBIOS = 1
+ self.ENABLE_CSME_UPDATE = 1
+
+ # CSME update library is required to enable this option and will be available as part of CSME kit
+ self.BUILD_CSME_UPDATE_DRIVER = 0
+
+ self.STAGE1A_XIP = 1
+ self.STAGE1B_XIP = 1
+ self.STAGE2_XIP = 0
+
+ self.STAGE1A_SIZE = 0x0001B000
+ self.STAGE1_STACK_SIZE = 0x00002000
+ self.STAGE1_DATA_SIZE = 0x00014000
+ self.FSP_M_STACK_TOP = 0xFEF7FF00
+ self.STAGE1B_SIZE = 0x00200000
+ if self.FSPDEBUG_MODE:
+ self.STAGE2_SIZE = 0x000CE000
+ else:
+ self.STAGE2_SIZE = 0x000C3000
+ self.STAGE2_FD_BASE = 0x01000000
+ self.STAGE2_FD_SIZE = 0x001F0000
+
+ self.PAYLOAD_SIZE = 0x00030000
+ self.EPAYLOAD_SIZE = 0x00161000
+
+ self.ENABLE_FAST_BOOT = 0
+
+ if self.ENABLE_FAST_BOOT:
+ self.ENABLE_SPLASH = 0
+ self.ENABLE_FRAMEBUFFER_INIT = 0
+ self.RELEASE_MODE = 1
+ self.HAVE_VERIFIED_BOOT = 0
+ self.HAVE_MEASURED_BOOT = 0
+ self.VERIFIED_BOOT_HASH_MASK = 0
+ self.FSPDEBUG_MODE = 0
+ self.ENABLE_SOURCE_DEBUG = 0
+
+ if self.RELEASE_MODE and self.ENABLE_FAST_BOOT:
+ self.STAGE1A_SIZE = 0x0001A000
+ self.STAGE1B_SIZE = 0x000E0000
+ self.STAGE2_SIZE = 0x00079000
+ self.STAGE2_FD_SIZE = 0x000F0000
+ self.PAYLOAD_SIZE = 0x00020000
+
+ if self.ENABLE_SOURCE_DEBUG:
+ if self.FSPDEBUG_MODE:
+ self.STAGE2_SIZE += 0x2000
+
+ self.UEFI_VARIABLE_SIZE = 0x1000
+
+ if len(self._PAYLOAD_NAME.split(';')) > 1:
+ self.UEFI_VARIABLE_SIZE = 0x00040000
+
+ self.UCODE_SIZE = 0x000C3000
+ self.MRCDATA_SIZE = 0x00010000
+ self.CFGDATA_SIZE = 0x00004000
+ self.KEYHASH_SIZE = 0x00001000
+ self.VARIABLE_SIZE = 0x00002000
+ self.SBLRSVD_SIZE = 0x00001000
+ self.FWUPDATE_SIZE = 0x00020000 if self.ENABLE_FWU else 0
+
+ self.TOP_SWAP_SIZE = 0x00080000
+ self.REDUNDANT_SIZE = self.UCODE_SIZE + self.STAGE2_SIZE + self.STAGE1B_SIZE + \
+ self.FWUPDATE_SIZE + self.CFGDATA_SIZE + self.KEYHASH_SIZE
+ self.REDUNDANT_SIZE = ((self.REDUNDANT_SIZE + 0xFFFF) & ~0xFFFF)
+ self.SIIPFW_SIZE = 0x1000
+
+ self.OS_LOADER_FD_SIZE = 0x58000
+ self.OS_LOADER_FD_NUMBLK = self.OS_LOADER_FD_SIZE // self.FLASH_BLOCK_SIZE
+
+ self.NON_REDUNDANT_SIZE = 0x3BF000 + self.SIIPFW_SIZE
+ self.NON_VOLATILE_SIZE = 0x001000
+ self.SLIMBOOTLOADER_SIZE = (self.TOP_SWAP_SIZE + self.REDUNDANT_SIZE) * 2 + \
+ self.NON_REDUNDANT_SIZE + self.NON_VOLATILE_SIZE
+ self.SLIMBOOTLOADER_SIZE = ((self.SLIMBOOTLOADER_SIZE + 0xFFFFF) & ~0xFFFFF)
+ self.PLD_HEAP_SIZE = 0x04000000
+ self.PLD_STACK_SIZE = 0x00020000
+ self.PLD_RSVD_MEM_SIZE = 0x00500000
+
+ self.KM_SIZE = 0x00000400
+ self.BPM_SIZE = 0x00000600
+ self.ACM_SIZE = 0x00040000 + self.KM_SIZE + self.BPM_SIZE
+
+ # adjust ACM_SIZE to meet 256KB alignment (to align 256KB ACM size)
+ if self.ACM_SIZE > 0:
+ acm_top = self.FLASH_LAYOUT_START - self.STAGE1A_SIZE
+ acm_btm = acm_top - self.ACM_SIZE
+ acm_btm = (acm_btm & 0xFFFC0000)
+ self.ACM_SIZE = acm_top - acm_btm
+
+ self.LOADER_RSVD_MEM_SIZE = 0x500000
+
+ self.CFG_DATABASE_SIZE = self.CFGDATA_SIZE
+ self._generated_cfg_file_prefix = 'Autogen_'
+
+ self._CFGDATA_INT_FILE = []
+ self._CFGDATA_EXT_FILE = [self._generated_cfg_file_prefix + 'CfgDataInt_Azb_Crb_Lpddr5.dlt']
+
+
+ def PlatformBuildHook (self, build, phase):
+ if phase == 'pre-build:before':
+ # create build folder if not exist
+ if not os.path.exists(build._fv_dir):
+ os.makedirs(build._fv_dir)
+
+ # Generate the dlt files based on feature
+ brd_cfg_src_dir = os.path.join(os.environ['PLT_SOURCE'], 'Platform', self.BOARD_PKG_NAME, 'CfgData')
+ brd_cfg2_src_dir = '.'
+ if hasattr(self, 'BOARD_PKG_NAME_OVERRIDE'):
+ brd_cfg2_src_dir = os.path.join(os.environ['PLT_SOURCE'], 'Platform', self.BOARD_PKG_NAME_OVERRIDE, 'CfgData')
+ for dlt_file in self._CFGDATA_EXT_FILE:
+ cfg_dlt_file = os.path.join(brd_cfg_src_dir, dlt_file[len (self._generated_cfg_file_prefix):])
+ if not os.path.exists(cfg_dlt_file):
+ cfg_dlt_file = os.path.join(brd_cfg2_src_dir, dlt_file[len (self._generated_cfg_file_prefix):])
+ lines = open (cfg_dlt_file).read()
+
+ # Write to generated final dlt file
+ output_cfg_dlt_file = os.path.join(build._fv_dir, dlt_file)
+ open(output_cfg_dlt_file, 'w').write(lines)
+
+
+ def GetPlatformDsc (self, BuildPkgName = "BootLoaderCorePkg"):
+ dsc = {}
+ # These libraries will be added into the DSC files
+ dsc['LibraryClasses.%s' % self.BUILD_ARCH] = [
+ 'LoaderLib|Platform/CommonBoardPkg/Library/LoaderLib/LoaderLib.inf',
+ 'SerialPortLib|BootloaderCommonPkg/Library/SerialPortLib/SerialPortLib.inf',
+ 'PlatformHookLib|Silicon/$(SILICON_PKG_NAME)/Library/PlatformHookLib/PlatformHookLib.inf',
+ 'ResetSystemLib|Platform/$(BOARD_PKG_NAME)/Library/ResetSystemLib/ResetSystemLib.inf',
+ 'GpioLib|Silicon/CommonSocPkg/Library/GpioLib/GpioLib.inf',
+ 'GpioSiLib|Silicon/$(SILICON_PKG_NAME)/Library/GpioSiLib/GpioSiLib.inf',
+ 'PchSbiAccessLib|Silicon/CommonSocPkg/Library/PchSbiAccessLib/PchSbiAccessLib.inf',
+ 'TccLib|Silicon/CommonSocPkg/Library/TccLib/TccLib.inf',
+ 'ShellExtensionLib|Platform/$(BOARD_PKG_NAME)/Library/ShellExtensionLib/ShellExtensionLib.inf',
+ 'FspmUpdUpdateLib|Platform/$(BOARD_PKG_NAME)/Library/FspmUpdUpdateLib/FspmUpdUpdateLibAzb.inf',
+ 'FspsUpdUpdateLib|Platform/$(BOARD_PKG_NAME)/Library/FspsUpdUpdateLib/FspsUpdUpdateLibAzb.inf',
+ 'PchInfoLib|Silicon/$(SILICON_PKG_NAME)/Library/PchInfoLib/PchInfoLib.inf',
+ 'PchPciBdfLib|Silicon/$(SILICON_PKG_NAME)/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf',
+ 'PchPcrLib|Silicon/CommonSocPkg/Library/PchPcrLib/PchPcrLib.inf',
+ 'PchSpiLib|Silicon/CommonSocPkg/Library/PchSpiLib/PchSpiLib.inf',
+ 'SpiFlashLib|Silicon/CommonSocPkg/Library/SpiFlashLib/SpiFlashLib.inf',
+ 'BootGuardLib|Silicon/CommonSocPkg/Library/BootGuardLibCBnT/BootGuardLibCBnT.inf',
+ 'BdatLib|Silicon/CommonSocPkg/Library/BdatLib/BdatLib.inf',
+ 'SmbusLib|Silicon/CommonSocPkg/Library/SmbusLib/SmbusLib.inf',
+ 'IgdOpRegionLib|Silicon/CommonSocPkg/Library/IgdOpRegionLib/IgdOpRegionLib.inf',
+ 'HeciLib|Silicon/CommonSocPkg/Library/HeciLib/HeciLib.inf',
+ 'MeChipsetLib|Silicon/$(SILICON_PKG_NAME)/Library/MeChipsetLib/MeChipsetLib.inf',
+ 'VtdLib|Silicon/$(SILICON_PKG_NAME)/Library/VTdLib/VTdLib.inf',
+ 'PsdLib|Silicon/$(SILICON_PKG_NAME)/Library/PsdLib/PsdLib.inf',
+ 'HeciMeExtLib|Silicon/$(SILICON_PKG_NAME)/Library/HeciMeExtLib/HeciMeExtLib.inf',
+ 'MeExtMeasurementLib|Silicon/$(SILICON_PKG_NAME)/Library/MeExtMeasurementLib/MeExtMeasurementLib.inf',
+ 'CpuPcieHsPhyInitLib|Silicon/$(SILICON_PKG_NAME)/Library/CpuPcieHsPhyInitLib/CpuPcieHsPhyInitLib.inf',
+ 'WatchDogTimerLib|Silicon/CommonSocPkg/Library/WatchDogTimerLib/WatchDogTimerLib.inf',
+ 'TcoTimerLib|Silicon/CommonSocPkg/Library/TcoTimerLib/TcoTimerLib.inf',
+ 'TopSwapLib|Silicon/CommonSocPkg/Library/TopSwapLib/TopSwapLib.inf',
+ ]
+
+ if self.BUILD_CSME_UPDATE_DRIVER:
+ dsc['LibraryClasses.%s' % self.BUILD_ARCH].append ('MeFwUpdateLib|Silicon/$(SILICON_PKG_NAME)/Library/MeFwUpdateLib/MeFwUpdateLib.inf')
+
+ if self.ENABLE_PCIE_PM:
+ lib = [
+ 'PciePm|Silicon/$(SILICON_PKG_NAME)/Library/PciePm/PciePm.inf',
+ 'PciExpressHelpersLib|Silicon/$(SILICON_PKG_NAME)/Library/PciExpressHelpersLibrary/PciExpressHelpersLibrary.inf',
+ 'BasePcieHelperLib|Silicon/$(SILICON_PKG_NAME)/Library/BasePcieHelperLib/BasePcieHelperLib.inf',
+ 'PcieClientRpLib|Silicon/$(SILICON_PKG_NAME)/Library/PcieClientRpLib/PcieClientRpLib.inf',
+ 'BasePchPciBdfLib|Silicon/$(SILICON_PKG_NAME)/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf',
+ ]
+ dsc['LibraryClasses.%s' % self.BUILD_ARCH].extend (lib)
+ else:
+ dsc['LibraryClasses.%s' % self.BUILD_ARCH].append ('PciePm|Silicon/CommonSocPkg/Library/PciePmNull/PciePmNull.inf')
+
+ dsc['PcdsFixedAtBuild'] = ['gPlatformModuleTokenSpaceGuid.PcdAcpiTablesMaxEntry | 40']
+
+ if self._LP_SUPPORT:
+ dsc['PcdsFixedAtBuild'].append ('gPlatformAlderLakeTokenSpaceGuid.PcdAdlLpSupport | TRUE')
+
+ if self._AZB_SUPPORT:
+ dsc['PcdsFixedAtBuild'].append ('gPlatformAlderLakeTokenSpaceGuid.PcdAzbSupport | TRUE')
+
+ if self._AZB_WWAN_SUPPORT:
+ dsc['PcdsFixedAtBuild'].append ('gPlatformAlderLakeTokenSpaceGuid.PcdAzbWwanSupport | TRUE')
+
+ return dsc
+
+
+ def GetKeyHashList (self):
+ # Define a set of new key used for different purposes
+ # The key is either key id or public key PEM format or private key PEM format
+ pub_key_list = [
+ (
+ # Key for verifying Config data blob
+ HASH_USAGE['PUBKEY_CFG_DATA'],
+ 'KEY_ID_CFGDATA' + '_' + self._RSA_SIGN_TYPE
+ ),
+ (
+ # Key for verifying firmware update
+ HASH_USAGE['PUBKEY_FWU'],
+ 'KEY_ID_FIRMWAREUPDATE' + '_' + self._RSA_SIGN_TYPE
+ ),
+ (
+ # Key for verifying container header
+ HASH_USAGE['PUBKEY_CONT_DEF'],
+ 'KEY_ID_CONTAINER' + '_' + self._RSA_SIGN_TYPE
+ ),
+ (
+ # Use RSA2048 key for verifying OS image signed with RSA2048
+ HASH_USAGE['PUBKEY_OS'],
+ 'KEY_ID_OS1_PUBLIC_RSA2048'
+ ),
+ (
+ # Use RSA3072 key for verifying OS image signed with RSA3072
+ HASH_USAGE['PUBKEY_OS'],
+ 'KEY_ID_OS1_PUBLIC_RSA3072'
+ ),
+ ]
+ return pub_key_list
+
+
+ def GetContainerList (self):
+ container_list = []
+ container_list_auth_type = self._RSA_SIGN_TYPE + '_'+ self._SIGNING_SCHEME[4:] + '_' + self._SIGN_HASH
+ container_list.append (
+ # Name | Image File | CompressAlg | AuthType | Key File | Region Align | Region Size | Svn Info
+ # ========================================================================================================================================================
+ ('IPFW', 'SIIPFW.bin', '', container_list_auth_type, 'KEY_ID_CONTAINER'+'_'+self._RSA_SIGN_TYPE, 0, 0 , 0), # Container Header
+ )
+
+ bins = os.path.join(os.path.dirname(os.path.realpath(__file__)), 'Binaries')
+
+ return [container_list]
+
+
+ def GetOutputImages (self):
+ # define extra images that will be copied to output folder
+ img_list = ['SlimBootloader.txt',
+ 'FlashMap.txt',
+ 'CfgDataStitch.py',
+ 'CfgDataDef.yaml']
+ return img_list
+
+
+ def GetImageLayout (self):
+ img_list = []
+
+ acm_flag = 0 if self.ACM_SIZE > 0 else STITCH_OPS.MODE_FILE_IGNOR
+ fwu_flag = 0 if self.ENABLE_FWU else STITCH_OPS.MODE_FILE_IGNOR
+ cfg_flag = 0 if len(self._CFGDATA_EXT_FILE) > 0 and self.CFGDATA_REGION_TYPE == FLASH_REGION_TYPE.BIOS else STITCH_OPS.MODE_FILE_IGNOR
+
+ if len(self._CFGDATA_EXT_FILE) > 0 and self.CFGDATA_REGION_TYPE == FLASH_REGION_TYPE.PLATFORMDATA:
+ img_list.extend ([
+ ('CFGDATA_PDR.bin', [
+ ('CFGDATA.bin', '', self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
+ ]
+ ),
+ ])
+
+ img_list.extend ([
+ ('NON_VOLATILE.bin', [
+ ('SBLRSVD.bin', '' , self.SBLRSVD_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
+ ]
+ ),
+ ('NON_REDUNDANT.bin', [
+ ('SIIPFW.bin' , '' , self.SIIPFW_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
+ ('VARIABLE.bin' , '' , self.VARIABLE_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
+ ('MRCDATA.bin' , '' , self.MRCDATA_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
+ ('EPAYLOAD.bin', '' , self.EPAYLOAD_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
+ ('PAYLOAD.bin' , 'Lz4' , self.PAYLOAD_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
+ ('UEFIVARIABLE.bin', '' , self.UEFI_VARIABLE_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
+ ]
+ ),
+ ('REDUNDANT_A.bin', [
+ ('UCODE.bin' , '' , self.UCODE_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
+ ('STAGE2.fd' , 'Lz4' , self.STAGE2_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
+ ('FWUPDATE.bin' , 'Lzma' , self.FWUPDATE_SIZE, STITCH_OPS.MODE_FILE_PAD | fwu_flag, STITCH_OPS.MODE_POS_TAIL),
+ ('CFGDATA.bin' , '' , self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD | cfg_flag, STITCH_OPS.MODE_POS_TAIL),
+ ('KEYHASH.bin' , '' , self.KEYHASH_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
+ ('STAGE1B_A.fd' , '' , self.STAGE1B_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
+ ]
+ ),
+ ('REDUNDANT_B.bin', [
+ ('UCODE.bin' , '' , self.UCODE_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
+ ('STAGE2.fd' , 'Lz4' , self.STAGE2_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
+ ('FWUPDATE.bin' , 'Lzma' , self.FWUPDATE_SIZE, STITCH_OPS.MODE_FILE_PAD | fwu_flag, STITCH_OPS.MODE_POS_TAIL),
+ ('CFGDATA.bin' , '' , self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD | cfg_flag, STITCH_OPS.MODE_POS_TAIL),
+ ('KEYHASH.bin' , '' , self.KEYHASH_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
+ ('STAGE1B_B.fd' , '' , self.STAGE1B_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
+ ]
+ ),
+ ('TOP_SWAP_A.bin', [
+ ('ACM.bin' , '' , self.ACM_SIZE, STITCH_OPS.MODE_FILE_NOP | acm_flag, STITCH_OPS.MODE_POS_TAIL),
+ ('STAGE1A_A.fd' , '' , self.STAGE1A_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
+ ]
+ ),
+ ('TOP_SWAP_B.bin', [
+ ('ACM.bin' , '' , self.ACM_SIZE, STITCH_OPS.MODE_FILE_NOP | acm_flag, STITCH_OPS.MODE_POS_TAIL),
+ ('STAGE1A_B.fd' , '' , self.STAGE1A_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
+ ]
+ ),
+ ('SlimBootloader.bin', [
+ ('NON_VOLATILE.bin' , '' , self.NON_VOLATILE_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
+ ('NON_REDUNDANT.bin' , '' , self.NON_REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
+ ('REDUNDANT_B.bin' , '' , self.REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
+ ('REDUNDANT_A.bin' , '' , self.REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
+ ('TOP_SWAP_B.bin' , '' , self.TOP_SWAP_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
+ ('TOP_SWAP_A.bin' , '' , self.TOP_SWAP_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
+ ]
+ ),
+ ])
+
+ return img_list
diff --git a/Platform/AlderlakeBoardPkg/CfgData/CfgDataDefAzb.yaml b/Platform/AlderlakeBoardPkg/CfgData/CfgDataDefAzb.yaml
new file mode 100644
index 00000000..0fbfb9ab
--- /dev/null
+++ b/Platform/AlderlakeBoardPkg/CfgData/CfgDataDefAzb.yaml
@@ -0,0 +1,60 @@
+## @file
+#
+# Slim Bootloader CFGDATA Default File.
+#
+# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+variable:
+ COND_S0IX_DIS : ($FEATURES_CFG_DATA.Features.S0ix == 0)
+ COND_PLD_SEL_EN: ($PLDSEL_CFG_DATA.PldSelGpio.Enable == 1)
+template:
+
+ - !include Template_CfgData.yaml
+
+configs:
+ - $ACTION :
+ page : PLT::"Platform", MEM::"Memory Settings", SIL::"Silicon Settings", GEN::"General Settings", GIO::"Gpio Settings", OS::"OS Boot Options", SEC::"Security Settings"
+ - Signature :
+ length : 0x04
+ value : {'CFGD'}
+ - HeaderLength :
+ length : 0x01
+ value : 0x10
+ - Reserved :
+ length : 0x03
+ value : {0,0,0}
+ - UsedLength :
+ length : 0x04
+ value : _LENGTH_
+ - TotalLength :
+ length : 0x04
+ value : 0x2000
+
+ - !include CfgData_Features.yaml
+
+ - !include CfgData_Gpio_Azb.yaml
+
+ - !include Platform/CommonBoardPkg/CfgData/CfgData_Platform.yaml
+
+ - !include Platform/CommonBoardPkg/CfgData/CfgData_Common.yaml
+
+ - !include CfgData_BootOption_Azb.yaml
+
+ - !include CfgData_Memory.yaml
+
+ - !include CfgData_MemSpd_Azb.yaml
+
+ - !include CfgData_Dynamic.yaml
+
+ - !include CfgData_Silicon.yaml
+
+ - !include CfgData_Power.yaml
+
+ - !include CfgData_Security.yaml
+
+ - !include CfgData_PepConstraints.yaml
+
+ - !include CfgData_CapsuleInformation.yaml
diff --git a/Platform/AlderlakeBoardPkg/CfgData/CfgDataInt_Azb_Crb_Lpddr5.dlt b/Platform/AlderlakeBoardPkg/CfgData/CfgDataInt_Azb_Crb_Lpddr5.dlt
new file mode 100644
index 00000000..e05caa64
--- /dev/null
+++ b/Platform/AlderlakeBoardPkg/CfgData/CfgDataInt_Azb_Crb_Lpddr5.dlt
@@ -0,0 +1,125 @@
+#/** @file
+#
+# Platform Configuration Delta File.
+#
+# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+#**/
+
+
+#
+# Delta configuration values for platform ID 0x0009
+#
+
+PLATFORMID_CFG_DATA.PlatformId | 0x0009
+
+GPIO_CFG_DATA.GpioPinConfig0_GPP_H02 | 0x0100E2A1
+GPIO_CFG_DATA.GpioPinConfig1_GPP_H02 | 0x07020001
+GPIO_CFG_DATA.GpioPinConfig0_GPD02 | 0x03148DA1
+GPIO_CFG_DATA.GpioPinConfig1_GPD02 | 0x05020601
+GPIO_CFG_DATA.GpioPinConfig0_GPP_A12 | 0x0100E281
+GPIO_CFG_DATA.GpioPinConfig1_GPP_A12 | 0x020C0001
+GPIO_CFG_DATA.GpioPinConfig0_GPP_C02 | 0x0500E283
+GPIO_CFG_DATA.GpioPinConfig1_GPP_C02 | 0x0B020001
+GPIO_CFG_DATA.GpioPinConfig0_GPP_E00 | 0x03148DA1
+GPIO_CFG_DATA.GpioPinConfig1_GPP_E00 | 0x0E000601
+GPIO_CFG_DATA.GpioPinConfig0_GPP_E03 | 0x03148DE1
+GPIO_CFG_DATA.GpioPinConfig1_GPP_E03 | 0x0E030619
+GPIO_CFG_DATA.GpioPinConfig0_GPP_E07 | 0x05128DA1
+GPIO_CFG_DATA.GpioPinConfig1_GPP_E07 | 0x0E070601
+GPIO_CFG_DATA.GpioPinConfig0_GPP_E22 | 0x05008385
+GPIO_CFG_DATA.GpioPinConfig1_GPP_E22 | 0x0E160001
+GPIO_CFG_DATA.GpioPinConfig0_GPP_E23 | 0x0500E281
+GPIO_CFG_DATA.GpioPinConfig1_GPP_E23 | 0x0E170001
+GPIO_CFG_DATA.GpioPinConfig0_GPP_F07 | 0x0500E2A1
+GPIO_CFG_DATA.GpioPinConfig1_GPP_F07 | 0x0C070001
+GPIO_CFG_DATA.GpioPinConfig0_GPP_D06 | 0x00008383
+GPIO_CFG_DATA.GpioPinConfig1_GPP_D06 | 0x08060001
+GPIO_CFG_DATA.GpioPinConfig0_GPP_D12 | 0x0100E281
+GPIO_CFG_DATA.GpioPinConfig1_GPP_D12 | 0x080C0001
+GPIO_CFG_DATA.GpioPinConfig0_GPP_D13 | 0x03148DA1
+GPIO_CFG_DATA.GpioPinConfig1_GPP_D13 | 0x080D0601
+PLAT_NAME_CFG_DATA.PlatformName | 'AzbCrb'
+GEN_CFG_DATA.PayloadId | 'LINX'
+MEMORY_CFG_DATA.SpdAddressTable | { 0xa8, 0x00, 0xa8, 0x00, 0xa8, 0x00, 0xa8, 0x00, 0xa8, 0x00, 0xa8, 0x00, 0xa8, 0x00, 0xa8, 0x00 }
+MEMORY_CFG_DATA.SpdDataSel000 | 0x0
+MEMORY_CFG_DATA.SpdDataSel010 | 0x0
+MEMORY_CFG_DATA.SpdDataSel020 | 0x0
+MEMORY_CFG_DATA.SpdDataSel030 | 0x0
+MEMORY_CFG_DATA.SpdDataSel100 | 0x0
+MEMORY_CFG_DATA.SpdDataSel101 | 0x0
+MEMORY_CFG_DATA.SpdDataSel110 | 0x0
+MEMORY_CFG_DATA.SpdDataSel120 | 0x0
+MEMORY_CFG_DATA.SpdDataSel130 | 0x0
+MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch0 | { 0x04, 0x01, 0x07, 0x06, 0x00, 0x02, 0x05, 0x03, 0x08, 0x0f, 0x0e, 0x09, 0x0a, 0x0d, 0x0c, 0x0b }
+MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch1 | { 0x00, 0x05, 0x02, 0x07, 0x04, 0x03, 0x01, 0x06, 0x0c, 0x0a, 0x0d, 0x08, 0x0f, 0x0b, 0x0e, 0x09 }
+MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch2 | { 0x01, 0x03, 0x02, 0x00, 0x07, 0x04, 0x06, 0x05, 0x0c, 0x09, 0x0a, 0x08, 0x0d, 0x0b, 0x0e, 0x0f }
+MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch3 | { 0x0f, 0x0c, 0x0b, 0x0a, 0x0e, 0x08, 0x09, 0x0d, 0x07, 0x03, 0x06, 0x00, 0x04, 0x01, 0x05, 0x02 }
+MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch0 | { 0x04, 0x01, 0x07, 0x06, 0x00, 0x02, 0x05, 0x03, 0x08, 0x0f, 0x0e, 0x09, 0x0a, 0x0d, 0x0c, 0x0b }
+MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch1 | { 0x00, 0x05, 0x02, 0x07, 0x04, 0x03, 0x01, 0x06, 0x0c, 0x0a, 0x0d, 0x08, 0x0f, 0x0b, 0x0e, 0x09 }
+MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch2 | { 0x01, 0x03, 0x02, 0x00, 0x07, 0x04, 0x06, 0x05, 0x0c, 0x09, 0x0a, 0x08, 0x0d, 0x0b, 0x0e, 0x0f }
+MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch3 | { 0x0f, 0x0c, 0x0b, 0x0a, 0x0e, 0x08, 0x09, 0x0d, 0x07, 0x03, 0x06, 0x00, 0x04, 0x01, 0x05, 0x02 }
+MEMORY_CFG_DATA.DqsMapCpu2DramMc1Ch3 | { 1, 0}
+MEMORY_CFG_DATA.DqsMapCpu2DramMc0Ch3 | { 1, 0}
+MEMORY_CFG_DATA.DqPinsInterleaved | 0x0
+MEMORY_CFG_DATA.PlatformMemorySize | 0x8391000
+MEMORY_CFG_DATA.BootFrequency | 0x02
+MEMORY_CFG_DATA.ActiveCoreCount | 0x00
+MEMORY_CFG_DATA.SinitMemorySize | 0x0
+MEMORY_CFG_DATA.TxtHeapMemorySize | 0x0
+MEMORY_CFG_DATA.BiosAcmBase | 0xFFA40000
+MEMORY_CFG_DATA.PcieRpEnableMask | 0xFFFFFF
+MEMORY_CFG_DATA.PcieClkSrcUsage | { 0x04, 0x05, 0x06, 0x07, 0xff, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
+MEMORY_CFG_DATA.PcieClkSrcClkReq | { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0xff, 0xff }
+MEMORY_CFG_DATA.CpuPcieRpEnableMask | 0x1
+MEMORY_CFG_DATA.IpuLaneUsed | { 0x04, 0x01, 0x02, 0x04, 0x04, 0x04, 0x00, 0x00 }
+MEMORY_CFG_DATA.CsiSpeed | { 0x02, 0x01, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00 }
+MEMORY_CFG_DATA.CpuDmiHwEqGen3CoeffListCm | { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
+MEMORY_CFG_DATA.CpuDmiHwEqGen3CoeffListCp | { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
+MEMORY_CFG_DATA.CpuDmiHwEqGen4CoeffListCm | { 0x00, 0x0e, 0x0a, 0x07, 0x07, 0x07, 0x07, 0x07 }
+MEMORY_CFG_DATA.CpuDmiHwEqGen4CoeffListCp | { 0x00, 0x07, 0x06, 0x07, 0x07, 0x07, 0x07, 0x07 }
+MEMORY_CFG_DATA.TcssItbtPcie0En | 0x1
+MEMORY_CFG_DATA.TcssItbtPcie1En | 0x1
+MEMORY_CFG_DATA.TcssItbtPcie2En | 0x1
+MEMORY_CFG_DATA.TcssItbtPcie3En | 0x1
+MEMORY_CFG_DATA.TcssXhciEn | 0x1
+MEMORY_CFG_DATA.TcssDma0En | 0x1
+MEMORY_CFG_DATA.TcssDma1En | 0x1
+MEMORY_CFG_DATA.UsbTcPortEnPreMem | 0x3
+MEMORY_CFG_DATA.UserBd | 0x0
+MEMORY_CFG_DATA.EnableC6Dram | 0x00
+MEMORY_CFG_DATA.BdatEnable | 0x0
+MEMORY_CFG_DATA.BiosSize | 0x4000
+SILICON_CFG_DATA.EnableItbm | 0x01
+SILICON_CFG_DATA.PchDmiAspmCtrl | 0x04
+SILICON_CFG_DATA.CpuPcieRpAspm | { 0x00, 0x02, 0x02, 0x00 }
+SILICON_CFG_DATA.CpuPcieRpPtmEnabled | { 0x01, 0x01, 0x01, 0x00 }
+SILICON_CFG_DATA.SataLedEnable | 0x00
+SILICON_CFG_DATA.SataPortsDevSlp | { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
+SILICON_CFG_DATA.PortUsb30Enable | { 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
+SILICON_CFG_DATA.Usb2OverCurrentPin | { 0x04, 0x05, 0xff, 0xff, 0x02, 0x02, 0xff, 0xff, 0xff, 0xff, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07 }
+SILICON_CFG_DATA.Usb3OverCurrentPin | { 0x02, 0x02, 0xff, 0xff, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04 }
+SILICON_CFG_DATA.Usb2PhyPetxiset | { 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
+SILICON_CFG_DATA.Usb2PhyPredeemp | { 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
+SILICON_CFG_DATA.SerialIoUartMode | { 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
+SILICON_CFG_DATA.SerialIoUartAutoFlow | { 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 }
+SILICON_CFG_DATA.SerialIoI2cMode | { 0x01, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00 }
+SILICON_CFG_DATA.CpuUsb3OverCurrentPin | { 0x04, 0x05, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }
+SILICON_CFG_DATA.PchIshI2cEnable | { 0x01, 0x01, 0x00 }
+SILICON_CFG_DATA.PchIshGpEnable | { 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01 }
+SILICON_CFG_DATA.PcieRpAspm | { 0x04, 0x00, 0x04, 0x00, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x04, 0x04, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 }
+SILICON_CFG_DATA.PtmEnabled | { 0x01, 0x01, 0x01, 0x01 }
+SILICON_CFG_DATA.CpuPcieRpMultiVcEnabled | { 0x01, 0x00, 0x00, 0x00 }
+POWER_CFG_DATA.TccActivationOffset | 0x0A
+POWER_CFG_DATA.TurboMode | 0x00
+POWER_CFG_DATA.EnergyEfficientTurbo | 0x01
+POWER_CFG_DATA.MaxRatio | 0x04
+POWER_CFG_DATA.PsysPmax | 0x0
+POWER_CFG_DATA.ImonSlope | { 0x00, 0x00, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
+POWER_CFG_DATA.TdcEnable | { 0x01, 0x01, 0x01, 0x00, 0x00 }
+PEP_CFG_DATA.PepPcieDg | 0x1
+PEP_CFG_DATA.PepUfs0 | 0x1
+PEP_CFG_DATA.PepUfs1 | 0x1
+CAPSULE_INFO_CFG_DATA.DevInstance | 0x1
diff --git a/Platform/AlderlakeBoardPkg/CfgData/CfgData_BootOption_Azb.yaml b/Platform/AlderlakeBoardPkg/CfgData/CfgData_BootOption_Azb.yaml
new file mode 100644
index 00000000..140ce9b1
--- /dev/null
+++ b/Platform/AlderlakeBoardPkg/CfgData/CfgData_BootOption_Azb.yaml
@@ -0,0 +1,20 @@
+## @file
+#
+# Slim Bootloader CFGDATA Option File.
+#
+# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+- $ACTION :
+ page : OS
+# usb
+- !expand { BOOT_OPTION_TMPL : [ 0 , 0 , 0 , 5 , 0 , 0xFF , 1 , 1 , '/boot/sbl_os' ] }
+- !expand { BOOT_OPTION_TMPL : [ 1 , 0 , 0 , 5 , 1 , 0xFF , 1 , 1 , '/boot/sbl_os' ] }
+# nvme
+- !expand { BOOT_OPTION_TMPL : [ 2 , 0 , 0 , 6 , 0 , 0x0 , 1 , 1 , '/boot/sbl_os' ] }
+- !expand { BOOT_OPTION_TMPL : [ 3 , 0 , 0 , 6 , 1 , 0x0 , 1 , 1 , '/boot/sbl_os' ] }
+# ufs
+- !expand { BOOT_OPTION_TMPL : [ 4 , 0 , 0 , 3 , 1 , 0x0 , 1 , 1 , '/boot/sbl_os' ] }
diff --git a/Platform/AlderlakeBoardPkg/CfgData/CfgData_Gpio_Azb.yaml b/Platform/AlderlakeBoardPkg/CfgData/CfgData_Gpio_Azb.yaml
new file mode 100644
index 00000000..e1ab61d6
--- /dev/null
+++ b/Platform/AlderlakeBoardPkg/CfgData/CfgData_Gpio_Azb.yaml
@@ -0,0 +1,270 @@
+## @file
+#
+# Slim Bootloader CFGDATA Option File.
+#
+# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+- $ACTION :
+ page : GIO
+- GPIO_CFG_DATA :
+ - !expand { CFGHDR_TMPL : [ GPIO_CFG_DATA, 0x400, 1, 0 ] }
+ - GPIO_CFG_HDR :
+ - GpioHeaderSize :
+ length : 0x01
+ value : _LENGTH_GPIO_CFG_HDR_
+ - GpioBaseTableId :
+ length : 0x01
+ value : 0xFF
+ - GpioItemSize :
+ length : 0x02
+ value : 8
+ - GpioItemCount :
+ length : 0x02
+ value : (_LENGTH_GPIO_CFG_DATA_ - _LENGTH_GPIO_CFG_HDR_ - 8) / 8
+ # Bit start offset within each GPIO entry array to identify a GPIO pin uniquely. EX: GPIO group id + pad id
+ # Offset is 2nd DWORD BIT16 = 1 * 32 + 16 = 48
+ - GpioItemIdBitOff :
+ length : 0x01
+ value : 48
+ # Bit length within each GPIO entry array to identify a GPIO pin uniquely.
+ # Length is 2nd DWORD BIT16 to BIT28 = 13
+ - GpioItemIdBitLen :
+ length : 0x01
+ value : 13
+ # Bit offset within each GPIO entry array to indicate SKIP a GPIO programming
+ # Offset is 2nd DWORD BIT31 = 63
+ - GpioItemValidBitOff :
+ length : 0x01
+ value : 63
+ - GpioItemUnused :
+ length : 0x01
+ value : 0
+ # Need 1 bit per GPIO. So this mask byte length needs to be at least (GpioNumber + 7) / 8
+ # Padding can be added to let the whole length aligned at DWORD boundary
+ - GpioBaseTableBitMask :
+ length : 38
+ value : {0}
+ - GpioTableData :
+ length : 0
+ value : 0
+ # The GrpIdx of GpioPinConfig1 is based on mPchLpGpioGroupInfo in GpioSiLib.c
+ # Refer to PadGroup options in CfgData_PayloadSelection_Azb.yaml
+ - !expand { GPIO_TMPL : [ GPP_R00, 0x0350A383, 0x83002019 ] }
+ - !expand { GPIO_TMPL : [ GPP_R01, 0x0350A383, 0x83012019 ] }
+ - !expand { GPIO_TMPL : [ GPP_R02, 0x0350A383, 0x83022019 ] }
+ - !expand { GPIO_TMPL : [ GPP_R03, 0x0350A383, 0x83032019 ] }
+ - !expand { GPIO_TMPL : [ GPP_R04, 0x0350A383, 0x83042019 ] }
+ - !expand { GPIO_TMPL : [ GPP_R05, 0x0350A383, 0x83052009 ] }
+ - !expand { GPIO_TMPL : [ GPP_R06, 0x0350A383, 0x83062001 ] }
+ - !expand { GPIO_TMPL : [ GPP_R07, 0x0350A381, 0x83072001 ] }
+ - !expand { GPIO_TMPL : [ GPP_R08, 0x0350A385, 0x83082001 ] }
+ - !expand { GPIO_TMPL : [ GPP_R09, 0x0350A385, 0x83092001 ] }
+ - !expand { GPIO_TMPL : [ GPP_R10, 0x0550A581, 0x830A2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_R11, 0x0550E281, 0x830B2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_R12, 0x0350A383, 0x830C2019 ] }
+ - !expand { GPIO_TMPL : [ GPP_R13, 0x0350E281, 0x830D2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_R14, 0x0550A281, 0x830E2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_R15, 0x0350A381, 0x830F2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_R16, 0x0350A383, 0x83102001 ] }
+ - !expand { GPIO_TMPL : [ GPP_R17, 0x0350A381, 0x83112001 ] }
+ - !expand { GPIO_TMPL : [ GPP_R18, 0x0350A383, 0x83122001 ] }
+ - !expand { GPIO_TMPL : [ GPP_R19, 0x0350A381, 0x83132001 ] }
+ - !expand { GPIO_TMPL : [ GPP_R20, 0x0350A381, 0x83142001 ] }
+ - !expand { GPIO_TMPL : [ GPP_R21, 0x0350A381, 0x83152001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B00, 0x0550E281, 0x80002001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B01, 0x0550E281, 0x80012001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B02, 0x00348DA1, 0x80022601 ] }
+ - !expand { GPIO_TMPL : [ GPP_B03, 0x000062E1, 0x80032601 ] }
+ - !expand { GPIO_TMPL : [ GPP_B04, 0x0350A383, 0x80042001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B05, 0x0350A383, 0x80052001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B06, 0x0350A383, 0x80062001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B07, 0x0350A383, 0x80072001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B08, 0x0350A383, 0x80082001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B09, 0x0350A383, 0x80092001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B10, 0x0350A383, 0x800A2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B11, 0x0350A383, 0x800B2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B12, 0x0550E281, 0x800C2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B13, 0x0550E281, 0x800D2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B14, 0x0550E281, 0x800E2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B15, 0x0550E281, 0x800F2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B16, 0x0350A383, 0x80102001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B17, 0x0350A283, 0x80112001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B18, 0x0350A383, 0x80122001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B19, 0x0314AD83, 0x80132601 ] }
+ - !expand { GPIO_TMPL : [ GPP_B20, 0x0350A383, 0x80142001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B21, 0x0350A383, 0x80152001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B22, 0x0350A383, 0x80162001 ] }
+ - !expand { GPIO_TMPL : [ GPP_B23, 0x0350A281, 0x80172001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H00, 0x0350A383, 0x87002001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H01, 0x0350A383, 0x87012001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H02, 0x0550E281, 0x87022001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H03, 0x0350A383, 0x87032001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H04, 0x0350A383, 0x87042001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H05, 0x0550E281, 0x87052001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H06, 0x0150A383, 0x87062001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H07, 0x0150A383, 0x87072001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H08, 0x0538AD81, 0x87082001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H09, 0x0350A381, 0x87092001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H10, 0x0150A281, 0x870A2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H11, 0x0150A281, 0x870B2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H12, 0x0518AD81, 0x870C2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H13, 0x0550E281, 0x870D2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H14, 0x0314AD81, 0x870E2601 ] }
+ - !expand { GPIO_TMPL : [ GPP_H15, 0x0550E281, 0x870F2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H16, 0x0350A383, 0x87102001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H17, 0x0350A383, 0x87112001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H18, 0x0350A383, 0x87122001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H19, 0x0350A383, 0x87132001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H20, 0x0350A381, 0x87142001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H21, 0x0350A381, 0x87152001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H22, 0x0350E281, 0x87162001 ] }
+ - !expand { GPIO_TMPL : [ GPP_H23, 0x0314AD81, 0x87172601 ] }
+ - !expand { GPIO_TMPL : [ GPD00, 0x0750A383, 0x85002019 ] }
+ - !expand { GPIO_TMPL : [ GPD01, 0x0750A383, 0x8501201F ] }
+ - !expand { GPIO_TMPL : [ GPD02, 0x0750A383, 0x8502201F ] }
+ - !expand { GPIO_TMPL : [ GPD03, 0x0750A383, 0x85032019 ] }
+ - !expand { GPIO_TMPL : [ GPD04, 0x0750A283, 0x85042001 ] }
+ - !expand { GPIO_TMPL : [ GPD05, 0x0750A283, 0x85052001 ] }
+ - !expand { GPIO_TMPL : [ GPD06, 0x0750A283, 0x85062001 ] }
+ - !expand { GPIO_TMPL : [ GPD07, 0x0750E281, 0x85072001 ] }
+ - !expand { GPIO_TMPL : [ GPD08, 0x0750A383, 0x85082001 ] }
+ - !expand { GPIO_TMPL : [ GPD09, 0x0750A283, 0x85092001 ] }
+ - !expand { GPIO_TMPL : [ GPD10, 0x0750A283, 0x850A2001 ] }
+ - !expand { GPIO_TMPL : [ GPD11, 0x0750A283, 0x850B2001 ] }
+ - !expand { GPIO_TMPL : [ GPD12, 0x0750A283, 0x850C2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_A00, 0x0350A383, 0x82002001 ] }
+ - !expand { GPIO_TMPL : [ GPP_A01, 0x0350A383, 0x82012019 ] }
+ - !expand { GPIO_TMPL : [ GPP_A02, 0x0350A383, 0x82022001 ] }
+ - !expand { GPIO_TMPL : [ GPP_A03, 0x0350A383, 0x82032019 ] }
+ - !expand { GPIO_TMPL : [ GPP_A04, 0x0350A383, 0x82040000 ] }
+ - !expand { GPIO_TMPL : [ GPP_A05, 0x0350A383, 0x82052019 ] }
+ - !expand { GPIO_TMPL : [ GPP_A06, 0x0350A383, 0x82062001 ] }
+ - !expand { GPIO_TMPL : [ GPP_A07, 0x0350A383, 0x82072001 ] }
+ - !expand { GPIO_TMPL : [ GPP_A08, 0x0350A381, 0x82082001 ] }
+ - !expand { GPIO_TMPL : [ GPP_A09, 0x0550E281, 0x82092001 ] }
+ - !expand { GPIO_TMPL : [ GPP_A10, 0x0550E281, 0x820A2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_A11, 0x0350A381, 0x820B2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_A12, 0x0350A381, 0x820C2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_A13, 0x0350A381, 0x820D2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_A14, 0x0350A381, 0x820E2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_A15, 0x0350A381, 0x820F2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_A16, 0x0350A381, 0x82102001 ] }
+ - !expand { GPIO_TMPL : [ GPP_A17, 0x0350A381, 0x82112001 ] }
+ - !expand { GPIO_TMPL : [ GPP_A18, 0x0350A381, 0x82122001 ] }
+ - !expand { GPIO_TMPL : [ GPP_A19, 0x0350A381, 0x82132001 ] }
+ - !expand { GPIO_TMPL : [ GPP_A20, 0x0350A381, 0x82142001 ] }
+ - !expand { GPIO_TMPL : [ GPP_A21, 0x0350A381, 0x82152001 ] }
+ - !expand { GPIO_TMPL : [ GPP_A22, 0x0350A381, 0x82162001 ] }
+ - !expand { GPIO_TMPL : [ GPP_A23, 0x0350A381, 0x82172001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C00, 0x0350A383, 0x8B002001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C01, 0x0350A383, 0x8B012001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C02, 0x0550E281, 0x8B022001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C03, 0x0350A383, 0x8B032001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C04, 0x0350A383, 0x8B042001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C05, 0x0550E281, 0x8B052001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C06, 0x0150A383, 0x8B062001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C07, 0x0150A383, 0x8B072001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C08, 0x0538AD81, 0x8B082001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C09, 0x0350A381, 0x8B092001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C10, 0x0150A281, 0x8B0A2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C11, 0x0150A281, 0x8B0B2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C12, 0x0518AD81, 0x8B0C2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C13, 0x0550E281, 0x8B0D2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C14, 0x0314AD81, 0x8B0E2601 ] }
+ - !expand { GPIO_TMPL : [ GPP_C15, 0x0550E281, 0x8B0F2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C16, 0x0350A383, 0x8B102001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C17, 0x0350A383, 0x8B112001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C18, 0x0350A383, 0x8B122001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C19, 0x0350A383, 0x8B132001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C20, 0x0350A381, 0x8B142001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C21, 0x0350A381, 0x8B152001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C22, 0x0350E281, 0x8B162001 ] }
+ - !expand { GPIO_TMPL : [ GPP_C23, 0x0314AD81, 0x8B172601 ] }
+ - !expand { GPIO_TMPL : [ GPP_S00, 0x0350A383, 0x86002001 ] }
+ - !expand { GPIO_TMPL : [ GPP_S01, 0x0350A383, 0x8601201F ] }
+ - !expand { GPIO_TMPL : [ GPP_S02, 0x0350A283, 0x8602201F ] }
+ - !expand { GPIO_TMPL : [ GPP_S03, 0x0350A383, 0x8603201F ] }
+ - !expand { GPIO_TMPL : [ GPP_S04, 0x0350A383, 0x86042001 ] }
+ - !expand { GPIO_TMPL : [ GPP_S05, 0x0550A281, 0x86052001 ] }
+ - !expand { GPIO_TMPL : [ GPP_S06, 0x0550E281, 0x86062001 ] }
+ - !expand { GPIO_TMPL : [ GPP_S07, 0x0350A381, 0x86072001 ] }
+ - !expand { GPIO_TMPL : [ GPP_E00, 0x0350A381, 0x8E002001 ] }
+ - !expand { GPIO_TMPL : [ GPP_E01, 0x0350A381, 0x8E012001 ] }
+ - !expand { GPIO_TMPL : [ GPP_E02, 0x0350A381, 0x8E022001 ] }
+ - !expand { GPIO_TMPL : [ GPP_E03, 0x0518A581, 0x8E032001 ] }
+ - !expand { GPIO_TMPL : [ GPP_E04, 0x0150A383, 0x8E042001 ] }
+ - !expand { GPIO_TMPL : [ GPP_E05, 0x0150A383, 0x8E052001 ] }
+ - !expand { GPIO_TMPL : [ GPP_E06, 0x0550E281, 0x8E062001 ] }
+ - !expand { GPIO_TMPL : [ GPP_E07, 0x0512AD81, 0x8E072001 ] }
+ - !expand { GPIO_TMPL : [ GPP_E08, 0x0550E281, 0x8E082001 ] }
+ - !expand { GPIO_TMPL : [ GPP_E09, 0x0350A383, 0x8E092001 ] }
+ - !expand { GPIO_TMPL : [ GPP_E10, 0x0350A381, 0x8E0A2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_E11, 0x0350A381, 0x8E0B2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_E12, 0x0350A381, 0x8E0C2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_E13, 0x0350A381, 0x8E0D2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_E14, 0x0350A383, 0x8E0E2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_E15, 0x0350A383, 0x8E0F2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_E16, 0x0350A385, 0x8E102001 ] }
+ - !expand { GPIO_TMPL : [ GPP_E17, 0x0538AD81, 0x8E112001 ] }
+ - !expand { GPIO_TMPL : [ GPP_E18, 0x0350A38B, 0x8E12201F ] }
+ - !expand { GPIO_TMPL : [ GPP_E19, 0x0350A28B, 0x8E13201F ] }
+ - !expand { GPIO_TMPL : [ GPP_E20, 0x0350A38B, 0x8E14201F ] }
+ - !expand { GPIO_TMPL : [ GPP_E21, 0x0350A28B, 0x8E15201F ] }
+ - !expand { GPIO_TMPL : [ GPP_E22, 0x0350A28B, 0x8E16201F ] }
+ - !expand { GPIO_TMPL : [ GPP_E23, 0x0350A28B, 0x8E17201F ] }
+ - !expand { GPIO_TMPL : [ GPP_F00, 0x0350A383, 0x8C002001 ] }
+ - !expand { GPIO_TMPL : [ GPP_F01, 0x0350A383, 0x8C012019 ] }
+ - !expand { GPIO_TMPL : [ GPP_F02, 0x0350A383, 0x8C022001 ] }
+ - !expand { GPIO_TMPL : [ GPP_F03, 0x0350A383, 0x8C032019 ] }
+ - !expand { GPIO_TMPL : [ GPP_F04, 0x0314AD81, 0x8C042601 ] }
+ - !expand { GPIO_TMPL : [ GPP_F05, 0x0314AD81, 0x8C052601 ] }
+ - !expand { GPIO_TMPL : [ GPP_F06, 0x0350A381, 0x8C062001 ] }
+ - !expand { GPIO_TMPL : [ GPP_F07, 0x0550E281, 0x8C072001 ] }
+ - !expand { GPIO_TMPL : [ GPP_F08, 0x0550E281, 0x8C082001 ] }
+ - !expand { GPIO_TMPL : [ GPP_F09, 0x0550E281, 0x8C092001 ] }
+ - !expand { GPIO_TMPL : [ GPP_F10, 0x0550E281, 0x8C0A2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_F11, 0x0350A381, 0x8C0B2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_F12, 0x0350A381, 0x8C0C2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_F13, 0x0350A381, 0x8C0D2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_F14, 0x0350A381, 0x8C0E2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_F15, 0x0350A381, 0x8C0F2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_F16, 0x0350A381, 0x8C102001 ] }
+ - !expand { GPIO_TMPL : [ GPP_F17, 0x0550E283, 0x8C112001 ] }
+ - !expand { GPIO_TMPL : [ GPP_F18, 0x05002483, 0x8C122001 ] }
+ - !expand { GPIO_TMPL : [ GPP_F19, 0x0350A383, 0x8C132001 ] }
+ - !expand { GPIO_TMPL : [ GPP_F20, 0x0550A281, 0x8C142001 ] }
+ - !expand { GPIO_TMPL : [ GPP_F21, 0x0550A581, 0x8C152001 ] }
+ - !expand { GPIO_TMPL : [ GPP_F22, 0x0350A381, 0x8C162001 ] }
+ - !expand { GPIO_TMPL : [ GPP_F23, 0x0350A381, 0x8C172001 ] }
+ - !expand { GPIO_TMPL : [ GPP_D00, 0x0350A383, 0x88002001 ] }
+ - !expand { GPIO_TMPL : [ GPP_D01, 0x0350A383, 0x88012001 ] }
+ - !expand { GPIO_TMPL : [ GPP_D02, 0x0350A383, 0x88022001 ] }
+ - !expand { GPIO_TMPL : [ GPP_D03, 0x0350A383, 0x88032001 ] }
+ - !expand { GPIO_TMPL : [ GPP_D04, 0x0350A383, 0x88042001 ] }
+ - !expand { GPIO_TMPL : [ GPP_D05, 0x0350A383, 0x88052001 ] }
+ - !expand { GPIO_TMPL : [ GPP_D06, 0x0350A383, 0x88062001 ] }
+ - !expand { GPIO_TMPL : [ GPP_D07, 0x0350A383, 0x88072001 ] }
+ - !expand { GPIO_TMPL : [ GPP_D08, 0x0350A383, 0x88082001 ] }
+ - !expand { GPIO_TMPL : [ GPP_D09, 0x0350A38B, 0x8809201F ] }
+ - !expand { GPIO_TMPL : [ GPP_D10, 0x0350A28B, 0x880A201F ] }
+ - !expand { GPIO_TMPL : [ GPP_D11, 0x0350A38B, 0x880B201F ] }
+ - !expand { GPIO_TMPL : [ GPP_D12, 0x0350A28B, 0x880C201F ] }
+ - !expand { GPIO_TMPL : [ GPP_D13, 0x0350A381, 0x880D2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_D14, 0x0350A381, 0x880E2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_D15, 0x0350A381, 0x880F2001 ] }
+ - !expand { GPIO_TMPL : [ GPP_D16, 0x0550E281, 0x88102001 ] }
+ - !expand { GPIO_TMPL : [ GPP_D17, 0x0350A383, 0x88112001 ] }
+ - !expand { GPIO_TMPL : [ GPP_D18, 0x0350A383, 0x88122001 ] }
+ - !expand { GPIO_TMPL : [ GPP_D19, 0x0350A381, 0x88132001 ] }
+ - !expand { GPIO_TMPL : [ GPP_D20, 0x0550E281, 0x88142001 ] }
+ - !expand { GPIO_TMPL : [ GPP_D21, 0x0350A383, 0x88152001 ] }
+ - !expand { GPIO_TMPL : [ GPP_D22, 0x0350A383, 0x88162001 ] }
+ - !expand { GPIO_TMPL : [ GPP_D23, 0x0350A381, 0x88172001 ] }
+ - !expand { GPIO_TMPL : [ GPP_T00, 0x0350A387, 0x81002001 ] }
+ - !expand { GPIO_TMPL : [ GPP_T01, 0x0350A387, 0x81012001 ] }
+ - !expand { GPIO_TMPL : [ GPP_T02, 0x0350A387, 0x81022001 ] }
+ - !expand { GPIO_TMPL : [ GPP_T03, 0x0350A387, 0x81032001 ] }
diff --git a/Platform/AlderlakeBoardPkg/CfgData/CfgData_MemSpd_Azb.yaml b/Platform/AlderlakeBoardPkg/CfgData/CfgData_MemSpd_Azb.yaml
new file mode 100644
index 00000000..93282243
--- /dev/null
+++ b/Platform/AlderlakeBoardPkg/CfgData/CfgData_MemSpd_Azb.yaml
@@ -0,0 +1,26 @@
+## @file
+#
+# Slim Bootloader CFGDATA Option File.
+#
+# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+- $ACTION :
+ page : MEM_SPD:MEM:"MEM SPD"
+- $ACTION :
+ page : MEM_SPD
+- MEM_SPD0_CFG_DATA :
+ - !expand { CFGHDR_TMPL : [ MEM_SPD0_CFG_DATA, 0x8F0, 0, 0 ] }
+ - MemorySpdPtr0 :
+ name : Memory SPD Data 0
+ type : Table
+ option : >
+ 0:1:HEX, 1:1:HEX, 2:1:HEX, 3:1:HEX, 4:1:HEX, 5:1:HEX, 6:1:HEX, 7:1:HEX,
+ 8:1:HEX, 9:1:HEX, A:1:HEX, B:1:HEX, C:1:HEX, D:1:HEX, E:1:HEX, F:1:HEX
+ help : >
+ Pointer to SPD data in Memory
+ length : 0x200
+ value : {FILE: Spd_Data_Azb_LPDDR5_DR.bin}
diff --git a/Platform/AlderlakeBoardPkg/CfgData/CfgData_Memory.yaml b/Platform/AlderlakeBoardPkg/CfgData/CfgData_Memory.yaml
index d60a16ed..58884764 100644
--- a/Platform/AlderlakeBoardPkg/CfgData/CfgData_Memory.yaml
+++ b/Platform/AlderlakeBoardPkg/CfgData/CfgData_Memory.yaml
@@ -334,12 +334,12 @@
- ActiveSmallCoreCount :
name : Number of active small cores
type : Combo
- option : 0x0:Disable all small cores, 0x1:1, 0x2:2, 0x3:3, 0xff:Active all small cores
+ option : 0x0:Disable all small cores, 0x1:1, 0x2:2, 0x3:3, 0x4:4, 0x8:8, 0xff:Active all small cores
help : >
- Number of active small cores(Depends on Number of small cores). Default 0xFF means to active all system supported small cores. 0xFF- Active all small cores; 0- Disable all small cores; 1- 1; 2- 2; 3- 3;
+ Number of active small cores(Depends on Number of small cores). Default 0xFF means to active all system supported small cores. 0xFF- Active all small cores; 0- Disable all small cores; 1- 1; 2- 2; 3- 3; 4- 4;
length : 0x0001
value : 0xff
- - BiosSize :
+ - BiosSize :
name : BiosSize
type : EditNum, HEX, (0x0, 0xFFFF)
help : >
@@ -617,7 +617,7 @@
value : {0x04, 0x04, 0x04, 0x04, 0x02, 0x01, 0x04, 0x04}
- CsiSpeed :
name : Speed of each CSI port
- type : EditNum, HEX, (0x00,0xFFFF)
+ type : EditNum, HEX, (0x0, 0xFFFF)
option : 0x0:Sensor default, 0x1:<416Mbps, 0x2:<1.5Gbps, 0x3:<2Gbps, 0x4:<2.5Gbps, 0x5:<4Gbps, 0x6:>4Gbps
help : >
Speed of each CSI port
diff --git a/Platform/AlderlakeBoardPkg/CfgData/Spd_Data_Azb_LPDDR5_DR.bin b/Platform/AlderlakeBoardPkg/CfgData/Spd_Data_Azb_LPDDR5_DR.bin
new file mode 100644
index 00000000..d680c51c
Binary files /dev/null and b/Platform/AlderlakeBoardPkg/CfgData/Spd_Data_Azb_LPDDR5_DR.bin differ
diff --git a/Platform/AlderlakeBoardPkg/CfgData/Spd_Data_Azb_LPDDR5_SR.bin b/Platform/AlderlakeBoardPkg/CfgData/Spd_Data_Azb_LPDDR5_SR.bin
new file mode 100644
index 00000000..5de3e41b
Binary files /dev/null and b/Platform/AlderlakeBoardPkg/CfgData/Spd_Data_Azb_LPDDR5_SR.bin differ
diff --git a/Platform/AlderlakeBoardPkg/CfgData/Template_Spd.yaml b/Platform/AlderlakeBoardPkg/CfgData/Template_Spd.yaml
index 4bc570c2..d1393ddd 100644
--- a/Platform/AlderlakeBoardPkg/CfgData/Template_Spd.yaml
+++ b/Platform/AlderlakeBoardPkg/CfgData/Template_Spd.yaml
@@ -2,7 +2,7 @@
#
# Slim Bootloader CFGDATA Template File.
#
-# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2020 - 2023, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -12,7 +12,7 @@ SPD_TMPL: >
- SpdDataSel$(1)$(2)$(3) :
name : Spd Data MC$(1) CH$(2) DIMM$(3)
type : Combo
- option : 0:NONE, 1:SPD0, 2:SPD1, 3:SPD2, 4:SPD3
+ option : 0:NONE, 1:SPD0, 2:SPD1, 3:SPD2, 4:SPD3, 5:SPD4, 6:SPD5, 7:SPD6, 8:SPD7
help : >
Select which SPD data should be used for MC$(1) CH$(2) DIMM$(3).SPD0 and SPD1 are associated with configurable SPD data block from MEM SPD. SPD data will be used only when SpdAddressTable SPD Address are marked as 00
length : 0x01
diff --git a/Platform/AlderlakeBoardPkg/Include/PlatformBoardId.h b/Platform/AlderlakeBoardPkg/Include/PlatformBoardId.h
index 2df2803b..8865e7e2 100644
--- a/Platform/AlderlakeBoardPkg/Include/PlatformBoardId.h
+++ b/Platform/AlderlakeBoardPkg/Include/PlatformBoardId.h
@@ -54,6 +54,10 @@ Defines Platform BoardIds
#define BoardIdAdlSAdpSDdr5SODimmCrb 0x30
#define PLATFORM_ID_ADL_S_ADP_S_DDR5_SODIMM_CRB 0x1C
+// ArizonaBeach Boards
+#define BoardIdAzbLp5Crb2A 0x22
+#define PLATFORM_ID_AZB_LP5_CRB2A 0x09
+
// Test boards
#define BoardIdTestSDdr5UDimm1DRvp 0x39
#define PLATFORM_ID_TEST_S_DDR5_UDIMM_RVP 0x19
diff --git a/Platform/AlderlakeBoardPkg/Library/FspmUpdUpdateLib/FspmUpdUpdateLib.inf b/Platform/AlderlakeBoardPkg/Library/FspmUpdUpdateLib/FspmUpdUpdateLib.inf
index 7e52a0ba..09500a76 100644
--- a/Platform/AlderlakeBoardPkg/Library/FspmUpdUpdateLib/FspmUpdUpdateLib.inf
+++ b/Platform/AlderlakeBoardPkg/Library/FspmUpdUpdateLib/FspmUpdUpdateLib.inf
@@ -51,4 +51,4 @@
[FixedPcd]
gPlatformCommonLibTokenSpaceGuid.PcdTccEnabled
- gPlatformModuleTokenSpaceGuid.PcdFusaSupport
\ No newline at end of file
+ gPlatformModuleTokenSpaceGuid.PcdFusaSupport
diff --git a/Platform/AlderlakeBoardPkg/Library/FspmUpdUpdateLib/FspmUpdUpdateLibAzb.c b/Platform/AlderlakeBoardPkg/Library/FspmUpdUpdateLib/FspmUpdUpdateLibAzb.c
new file mode 100644
index 00000000..be3ed5a3
--- /dev/null
+++ b/Platform/AlderlakeBoardPkg/Library/FspmUpdUpdateLib/FspmUpdUpdateLibAzb.c
@@ -0,0 +1,397 @@
+/** @file
+
+ Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "BoardSaConfigPreMem.h"
+
+typedef enum {
+ DciDbcDisabled = 0x0,
+ DciDbcUsb2 = 0x1,
+ DciDbcUsb3 = 0x2,
+ DciDbcBoth = 0x3,
+ DciDbcNoChange = 0x4,
+ DciDbcMax
+} DCI_DBC_MODE;
+
+
+/**
+ Update FSP-M UPD config data.
+
+ @param FspmUpdPtr The pointer to the FSP-M UPD to be updated.
+
+**/
+VOID
+EFIAPI
+UpdateFspConfig (
+ IN VOID *FspmUpdPtr
+ )
+{
+ FSPM_UPD *FspmUpd;
+ FSP_M_CONFIG *Fspmcfg;
+ MEMORY_CFG_DATA *MemCfgData;
+ PLATFORM_DATA *PlatformData;
+ FEATURES_CFG_DATA *FeaturesCfgData;
+ SILICON_CFG_DATA *SiCfgData;
+ UINT16 PlatformId;
+ UINT8 SaDisplayConfigTable[16] = { 0 };
+ UINT8 Index;
+ UINT8 DebugPort;
+ UINT32 SpdData[9];
+ UINT32 CarBase;
+ UINT32 CarSize;
+ EFI_STATUS Status;
+
+ FspmUpd = (FSPM_UPD *)FspmUpdPtr;
+ Fspmcfg = &FspmUpd->FspmConfig;
+
+ Status = GetTempRamInfo (&CarBase, &CarSize);
+ ASSERT_EFI_ERROR (Status);
+ FspmUpd->FspmArchUpd.StackBase = CarBase \
+ + FixedPcdGet32 (PcdStage1StackBaseOffset) \
+ + FixedPcdGet32 (PcdStage1StackSize) \
+ + FixedPcdGet32 (PcdStage1DataSize);
+ FspmUpd->FspmArchUpd.StackSize = CarBase + CarSize - FspmUpd->FspmArchUpd.StackBase;
+ DEBUG ((DEBUG_INFO, "CAR Base 0x%X (0x%X)\n", CarBase, CarSize));
+ DEBUG ((DEBUG_INFO, "FSPM Stack Base=0x%X, Size=0x%X\n", FspmUpd->FspmArchUpd.StackBase, FspmUpd->FspmArchUpd.StackSize));
+
+ DEBUG ((DEBUG_INFO, "FSPM CfgData assignment\n"));
+ MemCfgData = (MEMORY_CFG_DATA *)FindConfigDataByTag (CDATA_MEMORY_TAG);
+ if (MemCfgData == NULL) {
+ CpuHalt ("Failed to find memory CFGDATA!");
+ return;
+ }
+ CopyMem (&Fspmcfg->SpdAddressTable, MemCfgData->SpdAddressTable, sizeof(MemCfgData->SpdAddressTable));
+
+ DebugPort = GetDebugPort ();
+ if (DebugPort < GetPchMaxSerialIoUartControllersNum ()) {
+ Fspmcfg->PcdDebugInterfaceFlags = BIT4 | BIT5;
+ Fspmcfg->SerialIoUartDebugControllerNumber = DebugPort;
+ Fspmcfg->SerialIoUartDebugMode = 4;
+ } else {
+ Fspmcfg->PcdDebugInterfaceFlags = BIT1;
+ if (DebugPort == 0xFF) {
+ Fspmcfg->PcdIsaSerialUartBase = 0;
+ } else {
+ Fspmcfg->PcdIsaSerialUartBase = 1;
+ }
+ }
+ Fspmcfg->PcdSerialDebugLevel = 0x5;
+
+ // Memory SPD Data
+ SpdData[0] = 0;
+ SpdData[1] = (UINT32)(UINTN) (((MEM_SPD0_CFG_DATA *)FindConfigDataByTag (CDATA_MEM_SPD0_TAG))->MemorySpdPtr0);
+
+ Fspmcfg->MemorySpdPtr000 = SpdData[MemCfgData->SpdDataSel000];
+ Fspmcfg->MemorySpdPtr001 = SpdData[MemCfgData->SpdDataSel001];
+ Fspmcfg->MemorySpdPtr010 = SpdData[MemCfgData->SpdDataSel010];
+ Fspmcfg->MemorySpdPtr011 = SpdData[MemCfgData->SpdDataSel011];
+ Fspmcfg->MemorySpdPtr020 = SpdData[MemCfgData->SpdDataSel020];
+ Fspmcfg->MemorySpdPtr021 = SpdData[MemCfgData->SpdDataSel021];
+ Fspmcfg->MemorySpdPtr030 = SpdData[MemCfgData->SpdDataSel030];
+ Fspmcfg->MemorySpdPtr031 = SpdData[MemCfgData->SpdDataSel031];
+ Fspmcfg->MemorySpdPtr100 = SpdData[MemCfgData->SpdDataSel100];
+ Fspmcfg->MemorySpdPtr101 = SpdData[MemCfgData->SpdDataSel101];
+ Fspmcfg->MemorySpdPtr110 = SpdData[MemCfgData->SpdDataSel110];
+ Fspmcfg->MemorySpdPtr111 = SpdData[MemCfgData->SpdDataSel111];
+ Fspmcfg->MemorySpdPtr120 = SpdData[MemCfgData->SpdDataSel120];
+ Fspmcfg->MemorySpdPtr121 = SpdData[MemCfgData->SpdDataSel121];
+ Fspmcfg->MemorySpdPtr130 = SpdData[MemCfgData->SpdDataSel130];
+ Fspmcfg->MemorySpdPtr131 = SpdData[MemCfgData->SpdDataSel131];
+
+ //Dq/Dqs Mapping arrays
+ CopyMem (&Fspmcfg->DqsMapCpu2DramMc0Ch0, MemCfgData->DqsMapCpu2DramMc0Ch0, sizeof(MemCfgData->DqsMapCpu2DramMc0Ch0));
+ CopyMem (&Fspmcfg->DqsMapCpu2DramMc0Ch1, MemCfgData->DqsMapCpu2DramMc0Ch1, sizeof(MemCfgData->DqsMapCpu2DramMc0Ch1));
+ CopyMem (&Fspmcfg->DqsMapCpu2DramMc0Ch2, MemCfgData->DqsMapCpu2DramMc0Ch2, sizeof(MemCfgData->DqsMapCpu2DramMc0Ch2));
+ CopyMem (&Fspmcfg->DqsMapCpu2DramMc0Ch3, MemCfgData->DqsMapCpu2DramMc0Ch3, sizeof(MemCfgData->DqsMapCpu2DramMc0Ch3));
+ CopyMem (&Fspmcfg->DqsMapCpu2DramMc1Ch0, MemCfgData->DqsMapCpu2DramMc1Ch0, sizeof(MemCfgData->DqsMapCpu2DramMc1Ch0));
+ CopyMem (&Fspmcfg->DqsMapCpu2DramMc1Ch1, MemCfgData->DqsMapCpu2DramMc1Ch1, sizeof(MemCfgData->DqsMapCpu2DramMc1Ch1));
+ CopyMem (&Fspmcfg->DqsMapCpu2DramMc1Ch2, MemCfgData->DqsMapCpu2DramMc1Ch2, sizeof(MemCfgData->DqsMapCpu2DramMc1Ch2));
+ CopyMem (&Fspmcfg->DqsMapCpu2DramMc1Ch3, MemCfgData->DqsMapCpu2DramMc1Ch3, sizeof(MemCfgData->DqsMapCpu2DramMc1Ch3));
+
+ CopyMem (&Fspmcfg->DqMapCpu2DramMc0Ch0, MemCfgData->DqMapCpu2DramMc0Ch0, sizeof(MemCfgData->DqMapCpu2DramMc0Ch0));
+ CopyMem (&Fspmcfg->DqMapCpu2DramMc0Ch1, MemCfgData->DqMapCpu2DramMc0Ch1, sizeof(MemCfgData->DqMapCpu2DramMc0Ch1));
+ CopyMem (&Fspmcfg->DqMapCpu2DramMc0Ch2, MemCfgData->DqMapCpu2DramMc0Ch2, sizeof(MemCfgData->DqMapCpu2DramMc0Ch2));
+ CopyMem (&Fspmcfg->DqMapCpu2DramMc0Ch3, MemCfgData->DqMapCpu2DramMc0Ch3, sizeof(MemCfgData->DqMapCpu2DramMc0Ch3));
+ CopyMem (&Fspmcfg->DqMapCpu2DramMc1Ch0, MemCfgData->DqMapCpu2DramMc1Ch0, sizeof(MemCfgData->DqMapCpu2DramMc1Ch0));
+ CopyMem (&Fspmcfg->DqMapCpu2DramMc1Ch1, MemCfgData->DqMapCpu2DramMc1Ch1, sizeof(MemCfgData->DqMapCpu2DramMc1Ch1));
+ CopyMem (&Fspmcfg->DqMapCpu2DramMc1Ch2, MemCfgData->DqMapCpu2DramMc1Ch2, sizeof(MemCfgData->DqMapCpu2DramMc1Ch2));
+ CopyMem (&Fspmcfg->DqMapCpu2DramMc1Ch3, MemCfgData->DqMapCpu2DramMc1Ch3, sizeof(MemCfgData->DqMapCpu2DramMc1Ch3));
+
+ Fspmcfg->DqPinsInterleaved = MemCfgData->DqPinsInterleaved;
+
+ //RComp
+ Fspmcfg->RcompResistor = MemCfgData->RcompResistor;
+ CopyMem (&Fspmcfg->RcompTarget, MemCfgData->RcompTarget, sizeof(MemCfgData->RcompTarget));
+
+ // Mem cfg
+ Fspmcfg->RmtPerTask = MemCfgData->RmtPerTask;
+ Fspmcfg->MrcSafeConfig = MemCfgData->MrcSafeConfig;
+ Fspmcfg->ScramblerSupport = MemCfgData->ScramblerSupport;
+ Fspmcfg->EnhancedInterleave = MemCfgData->EnhancedInterleave;
+ Fspmcfg->RankInterleave = MemCfgData->RankInterleave;
+ Fspmcfg->RemapEnable = MemCfgData->RemapEnable;
+ Fspmcfg->ExitOnFailure = MemCfgData->ExitOnFailure;
+ Fspmcfg->ChHashEnable = MemCfgData->ChHashEnable;
+ Fspmcfg->ChHashInterleaveBit = MemCfgData->ChHashInterleaveBit;
+ Fspmcfg->ChHashMask = MemCfgData->ChHashMask;
+ Fspmcfg->MrcFastBoot = MemCfgData->MrcFastBoot;
+ // Maximum amt of memory needed
+ Fspmcfg->PlatformMemorySize = MemCfgData->PlatformMemorySize;
+ Fspmcfg->SafeMode = 0x0;
+
+ // Cpu Cfg
+ Fspmcfg->CpuRatio = MemCfgData->CpuRatio;
+ Fspmcfg->TmeEnable = MemCfgData->TmeEnable;
+ Fspmcfg->BootFrequency = MemCfgData->BootFrequency;
+ Fspmcfg->ActiveCoreCount = MemCfgData->ActiveCoreCount;
+ Fspmcfg->ActiveSmallCoreCount = MemCfgData->ActiveSmallCoreCount;
+ Fspmcfg->FClkFrequency = MemCfgData->FClkFrequency;
+ Fspmcfg->TxtDprMemoryBase = MemCfgData->TxtDprMemoryBase;
+ Fspmcfg->TxtDprMemorySize = MemCfgData->TxtDprMemorySize;
+ Fspmcfg->SinitMemorySize = MemCfgData->SinitMemorySize;
+ Fspmcfg->TxtHeapMemorySize = MemCfgData->TxtHeapMemorySize;
+ Fspmcfg->BiosSize = MemCfgData->BiosSize;
+ Fspmcfg->BiosAcmBase = MemCfgData->BiosAcmBase;
+ Fspmcfg->BiosGuard = 0x0; // Need to disable, else it will fails in FSPS
+ Fspmcfg->BiosGuardToolsInterface = 1;
+
+ // Skip CPU replacement check for embedded design to always enable fast boot
+ Fspmcfg->SkipCpuReplacementCheck = 1;
+
+ // MRC Training algorithms
+ Fspmcfg->RMT = MemCfgData->RMT;
+ Fspmcfg->BdatEnable = MemCfgData->BdatEnable;
+ Fspmcfg->BdatTestType = MemCfgData->BdatTestType;
+ Fspmcfg->RMC = MemCfgData->RMC;
+ Fspmcfg->MEMTST = MemCfgData->MEMTST;
+ Fspmcfg->ECT = MemCfgData->ECT;
+
+ // Pcie
+ Fspmcfg->PcieRpEnableMask = MemCfgData->PcieRpEnableMask;
+ CopyMem (Fspmcfg->PcieClkSrcUsage, MemCfgData->PcieClkSrcUsage, sizeof(MemCfgData->PcieClkSrcUsage));
+ CopyMem (Fspmcfg->PcieClkSrcClkReq, MemCfgData->PcieClkSrcClkReq, sizeof(MemCfgData->PcieClkSrcClkReq));
+
+ // Cpu Pcie
+ Fspmcfg->CpuPcieRpEnableMask = MemCfgData->CpuPcieRpEnableMask;
+ CopyMem (Fspmcfg->CpuPcieRpPcieSpeed, MemCfgData->CpuPcieRpPcieSpeed, sizeof(MemCfgData->CpuPcieRpPcieSpeed));
+ Fspmcfg->CpuPcieRpClockReqMsgEnable[0] = MemCfgData->CpuPcieRpClockReqMsgEnable[0];
+ Fspmcfg->CpuPcieRpClockReqMsgEnable[1] = MemCfgData->CpuPcieRpClockReqMsgEnable[1];
+ Fspmcfg->CpuPcieRpClockReqMsgEnable[2] = MemCfgData->CpuPcieRpClockReqMsgEnable[2];
+
+ Fspmcfg->SkipMbpHob = 0;
+ DEBUG ((DEBUG_INFO, "SkipMbpHob = 0x%x\n", Fspmcfg->SkipMbpHob));
+
+ // IBECC - removed in the latest FSP. Add them later when needed
+ Fspmcfg->Ibecc = MemCfgData->Ibecc;
+ Fspmcfg->IbeccOperationMode = MemCfgData->IbeccOperationMode;
+ for (Index = 0; Index < 8; Index++) {
+ Fspmcfg->IbeccProtectedRangeEnable[Index] = MemCfgData->IbeccProtectedRegionEnable[Index];
+ Fspmcfg->IbeccProtectedRangeBase[Index] = MemCfgData->IbeccProtectedRegionBase[Index];
+ if (MemCfgData->IbeccProtectedRegionMask[Index] > 0x03FFFFFF) {
+ MemCfgData->IbeccProtectedRegionMask[Index] = 0x03FFFFFF;
+ }
+ Fspmcfg->IbeccProtectedRangeMask[Index] = MemCfgData->IbeccProtectedRegionMask[Index];
+ }
+
+ // Vtd
+ PlatformData = (PLATFORM_DATA *)GetPlatformDataPtr ();
+ if (PlatformData != NULL) {
+ PlatformData->PlatformFeatures.VtdEnable = (!MemCfgData->VtdDisable) & FeaturePcdGet (PcdVtdEnabled);
+ Fspmcfg->VtdDisable = (UINT8)(!PlatformData->PlatformFeatures.VtdEnable);
+ if (PlatformData->PlatformFeatures.VtdEnable == 1) {
+ Fspmcfg->VtdIgdEnable = MemCfgData->VtdIgdEnable;
+ Fspmcfg->VtdIpuEnable = 0x1;
+ Fspmcfg->VtdIopEnable = 0x1;
+
+ Fspmcfg->VtdBaseAddress[0] = VTD_BASEADDRESS_0;
+ Fspmcfg->VtdBaseAddress[1] = 0x0;
+ Fspmcfg->VtdBaseAddress[2] = VTD_BASEADDRESS_2;
+
+ Fspmcfg->X2ApicOptOut = MemCfgData->X2ApicOptOut;
+ Fspmcfg->DmaBufferSize = MemCfgData->DmaBufferSize;
+ Fspmcfg->DmaControlGuarantee = MemCfgData->DmaControlGuarantee;
+ Fspmcfg->PreBootDmaMask = 0x1;
+ }
+ }
+
+ // Host Bridge
+ Fspmcfg->MmioSize = MemCfgData->MmioSize;
+ Fspmcfg->MmioSizeAdjustment = MemCfgData->MmioSizeAdjustment;
+
+ // Smbus
+ Fspmcfg->SmbusEnable = MemCfgData->SmbusEnable;
+ Fspmcfg->PchNumRsvdSmbusAddresses = MemCfgData->PchNumRsvdSmbusAddresses;
+ Fspmcfg->RsvdSmbusAddressTablePtr = MemCfgData->RsvdSmbusAddressTablePtr;
+
+ // Overclocking Cfg
+ Fspmcfg->RealtimeMemoryTiming = MemCfgData->RealtimeMemoryTiming;
+
+ // Tcc related settings
+ Fspmcfg->SaGv = MemCfgData->SaGv; // System Agent Geyserville - SAGV dynamically adjusts the system agent
+ // voltage and clock frequencies depending on power and performance requirements
+ Fspmcfg->DisPgCloseIdleTimeout = MemCfgData->DisPgCloseIdleTimeout; // controls Page Close Idle Timeout
+ Fspmcfg->PowerDownMode = MemCfgData->PowerDownMode; // controls command bus tristating during idle periods
+ Fspmcfg->WrcFeatureEnable = MemCfgData->WrcFeatureEnable;
+ Fspmcfg->HyperThreading = MemCfgData->HyperThreading;
+ Fspmcfg->GtClosEnable = MemCfgData->GtClosEnable;
+ Fspmcfg->VmxEnable = MemCfgData->VmxEnable;
+ Fspmcfg->Lp5BankMode = MemCfgData->Lp5BankMode;
+
+ // CSI port
+ CopyMem (Fspmcfg->IpuLaneUsed, MemCfgData->IpuLaneUsed, sizeof(MemCfgData->IpuLaneUsed));
+ CopyMem (Fspmcfg->CsiSpeed, MemCfgData->CsiSpeed, sizeof(MemCfgData->CsiSpeed));
+
+ // DMI cfg
+ Fspmcfg->DmiMaxLinkSpeed = MemCfgData->DmiMaxLinkSpeed;
+ Fspmcfg->DmiAspm = MemCfgData->DmiAspm;
+ Fspmcfg->DmiAspmCtrl = MemCfgData->DmiAspmCtrl;
+ Fspmcfg->DmiHweq = 0x2;
+ CopyMem (Fspmcfg->DmiGen3RootPortPreset, MemCfgData->DmiGen3RootPortPreset, sizeof(MemCfgData->DmiGen3RootPortPreset));
+ CopyMem (Fspmcfg->DmiGen3EndPointPreset, MemCfgData->DmiGen3EndPointPreset, sizeof(MemCfgData->DmiGen3EndPointPreset));
+ CopyMem (Fspmcfg->DmiGen3EndPointHint, MemCfgData->DmiGen3EndPointHint, sizeof(MemCfgData->DmiGen3EndPointHint));
+ Fspmcfg->DmiGen3Ltcpo[7] = 0x2;
+ for (Index = 0; Index < 8; Index++) {
+ Fspmcfg->DmiGen3Ltcpre[Index] = MemCfgData->DmiGen3Ltcpre[Index];
+ Fspmcfg->DmiGen3DsPortRxPreset[Index] = MemCfgData->DmiGen3DsPortRxPreset[Index];
+ Fspmcfg->DmiGen3DsPortTxPreset[Index] = MemCfgData->DmiGen3DsPortTxPreset[Index];
+ }
+ for (Index = 0; Index < 8; Index++) {
+ Fspmcfg->DmiGen4Ltcpo[Index] = 0x7;
+ }
+ CopyMem (Fspmcfg->CpuDmiHwEqGen3CoeffListCm, MemCfgData->CpuDmiHwEqGen3CoeffListCm, sizeof(MemCfgData->CpuDmiHwEqGen3CoeffListCm));
+ CopyMem (Fspmcfg->CpuDmiHwEqGen3CoeffListCp, MemCfgData->CpuDmiHwEqGen3CoeffListCp, sizeof(MemCfgData->CpuDmiHwEqGen3CoeffListCp));
+ CopyMem (Fspmcfg->CpuDmiHwEqGen4CoeffListCm, MemCfgData->CpuDmiHwEqGen4CoeffListCm, sizeof(MemCfgData->CpuDmiHwEqGen4CoeffListCm));
+ CopyMem (Fspmcfg->CpuDmiHwEqGen4CoeffListCp, MemCfgData->CpuDmiHwEqGen4CoeffListCp, sizeof(MemCfgData->CpuDmiHwEqGen4CoeffListCp));
+ CopyMem (Fspmcfg->PchDmiHwEqGen3CoeffListCm, MemCfgData->PchDmiHwEqGen3CoeffListCm, sizeof(MemCfgData->PchDmiHwEqGen3CoeffListCm));
+ CopyMem (Fspmcfg->PchDmiHwEqGen3CoeffListCp, MemCfgData->PchDmiHwEqGen3CoeffListCp, sizeof(MemCfgData->PchDmiHwEqGen3CoeffListCp));
+ Fspmcfg->Gen3EqPhase23Bypass = MemCfgData->Gen3EqPhase23Bypass;
+ Fspmcfg->Gen3EqPhase3Bypass = MemCfgData->Gen3EqPhase3Bypass;
+ Fspmcfg->Gen3LtcoEnable = MemCfgData->Gen3LtcoEnable;
+
+ // Tcss Dev enable bits
+ Fspmcfg->TcssItbtPcie0En = MemCfgData->TcssItbtPcie0En;
+ Fspmcfg->TcssItbtPcie1En = MemCfgData->TcssItbtPcie1En;
+ Fspmcfg->TcssItbtPcie2En = MemCfgData->TcssItbtPcie2En;
+ Fspmcfg->TcssItbtPcie3En = MemCfgData->TcssItbtPcie3En;
+ Fspmcfg->TcssXhciEn = MemCfgData->TcssXhciEn;
+ Fspmcfg->TcssDma0En = MemCfgData->TcssDma0En;
+ Fspmcfg->TcssDma1En = MemCfgData->TcssDma1En;
+ Fspmcfg->UsbTcPortEnPreMem = MemCfgData->UsbTcPortEnPreMem;
+
+ // Misc
+ Fspmcfg->UserBd = MemCfgData->UserBd;
+ Fspmcfg->EnableC6Dram = MemCfgData->EnableC6Dram;
+ Fspmcfg->TsegSize = MemCfgData->TsegSize;
+ Fspmcfg->SkipExtGfxScan = MemCfgData->SkipExtGfxScan;
+ Fspmcfg->LockPTMregs = MemCfgData->LockPTMregs;
+ Fspmcfg->CridEnable = 0x0;
+ Fspmcfg->Lfsr0Mask = 0xb;
+ Fspmcfg->Lfsr1Mask = 0xb;
+ Fspmcfg->RefreshPanicWm = 0x8;
+ Fspmcfg->RefreshHpWm = 0x7;
+
+ Fspmcfg->PlatformDebugConsent = MemCfgData->PlatformDebugConsent;
+ if (Fspmcfg->PlatformDebugConsent != 0) {
+ Fspmcfg->DciModphyPg = 0;
+ Fspmcfg->DciUsb3TypecUfpDbg = 2;
+ Fspmcfg->DebugInterfaceLockEnable = TRUE;
+ Fspmcfg->DciDbcMode = DciDbcNoChange;
+ Fspmcfg->DciEn = MemCfgData->DciEn;
+ Fspmcfg->CpuTraceHubMode = MemCfgData->CpuTraceHubMode;
+ Fspmcfg->PchTraceHubMode = MemCfgData->PchTraceHubMode;
+ Fspmcfg->CpuTraceHubMemReg0Size = MemCfgData->CpuTraceHubMemReg0Size;
+ Fspmcfg->CpuTraceHubMemReg1Size = MemCfgData->CpuTraceHubMemReg1Size;
+ Fspmcfg->PchTraceHubMemReg0Size = MemCfgData->PchTraceHubMemReg0Size;
+ Fspmcfg->PchTraceHubMemReg1Size = MemCfgData->PchTraceHubMemReg1Size;
+ }
+
+ PlatformId = GetPlatformId();
+ DEBUG((DEBUG_INFO, "PLATFORM_ID_AZB_LP5_CRB2A board Id %x .....\n", PlatformId));
+
+ Fspmcfg->DdiPortAConfig = SaDisplayConfigTable[0];
+ Fspmcfg->DdiPortBConfig = SaDisplayConfigTable[1];
+ Fspmcfg->DdiPortAHpd = SaDisplayConfigTable[2];
+ Fspmcfg->DdiPortBHpd = SaDisplayConfigTable[3];
+ Fspmcfg->DdiPortCHpd = SaDisplayConfigTable[4];
+ Fspmcfg->DdiPort1Hpd = SaDisplayConfigTable[5];
+ Fspmcfg->DdiPort2Hpd = SaDisplayConfigTable[6];
+ Fspmcfg->DdiPort3Hpd = SaDisplayConfigTable[7];
+ Fspmcfg->DdiPort4Hpd = SaDisplayConfigTable[8];
+ Fspmcfg->DdiPortADdc = SaDisplayConfigTable[9];
+ Fspmcfg->DdiPortBDdc = SaDisplayConfigTable[10];
+ Fspmcfg->DdiPortCDdc = SaDisplayConfigTable[11];
+ Fspmcfg->DdiPort1Ddc = SaDisplayConfigTable[12];
+ Fspmcfg->DdiPort2Ddc = SaDisplayConfigTable[13];
+ Fspmcfg->DdiPort3Ddc = SaDisplayConfigTable[14];
+ Fspmcfg->DdiPort4Ddc = SaDisplayConfigTable[15];
+
+ if (IsPchLp ()) {
+ switch (GetPlatformId ()) {
+ case PLATFORM_ID_AZB_LP5_CRB2A:
+ Fspmcfg->DdiPortBHpd = 0x1;
+ Fspmcfg->DmiHweq = 0x2;
+ Fspmcfg->PcieClkReqGpioMux[9] = 0x796e9000;
+ Fspmcfg->SkipCpuReplacementCheck = 0x0;
+ Fspmcfg->FirstDimmBitMask = 0;
+ Fspmcfg->FirstDimmBitMaskEcc = 0;
+ Fspmcfg->Lp5CccConfig = 0xFF;
+ Fspmcfg->GearRatio = 4;
+ Fspmcfg->DdrFreqLimit = 5200;
+ Fspmcfg->SaGv = MemCfgData->SaGv;
+ Fspmcfg->DisableMc0Ch0 = 1;
+ Fspmcfg->DisableMc0Ch1 = 1;
+ Fspmcfg->DisableMc0Ch2 = 1;
+ Fspmcfg->DisableMc0Ch3 = 1;
+ break;
+ default:
+ DEBUG ((DEBUG_INFO, "Unknown board for FSP-M UPD settings.\n"));
+ break;
+ }
+ }
+ if (PcdGetBool (PcdFastBootEnabled) && !(IsPchP ())) {
+ Fspmcfg->CpuPcieRpEnableMask = 0;
+ }
+
+ // S0ix is disabled if TSN is enabled.
+ FeaturesCfgData = (FEATURES_CFG_DATA *) FindConfigDataByTag (CDATA_FEATURES_TAG);
+ SiCfgData = (SILICON_CFG_DATA *)FindConfigDataByTag (CDATA_SILICON_TAG);
+ if ((SiCfgData != NULL) && (SiCfgData->PchTsnEnable == 1)) {
+ if (FeaturesCfgData != NULL) {
+ FeaturesCfgData->Features.S0ix = 0;
+ DEBUG ((DEBUG_INFO, "TSN is enabled, turn off S0ix\n"));
+ }
+ }
+
+ if (FeaturesCfgData != NULL) {
+ if (FeaturesCfgData->Features.S0ix == 1) {
+ Fspmcfg->TcssXdciEn = 0;
+ Fspmcfg->PchIshEnable = 1;
+ ZeroMem (Fspmcfg->PchHdaAudioLinkDmicEnable, sizeof (Fspmcfg->PchHdaAudioLinkDmicEnable));
+ DEBUG ((DEBUG_INFO, "Stage 1B S0ix config applied.\n"));
+ }
+ }
+}
diff --git a/Platform/AlderlakeBoardPkg/Library/FspmUpdUpdateLib/FspmUpdUpdateLibAzb.inf b/Platform/AlderlakeBoardPkg/Library/FspmUpdUpdateLib/FspmUpdUpdateLibAzb.inf
new file mode 100644
index 00000000..b13e7d39
--- /dev/null
+++ b/Platform/AlderlakeBoardPkg/Library/FspmUpdUpdateLib/FspmUpdUpdateLibAzb.inf
@@ -0,0 +1,48 @@
+## @file
+#
+# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = FspmUpdUpdateLib
+ FILE_GUID = 1A29F3A2-9E6F-4E04-B16C-BB6C647308896
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = FspmUpdUpdateLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources]
+ FspmUpdUpdateLibAzb.c
+ BoardSaConfigPreMem.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ BootloaderCorePkg/BootloaderCorePkg.dec
+ BootloaderCommonPkg/BootloaderCommonPkg.dec
+ Silicon/CommonSocPkg/CommonSocPkg.dec
+ Silicon/AlderlakePkg/AlderlakePkg.dec
+ Platform/CommonBoardPkg/CommonBoardPkg.dec
+ Platform/AlderlakeBoardPkg/AlderlakeBoardPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ ConfigDataLib
+ WatchDogTimerLib
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gPlatformModuleTokenSpaceGuid.PcdVtdEnabled
+ gPlatformModuleTokenSpaceGuid.PcdFastBootEnabled
+ gPlatformModuleTokenSpaceGuid.PcdStage1StackBaseOffset
+ gPlatformModuleTokenSpaceGuid.PcdStage1StackSize
+ gPlatformModuleTokenSpaceGuid.PcdStage1DataSize
diff --git a/Platform/AlderlakeBoardPkg/Library/FspsUpdUpdateLib/FspsUpdUpdateLibAzb.c b/Platform/AlderlakeBoardPkg/Library/FspsUpdUpdateLib/FspsUpdUpdateLibAzb.c
new file mode 100644
index 00000000..da05cd3a
--- /dev/null
+++ b/Platform/AlderlakeBoardPkg/Library/FspsUpdUpdateLib/FspsUpdUpdateLibAzb.c
@@ -0,0 +1,628 @@
+/** @file
+
+ Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define CPU_PCIE_DT_HALO_MAX_ROOT_PORT 3
+#define CPU_PCIE_ULT_ULX_MAX_ROOT_PORT 3
+#define MAX_TCSS_USB3_PORTS 4
+#define TURBO_RATIO_LIMIT_ARRAY_SIZE 8
+
+/**
+ Return CPU Family ID
+
+ @retval CPU_FAMILY CPU Family ID
+**/
+CPU_FAMILY
+EFIAPI
+GetCpuFamily1 (
+ VOID
+ )
+{
+ CPUID_VERSION_INFO_EAX Eax;
+ ///
+ /// Read the CPUID information
+ ///
+ AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL);
+ return (Eax.Uint32 & CPUID_FULL_FAMILY_MODEL);
+}
+
+/**
+ Get Maximum CPU Pcie Root Port Number
+
+ @retval Maximum CPU Pcie Root Port Number
+**/
+UINT8
+GetMaxCpuPciePortNum (
+ VOID
+ )
+{
+ switch (GetCpuFamily1()) {
+ case CPUID_FULL_FAMILY_MODEL_ALDERLAKE_DT_HALO:
+ return CPU_PCIE_DT_HALO_MAX_ROOT_PORT;
+ default:
+ return CPU_PCIE_ULT_ULX_MAX_ROOT_PORT;
+ }
+}
+
+/**
+ Update FSP-S UPD config data.
+
+ @param FspsUpdPtr The pointer to the FSP-S UPD to be updated.
+
+**/
+VOID
+UpdateFspConfig (
+ VOID *FspsUpdPtr
+ )
+{
+ FSPS_UPD *FspsUpd;
+ FSP_S_CONFIG *FspsConfig;
+ SILICON_CFG_DATA *SiCfgData;
+ FEATURES_CFG_DATA *FeaturesCfgData;
+ POWER_CFG_DATA *PowerCfgData;
+ UINT8 DebugPort;
+ UINTN Length;
+ UINT8 Index;
+ UINT8 MaxPcieRootPorts;
+ UINT8 PrIndex;
+ UINT32 SmiEn;
+ UINT32 BaseAddress;
+ UINT32 TotalSize;
+ UINT32 Address;
+ UINT32 VarSize;
+ BOOLEAN BiosProtected;
+ EFI_STATUS Status;
+
+ Address = 0;
+ FspsUpd = (FSPS_UPD *) FspsUpdPtr;
+ FspsConfig = &FspsUpd->FspsConfig;
+
+ FspsUpd->FspUpdHeader.Signature = FSPS_UPD_SIGNATURE;
+ FspsUpd->FspUpdHeader.Revision = 0x2;
+
+ FspsUpd->FspsArchUpd.EnableMultiPhaseSiliconInit = 0;
+
+ FeaturesCfgData = (FEATURES_CFG_DATA *) FindConfigDataByTag (CDATA_FEATURES_TAG);
+
+ if (GetBootMode () != BOOT_ON_FLASH_UPDATE) {
+ BiosProtected = FALSE;
+ PrIndex = 0;
+ Status = SpiGetRegionAddress (FlashRegionBios, &BaseAddress, &TotalSize);
+ if (!EFI_ERROR (Status)) {
+ BiosProtected = TRUE;
+ Status = GetComponentInfo (FLASH_MAP_SIG_UEFIVARIABLE, &Address, &VarSize);
+ if (!EFI_ERROR (Status)) {
+ //
+ // Protect the BIOS region except for the UEFI variable region
+ //
+ Address -= ((UINT32)(~TotalSize) + 1);
+
+ FspsConfig->PchWriteProtectionEnable[PrIndex] = TRUE;
+ FspsConfig->PchReadProtectionEnable[PrIndex] = FALSE;
+ FspsConfig->PchProtectedRangeBase[PrIndex] = (UINT16) (BaseAddress >> 12);
+ FspsConfig->PchProtectedRangeLimit[PrIndex] = (UINT16) ((BaseAddress + Address - 1) >> 12);
+ PrIndex++;
+
+ FspsConfig->PchWriteProtectionEnable[PrIndex] = TRUE;
+ FspsConfig->PchReadProtectionEnable[PrIndex] = FALSE;
+ FspsConfig->PchProtectedRangeBase[PrIndex] = (UINT16) ((BaseAddress + Address + VarSize) >> 12);
+ FspsConfig->PchProtectedRangeLimit[PrIndex] = (UINT16) ((BaseAddress + TotalSize - 1) >> 12);
+ PrIndex++;
+ } else {
+ //
+ // Protect the whole BIOS region
+ //
+ FspsConfig->PchWriteProtectionEnable[PrIndex] = TRUE;
+ FspsConfig->PchReadProtectionEnable[PrIndex] = FALSE;
+ FspsConfig->PchProtectedRangeBase[PrIndex] = (UINT16) (BaseAddress >> 12);
+ FspsConfig->PchProtectedRangeLimit[PrIndex] = (UINT16) ((BaseAddress + TotalSize - 1) >> 12);
+ PrIndex++;
+ }
+ }
+ DEBUG (((BiosProtected) ? DEBUG_INFO : DEBUG_WARN, "BIOS SPI region will %a protected\n", (BiosProtected) ? "be" : "NOT BE"));
+ }
+
+ DEBUG ((DEBUG_INFO, "Frame Buffer Disabled\n"));
+ FspsConfig->GraphicsConfigPtr = 0;
+ FspsConfig->PeiGraphicsPeimInit = 0;
+ FspsConfig->LidStatus = 0x0;
+
+ SiCfgData = (SILICON_CFG_DATA *)FindConfigDataByTag (CDATA_SILICON_TAG);
+ if (SiCfgData == NULL) {
+ DEBUG ((DEBUG_INFO, "Failed to find Silicon Cfg Data\n"));
+ } else {
+ FspsUpd->FspsConfig.PchDmiAspmCtrl = SiCfgData->PchDmiAspmCtrl;// ASPM configuration on the PCH side of the DMI/OPI Link
+ FspsUpd->FspsConfig.PchLegacyIoLowLatency = SiCfgData->PchLegacyIoLowLatency;
+ FspsUpd->FspsConfig.RenderStandby = SiCfgData->RenderStandby; // IGFX RenderStandby
+ FspsUpd->FspsConfig.PmSupport = SiCfgData->PmSupport; // IGFX PmSupport
+ MaxPcieRootPorts = GetMaxCpuPciePortNum ();
+ for (Index = 0; Index < MaxPcieRootPorts; Index++) {
+ FspsUpd->FspsConfig.CpuPcieClockGating[Index] = SiCfgData->CpuPcieClockGating; // Describes whether PCI Express Clock Gating for each root port is enabled by platform modules
+ FspsUpd->FspsConfig.CpuPcieRpAspm[Index] = SiCfgData->CpuPcieRpAspm[Index]; // Cpu Aspm
+ FspsUpd->FspsConfig.CpuPcieRpL1Substates[Index] = SiCfgData->CpuPcieRpL1Substates[Index]; // Cpu L1 substates
+ FspsUpd->FspsConfig.CpuPcieRpPtmEnabled[Index] = SiCfgData->CpuPcieRpPtmEnabled[Index] ;
+ FspsUpd->FspsConfig.CpuPcieRpMultiVcEnabled[Index] = SiCfgData->CpuPcieRpMultiVcEnabled[Index];
+ }
+
+ // USB
+ CopyMem (&FspsConfig->PortUsb20Enable, SiCfgData->PortUsb20Enable, sizeof(SiCfgData->PortUsb20Enable));
+ CopyMem (&FspsConfig->Usb2OverCurrentPin, SiCfgData->Usb2OverCurrentPin, sizeof(SiCfgData->Usb2OverCurrentPin));
+ CopyMem (&FspsConfig->Usb3OverCurrentPin, SiCfgData->Usb3OverCurrentPin, sizeof(SiCfgData->Usb3OverCurrentPin));
+ CopyMem (&FspsConfig->PortUsb30Enable, SiCfgData->PortUsb30Enable, sizeof(SiCfgData->PortUsb30Enable));
+ for (Index = 0; Index < GetPchUsb2MaxPhysicalPortNum (); Index++) {
+ CopyMem (&FspsConfig->Usb2PhyPetxiset, SiCfgData->Usb2PhyPetxiset, sizeof(SiCfgData->Usb2PhyPetxiset));
+ CopyMem (&FspsConfig->Usb2PhyTxiset, SiCfgData->Usb2PhyTxiset, sizeof(SiCfgData->Usb2PhyTxiset));
+ CopyMem (&FspsConfig->Usb2PhyPredeemp, SiCfgData->Usb2PhyPredeemp, sizeof(SiCfgData->Usb2PhyPredeemp));
+ CopyMem (&FspsConfig->Usb2PhyPehalfbit, SiCfgData->Usb2PhyPehalfbit, sizeof(SiCfgData->Usb2PhyPehalfbit));
+ }
+
+ //PCH Serial UART
+ Length = GetPchMaxSerialIoUartControllersNum ();
+ for (Index = 0; Index < Length ; Index++) {
+ FspsConfig->SerialIoUartMode[Index] = SiCfgData->SerialIoUartMode[Index];
+ FspsConfig->SerialIoUartPowerGating[Index] = SiCfgData->SerialIoUartPowerGating[Index];
+ FspsConfig->SerialIoUartDmaEnable[Index] = SiCfgData->SerialIoUartDmaEnable[Index];
+ FspsConfig->SerialIoUartAutoFlow[Index] = SiCfgData->SerialIoUartAutoFlow[Index];
+ }
+ DebugPort = GetDebugPort ();
+ if (DebugPort < Length) {
+ // Inform FSP to skip debug UART init
+ FspsConfig->SerialIoDebugUartNumber = DebugPort;
+ FspsConfig->SerialIoUartMode[DebugPort] = 0x4;
+ }
+
+ // SPI
+ FspsConfig->SerialIoSpiMode[1] = 0x1;
+ CopyMem (&FspsConfig->SerialIoSpiCsPolarity, SiCfgData->SerialIoSpiCsPolarity, sizeof(SiCfgData->SerialIoSpiCsPolarity));
+
+ // I2C
+ Length = GetPchMaxSerialIoI2cControllersNum ();
+ for (Index = 0; Index < Length ; Index++) {
+ FspsConfig->SerialIoI2cMode[Index] = SiCfgData->SerialIoI2cMode[Index];
+ FspsConfig->PchSerialIoI2cPadsTermination[Index] = SiCfgData->PchSerialIoI2cPadsTermination[Index];
+ }
+
+ for (Index = 0; Index < MAX_TCSS_USB3_PORTS; Index++) {
+ FspsConfig->CpuUsb3OverCurrentPin[Index] = SiCfgData->CpuUsb3OverCurrentPin[Index];
+ }
+
+ // ISH
+ CopyMem (&FspsConfig->PchIshI2cEnable, SiCfgData->PchIshI2cEnable, sizeof(SiCfgData->PchIshI2cEnable));
+ CopyMem (&FspsConfig->PchIshGpEnable, SiCfgData->PchIshGpEnable, sizeof(SiCfgData->PchIshGpEnable));
+
+ // Pcie Root Port
+ MaxPcieRootPorts = GetPchMaxPciePortNum ();
+ for (Index = 0; Index < MaxPcieRootPorts; Index++) {
+ FspsConfig->PcieRpMaxPayload[Index] = SiCfgData->PcieRpMaxPayload[Index];
+ FspsConfig->PcieRpL1Substates[Index] = SiCfgData->PcieRpL1Substates[Index];
+ FspsConfig->PcieRpLtrEnable[Index] = SiCfgData->PcieRpLtrEnable[Index];
+ FspsConfig->PcieRpClkReqDetect[Index] = SiCfgData->PcieRpClkReqDetect[Index];
+ FspsConfig->PcieRpAdvancedErrorReporting[Index] = SiCfgData->PcieRpAdvancedErrorReporting[Index];
+ FspsConfig->PcieRpAspm[Index] = SiCfgData->PcieRpAspm[Index];
+ FspsConfig->PcieRpLtrMaxSnoopLatency[Index] = 0x1003;
+ FspsConfig->PcieRpLtrMaxNoSnoopLatency[Index] = 0x1003;
+ FspsConfig->PciePtm[Index] = SiCfgData->PciePtm[Index];
+ FspsConfig->PcieRpPcieSpeed[Index] = SiCfgData->PcieRpPcieSpeed[Index];
+ }
+
+ for (Index = 0; Index < 4; Index++) {
+ FspsConfig->PtmEnabled[Index] = SiCfgData->PtmEnabled[Index];
+ }
+
+ FspsConfig->PchPmSlpAMinAssert = SiCfgData->PchPmSlpAMinAssert;
+ FspsConfig->EnableTcoTimer = 0x1;
+
+ // UFS
+ if (IsPchLp ()) {
+ FspsConfig->UfsEnable[0] = SiCfgData->PchUfsEnable[0];
+ FspsConfig->UfsEnable[1] = SiCfgData->PchUfsEnable[1];
+ }
+
+ // When fast boot is enabled, program SLP_A_MIN_ASST_WDTH to 0
+ // to reduce boottime.
+ if (PcdGetBool (PcdFastBootEnabled)) {
+ FspsConfig->PchPmSlpAMinAssert = 1;
+ }
+
+ FspsConfig->IehMode = SiCfgData->IehMode;
+ FspsConfig->D3HotEnable = SiCfgData->D3HotEnable;
+ FspsConfig->D3ColdEnable = SiCfgData->D3ColdEnable;
+ FspsConfig->TcCstateLimit = SiCfgData->TcCstateLimit;
+ FspsConfig->VccSt = SiCfgData->VccSt;
+ // Cpu Pcie
+ FspsConfig->CpuPciePowerGating[0] = SiCfgData->CpuPciePowerGating;
+ FspsConfig->CpuPciePowerGating[1] = SiCfgData->CpuPciePowerGating;
+ FspsConfig->CpuPciePowerGating[2] = SiCfgData->CpuPciePowerGating;
+ FspsConfig->CpuPciePowerGating[3] = SiCfgData->CpuPciePowerGating;
+ }
+
+ for (Index = 0; Index < 8; Index++) {
+ FspsConfig->PcieRpSnoopLatencyOverrideMode[Index] = 0x2;
+ FspsConfig->PcieRpNonSnoopLatencyOverrideMode[Index] = 0x2;
+ }
+
+ if(GetPayloadId () == 0) {
+ // Disable SMI sources
+ SmiEn = IoRead32((UINT32)(ACPI_BASE_ADDRESS + R_ACPI_IO_SMI_EN));
+ IoWrite32 ((UINTN) (ACPI_BASE_ADDRESS + R_ACPI_IO_SMI_EN), SmiEn & (UINT32) (~B_ACPI_IO_SMI_EN_GBL_SMI));
+
+ // Lock down SMI
+ FspsConfig->PchLockDownGlobalSmi = 0x1;
+ }
+
+ //Disable VMD by default
+ FspsConfig->VmdEnable = 0;
+
+ // Cpu Pcie
+ FspsConfig->CpuPcieRpFunctionSwap = 0x0;
+ for (Index = 0; Index < 3; Index++) {
+ FspsConfig->CpuPcieRpMaxPayload[Index] = 0x1;
+ FspsConfig->CpuPcieRpLtrEnable[Index] = 0x1;
+ FspsConfig->CpuPcieRpPmSci[Index] = 0x1;
+ }
+
+ // PCH Flash protection
+ FspsConfig->PchPwrOptEnable = 0x1;
+
+ // MISC
+ FspsConfig->PchFivrExtV1p05RailVoltage = 0x1a4;
+ FspsConfig->PchFivrExtVnnRailVoltage = 0x1a4;
+ FspsConfig->PchFivrExtVnnRailSxVoltage = 0x1a4;
+ FspsConfig->PchFivrVccinAuxLowToHighCurModeVolTranTime = 0xc;
+ FspsConfig->PchFivrVccinAuxRetToHighCurModeVolTranTime = 0x36;
+ FspsConfig->PchFivrVccinAuxRetToLowCurModeVolTranTime = 0x2b;
+ FspsConfig->PchFivrVccinAuxOffToHighCurModeVolTranTime = 0x96;
+ FspsConfig->PchFivrDynPm = 0x1;
+ FspsConfig->PchFivrExtV1p05RailIccMaximum = 0x1f4;
+ FspsConfig->PchFivrExtVnnRailIccMaximum = 0x1f4;
+ FspsConfig->PchFivrExtVnnRailSxIccMaximum = 0x1f4;
+ FspsConfig->PchMemoryPmsyncEnable[0] = 0x1;
+ FspsConfig->PchMemoryPmsyncEnable[1] = 0x1;
+ FspsConfig->PchMemoryC0TransmitEnable[0] = 0x1;
+ FspsConfig->PchMemoryC0TransmitEnable[1] = 0x1;
+ FspsConfig->PchPmSlpS3MinAssert = 0x3;
+ FspsConfig->PchPmSlpS4MinAssert = 0x1;
+ FspsConfig->PchPmSlpSusMinAssert = 0x4;
+ FspsConfig->PchPmPwrBtnOverridePeriod = 0x0;
+ FspsConfig->PchEspiLgmrEnable = 0x0;
+ FspsConfig->ForcMebxSyncUp = 0x0;
+ FspsConfig->PmcModPhySusPgEnable = 0x0;
+ FspsConfig->IomTypeCPortPadCfg[2] = 0x6040000;
+ FspsConfig->IomTypeCPortPadCfg[3] = 0x6040011;
+ FspsConfig->DmiTS0TW = 0x3;
+ FspsConfig->DmiTS1TW = 0x2;
+ FspsConfig->DmiTS2TW = 0x1;
+ FspsConfig->MeUnconfigOnRtcClear = 0x1;
+ FspsConfig->PsOnEnable = 0x1;
+ FspsConfig->PmcAdrTimerEn = 0x1;
+ FspsConfig->PmcAdrTimer1Val = 0x20;
+ FspsConfig->PmcAdrMultiplier1Val = 0x6;
+ FspsConfig->PmcAdrHostPartitionReset = 0x1;
+ FspsConfig->PmcLpmS0ixSubStateEnableMask = 0x3;
+ FspsConfig->PmcUsb2PhySusPgEnable = 0x0;
+ FspsConfig->SkipCdClockInit = 0x0;
+ FspsConfig->VccInAuxImonIccImax = 0x0;
+ FspsConfig->CpuPcieRpGen3Uptp[0] = 0x5;
+ FspsConfig->CpuPcieRpGen4Uptp[0] = 0x8;
+ FspsConfig->CpuPcieRpGen4Uptp[1] = 0x7;
+ FspsConfig->CpuPcieRpGen4Uptp[2] = 0x7;
+ FspsConfig->CpuPcieRpGen4Dptp[0] = 0x9;
+ FspsConfig->CpuPcieRpGen4Dptp[1] = 0x5;
+ FspsConfig->CpuPcieRpGen4Dptp[2] = 0x5;
+ FspsConfig->CpuPcieRpGen5Uptp[0] = 0x5;
+ FspsConfig->CpuPcieRpGen5Uptp[1] = 0x5;
+ FspsConfig->CpuPcieRpGen5Uptp[2] = 0x5;
+
+ // EndOfPost Upd
+ FspsUpd->FspsConfig.EndOfPostMessage = 1;
+
+ if (FeaturesCfgData != NULL) {
+ if (FeaturesCfgData->Features.S0ix == 1) {
+ FspsConfig->XdciEnable = 0;
+ FspsConfig->EnableItbm = 0;
+
+ ZeroMem (FspsConfig->CpuPcieRpMultiVcEnabled, sizeof (FspsConfig->CpuPcieRpMultiVcEnabled));
+ ZeroMem (FspsConfig->PchIshI2cEnable, sizeof (FspsConfig->PchIshI2cEnable));
+ ZeroMem (FspsConfig->PchIshGpEnable, sizeof (FspsConfig->PchIshGpEnable));
+ DEBUG ((DEBUG_INFO, "Stage 2 S0ix config applied.\n"));
+ }
+ }
+
+ for (Index = 0; Index < 3; Index++) {
+ FspsConfig->CpuPcieRpLtrMaxSnoopLatency[Index] = 0x100f;
+ FspsConfig->CpuPcieRpLtrMaxNoSnoopLatency[Index] = 0x100f;
+ }
+
+ // Force Eiss and BiosLock off for now.
+ // Enable it later in OS loader/EndofStages
+ FspsConfig->PchLockDownBiosLock = 0x0;
+
+ // Disable IEH
+ FspsConfig->IehMode = 0x0;
+ FspsConfig->PchCrid = 0x0;
+ if (GetBootMode() == BOOT_ON_FLASH_UPDATE) {
+ FspsUpd->FspsConfig.PchLockDownBiosInterface = FALSE;
+ FspsUpd->FspsConfig.PchSbAccessUnlock = TRUE;
+ FspsUpd->FspsConfig.RtcBiosInterfaceLock = FALSE;
+ DEBUG ((DEBUG_INFO, "Firmware update mode, unlock Bios setting\n"));
+ } else {
+ FspsUpd->FspsConfig.PchLockDownBiosInterface = TRUE;
+ FspsUpd->FspsConfig.PchSbAccessUnlock = FALSE;
+ FspsUpd->FspsConfig.RtcBiosInterfaceLock = TRUE;
+ }
+
+ FspsConfig->AmtEnabled = 0x0;
+ FspsConfig->VccInAuxImonSlope = 0x6f;
+
+ PowerCfgData = (POWER_CFG_DATA *) FindConfigDataByTag (CDATA_POWER_TAG);
+ if (PowerCfgData == NULL) {
+ DEBUG ((DEBUG_ERROR, "Missing power Cfg Data!\n"));
+ } else {
+ //CPU Power Management Basic Config
+ FspsConfig->Hwp = PowerCfgData->Hwp;
+ FspsConfig->HdcControl = PowerCfgData->HdcControl;
+ FspsConfig->EnableItbm = PowerCfgData->EnableItbm;
+ FspsConfig->PowerLimit2 = PowerCfgData->PowerLimit2;
+ FspsConfig->TurboPowerLimitLock = PowerCfgData->TurboPowerLimitLock;
+ FspsConfig->PowerLimit3DutyCycle = PowerCfgData->PowerLimit3DutyCycle;
+ FspsConfig->PowerLimit3Lock = PowerCfgData->PowerLimit3Lock;
+ FspsConfig->PowerLimit4Lock = PowerCfgData->PowerLimit4Lock;
+ FspsConfig->TccOffsetClamp = PowerCfgData->TccOffsetClamp;
+ FspsConfig->TccOffsetLock = PowerCfgData->TccOffsetLock;
+ FspsConfig->TurboMode = PowerCfgData->TurboMode;
+ FspsConfig->TccActivationOffset = PowerCfgData->TccActivationOffset;
+ FspsConfig->PowerLimit1 = PowerCfgData->PowerLimit1;
+ FspsConfig->PowerLimit2Power = PowerCfgData->PowerLimit2Power;
+ FspsConfig->PowerLimit3 = PowerCfgData->PowerLimit3;
+ FspsConfig->PowerLimit4 = PowerCfgData->PowerLimit4;
+ FspsConfig->PowerLimit1Time = PowerCfgData->PowerLimit1Time;
+ FspsConfig->PowerLimit3Time = PowerCfgData->PowerLimit3Time;
+ FspsConfig->TccOffsetTimeWindowForRatl = PowerCfgData->TccOffsetTimeWindowForRatl;
+ FspsConfig->HwpInterruptControl = PowerCfgData->HwpInterruptControl;
+ FspsConfig->EnablePerCorePState = PowerCfgData->EnablePerCorePState;
+ FspsConfig->EnableHwpAutoPerCorePstate = PowerCfgData->EnableHwpAutoPerCorePstate;
+ FspsConfig->EnableHwpAutoEppGrouping = PowerCfgData->EnableHwpAutoEppGrouping;
+ FspsConfig->EnableEpbPeciOverride = PowerCfgData->EnableEpbPeciOverride;
+ FspsConfig->EnableFastMsrHwpReq = PowerCfgData->EnableFastMsrHwpReq;
+ FspsConfig->MinRingRatioLimit = PowerCfgData->MinRingRatioLimit;
+ FspsConfig->MaxRingRatioLimit = PowerCfgData->MaxRingRatioLimit;
+
+ //CPU VR Power Management Custom Config
+ CopyMem (FspsConfig->VrConfigEnable, PowerCfgData->VrConfigEnable, sizeof(PowerCfgData->VrConfigEnable));
+ CopyMem (FspsConfig->TdcCurrentLimit, PowerCfgData->TdcCurrentLimit, sizeof(PowerCfgData->TdcCurrentLimit));
+ CopyMem (FspsConfig->DcLoadline, PowerCfgData->DcLoadline, sizeof(PowerCfgData->DcLoadline));
+ CopyMem (FspsConfig->AcLoadline, PowerCfgData->AcLoadline, sizeof(PowerCfgData->AcLoadline));
+ CopyMem (FspsConfig->Psi1Threshold, PowerCfgData->Psi1Threshold, sizeof(PowerCfgData->Psi1Threshold));
+ CopyMem (FspsConfig->Psi2Threshold, PowerCfgData->Psi2Threshold, sizeof(PowerCfgData->Psi2Threshold));
+ CopyMem (FspsConfig->Psi3Threshold, PowerCfgData->Psi3Threshold, sizeof(PowerCfgData->Psi3Threshold));
+ CopyMem (FspsConfig->Psi3Enable, PowerCfgData->Psi3Enable, sizeof(PowerCfgData->Psi3Enable));
+ CopyMem (FspsConfig->Psi4Enable, PowerCfgData->Psi4Enable, sizeof(PowerCfgData->Psi4Enable));
+ CopyMem (FspsConfig->ImonSlope, PowerCfgData->ImonSlope, sizeof(PowerCfgData->ImonSlope));
+ CopyMem (FspsConfig->IccMax, PowerCfgData->IccMax, sizeof(PowerCfgData->IccMax));
+ CopyMem (FspsConfig->ImonOffset, PowerCfgData->ImoniOffset, sizeof(PowerCfgData->ImoniOffset));
+
+ CopyMem (FspsConfig->VrVoltageLimit, PowerCfgData->VrVoltageLimit, sizeof(PowerCfgData->VrVoltageLimit));
+ CopyMem (FspsConfig->TdcEnable, PowerCfgData->TdcEnable, sizeof(PowerCfgData->TdcEnable));
+ CopyMem (FspsConfig->TdcTimeWindow, PowerCfgData->TdcTimeWindow, sizeof(PowerCfgData->TdcTimeWindow));
+
+ FspsConfig->AcousticNoiseMitigation = 0x0;
+ FspsConfig->FivrSpreadSpectrum = 0x8;
+
+ //CPU Power Management Custom Config
+ FspsConfig->MaxRatio = PowerCfgData->MaxRatio;
+ FspsConfig->Custom1PowerLimit1 = PowerCfgData->Custom1PowerLimit1;
+ FspsConfig->Custom1PowerLimit2 = PowerCfgData->Custom1PowerLimit2;
+ FspsConfig->Custom1PowerLimit1Time = PowerCfgData->Custom1PowerLimit1Time;
+ FspsConfig->Custom1TurboActivationRatio = PowerCfgData->Custom1TurboActivationRatio;
+ FspsConfig->Custom2PowerLimit1 = PowerCfgData->Custom2PowerLimit1;
+ FspsConfig->Custom2PowerLimit2 = PowerCfgData->Custom2PowerLimit2;
+ FspsConfig->Custom2PowerLimit1Time = PowerCfgData->Custom2PowerLimit1Time;
+ FspsConfig->Custom2TurboActivationRatio = PowerCfgData->Custom2TurboActivationRatio;
+ FspsConfig->Custom3PowerLimit1 = PowerCfgData->Custom3PowerLimit1;
+ FspsConfig->Custom3PowerLimit2 = PowerCfgData->Custom3PowerLimit2;
+ FspsConfig->Custom3PowerLimit1Time = PowerCfgData->Custom3PowerLimit1Time;
+ FspsConfig->Custom3TurboActivationRatio = PowerCfgData->Custom3TurboActivationRatio;
+
+ //CPU Power Management Psys Config
+ FspsConfig->PsysPowerLimit1Power = PowerCfgData->PsysPowerLimit1Power;
+ FspsConfig->PsysPowerLimit2Power = PowerCfgData->PsysPowerLimit2Power;
+ FspsConfig->PsysPmax = PowerCfgData->PsysPmax;
+ FspsConfig->PsysPowerLimit1 = PowerCfgData->PsysPowerLimit1;
+ FspsConfig->PsysPowerLimit1Time = PowerCfgData->PsysPowerLimit1Time;
+ FspsConfig->PsysPowerLimit2 = PowerCfgData->PsysPowerLimit2;
+
+ //CPU Power Management Test Config
+ FspsConfig->Eist = PowerCfgData->Eist;
+ FspsConfig->EnergyEfficientPState = PowerCfgData->EnergyEfficientPState;
+ FspsConfig->EnergyEfficientTurbo = PowerCfgData->EnergyEfficientTurbo;
+ FspsConfig->TStates = PowerCfgData->TStates;
+ FspsConfig->BiProcHot = PowerCfgData->BiProcHot;
+ FspsConfig->DisableProcHotOut = PowerCfgData->DisableProcHotOut;
+ FspsConfig->ProcHotResponse = PowerCfgData->ProcHotResponse;
+ FspsConfig->DisableVrThermalAlert = PowerCfgData->DisableVrThermalAlert;
+ FspsConfig->EnableAllThermalFunctions = PowerCfgData->EnableAllThermalFunctions;
+ FspsConfig->ThermalMonitor = PowerCfgData->ThermalMonitor;
+ FspsConfig->Cx = PowerCfgData->Cx;
+ FspsConfig->PmgCstCfgCtrlLock = PowerCfgData->PmgCstCfgCtrlLock;
+ FspsConfig->C1e = PowerCfgData->C1e;
+ FspsConfig->C1StateAutoDemotion = PowerCfgData->C1StateAutoDemotion;
+ FspsConfig->C1StateUnDemotion = PowerCfgData->C1StateUnDemotion;
+ FspsConfig->CStatePreWake = PowerCfgData->CStatePreWake;
+ FspsConfig->TimedMwait = PowerCfgData->TimedMwait;
+ FspsConfig->CstCfgCtrIoMwaitRedirection = PowerCfgData->CstCfgCtrIoMwaitRedirection;
+ FspsConfig->ProcHotLock = PowerCfgData->ProcHotLock;
+ FspsConfig->ConfigTdpLevel = PowerCfgData->ConfigTdpLevel;
+ FspsConfig->RaceToHalt = PowerCfgData->RaceToHalt;
+ FspsConfig->CstateLatencyControl1TimeUnit = PowerCfgData->CstateLatencyControl1TimeUnit;
+ FspsConfig->CstateLatencyControl2TimeUnit = PowerCfgData->CstateLatencyControl2TimeUnit;
+ FspsConfig->CstateLatencyControl3TimeUnit = PowerCfgData->CstateLatencyControl3TimeUnit;
+ FspsConfig->CstateLatencyControl4TimeUnit = PowerCfgData->CstateLatencyControl4TimeUnit;
+ FspsConfig->CstateLatencyControl5TimeUnit = PowerCfgData->CstateLatencyControl5TimeUnit;
+ FspsConfig->PkgCStateLimit = PowerCfgData->PkgCStateLimit;
+ FspsConfig->CstateLatencyControl1Irtl = PowerCfgData->CstateLatencyControl1Irtl;
+ FspsConfig->CstateLatencyControl2Irtl = PowerCfgData->CstateLatencyControl2Irtl;
+ FspsConfig->CstateLatencyControl3Irtl = PowerCfgData->CstateLatencyControl3Irtl;
+ FspsConfig->CstateLatencyControl4Irtl = PowerCfgData->CstateLatencyControl4Irtl;
+ FspsConfig->CstateLatencyControl5Irtl = PowerCfgData->CstateLatencyControl5Irtl;
+
+ // Cpu power related settings
+ for (Index = 0; Index < TURBO_RATIO_LIMIT_ARRAY_SIZE; Index++) {
+ FspsConfig->TurboRatioLimitRatio[Index] = PowerCfgData->TurboRatioLimitRatio[Index];
+ FspsConfig->TurboRatioLimitNumCore[Index] = PowerCfgData->TurboRatioLimitNumCore[Index];
+ FspsConfig->AtomTurboRatioLimitRatio[Index] = PowerCfgData->AtomTurboRatioLimitRatio[Index];
+ FspsConfig->AtomTurboRatioLimitNumCore[Index] = PowerCfgData->AtomTurboRatioLimitNumCore[Index];
+ }
+ }
+
+ FspsConfig->TdcTimeWindow[0] = 0x3e8;
+ FspsConfig->TdcTimeWindow[1] = 0x3e8;
+ FspsConfig->Device4Enable = 0x1;
+
+ if (IsPchLp ()) {
+ for (Index = 0; Index < 4; Index++) {
+ FspsConfig->CpuPcieRpLtrMaxSnoopLatency[Index] = 0x100f;
+ FspsConfig->CpuPcieRpLtrMaxNoSnoopLatency[Index] = 0x100f;
+ }
+
+ FspsConfig->SataPortDevSlpPinMux[0] = 0x59673e0c;
+ FspsConfig->SataPortDevSlpPinMux[1] = 0x5967400d;
+ FspsConfig->PchSerialIoI2cSdaPinMux[0] = 0x1947c404;
+ FspsConfig->PchSerialIoI2cSdaPinMux[1] = 0x1947c606;
+ FspsConfig->PchSerialIoI2cSdaPinMux[4] = 0;
+ FspsConfig->PchSerialIoI2cSdaPinMux[7] = 0x1947d20c;
+ FspsConfig->PchSerialIoI2cSclPinMux[0] = 0x1947a405;
+ FspsConfig->PchSerialIoI2cSclPinMux[1] = 0x1947a607;
+ FspsConfig->PchSerialIoI2cSclPinMux[4] = 0;
+ FspsConfig->PchSerialIoI2cSclPinMux[7] = 0x1947b20d;
+ FspsConfig->IshGpGpioPinMuxing[4] = 0x290ea809;
+ FspsConfig->IshGpGpioPinMuxing[5] = 0x4900aa04;
+ FspsConfig->IshGpGpioPinMuxing[6] = 0x4907ac0c;
+ FspsConfig->IshGpGpioPinMuxing[7] = 0x5900ae0f;
+ FspsConfig->PchFivrExtV1p05RailSupportedVoltageStates = 0x2;
+ FspsConfig->PchFivrExtV1p05RailVoltage = 0x0;
+ FspsConfig->PchFivrExtVnnRailVoltage = 0x0;
+ FspsConfig->PchFivrExtVnnRailSxVoltage = 0x0;
+ FspsConfig->PchFivrVccinAuxLowToHighCurModeVolTranTime = 0xc;
+ FspsConfig->PchFivrVccinAuxRetToHighCurModeVolTranTime = 0x36;
+ FspsConfig->PchFivrVccinAuxRetToLowCurModeVolTranTime = 0x2b;
+ FspsConfig->PchFivrVccinAuxOffToHighCurModeVolTranTime = 0x96;
+ FspsConfig->PchFivrExtVnnRailSxIccMaximum = 0x0;
+ FspsConfig->CnviRfResetPinMux = 0x194ce404;
+ FspsConfig->CnviClkreqPinMux = 0x294ce605;
+ FspsConfig->PmcUsb2PhySusPgEnable = 0x1;
+ FspsConfig->PmcModPhySusPgEnable = 0x1;
+ FspsConfig->IomTypeCPortPadCfg[2] = 0x0;
+ FspsConfig->IomTypeCPortPadCfg[3] = 0x0;
+ FspsConfig->ITbtPcieTunnelingForUsb4 = 0x1;
+ FspsConfig->ITbtPcieRootPortEn[0] = 0x1;
+ FspsConfig->ITbtPcieRootPortEn[1] = 0x1;
+ FspsConfig->ITbtPcieRootPortEn[2] = 0x1;
+ FspsConfig->ITbtPcieRootPortEn[3] = 0x1;
+ FspsConfig->SaPcieItbtRpSnoopLatencyOverrideValue[2] = 0xc8;
+ FspsConfig->TdcTimeWindow[0] = 0x3e8;
+ FspsConfig->TdcTimeWindow[1] = 0x3e8;
+ FspsConfig->IehMode = 0x0;
+ FspsConfig->PortResetMessageEnable[0] = 0x1;
+ FspsConfig->PortResetMessageEnable[1] = 0x1;
+ FspsConfig->PortResetMessageEnable[2] = 0x1;
+ FspsConfig->PortResetMessageEnable[4] = 0x1;
+ FspsConfig->PkgCStateLimit = 0xff;
+ FspsConfig->CstCfgCtrIoMwaitRedirection = 0;
+ FspsConfig->PmcLpmS0ixSubStateEnableMask = 0x9;
+ FspsConfig->VbtSize = 0x2200;
+ FspsConfig->CpuPcieRpGen3Uptp[2] = 0x5;
+ FspsConfig->CpuPcieRpGen4Uptp[2] = 0x8;
+ FspsConfig->CpuPcieRpGen4Dptp[2] = 0x9;
+ FspsConfig->PchPmPwrBtnOverridePeriod = 0x3;
+ FspsConfig->PsOnEnable = 0x0;
+ FspsConfig->IomStayInTCColdSeconds = 0x0;
+ FspsConfig->IomBeforeEnteringTCColdSeconds = 0x0;
+ FspsConfig->Irms[0] = 0x0;
+ FspsConfig->AtomTurboRatioLimitNumCore[1] = 0x2;
+ FspsConfig->AtomTurboRatioLimitNumCore[2] = 0x3;
+ FspsConfig->AtomTurboRatioLimitNumCore[3] = 0x4;
+ FspsConfig->AtomTurboRatioLimitNumCore[4] = 0x5;
+ FspsConfig->AtomTurboRatioLimitNumCore[5] = 0x6;
+ FspsConfig->AtomTurboRatioLimitNumCore[6] = 0x7;
+ FspsConfig->AtomTurboRatioLimitNumCore[7] = 0x8;
+
+ switch (GetPlatformId ()) {
+ case PLATFORM_ID_AZB_LP5_CRB2A:
+ FspsConfig->PcieRpDetectTimeoutMs[1] = 0x12c;
+ //
+ // Maximum Tcss port support is 2 and minimum is 1;
+ // In case of CRB it is 1.
+ //
+ FspsConfig->NumberOfTcssPortsSupported = 0x1;
+ FspsConfig->EnableTcssCovTypeA[0] = 0x1;
+ FspsConfig->MappingPchXhciUsbA[0] = 0x1;
+ FspsConfig->PchLanEnable = 0x0;
+ FspsConfig->PchPmVrAlert = 0x1;
+ FspsConfig->PcieRpDetectTimeoutMs[3] = 0x12c;
+ FspsConfig->UsbTcPortEn = 0x3;
+ FspsConfig->PchPmSlpSusMinAssert = 0x4;
+ FspsConfig->PchPmSlpAMinAssert = 0x4;
+ FspsConfig->UfsEnable[1] = 0x1;
+ FspsConfig->SendEcCmd = 0x42335518;
+ FspsConfig->EcCmdProvisionEav = 0xb1;
+ FspsConfig->EcCmdLock = 0xb2;
+ FspsConfig->PortResetMessageEnable[2] = 0x0;
+ FspsConfig->PortResetMessageEnable[4] = 0x0;
+ FspsConfig->CpuPcieRpPmSci[1] = 0x0;
+ FspsConfig->CpuPcieRpPmSci[2] = 0x0;
+ FspsConfig->CpuPcieRpMaxPayload[1] = 0x0;
+ FspsConfig->CpuPcieRpMaxPayload[2] = 0x0;
+ FspsConfig->CpuPcieRpAspm[1] = 0x3;
+ FspsConfig->CpuPcieRpAspm[2] = 0x3;
+ FspsConfig->CpuPcieRpLtrEnable[1] = 0x0;
+ FspsConfig->CpuPcieRpLtrEnable[2] = 0x0;
+ FspsConfig->PkgCStateLimit = 0x0;
+ FspsConfig->CpuPcieRpGen3Uptp[2] = 0x7;
+ FspsConfig->CpuPcieRpGen4Uptp[1] = 0x8;
+ FspsConfig->CpuPcieRpGen4Dptp[1] = 0x9;
+ FspsConfig->CpuPcieRpGen5Uptp[1] = 0x7;
+ FspsConfig->CpuPcieRpGen5Uptp[2] = 0x7;
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (FeaturePcdGet (PcdEnablePciePm)) {
+ StoreRpConfig (FspsConfig);
+ }
+}
diff --git a/Platform/AlderlakeBoardPkg/Library/FspsUpdUpdateLib/FspsUpdUpdateLibAzb.inf b/Platform/AlderlakeBoardPkg/Library/FspsUpdUpdateLib/FspsUpdUpdateLibAzb.inf
new file mode 100644
index 00000000..73557591
--- /dev/null
+++ b/Platform/AlderlakeBoardPkg/Library/FspsUpdUpdateLib/FspsUpdUpdateLibAzb.inf
@@ -0,0 +1,46 @@
+## @file
+#
+# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = FspsUpdUpdateLib
+ FILE_GUID = F0F0D153-A1A6-4455-89C5-F2BDD02C25459
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = FspsUpdUpdateLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources]
+ FspsUpdUpdateLibAzb.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ BootloaderCorePkg/BootloaderCorePkg.dec
+ BootloaderCommonPkg/BootloaderCommonPkg.dec
+ Silicon/AlderlakePkg/AlderlakePkg.dec
+ Silicon/CommonSocPkg/CommonSocPkg.dec
+ Platform/CommonBoardPkg/CommonBoardPkg.dec
+ Platform/AlderlakeBoardPkg/AlderlakeBoardPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ ConfigDataLib
+ WatchDogTimerLib
+ TpmLib
+
+[Pcd]
+ gPlatformModuleTokenSpaceGuid.PcdEnablePciePm
+ gPlatformModuleTokenSpaceGuid.PcdFastBootEnabled
+ gPlatformModuleTokenSpaceGuid.PcdSblResiliencyEnabled
+ gPlatformCommonLibTokenSpaceGuid.PcdMeasuredBootEnabled
diff --git a/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/EcSupport.c b/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/EcSupport.c
index 41623659..bf2355ef 100644
--- a/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/EcSupport.c
+++ b/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/EcSupport.c
@@ -395,6 +395,9 @@ GetBoardId (
case BoardIdAdlNLp5Rvp:
*PlatformId = PLATFORM_ID_ADL_N_LPDDR5_RVP;
break;
+ case BoardIdAzbLp5Crb2A:
+ *PlatformId = PLATFORM_ID_AZB_LP5_CRB2A;
+ break;
case BoardIdTestSDdr5UDimm1DRvp:
*PlatformId = PLATFORM_ID_TEST_S_DDR5_UDIMM_RVP;
break;
diff --git a/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/GpioTableAzbPreMem.h b/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/GpioTableAzbPreMem.h
new file mode 100644
index 00000000..3407fdf7
--- /dev/null
+++ b/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/GpioTableAzbPreMem.h
@@ -0,0 +1,68 @@
+/** @file
+ ArizonaBeach GPIO definition table for Pre-Memory Initialization
+
+ Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+#ifndef _ARIZONA_BEACH_LPDDR5_PREMEM_GPIO_TABLE_H_
+#define _ARIZONA_BEACH_LPDDR5_PREMEM_GPIO_TABLE_H_
+
+#include
+#include
+
+GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTablePreMemAzbLp5[] =
+{
+ // CPU M.2 SSD
+ {GPIO_VER2_LP_GPP_D16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, // M.2_CPU_SSD_PWREN
+ {GPIO_VER2_LP_GPP_H13, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, // M2_CPU_SSD1_RESET_N
+
+ // x1 PCIe DT Slot
+ {GPIO_VER2_LP_GPP_D14, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, // X1_PCIE_SLOT1_PWR_EN
+ {GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, // X1_Slot_RESET
+ {GPIO_VER2_LP_GPP_D17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, // X1_PCIE_SLOT_WAKE_N
+
+ {GPIO_VER2_LP_GPP_E4, {GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone }}, // TC_RETIMER_FORCE_PWR
+
+ // USB Type-A
+ {GPIO_VER2_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone }}, // USB_TYPEA_OC2_N
+ {GPIO_VER2_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone }}, // USB_TYPEA_PWR_EN
+
+ // PCH M.2 SSD
+ {GPIO_VER2_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, // M2_PCH_SSD_PWREN
+ {GPIO_VER2_LP_GPP_H0, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, // M2_SSD_RST_N
+
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTableAzbLp5WwanOnEarlyPreMem[] =
+{
+ {GPIO_VER2_LP_GPP_A8, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock }}, // WWAN_PWRE
+ {GPIO_VER2_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock }}, // WWAN_FCP_OFF_N
+ {GPIO_VER2_LP_GPP_E5, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock }}, // WWAN_RST_N
+ {GPIO_VER2_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock }}, // WWAN_PERST_N
+ {GPIO_VER2_LP_GPP_D18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, // WWAN_WAKE_N
+ {GPIO_VER2_LP_GPP_D15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock }}, // WWAN_DISABLE_N
+ {GPIO_VER2_LP_GPP_A6, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, // SAE_DPR_PCH
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTableAzbLp5WwanOffEarlyPreMem[] =
+{
+ {GPIO_VER2_LP_GPP_E5, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock }}, // WWAN_RST_N
+ {GPIO_VER2_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock }}, // WWAN_PERST_N
+ {GPIO_VER2_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock }}, // WWAN_FCP_OFF_N
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTableAzbM80WwanEarlyPreMem[] =
+{
+ {GPIO_VER2_LP_GPP_A8, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock }}, // WWAN_PWREN
+ {GPIO_VER2_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock }}, // WWAN_FCP_OFF_N
+ {GPIO_VER2_LP_GPP_E5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock }}, // WWAN_RST_N
+ {GPIO_VER2_LP_GPP_C5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock }}, // WWAN_PERST_N
+ {GPIO_VER2_LP_GPP_D18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, // WWAN_WAKE_N
+ {GPIO_VER2_LP_GPP_D15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock }}, // WWAN_DISABLE_N
+ {GPIO_VER2_LP_GPP_A6, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, // SAR_DPR_PCH
+};
+
+#endif // _ARIZONA_BEACH_LPDDR5_PREMEM_GPIO_TABLE_H_
diff --git a/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.c b/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.c
index a2bf30e8..6ccc6e9c 100644
--- a/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.c
+++ b/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.c
@@ -20,6 +20,18 @@ CONST PLT_DEVICE mPlatformDevices[] = {
.Type = OsBootDeviceUsb,
.Instance = 0
},
+ {
+ .Dev = {
+ .PciDev = {
+ .PciFunctionNumber = PCI_FUNCTION_NUMBER_PCH_XHCI_1,
+ .PciDeviceNumber = PCI_DEVICE_NUMBER_PCH_XHCI_1,
+ .PciBusNumber = DEFAULT_PCI_BUS_NUMBER_PCH,
+ .IsMmioDevice = 0
+ }
+ },
+ .Type = OsBootDeviceUsb,
+ .Instance = 1
+ },
{
.Dev = {
.PciDev = {
@@ -652,6 +664,30 @@ DEBUG_CODE_END();
break;
case PLATFORM_ID_ADL_N_LPDDR5_RVP:
ConfigureGpio (CDATA_NO_TAG, sizeof (mGpioTablePreMemAdlNLpddr5Rvp) / sizeof (mGpioTablePreMemAdlNLpddr5Rvp[0]), (UINT8*)mGpioTablePreMemAdlNLpddr5Rvp);
+ break;
+ case PLATFORM_ID_AZB_LP5_CRB2A:
+#if FixedPcdGetBool(PcdAzbWwanSupport)
+ ConfigureGpio (CDATA_NO_TAG, sizeof (mGpioTablePreMemAzbLp5) / sizeof (mGpioTablePreMemAzbLp5[0]), (UINT8*)mGpioTablePreMemAzbLp5);
+
+ GpioSetOutputValue ( GPIO_VER2_LP_GPP_C5, 0);
+ MicroSecondDelay (20 * 1000); // Delay by 20ms
+
+ GpioSetOutputValue ( GPIO_VER2_LP_GPP_E5, 0);
+ MicroSecondDelay (10 * 1000); // Delay by 10ms
+
+ GpioSetOutputValue ( GPIO_VER2_LP_GPP_D9, 0);
+ MicroSecondDelay (500 * 1000); // Delay by 500ms
+
+ ConfigureGpio (CDATA_NO_TAG, sizeof (mGpioTableAzbM80WwanEarlyPreMem) / sizeof (mGpioTableAzbM80WwanEarlyPreMem[0]), (UINT8*)mGpioTableAzbM80WwanEarlyPreMem);
+
+ MicroSecondDelay (20 * 1000); // Delay by 20ms
+
+ GpioSetOutputValue ( GPIO_VER2_LP_GPP_E5, 1);
+ MicroSecondDelay (80 * 1000); // Delay by 80ms
+
+ GpioSetOutputValue ( GPIO_VER2_LP_GPP_C5, 1);
+#endif
+
break;
default:
DEBUG ((DEBUG_ERROR, "Could not find pre-mem GPIO for PlatformId 0x%X!\n", GetPlatformId ()));
diff --git a/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.h b/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.h
index 0dabff1e..28563917 100644
--- a/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.h
+++ b/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.h
@@ -50,6 +50,7 @@
#include "GpioTableAdlPPreMem.h"
#include "GpioTableAdlNPreMem.h"
#include "GpioTableAdlPsPreMem.h"
+#include "GpioTableAzbPreMem.h"
#include "GpioTableTestPreMem.h"
#include
#include
diff --git a/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.inf b/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.inf
index cf089ca9..0749ab7a 100644
--- a/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.inf
+++ b/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.inf
@@ -1,6 +1,6 @@
## @file
#
-# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.
+# Copyright (c) 2020 - 2023, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -24,6 +24,7 @@
GpioTableAdlPPreMem.h
GpioTableTestPreMem.h
GpioTableAdlNPreMem.h
+ GpioTableAzbPreMem.h
Stage1BBoardInitLib.h
Stage1BBoardInitLib.c
RtcInit.c
@@ -86,3 +87,4 @@
[FixedPcd]
gPlatformAlderLakeTokenSpaceGuid.PcdAdlLpSupport
+ gPlatformAlderLakeTokenSpaceGuid.PcdAzbWwanSupport
diff --git a/Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/AcpiPlatform.c b/Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/AcpiPlatform.c
index afac5681..81c30426 100644
--- a/Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/AcpiPlatform.c
+++ b/Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/AcpiPlatform.c
@@ -1199,6 +1199,8 @@ PlatformUpdateAcpiGnvs (
PlatformNvs->WlanWakeGpio = GPIO_VER2_LP_GPP_D13;
PlatformNvs->WlanRootPortNumber = 4;
break;
+ case PLATFORM_ID_AZB_LP5_CRB2A:
+ break;
default:
DEBUG ((DEBUG_ERROR, "Could not find PlatformNvs settings for PlatformId 0x%X!\n", GetPlatformId ()));
break;
diff --git a/Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/CpuInfoLib.c b/Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/CpuInfoLib.c
index cf2a14b6..42a19d10 100644
--- a/Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/CpuInfoLib.c
+++ b/Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/CpuInfoLib.c
@@ -109,6 +109,12 @@ GetCpuSkuInfo (
CpuType = EnumCpuUlt;
SkuFound = TRUE;
break;
+ case V_SA_DEVICE_ID_MB_ULX_17: // ArizonaBeach (0+8+0)
+ case V_SA_DEVICE_ID_MB_ULX_18: // ArizonaBeach (0+4+0)
+ case V_SA_DEVICE_ID_MB_ULX_19: // ArizonaBeach (0+2+0)
+ CpuType = EnumCpuUlx;
+ SkuFound = TRUE;
+ break;
default:
break;
}
diff --git a/Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/MiscInit.c b/Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/MiscInit.c
index dfd4c3cc..acfdc399 100644
--- a/Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/MiscInit.c
+++ b/Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/MiscInit.c
@@ -21,14 +21,16 @@ UpdatePayloadId (
VOID
)
{
- EFI_STATUS Status;
UINT32 PayloadId;
GEN_CFG_DATA *GenericCfgData;
+#if !FixedPcdGetBool(PcdAzbSupport)
+ EFI_STATUS Status;
PLDSEL_CFG_DATA *PldSelCfgData;
UINT32 PayloadSelGpioData;
UINT32 PayloadSelGpioPad;
PayloadSelGpioData = 0;
+#endif
PayloadId = GetPayloadId ();
GenericCfgData = (GEN_CFG_DATA *)FindConfigDataByTag (CDATA_GEN_TAG);
@@ -49,6 +51,7 @@ UpdatePayloadId (
}
}
+#if !FixedPcdGetBool(PcdAzbSupport)
//
// Switch payloads based on configured GPIO pin
//
@@ -72,6 +75,6 @@ UpdatePayloadId (
DEBUG ((DEBUG_INFO, "Set PayloadId to 0x%08X based on GPIO config\n", PayloadId));
}
}
-
+#endif
SetPayloadId (PayloadId);
}
diff --git a/Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c b/Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
index b75a364c..da427ed1 100644
--- a/Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
+++ b/Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
@@ -450,7 +450,7 @@ BoardInit (
}
}
Status = PcdSet32S (PcdFuncCpuInitHook, (UINT32)(UINTN) PlatformCpuInit);
-
+#if !FixedPcdGetBool(PcdAzbSupport)
if (PcdGetBool (PcdFastBootEnabled) == FALSE) {
if (IsPchS ()) {
Status = HsPhyLoadAndInit ();
@@ -459,7 +459,7 @@ BoardInit (
}
}
}
-
+#endif
break;
case PostSiliconInit:
FusaConfigPostSi();
@@ -542,7 +542,9 @@ BoardInit (
/// Initialize the IGD OpRegion
///
}
+#if !FixedPcdGetBool(PcdAzbSupport)
IgdOpRegionPlatformInit ();
+#endif
///
/// Initialize the HECI device (for test HeciInitLib only)
diff --git a/Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.inf b/Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.inf
index 558e1cd0..47d60ec4 100644
--- a/Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.inf
+++ b/Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.inf
@@ -126,3 +126,4 @@
[FixedPcd]
gPlatformAlderLakeTokenSpaceGuid.PcdAdlLpSupport
gPlatformCommonLibTokenSpaceGuid.PcdTccEnabled
+ gPlatformAlderLakeTokenSpaceGuid.PcdAzbSupport
diff --git a/Platform/AlderlakeBoardPkg/Script/StitchIfwiConfig_azb.py b/Platform/AlderlakeBoardPkg/Script/StitchIfwiConfig_azb.py
new file mode 100644
index 00000000..6caf3619
--- /dev/null
+++ b/Platform/AlderlakeBoardPkg/Script/StitchIfwiConfig_azb.py
@@ -0,0 +1,254 @@
+## @ StitchIfwiConfig.py
+# This is an IFWI stitch config script for ADL Slim Bootloader
+#
+# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+extra_usage_txt = \
+"""This is an IFWI stitch config script for Slim Bootloader For the FIT tool and
+stitching ingredients listed in step 2 below, please contact your Intel representative.
+
+ 1. Create a stitching workspace directory. The paths mentioned below are all
+ relative to it.
+
+ 2. Extract required tools and ingredients to stitching workspace.
+ - FIT tool
+ Copy 'fit.exe' or 'fit' and 'vsccommn.bin' to 'Fit' folder
+ - BPMGEN2 Tool
+ Copy the contents of the tool to Bpmgen2 folder
+ Rename the bpmgen2 parameter to bpmgen2.params if its name is not this name.
+ - Components
+ Copy 'cse_image.bin' to 'Input/cse_image.bin'
+ Copy PMC firmware image to 'Input/pmc.bin'.
+ Copy EC firmware image to 'Input/ec.bin'.
+ copy ECregionpointer.bin to 'Input/ecregionpointer.bin'
+ Copy GBE binary image to 'Input/gbe.bin'.
+ Copy ACM firmware image to 'Input/acm.bin'.
+ Copy DiagnosticACM firmware image to 'Input/DiagnosticAcm.bin'.
+
+ 3. Openssl
+ Openssl is required for stitch. the stitch tool will search evn OPENSSL_PATH,
+ to find Openssl. If evn OPENSSL_PATH is not found, will find openssl from
+ "C:\\Openssl\\Openssl"
+
+ 4. Stitch the final image
+ EX:
+ Assuming stitching workspace is at D:\Stitch and building ifwi for ADL platform
+ To stitch IFWI with SPI QUAD mode and Boot Guard profile VM:
+ StitchIfwi.py -b vm -p adl -w D:\Stitch -s Stitch_Components.zip -c StitchIfwiConfig.py
+
+"""
+
+def get_bpmgen2_params_change_list ():
+ params_change_list = []
+ params_change_list.append ([
+ # variable | value |
+ # ===================================
+ ('PlatformRules', 'ADL Client'),
+ ('BpmStrutVersion', '0x20'),
+ ('BpmRevision', '0x01'),
+ ('BpmRevocation', '1'),
+ ('AcmRevocation', '2'),
+ ('NEMPages', '3'),
+ ('AcpiBase', '0x1800'),
+ ('IbbFlags', '0x2'),
+ ('IbbHashAlgID', '0x0C:SHA384'),
+ ('TxtInclude', 'FALSE'),
+ ('PcdInclude', 'TRUE'),
+ ('BpmSigScheme', '0x16:RSAPSS'),
+ ('BpmSigPubKey', r'BpmGen2/keys/bpm_pubkey_3072.pem'),
+ ('BpmSigPrivKey', r'BpmGen2/keys/bpm_privkey_3072.pem'),
+ ('BpmKeySizeBits', '3072'),
+ ('BpmSigHashAlgID', '0x0C:SHA384'),
+ ])
+ return params_change_list
+
+def get_platform_sku():
+ platform_sku ={
+ 'azb' : 'Intel(R) AlderLake P Chipset - Consumer - SPI',
+ }
+ return platform_sku
+
+def get_component_replace_list(plt_params_list):
+ replace_list = [
+ # Path file name compress Key SVN
+ ('IFWI/BIOS/TS0/ACM0', 'Input/acm0.bin', 'dummy', '', ''),
+ ('IFWI/BIOS/TS1/ACM0', 'Input/acm0.bin', 'dummy', '', ''),
+ ]
+
+ return replace_list
+
+def check_parameter(para_list):
+ print (para_list)
+ para_supported = {
+ 'lp5' : {},
+ 'debug' : {},
+ 'crb' : {},
+ }
+
+ para_help = \
+ """
+ 'lp5' -- Stitch for LP5 board, default configuration is set for LP5 board
+ 'debug' -- Enable DAM and DCI configuration (Only use for debug purpose but not for final production!)
+ 'crb' -- Select board type as CRB
+ """
+ for para in para_list:
+ if para == '':
+ print ("No platform specific parameter provided")
+ return True
+ if para not in para_supported:
+ print ("NOT support platform parameter: %s" % para)
+ print ("platform parameter list:\n")
+ print (para_help)
+ return False
+
+ if para_list[para] != None:
+ if para_list[para] not in para_supported[para]:
+ print ("NOT support platform parameter: %s" % para_list[para])
+ print ("platform parameter list:", para_supported[para])
+ return False
+ return True
+
+def get_oemkeymanifest_change_list():
+ xml_change_list = []
+ xml_change_list.append ([
+ # Path | value |
+ # =========================================================================================
+ ('./KeyManifestEntries/KeyManifestEntry/Usage', 'OemDebugManifest'),
+ ('./KeyManifestEntries/KeyManifestEntry/HashBinary', 'Temp/kmsigpubkey.hash'),
+ ])
+
+ return xml_change_list
+
+def get_xml_change_list (platform, plt_params_list):
+ xml_change_list = []
+ xml_change_list.append ([
+ # Path | value |
+ # =========================================================================================
+ #Region Order
+ ('./BuildSettings/BuildResults/RegionOrder', '653241'),
+ ('./BuildSettings/HarnessGlobalData/SelectedRvp', 'ADL-M LP5 RVP2A (ADL-M + ADP-P)'),
+ ('./FlashLayout/BiosRegion/InputFile', '$SourceDir\BiosRegion.bin'),
+ ('./FlashLayout/Ifwi_IntelMePmcRegion/MeRegionFile', '$SourceDir\MeRegionFile.bin'),
+ ('./FlashLayout/Ifwi_IntelMePmcRegion/PmcBinary', '$SourceDir\PmcBinary.bin'),
+ ('./FlashLayout/GbeRegion/InputFile', '$SourceDir\GbeRegion.bin'),
+ ('./FlashLayout/GbeRegion/Enabled', 'Enabled'),
+ ('./FlashLayout/SubPartitions/PchcSubPartitionData/InputFile', '$SourceDir\PchcSubPartitionData.bin'),
+ ('./FlashSettings/FlashConfiguration/SpiDualIoReadEnable', 'No'),
+ ('./FlashSettings/FlashConfiguration/SpiDualOutReadEnable', 'No'),
+ ('./PlatformProtection/ContentProtection/PavpSupported', 'Yes'),
+ ('./PlatformProtection/BootGuardConfiguration/BtGuardKeyManifestId', '0x1'),
+ ('./PlatformProtection/TpmOverSpiBusConfiguration/SpiOverTpmBusEnable', 'Yes'),
+ ('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC0', 'Enabled'),
+ ('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC1', 'Enabled'),
+ ('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC2', 'Enabled'),
+ ('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC3', 'Enabled'),
+ ('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC4', 'Enabled'),
+ ('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC5', 'Enabled'),
+ ('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC6', 'Disabled'),
+ ('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC7', 'Disabled'),
+ ('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC8', 'Disabled'),
+ ('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC9', 'Disabled'),
+ ('./NetworkingConnectivity/WiredLanConfiguration/PhyConnected', 'PHY on SMLink0'),
+ ('./NetworkingConnectivity/WiredLanConfiguration/GbePCIePortSelect', 'None'),
+ ('./IntegratedSensorHub/IntegratedSensorHub/IshPowerUpState', 'Enabled'),
+ ('./IntegratedSensorHub/IshImage/InputFile', '$SourceDir\IshImage.bin'),
+ ('./IntegratedSensorHub/IshData/PdtBinary', '$SourceDir\PdtBinary.bin'),
+ ('./Debug/DelayedAuthenticationModeConfiguration/DelayedAuthMode', 'No'),
+ ('./FlexIO/Type-CSubsystemConfiguration/IomBinaryFile', '$SourceDir\Iom_L0R0.bin'),
+ ('./FlexIO/Type-CSubsystemConfiguration/PhyBinaryFile', '$SourceDir\TypeC_NorthPHYRegion_L1.bin'),
+ ('./FlexIO/Type-CSubsystemConfiguration/TbtBinaryFile', '$SourceDir\TBT.bin'),
+ ('./FlexIO/Type-CSubsystemConfiguration/IomBinaryFile', '$SourceDir\Iom.bin'),
+ ('./FlexIO/Type-CSubsystemConfiguration/PhyBinaryFile', '$SourceDir\TypeC_NorthPHYRegion.bin'),
+ ('./PlatformProtection/IntelPttConfiguration/PttSupported', 'No'),
+ ('./PlatformProtection/IntelPttConfiguration/PttPwrUpState', 'Disabled'),
+ ('./PlatformProtection/BiosGuardConfiguration/BiosGrdProtOvrdEn', 'Yes'),
+ ('./NetworkingConnectivity/WiredLanConfiguration/LanEnable', 'No'),
+ ('./NetworkingConnectivity/WirelessLanConfiguration/MeClinkEnable', 'No'),
+ ('./FlexIO/PcieLaneReversalConfiguration/PCIeCtrl3LnReversal', 'No'),
+ ('./FlexIO/SataPcieComboPortConfiguration/SataPCIeComboPort0', 'Disabled'),
+ ('./FlexIO/SataPcieComboPortConfiguration/SataPCIeComboPort1', 'Disabled'),
+ ('./FlexIO/Usb3PortConfiguration/USB3PCIeComboPort3', 'PCIe'),
+ ('./FlexIO/Usb2PortConfiguration/USB2Prt4ConTypeSel', 'Express Card / M.2 S2'),
+ ('./InternalPchBuses/EspiConfiguration/EspiEcMaxIoMode', 'Single, Dual and Quad'),
+ ('./CpuStraps/CpuStraps/Mipi124RailSrcPlat', 'Yes'),
+ ('./CpuStraps/CpuStraps/VccSaSvidVrAddr', '0x2'),
+ ('./FlexIO/Type-CSubsystemConfiguration/TypeCPort3Config', 'DP Fixed Connection'),
+ ('./FlexIO/ThunderboltConfiguration/TboltEnable', 'No'),
+ ('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort3Mode', 'No'),
+ ('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort3RetimerEnabled','No'),
+ ('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort4Mode', 'No'),
+ ('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort4RetimerEnabled','No'),
+ ('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort4SmbusAddr', 'No'),
+ ('./FlexIO/PowerDelivery_PdControllerConfiguration/USB2PortForTypeCPort4', 'USB2 Port 4'),
+ ('./Gpio/GpioVccioVoltageControl/GppA23voltSelect', '3.3Volts'),
+ ('./Gpio/ThunderboltLsxBssb-LsConfiguration/TbltLsxBssbLs2Cfg', 'Legacy VCCIO'),
+ ('./Gpio/ThunderboltLsxBssb-LsConfiguration/TbltLsxBssbLs3Cfg', 'Legacy VCCIO'),
+ ('./InternalPchBuses/EspiConfiguration/EspiEcBusfreq', '20MHZ'),
+ ('./FlashLayout/EcRegion/InputFile', '$SourceDir\EcRegion.bin'),
+ ('./FlashLayout/EcRegion/Enabled', 'Enabled'),
+ ('./FlashLayout/EcRegion/EcRegionPointer', '$SourceDir\EcRegionPointer.bin'),
+ ('./FlashSettings/BiosConfiguration/TopSwapOverride', '256KB'),
+ ('./PlatformProtection/PlatformIntegrity/OemPublicKeyHash', '17 D1 1C 85 98 77 13 B3 15 3D E5 80 F5 2F C0 F6 03 7C CE 22 91 E8 A6 B2 BD D4 95 20 BC 5E 00 6F 38 F8 18 60 6A 3A 7B 62 89 DA 05 7F D9 4E 50 B9'),
+ ('./FlexIO/PciePortConfiguration/PCIeController2Config', '4x1'),
+ ('./FlexIO/PciePortConfiguration/PCIeController3Config', '4x1'),
+ ('./CpuStraps/CpuStraps/GtsVrType', 'Fixed VR'),
+ ('./FlashSettings/FlashConfiguration/QuadOutReadEnable', 'No'),
+ ('./FlashSettings/FlashConfiguration/QuadIoReadEnable', 'No'),
+ ('./FlashSettings/FlashConfiguration/FastReadSupport', 'No'),
+ ('./FlexIO/UfsConfiguration/UfsCont1Config', 'X1'),
+ ('./Gpio/GpioVccioVoltageControl/GppH3voltSelect', '3.3Volts'),
+ ('./Gpio/GpioVccioVoltageControl/GppH4voltSelect', '3.3Volts'),
+ ('./Gpio/GpioVccioVoltageControl/GppH5voltSelect', '3.3Volts'),
+ ('./Gpio/GpioVccioVoltageControl/GppH6voltSelect', '3.3Volts'),
+ ('./Gpio/GpioVccioVoltageControl/GppH7voltSelect', '3.3Volts'),
+ ('./Gpio/GpioVccioVoltageControl/GppH12voltSelect', '3.3Volts'),
+ ('./Dnx/OEMandPlatformIDs/DnxEnabled', 'No'),
+ ('./FlexIO/Usb3PortConfiguration/USB3PCIeComboPort1', 'PCIe'),
+ ('./FlexIO/Usb2PortConfiguration/USB2Prt3ConTypeSel', 'Express Card / M.2 S2'),
+ ('./FlexIO/Usb2PortConfiguration/USB2Prt5ConTypeSel', 'Express Card / M.2 S2'),
+ ('./FlexIO/Usb2PortConfiguration/USB2Prt6ConTypeSel', 'Express Card / M.2 S2'),
+ ('./FlashSettings/FlashConfiguration/FastReadClockFreq', '14MHz'),
+ ('./FlashSettings/FlashConfiguration/WriteEraseClockFreq', '14MHz'),
+ ('./FlashSettings/FlashConfiguration/ReadIdAndReadStatClkFreq', '14MHz'),
+ ('./PlatformProtection/IntelPttConfiguration/PttSupportedFpf', 'No'),
+ ('./Power/DeepSx/DeepSxSupportEnable', 'No'),
+ ('./Camera/IPUSecurity/SecureTouchCameraMask', '0x0'),
+ ('./Debug/IntelMeFirmwareDebuggingOverrides/DbgOverridePreProdSi', '0x0'),
+ ('./Debug/DirectConnectInterfaceConfiguration/DciDbcEnable', 'No'),
+ ('./Debug/DirectConnectInterfaceConfiguration/Usb1DciOobEnable', 'No'),
+ ('./Debug/DirectConnectInterfaceConfiguration/Usb2DciOobEnable', 'No'),
+ ('./Debug/DirectConnectInterfaceConfiguration/Usb3DciOobEnable', 'No'),
+ ('./Debug/DirectConnectInterfaceConfiguration/Usb4DciOobEnable', 'No'),
+ ('./FlexIO/Usb3PortConfiguration/USB3Prt1ConTypeSel', 'Type A / Type C'),
+ ('./FlexIO/Usb3PortConfiguration/USB3Prt2ConTypeSel', 'Express Card / M.2 S2'),
+ ('./FlexIO/Usb3PortConfiguration/USB3Prt3ConTypeSel', 'Type A / Type C'),
+ ('./FlexIO/Usb2PortConfiguration/USB2Prt1ConTypeSel', 'Type A / Type C'),
+ ('./FlexIO/Usb2PortConfiguration/USB2Prt2ConTypeSel', 'Type A / Type C'),
+ ('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort1Mode', 'No'),
+ ('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort1RetimerEnabled','No'),
+ ('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort1SmbusAddr', '0x0'),
+ ('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort2Mode', 'No'),
+ ('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort2RetimerEnabled','No'),
+ ('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort2SMBusAddr', '0x0'),
+ ('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort3SmbusAddr', '0x0'),
+ ('./IntelUniquePlatformId/EntitlementsConfiguration/IcpsSwSkuing', 'Yes'),
+ ('./FlexIO/Type-CSubsystemConfiguration/TypecPort1ConTypeSel', 'Type C'),
+ ('./FlexIO/Type-CSubsystemConfiguration/TcssPortEnMask', '0x1'),
+ ('./FlexIO/Type-CSubsystemConfiguration/TypeCPort1Config', 'No Thunderbolt'),
+ ])
+
+ if 'debug' in plt_params_list:
+ print ("Applying changes to enable DAM and DCI")
+ xml_change_list.append ([
+ ('./Debug/DelayedAuthenticationModeConfiguration/DelayedAuthMode', 'Yes'),
+ ('./PlatformProtection/BootGuardConfiguration/BtGuardCpuDebugEnable', 'Enabled'),
+ ('./Debug/DirectConnectInterfaceConfiguration/DciDbcEnable', 'Yes'),
+ ('./Debug/DirectConnectInterfaceConfiguration/Usb1DciOobEnable', 'Yes'),
+ ('./Debug/DirectConnectInterfaceConfiguration/Usb2DciOobEnable', 'Yes'),
+ ('./Debug/DirectConnectInterfaceConfiguration/Usb3DciOobEnable', 'Yes'),
+ ('./Debug/DirectConnectInterfaceConfiguration/Usb4DciOobEnable', 'Yes'),
+ ])
+ return xml_change_list
diff --git a/Silicon/.gitignore b/Silicon/.gitignore
index 54c4352d..5be63af6 100644
--- a/Silicon/.gitignore
+++ b/Silicon/.gitignore
@@ -4,3 +4,4 @@ FspRel.bin
Fsp*.h
*.mcb
ElkhartlakePkg/Include/MemInfoHob.h
+FSP_License.pdf
diff --git a/Silicon/AlderlakePkg/AlderlakePkg.dec b/Silicon/AlderlakePkg/AlderlakePkg.dec
index fd40af56..4bcfc62e 100644
--- a/Silicon/AlderlakePkg/AlderlakePkg.dec
+++ b/Silicon/AlderlakePkg/AlderlakePkg.dec
@@ -24,6 +24,8 @@
[PcdsFixedAtBuild]
gPlatformAlderLakeTokenSpaceGuid.PcdAdlLpSupport | FALSE | BOOLEAN | 0x30000100
gPlatformAlderLakeTokenSpaceGuid.PcdAdlNSupport | FALSE | BOOLEAN | 0x30000101
+ gPlatformAlderLakeTokenSpaceGuid.PcdAzbSupport | FALSE | BOOLEAN | 0x30000102
+ gPlatformAlderLakeTokenSpaceGuid.PcdAzbWwanSupport | FALSE | BOOLEAN | 0x30000103
[PcdsDynamic]
- gPlatformAlderLakeTokenSpaceGuid.PcdFusaDiagnosticBoot | 0 | BOOLEAN | 0x30000200
\ No newline at end of file
+ gPlatformAlderLakeTokenSpaceGuid.PcdFusaDiagnosticBoot | 0 | BOOLEAN | 0x30000200
diff --git a/Silicon/AlderlakePkg/FspBin/FspBin.inf b/Silicon/AlderlakePkg/FspBin/FspBin.inf
index e35109b3..73734d6a 100644
--- a/Silicon/AlderlakePkg/FspBin/FspBin.inf
+++ b/Silicon/AlderlakePkg/FspBin/FspBin.inf
@@ -50,3 +50,12 @@
AlderLakeFspBinPkg/IoT/AlderLakeN/Include/FspmUpd.h : Silicon/AlderlakePkg/Adln/Include/FspmUpd.h
AlderLakeFspBinPkg/IoT/AlderLakeN/Include/FspsUpd.h : Silicon/AlderlakePkg/Adln/Include/FspsUpd.h
FSP_License.pdf : Silicon/AlderlakePkg/Adln/FspBin/FSP_License.pdf
+# For AZB
+ AlderLakeFspBinPkg/IoT/ArizonaBeach/Fsp.fd : Silicon/AlderlakePkg/Azb/FspBin/FspDbg.bin
+ AlderLakeFspBinPkg/IoT/ArizonaBeach/Fsp.fd : Silicon/AlderlakePkg/Azb/FspBin/FspRel.bin
+ AlderLakeFspBinPkg/IoT/ArizonaBeach/Fsp.bsf : Silicon/AlderlakePkg/Azb/FspBin/Fsp.bsf
+ AlderLakeFspBinPkg/IoT/ArizonaBeach/Include/FspUpd.h : Silicon/AlderlakePkg/Azb/Include/FspUpd.h
+ AlderLakeFspBinPkg/IoT/ArizonaBeach/Include/FsptUpd.h : Silicon/AlderlakePkg/Azb/Include/FsptUpd.h
+ AlderLakeFspBinPkg/IoT/ArizonaBeach/Include/FspmUpd.h : Silicon/AlderlakePkg/Azb/Include/FspmUpd.h
+ AlderLakeFspBinPkg/IoT/ArizonaBeach/Include/FspsUpd.h : Silicon/AlderlakePkg/Azb/Include/FspsUpd.h
+ FSP_License.pdf : Silicon/AlderlakePkg/Azb/FspBin/FSP_License.pdf
diff --git a/Silicon/AlderlakePkg/Include/GpioPinsVer2Lp.h b/Silicon/AlderlakePkg/Include/GpioPinsVer2Lp.h
index 02954a83..a7aad6a9 100644
--- a/Silicon/AlderlakePkg/Include/GpioPinsVer2Lp.h
+++ b/Silicon/AlderlakePkg/Include/GpioPinsVer2Lp.h
@@ -1,7 +1,7 @@
/**@file
GPIO pins for ADL-PCH-LP,
- Copyright (c) 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -54,6 +54,7 @@
#define GPIO_VER2_LP_GPP_A1 0x09020001
#define GPIO_VER2_LP_GPP_A2 0x09020002
+#define GPIO_VER2_LP_GPP_A6 0x09020006
#define GPIO_VER2_LP_GPP_A7 0x09020007
#define GPIO_VER2_LP_GPP_A8 0x09020008
#define GPIO_VER2_LP_GPP_A11 0x0902000B
@@ -83,11 +84,14 @@
#define GPIO_VER2_LP_GPP_H3 0x09070003
#define GPIO_VER2_LP_GPP_H10 0x0907000A
#define GPIO_VER2_LP_GPP_H11 0x0907000B
+#define GPIO_VER2_LP_GPP_H13 0x0907000D
#define GPIO_VER2_LP_GPP_H17 0x09070011
#define GPIO_VER2_LP_GPP_H19 0x09070013
#define GPIO_VER2_LP_GPP_H23 0x09070017
#define GPIO_VER2_LP_GPP_D1 0x09080001
+#define GPIO_VER2_LP_GPP_D9 0x09080009
+#define GPIO_VER2_LP_GPP_D10 0x0908000A
#define GPIO_VER2_LP_GPP_D11 0x0908000B
#define GPIO_VER2_LP_GPP_D13 0x0908000D
#define GPIO_VER2_LP_GPP_D14 0x0908000E
@@ -98,6 +102,7 @@
#define GPIO_VER2_LP_GPP_C2 0x090B0002
+#define GPIO_VER2_LP_GPP_C5 0x090B0005
#define GPIO_VER2_LP_GPP_F1 0x090C0001
diff --git a/Silicon/AlderlakePkg/Include/Register/PchBdfAssignment.h b/Silicon/AlderlakePkg/Include/Register/PchBdfAssignment.h
index 621438cf..6ace67ee 100644
--- a/Silicon/AlderlakePkg/Include/Register/PchBdfAssignment.h
+++ b/Silicon/AlderlakePkg/Include/Register/PchBdfAssignment.h
@@ -50,6 +50,9 @@
#define PCI_DEVICE_NUMBER_PCH_XHCI 20
#define PCI_FUNCTION_NUMBER_PCH_XHCI 0
+#define PCI_DEVICE_NUMBER_PCH_XHCI_1 13
+#define PCI_FUNCTION_NUMBER_PCH_XHCI_1 0
+
//
// xDCI (OTG) USB Device Controller
//
diff --git a/Silicon/AlderlakePkg/Include/Register/SaRegsHostBridge.h b/Silicon/AlderlakePkg/Include/Register/SaRegsHostBridge.h
index a086ea34..116e9cc9 100644
--- a/Silicon/AlderlakePkg/Include/Register/SaRegsHostBridge.h
+++ b/Silicon/AlderlakePkg/Include/Register/SaRegsHostBridge.h
@@ -107,6 +107,10 @@
#define V_SA_DEVICE_ID_INDU_ULX_16 0x4675 ///< ASL (0+8) 2C IOT_INDU
#define V_SA_DEVICE_ID_INDU_ULX_17 0x4632 ///< ASL (0+8) 2C IOT_INDU IPU Defeature SKU
+#define V_SA_DEVICE_ID_MB_ULX_17 0x4672 ///< ArizonaBeach (0+8+0) SA DID
+#define V_SA_DEVICE_ID_MB_ULX_18 0x4676 ///< ArizonaBeach (0+4+0) SA DID
+#define V_SA_DEVICE_ID_MB_ULX_19 0x467A ///< ArizonaBeach (0+2+0) SA DID
+
/**
Description:
This is the base address for the PCI Express Egress Port MMIO Configuration space. There is no physical memory within this 4KB window that can be addressed. The 4KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, the EGRESS port MMIO configuration space is disabled and must be enabled by writing a 1 to PXPEPBAREN [Dev 0, offset 40h, bit 0].
diff --git a/Silicon/AlderlakePkg/Microcode/MicrocodeAzb.inf b/Silicon/AlderlakePkg/Microcode/MicrocodeAzb.inf
new file mode 100644
index 00000000..a5d7e4ec
--- /dev/null
+++ b/Silicon/AlderlakePkg/Microcode/MicrocodeAzb.inf
@@ -0,0 +1,24 @@
+## @file
+#
+# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = Microcode
+ FILE_GUID = 40762366-24D3-4A6E-9F43-5AC5085D34EB
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ m_40_906a4_00000005.mcb
+
+[UserExtensions.SBL."CloneRepo"]
+ REPO = https://github.com/slimbootloader/firmwareblob.git
+ COMMIT = 1e0bf6741239bbcb5bfd6a0dec78912afee18324
+
+[UserExtensions.SBL."CopyList"]
+ Microcode/AlderLake/m_40_906a4_00000005.pdb : Silicon/AlderlakePkg/Microcode/m_40_906a4_00000005.mcb