diff --git a/Silicon/ArrowlakePkg/Include/GpioPinsVer2Lp.h b/Silicon/ArrowlakePkg/Include/GpioPinsVer2Lp.h
deleted file mode 100644
index 6bdf6561..00000000
--- a/Silicon/ArrowlakePkg/Include/GpioPinsVer2Lp.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/** @file
- GPIO pins for TGL-PCH-LP,
-
- Copyright (c) 2024, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-#ifndef _GPIO_PINS_VER2_LP_H_
-#define _GPIO_PINS_VER2_LP_H_
-
-///
-/// Unique ID used in GpioPad defines
-///
-#define GPIO_VER2_LP_CHIPSET_ID 0x9
-
-///
-/// TGL LP GPIO Groups
-/// Use below for functions from PCH GPIO Lib which
-/// require GpioGroup as argument
-///
-#define GPIO_VER2_LP_GROUP_GPP_B 0x0900
-#define GPIO_VER2_LP_GROUP_GPP_T 0x0901
-#define GPIO_VER2_LP_GROUP_GPP_A 0x0902
-#define GPIO_VER2_LP_GROUP_GPP_R 0x0903
-#define GPIO_VER2_LP_GROUP_GPD 0x0905
-#define GPIO_VER2_LP_GROUP_GPP_S 0x0906
-#define GPIO_VER2_LP_GROUP_GPP_H 0x0907
-#define GPIO_VER2_LP_GROUP_GPP_D 0x0908
-#define GPIO_VER2_LP_GROUP_GPP_U 0x0909
-#define GPIO_VER2_LP_GROUP_VGPIO 0x090A
-#define GPIO_VER2_LP_GROUP_GPP_C 0x090B
-#define GPIO_VER2_LP_GROUP_GPP_F 0x090C
-#define GPIO_VER2_LP_GROUP_GPP_E 0x090E
-
-
-#endif // _GPIO_PINS_VER2_LP_H_
diff --git a/Silicon/ArrowlakePkg/Include/GpioPinsVer4S.h b/Silicon/ArrowlakePkg/Include/GpioPinsVer4S.h
deleted file mode 100644
index 3638bae4..00000000
--- a/Silicon/ArrowlakePkg/Include/GpioPinsVer4S.h
+++ /dev/null
@@ -1,473 +0,0 @@
-/** @file
- GPIO pins for ADL-PCH-S,
-
- Copyright (c) 2024, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-#ifndef _GPIO_PINS_VER4_S_H_
-#define _GPIO_PINS_VER4_S_H_
-
-///
-/// Unique ID used in GpioPad defines
-///
-#define GPIO_VER4_S_CHIPSET_ID 0x8
-
-///
-/// ADL S GPIO Groups
-/// Use below for functions from PCH GPIO Lib which
-/// require GpioGroup as argument
-///
-#define GPIO_VER4_S_GROUP_GPD 0x0808
-
-
-///
-/// Unique ID used in GpioPad defines
-///
-#define GPIO_VER6_SOC_S_CHIPSET_ID 0xA
-
-///
-/// MTL SoC-S GPIO Groups
-/// Use below for functions from PCH GPIO Lib which
-/// require GpioGroup as argument
-///
-// COM0
-#define GPIO_VER6_SOC_S_GROUP_GPP_A ((GPIO_VER6_SOC_S_CHIPSET_ID << 8) | 0x00)
-#define GPIO_VER6_SOC_S_GROUP_VGPIO_0 ((GPIO_VER6_SOC_S_CHIPSET_ID << 8) | 0x01)
-#define GPIO_VER6_SOC_S_GROUP_GPP_C ((GPIO_VER6_SOC_S_CHIPSET_ID << 8) | 0x02)
-// COM1
-#define GPIO_VER6_SOC_S_GROUP_GPP_B ((GPIO_VER6_SOC_S_CHIPSET_ID << 8) | 0x03)
-#define GPIO_VER6_SOC_S_GROUP_VGPIO_3 ((GPIO_VER6_SOC_S_CHIPSET_ID << 8) | 0x04)
-#define GPIO_VER6_SOC_S_GROUP_GPP_D ((GPIO_VER6_SOC_S_CHIPSET_ID << 8) | 0x05)
-// COM2
-// COM3
-#define GPIO_VER6_SOC_S_GROUP_JTAG ((GPIO_VER6_SOC_S_CHIPSET_ID << 8) | 0x06)
-#define GPIO_VER6_SOC_S_GROUP_VGPIO_4 ((GPIO_VER6_SOC_S_CHIPSET_ID << 8) | 0x07)
-
-
-///
-/// Unique ID used in GpioPad defines
-///
-#define GPIO_VER6_SOC_M_CHIPSET_ID 0xA
-
-///
-/// MTL SoC-M GPIO Groups
-/// Use below for functions from PCH GPIO Lib which
-/// require GpioGroup as argument
-///
-// COM0
-#define GPIO_VER6_SOC_M_GROUP_CPU ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x00)
-#define GPIO_VER6_SOC_M_GROUP_GPP_V ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x01)
-#define GPIO_VER6_SOC_M_GROUP_GPP_C ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x02)
-// COM1
-#define GPIO_VER6_SOC_M_GROUP_GPP_A ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x03)
-#define GPIO_VER6_SOC_M_GROUP_GPP_E ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x04)
-// COM2
-// COM3
-#define GPIO_VER6_SOC_M_GROUP_GPP_H ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x05)
-#define GPIO_VER6_SOC_M_GROUP_GPP_F ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x06)
-#define GPIO_VER6_SOC_M_GROUP_SPI_SYS ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x07)
-#define GPIO_VER6_SOC_M_GROUP_USB_THC ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x08)
-// COM4
-#define GPIO_VER6_SOC_M_GROUP_GPP_S ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x09)
-#define GPIO_VER6_SOC_M_GROUP_JTAG ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x0A)
-// COM5
-#define GPIO_VER6_SOC_M_GROUP_GPP_B ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x0B)
-#define GPIO_VER6_SOC_M_GROUP_GPP_D ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x0C)
-#define GPIO_VER6_SOC_M_GROUP_VGPIO ((GPIO_VER6_SOC_M_CHIPSET_ID << 8) | 0x0D)
-
-///
-/// MTL SOC GPIO pins
-/// Use below for functions from PCH GPIO Lib which
-/// require GpioPad as argument. Encoding used here
-/// has all information required by library functions
-///
-// COM0
-#define GPIO_VER6_SOC_M_CPU_PECI ((GPIO_VER6_SOC_M_GROUP_CPU << 16 ) | 0x00)
-#define GPIO_VER6_SOC_M_CPU_RESET_B ((GPIO_VER6_SOC_M_GROUP_CPU << 16 ) | 0x01)
-#define GPIO_VER6_SOC_M_CPU_SOUT ((GPIO_VER6_SOC_M_GROUP_CPU << 16 ) | 0x02)
-#define GPIO_VER6_SOC_M_CPU_SCK ((GPIO_VER6_SOC_M_GROUP_CPU << 16 ) | 0x03)
-#define GPIO_VER6_SOC_M_CPU_ALERT_B ((GPIO_VER6_SOC_M_GROUP_CPU << 16 ) | 0x04)
-
-#define GPIO_VER6_SOC_M_GPP_V0 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x00)
-#define GPIO_VER6_SOC_M_GPP_V1 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x01)
-#define GPIO_VER6_SOC_M_GPP_V2 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x02)
-#define GPIO_VER6_SOC_M_GPP_V3 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x03)
-#define GPIO_VER6_SOC_M_GPP_V4 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x04)
-#define GPIO_VER6_SOC_M_GPP_V5 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x05)
-#define GPIO_VER6_SOC_M_GPP_V6 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x06)
-#define GPIO_VER6_SOC_M_GPP_V7 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x07)
-#define GPIO_VER6_SOC_M_GPP_V8 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x08)
-#define GPIO_VER6_SOC_M_GPP_V9 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x09)
-#define GPIO_VER6_SOC_M_GPP_V10 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x0A)
-#define GPIO_VER6_SOC_M_GPP_V11 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x0B)
-#define GPIO_VER6_SOC_M_GPP_V12 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x0C)
-#define GPIO_VER6_SOC_M_GPP_V13 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x0D)
-#define GPIO_VER6_SOC_M_GPP_V14 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x0E)
-#define GPIO_VER6_SOC_M_GPP_V15 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x0F)
-#define GPIO_VER6_SOC_M_GPP_V16 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x10)
-#define GPIO_VER6_SOC_M_GPP_V17 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x11)
-#define GPIO_VER6_SOC_M_GPP_V18 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x12)
-#define GPIO_VER6_SOC_M_GPP_V19 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x13)
-#define GPIO_VER6_SOC_M_GPP_V20 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x14)
-#define GPIO_VER6_SOC_M_GPP_V21 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x15)
-#define GPIO_VER6_SOC_M_GPP_V22 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x16)
-#define GPIO_VER6_SOC_M_GPP_V23 ((GPIO_VER6_SOC_M_GROUP_GPP_V << 16 ) | 0x17)
-
-#define GPIO_VER6_SOC_M_GPP_C0 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x00)
-#define GPIO_VER6_SOC_M_GPP_C1 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x01)
-#define GPIO_VER6_SOC_M_GPP_C2 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x02)
-#define GPIO_VER6_SOC_M_GPP_C3 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x03)
-#define GPIO_VER6_SOC_M_GPP_C4 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x04)
-#define GPIO_VER6_SOC_M_GPP_C5 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x05)
-#define GPIO_VER6_SOC_M_GPP_C6 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x06)
-#define GPIO_VER6_SOC_M_GPP_C7 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x07)
-#define GPIO_VER6_SOC_M_GPP_C8 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x08)
-#define GPIO_VER6_SOC_M_GPP_C9 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x09)
-#define GPIO_VER6_SOC_M_GPP_C10 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x0A)
-#define GPIO_VER6_SOC_M_GPP_C11 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x0B)
-#define GPIO_VER6_SOC_M_GPP_C12 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x0C)
-#define GPIO_VER6_SOC_M_GPP_C13 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x0D)
-#define GPIO_VER6_SOC_M_GPP_C14 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x0E)
-#define GPIO_VER6_SOC_M_GPP_C15 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x0F)
-#define GPIO_VER6_SOC_M_GPP_C16 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x10)
-#define GPIO_VER6_SOC_M_GPP_C17 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x11)
-#define GPIO_VER6_SOC_M_GPP_C18 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x12)
-#define GPIO_VER6_SOC_M_GPP_C19 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x13)
-#define GPIO_VER6_SOC_M_GPP_C20 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x14)
-#define GPIO_VER6_SOC_M_GPP_C21 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x15)
-#define GPIO_VER6_SOC_M_GPP_C22 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x16)
-#define GPIO_VER6_SOC_M_GPP_C23 ((GPIO_VER6_SOC_M_GROUP_GPP_C << 16 ) | 0x17)
-
-// COM1
-#define GPIO_VER6_SOC_M_GPP_A0 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x00)
-#define GPIO_VER6_SOC_M_GPP_A1 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x01)
-#define GPIO_VER6_SOC_M_GPP_A2 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x02)
-#define GPIO_VER6_SOC_M_GPP_A3 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x03)
-#define GPIO_VER6_SOC_M_GPP_A4 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x04)
-#define GPIO_VER6_SOC_M_GPP_A5 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x05)
-#define GPIO_VER6_SOC_M_GPP_A6 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x06)
-#define GPIO_VER6_SOC_M_GPP_A7 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x07)
-#define GPIO_VER6_SOC_M_GPP_A8 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x08)
-#define GPIO_VER6_SOC_M_GPP_A9 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x09)
-#define GPIO_VER6_SOC_M_GPP_A10 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x0A)
-#define GPIO_VER6_SOC_M_GPP_A11 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x0B)
-#define GPIO_VER6_SOC_M_GPP_A12 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x0C)
-#define GPIO_VER6_SOC_M_GPP_A13 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x0D)
-#define GPIO_VER6_SOC_M_GPP_A14 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x0E)
-#define GPIO_VER6_SOC_M_GPP_A15 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x0F)
-#define GPIO_VER6_SOC_M_GPP_A16 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x10)
-#define GPIO_VER6_SOC_M_GPP_A17 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x11)
-#define GPIO_VER6_SOC_M_GPP_A18 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x12)
-#define GPIO_VER6_SOC_M_GPP_A19 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x13)
-#define GPIO_VER6_SOC_M_GPP_A20 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x14)
-#define GPIO_VER6_SOC_M_GPP_A21 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x15)
-#define GPIO_VER6_SOC_M_GPP_A22 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x16)
-#define GPIO_VER6_SOC_M_GPP_A23 ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x17)
-#define GPIO_VER6_SOC_M_ESPI_CLK_LOOPBK ((GPIO_VER6_SOC_M_GROUP_GPP_A << 16 ) | 0x18)
-
-#define GPIO_VER6_SOC_M_GPP_E0 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x00)
-#define GPIO_VER6_SOC_M_GPP_E1 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x01)
-#define GPIO_VER6_SOC_M_GPP_E2 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x02)
-#define GPIO_VER6_SOC_M_GPP_E3 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x03)
-#define GPIO_VER6_SOC_M_GPP_E4 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x04)
-#define GPIO_VER6_SOC_M_GPP_E5 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x05)
-#define GPIO_VER6_SOC_M_GPP_E6 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x06)
-#define GPIO_VER6_SOC_M_GPP_E7 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x07)
-#define GPIO_VER6_SOC_M_GPP_E8 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x08)
-#define GPIO_VER6_SOC_M_GPP_E9 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x09)
-#define GPIO_VER6_SOC_M_GPP_E10 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x0A)
-#define GPIO_VER6_SOC_M_GPP_E11 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x0B)
-#define GPIO_VER6_SOC_M_GPP_E12 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x0C)
-#define GPIO_VER6_SOC_M_GPP_E13 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x0D)
-#define GPIO_VER6_SOC_M_GPP_E14 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x0E)
-#define GPIO_VER6_SOC_M_GPP_E15 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x0F)
-#define GPIO_VER6_SOC_M_GPP_E16 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x10)
-#define GPIO_VER6_SOC_M_GPP_E17 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x11)
-#define GPIO_VER6_SOC_M_GPP_E18 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x12)
-#define GPIO_VER6_SOC_M_GPP_E19 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x13)
-#define GPIO_VER6_SOC_M_GPP_E20 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x14)
-#define GPIO_VER6_SOC_M_GPP_E21 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x15)
-#define GPIO_VER6_SOC_M_GPP_E22 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x16)
-#define GPIO_VER6_SOC_M_GPP_E23 ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x17)
-#define GPIO_VER6_SOC_M_THC0_GPSI0_CLK_LOOPBK ((GPIO_VER6_SOC_M_GROUP_GPP_E << 16 ) | 0x18)
-
-// COM2
-// COM3
-#define GPIO_VER6_SOC_M_GPP_H0 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x00)
-#define GPIO_VER6_SOC_M_GPP_H1 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x01)
-#define GPIO_VER6_SOC_M_GPP_H2 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x02)
-#define GPIO_VER6_SOC_M_GPP_H3 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x03)
-#define GPIO_VER6_SOC_M_GPP_H4 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x04)
-#define GPIO_VER6_SOC_M_GPP_H5 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x05)
-#define GPIO_VER6_SOC_M_GPP_H6 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x06)
-#define GPIO_VER6_SOC_M_GPP_H7 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x07)
-#define GPIO_VER6_SOC_M_GPP_H8 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x08)
-#define GPIO_VER6_SOC_M_GPP_H9 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x09)
-#define GPIO_VER6_SOC_M_GPP_H10 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x0A)
-#define GPIO_VER6_SOC_M_GPP_H11 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x0B)
-#define GPIO_VER6_SOC_M_GPP_H12 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x0C)
-#define GPIO_VER6_SOC_M_GPP_H13 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x0D)
-#define GPIO_VER6_SOC_M_GPP_H14 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x0E)
-#define GPIO_VER6_SOC_M_GPP_H15 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x0F)
-#define GPIO_VER6_SOC_M_GPP_H16 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x10)
-#define GPIO_VER6_SOC_M_GPP_H17 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x11)
-#define GPIO_VER6_SOC_M_GPP_H18 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x12)
-#define GPIO_VER6_SOC_M_GPP_H19 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x13)
-#define GPIO_VER6_SOC_M_GPP_H20 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x14)
-#define GPIO_VER6_SOC_M_GPP_H21 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x15)
-#define GPIO_VER6_SOC_M_GPP_H22 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x16)
-#define GPIO_VER6_SOC_M_GPP_H23 ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x17)
-#define GPIO_VER6_SOC_M_LPI3C1_CLK_LOOPBK ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x18)
-#define GPIO_VER6_SOC_M_LPI3C0_CLK_LOOPBK ((GPIO_VER6_SOC_M_GROUP_GPP_H << 16 ) | 0x19)
-
-#define GPIO_VER6_SOC_M_GPP_F0 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x00)
-#define GPIO_VER6_SOC_M_GPP_F1 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x01)
-#define GPIO_VER6_SOC_M_GPP_F2 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x02)
-#define GPIO_VER6_SOC_M_GPP_F3 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x03)
-#define GPIO_VER6_SOC_M_GPP_F4 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x04)
-#define GPIO_VER6_SOC_M_GPP_F5 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x05)
-#define GPIO_VER6_SOC_M_GPP_F6 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x06)
-#define GPIO_VER6_SOC_M_GPP_F7 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x07)
-#define GPIO_VER6_SOC_M_GPP_F8 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x08)
-#define GPIO_VER6_SOC_M_GPP_F9 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x09)
-#define GPIO_VER6_SOC_M_GPP_F10 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x0A)
-#define GPIO_VER6_SOC_M_GPP_F11 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x0B)
-#define GPIO_VER6_SOC_M_GPP_F12 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x0C)
-#define GPIO_VER6_SOC_M_GPP_F13 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x0D)
-#define GPIO_VER6_SOC_M_GPP_F14 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x0E)
-#define GPIO_VER6_SOC_M_GPP_F15 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x0F)
-#define GPIO_VER6_SOC_M_GPP_F16 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x10)
-#define GPIO_VER6_SOC_M_GPP_F17 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x11)
-#define GPIO_VER6_SOC_M_GPP_F18 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x12)
-#define GPIO_VER6_SOC_M_GPP_F19 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x13)
-#define GPIO_VER6_SOC_M_GPP_F20 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x14)
-#define GPIO_VER6_SOC_M_GPP_F21 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x15)
-#define GPIO_VER6_SOC_M_GPP_F22 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x16)
-#define GPIO_VER6_SOC_M_GPP_F23 ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x17)
-#define GPIO_VER6_SOC_M_THC1_GSPI1_CLK_LOOPBK ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x18)
-#define GPIO_VER6_SOC_M_GSPI0A_CLK_LOOPBK ((GPIO_VER6_SOC_M_GROUP_GPP_F << 16 ) | 0x19)
-
-#define GPIO_VER6_SOC_M_SPI0_IO2 ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x00)
-#define GPIO_VER6_SOC_M_SPI0_IO3 ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x01)
-#define GPIO_VER6_SOC_M_SPI0_MOSI_IO_0 ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x02)
-#define GPIO_VER6_SOC_M_SPI0_MISO_IO_0 ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x03)
-#define GPIO_VER6_SOC_M_SPI0_TPM_CS_B ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x04)
-#define GPIO_VER6_SOC_M_SPI0_FLASH_0_CS_B ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x05)
-#define GPIO_VER6_SOC_M_SPI0_FLASH_1_CS_B ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x06)
-#define GPIO_VER6_SOC_M_SPI0_CLK ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x07)
-#define GPIO_VER6_SOC_M_BKLTEN ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x08)
-#define GPIO_VER6_SOC_M_BKLTCTL ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x09)
-#define GPIO_VER6_SOC_M_VDDEN ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x0A)
-#define GPIO_VER6_SOC_M_SYS_PWROK ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x0B)
-#define GPIO_VER6_SOC_M_SYS_RESET_B ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x0C)
-#define GPIO_VER6_SOC_M_MLK_RST_B ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x0D)
-#define GPIO_VER6_SOC_M_SPI0_CLK_LOOPBK ((GPIO_VER6_SOC_M_GROUP_SPI_SYS << 16 ) | 0x0E)
-
-#define GPIO_VER6_SOC_M_USB_0 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x00)
-#define GPIO_VER6_SOC_M_USB_1 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x01)
-#define GPIO_VER6_SOC_M_USB_2 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x02)
-#define GPIO_VER6_SOC_M_USB_3 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x03)
-#define GPIO_VER6_SOC_M_USB_4 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x04)
-#define GPIO_VER6_SOC_M_USB_5 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x05)
-#define GPIO_VER6_SOC_M_USB_6 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x06)
-#define GPIO_VER6_SOC_M_USB_7 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x07)
-#define GPIO_VER6_SOC_M_TS_0 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x08)
-#define GPIO_VER6_SOC_M_TS_1 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x09)
-#define GPIO_VER6_SOC_M_THC_0 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x0A)
-#define GPIO_VER6_SOC_M_THC_1 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x0B)
-#define GPIO_VER6_SOC_M_THC_2 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x0C)
-#define GPIO_VER6_SOC_M_THC_3 ((GPIO_VER6_SOC_M_GROUP_USB_THC << 16 ) | 0x0D)
-
-// COM4
-#define GPIO_VER6_SOC_M_GPP_S0 ((GPIO_VER6_SOC_M_GROUP_GPP_S << 16) | 0x00)
-#define GPIO_VER6_SOC_M_GPP_S1 ((GPIO_VER6_SOC_M_GROUP_GPP_S << 16) | 0x01)
-#define GPIO_VER6_SOC_M_GPP_S2 ((GPIO_VER6_SOC_M_GROUP_GPP_S << 16) | 0x02)
-#define GPIO_VER6_SOC_M_GPP_S3 ((GPIO_VER6_SOC_M_GROUP_GPP_S << 16) | 0x03)
-#define GPIO_VER6_SOC_M_GPP_S4 ((GPIO_VER6_SOC_M_GROUP_GPP_S << 16) | 0x04)
-#define GPIO_VER6_SOC_M_GPP_S5 ((GPIO_VER6_SOC_M_GROUP_GPP_S << 16) | 0x05)
-#define GPIO_VER6_SOC_M_GPP_S6 ((GPIO_VER6_SOC_M_GROUP_GPP_S << 16) | 0x06)
-#define GPIO_VER6_SOC_M_GPP_S7 ((GPIO_VER6_SOC_M_GROUP_GPP_S << 16) | 0x07)
-
-#define GPIO_VER6_SOC_M_MBPB0 ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x00)
-#define GPIO_VER6_SOC_M_MBPB1 ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x01)
-#define GPIO_VER6_SOC_M_MBPB2 ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x02)
-#define GPIO_VER6_SOC_M_MBPB3 ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x03)
-#define GPIO_VER6_SOC_M_JTAG_TDO ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x04)
-#define GPIO_VER6_SOC_M_PRDY_B ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x05)
-#define GPIO_VER6_SOC_M_PREQ_B ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x06)
-#define GPIO_VER6_SOC_M_JTAG_TDI ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x07)
-#define GPIO_VER6_SOC_M_JTAG_TMS ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x08)
-#define GPIO_VER6_SOC_M_JTAG_TCK ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x09)
-#define GPIO_VER6_SOC_M_DBG_PMODE ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x0A)
-#define GPIO_VER6_SOC_M_JTAG_TRST_B ((GPIO_VER6_SOC_M_GROUP_JTAG << 16) | 0x0B)
-
-// COM5
-#define GPIO_VER6_SOC_M_GPP_B0 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x00)
-#define GPIO_VER6_SOC_M_GPP_B1 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x01)
-#define GPIO_VER6_SOC_M_GPP_B2 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x02)
-#define GPIO_VER6_SOC_M_GPP_B3 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x03)
-#define GPIO_VER6_SOC_M_GPP_B4 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x04)
-#define GPIO_VER6_SOC_M_GPP_B5 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x05)
-#define GPIO_VER6_SOC_M_GPP_B6 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x06)
-#define GPIO_VER6_SOC_M_GPP_B7 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x07)
-#define GPIO_VER6_SOC_M_GPP_B8 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x08)
-#define GPIO_VER6_SOC_M_GPP_B9 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x09)
-#define GPIO_VER6_SOC_M_GPP_B10 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x0A)
-#define GPIO_VER6_SOC_M_GPP_B11 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x0B)
-#define GPIO_VER6_SOC_M_GPP_B12 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x0C)
-#define GPIO_VER6_SOC_M_GPP_B13 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x0D)
-#define GPIO_VER6_SOC_M_GPP_B14 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x0E)
-#define GPIO_VER6_SOC_M_GPP_B15 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x0F)
-#define GPIO_VER6_SOC_M_GPP_B16 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x10)
-#define GPIO_VER6_SOC_M_GPP_B17 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x11)
-#define GPIO_VER6_SOC_M_GPP_B18 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x12)
-#define GPIO_VER6_SOC_M_GPP_B19 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x13)
-#define GPIO_VER6_SOC_M_GPP_B20 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x14)
-#define GPIO_VER6_SOC_M_GPP_B21 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x15)
-#define GPIO_VER6_SOC_M_GPP_B22 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x16)
-#define GPIO_VER6_SOC_M_GPP_B23 ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x17)
-#define GPIO_VER6_SOC_M_ISHI3C0_CLK_LOOPBK ((GPIO_VER6_SOC_M_GROUP_GPP_B << 16 ) | 0x18)
-
-#define GPIO_VER6_SOC_M_GPP_D0 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x00)
-#define GPIO_VER6_SOC_M_GPP_D1 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x01)
-#define GPIO_VER6_SOC_M_GPP_D2 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x02)
-#define GPIO_VER6_SOC_M_GPP_D3 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x03)
-#define GPIO_VER6_SOC_M_GPP_D4 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x04)
-#define GPIO_VER6_SOC_M_GPP_D5 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x05)
-#define GPIO_VER6_SOC_M_GPP_D6 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x06)
-#define GPIO_VER6_SOC_M_GPP_D7 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x07)
-#define GPIO_VER6_SOC_M_GPP_D8 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x08)
-#define GPIO_VER6_SOC_M_GPP_D9 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x09)
-#define GPIO_VER6_SOC_M_GPP_D10 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x0A)
-#define GPIO_VER6_SOC_M_GPP_D11 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x0B)
-#define GPIO_VER6_SOC_M_GPP_D12 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x0C)
-#define GPIO_VER6_SOC_M_GPP_D13 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x0D)
-#define GPIO_VER6_SOC_M_GPP_D14 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x0E)
-#define GPIO_VER6_SOC_M_GPP_D15 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x0F)
-#define GPIO_VER6_SOC_M_GPP_D16 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x10)
-#define GPIO_VER6_SOC_M_GPP_D17 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x11)
-#define GPIO_VER6_SOC_M_GPP_D18 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x12)
-#define GPIO_VER6_SOC_M_GPP_D19 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x13)
-#define GPIO_VER6_SOC_M_GPP_D20 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x14)
-#define GPIO_VER6_SOC_M_GPP_D21 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x15)
-#define GPIO_VER6_SOC_M_GPP_D22 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x16)
-#define GPIO_VER6_SOC_M_GPP_D23 ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x17)
-#define GPIO_VER6_SOC_M_BOOTHALT_B ((GPIO_VER6_SOC_M_GROUP_GPP_D << 16 ) | 0x18)
-
-#define GPIO_VER6_SOC_M_VGPIO0 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x00)
-#define GPIO_VER6_SOC_M_VGPIO4 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x01)
-#define GPIO_VER6_SOC_M_VGPIO5 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x02)
-#define GPIO_VER6_SOC_M_VGPIO6 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x03)
-#define GPIO_VER6_SOC_M_VGPIO7 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x04)
-#define GPIO_VER6_SOC_M_VGPIO8 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x05)
-#define GPIO_VER6_SOC_M_VGPIO9 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x06)
-#define GPIO_VER6_SOC_M_VGPIO10 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x07)
-#define GPIO_VER6_SOC_M_VGPIO11 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x08)
-#define GPIO_VER6_SOC_M_VGPIO12 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x09)
-#define GPIO_VER6_SOC_M_VGPIO13 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x0A)
-#define GPIO_VER6_SOC_M_VGPIO18 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x0B)
-#define GPIO_VER6_SOC_M_VGPIO19 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x0C)
-#define GPIO_VER6_SOC_M_VGPIO20 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x0D)
-#define GPIO_VER6_SOC_M_VGPIO21 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x0E)
-#define GPIO_VER6_SOC_M_VGPIO22 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x0F)
-#define GPIO_VER6_SOC_M_VGPIO23 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x10)
-#define GPIO_VER6_SOC_M_VGPIO24 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x11)
-#define GPIO_VER6_SOC_M_VGPIO25 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x12)
-#define GPIO_VER6_SOC_M_VGPIO30 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x13)
-#define GPIO_VER6_SOC_M_VGPIO31 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x14)
-#define GPIO_VER6_SOC_M_VGPIO32 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x15)
-#define GPIO_VER6_SOC_M_VGPIO33 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x16)
-#define GPIO_VER6_SOC_M_VGPIO34 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x17)
-#define GPIO_VER6_SOC_M_VGPIO35 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x18)
-#define GPIO_VER6_SOC_M_VGPIO36 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x19)
-#define GPIO_VER6_SOC_M_VGPIO37 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x1A)
-#define GPIO_VER6_SOC_M_VGPIO40 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x1B)
-#define GPIO_VER6_SOC_M_VGPIO41 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x1C)
-#define GPIO_VER6_SOC_M_VGPIO42 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x1D)
-#define GPIO_VER6_SOC_M_VGPIO43 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x1E)
-#define GPIO_VER6_SOC_M_VGPIO44 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x1F)
-#define GPIO_VER6_SOC_M_VGPIO45 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x20)
-#define GPIO_VER6_SOC_M_VGPIO46 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x21)
-#define GPIO_VER6_SOC_M_VGPIO47 ((GPIO_VER6_SOC_M_GROUP_VGPIO << 16 ) | 0x22)
-
-//
-// GPIO Pin Muxing
-// Determines a selection of physical pad for a given signal.
-// Please refer to GPIO_NATIVE_PAD type.
-// If certain signal is not listed below it means that it can be enabled
-// only on a single pad and muxing setting is not needed.
-//
-#define GPIO_VER6_SOC_M_MUXING_ISH_SPI0_CS_GPP_D5 0x3A2CA005 // Native Function 3
-#define GPIO_VER6_SOC_M_MUXING_ISH_SPI0_CS_GPP_F17 0x4A26A011 // Native Function 4
-#define GPIO_VER6_SOC_M_MUXING_ISH_SPI0_CLK_GPP_D6 0x3A2C9006 // Native Function 3
-#define GPIO_VER6_SOC_M_MUXING_ISH_SPI0_CLK_GPP_F11 0x4A26900B // Native Function 4
-#define GPIO_VER6_SOC_M_MUXING_ISH_SPI0_MISO_GPP_D7 0x3A2C8007 // Native Function 3
-#define GPIO_VER6_SOC_M_MUXING_ISH_SPI0_MISO_GPP_F12 0x4A26800C // Native Function 4
-#define GPIO_VER6_SOC_M_MUXING_ISH_SPI0_MOSI_GPP_D8 0x3A2C7008 // Native Function 3
-#define GPIO_VER6_SOC_M_MUXING_ISH_SPI0_MOSI_GPP_F13 0x4A26700D // Native Function 4
-
-#define GPIO_VER6_SOC_M_MUXING_ISH_UART1_RXD_GPP_H14 0x1A25220E // Native Function 1
-#define GPIO_VER6_SOC_M_MUXING_ISH_UART1_RXD_GPP_H6 0x3A252206 // Native Function 3
-#define GPIO_VER6_SOC_M_MUXING_ISH_UART1_TXD_GPP_H15 0x1A25320F // Native Function 1
-#define GPIO_VER6_SOC_M_MUXING_ISH_UART1_TXD_GPP_H7 0x3A253207 // Native Function 3
-
-#define GPIO_VER6_SOC_M_MUXING_ISH_I2C2_SDA_GPP_B18 0x1A2BE412 // Native Function 1
-#define GPIO_VER6_SOC_M_MUXING_ISH_I2C2_SDA_GPP_D1 0x3A2CE401 // Native Function 3
-#define GPIO_VER6_SOC_M_MUXING_ISH_I2C2_SCL_GPP_B19 0x1A2BD413 // Native Function 1
-#define GPIO_VER6_SOC_M_MUXING_ISH_I2C2_SCL_GPP_D2 0x3A2CD402 // Native Function 3
-
-#define GPIO_VER6_SOC_M_MUXING_ISH_GP5_GPP_B22 0x4A0BAA16 // Native Function 4
-#define GPIO_VER6_SOC_M_MUXING_ISH_GP5_GPP_E15 0x8A04AA0F // Native Function 8
-#define GPIO_VER6_SOC_M_MUXING_ISH_GP6_GPP_B23 0x4A0BAC17 // Native Function 4
-#define GPIO_VER6_SOC_M_MUXING_ISH_GP6_GPP_F10 0x8A06AC0A // Native Function 8
-#define GPIO_VER6_SOC_M_MUXING_ISH_GP8_GPP_B20 0x4A0BB014 // Native Function 4
-#define GPIO_VER6_SOC_M_MUXING_ISH_GP8_GPP_F22 0x8A06B016 // Native Function 8
-#define GPIO_VER6_SOC_M_MUXING_ISH_GP9_GPP_B21 0x4A0BB215 // Native Function 4
-#define GPIO_VER6_SOC_M_MUXING_ISH_GP9_GPP_F23 0x8A06B217 // Native Function 8
-#define GPIO_VER6_SOC_M_MUXING_ISH_GP10_GPP_E16 0x8A04B410 // Native Function 8
-#define GPIO_VER6_SOC_M_MUXING_ISH_GP10_GPP_H10 0x8A05B40A // Native Function 8
-#define GPIO_VER6_SOC_M_MUXING_ISH_GP11_GPP_F9 0x8A06B609 // Native Function 8
-#define GPIO_VER6_SOC_M_MUXING_ISH_GP11_GPP_H11 0x8A05B60B // Native Function 8
-
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_SPI0_CS_GPP_E10 0x5A04700A // Native Function 5
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_SPI0_CS_GPP_F18 0x8A067012 // Native Function 8
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_SPI0_CLK_GPP_E11 0x5A04600B // Native Function 5
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_SPI0_CLK_GPP_F16 0x8A066010 // Native Function 8
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_SPI0_MISO_GPP_E12 0x5A04500C // Native Function 5
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_SPI0_MISO_GPP_F15 0x8A06500F // Native Function 8
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_SPI0_MOSI_GPP_E13 0x5A04400D // Native Function 5
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_SPI0_MOSI_GPP_F14 0x8A06400E // Native Function 8
-
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C2_SDA_GPP_H4 0x1A45C804 // Native Function 1
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C2_SDA_GPP_B2 0x8A4BC802 // Native Function 8
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C2_SCL_GPP_H5 0x1A45A805 // Native Function 1
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C2_SCL_GPP_B3 0x8A4BA803 // Native Function 8
-
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C3_SDA_GPP_H6 0x1A45CA06 // Native Function 1
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C3_SDA_GPP_D1 0x1A4CCA01 // Native Function 1
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C3_SCL_GPP_H7 0x1A45AA07 // Native Function 1
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C3_SCL_GPP_D2 0x1A4CAA02 // Native Function 1
-
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C4_SDA_GPP_E12 0x8A44CC0C // Native Function 8
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C4_SDA_GPP_B18 0x2A4BCC12 // Native Function 2
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C4_SCL_GPP_E13 0x8A44AC0D // Native Function 8
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C4_SCL_GPP_B19 0x2A4BAC13 // Native Function 2
-
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C5_SDA_GPP_F13 0x8A46CE0D // Native Function 8
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C5_SDA_GPP_B20 0x2A4BCE14 // Native Function 2
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C5_SCL_GPP_F12 0x8A46AE0C // Native Function 8
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I2C5_SCL_GPP_B21 0x2A4BAE15 // Native Function 2
-
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I3C1_SDA_GPP_H21 0x2A652015 // Native Function 2
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I3C1_SDA_GPP_H10 0x2A65200A // Native Function 2
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I3C1_SCL_GPP_H22 0x2A651C16 // Native Function 2
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I3C1_SCL_GPP_H11 0x2A651C0B // Native Function 2
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I3C1_SCL_FB 0x2A65C018 // Native Function 2
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_I3C1_SCL_FB_A 0x3A65C018 // Native Function 3
-
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_UART1_RXD_GPP_H6 0x2A050406 // Native Function 2
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_UART1_RXD_GPP_H14 0x2A05040E // Native Function 2
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_UART1_TXD_GPP_H7 0x2A051407 // Native Function 2
-#define GPIO_VER6_SOC_M_MUXING_SERIALIO_UART1_TXD_GPP_H15 0x2A05140F // Native Function 2
-
-#endif // _GPIO_PINS_VER4_S_H_
diff --git a/Silicon/ArrowlakePkg/Include/GpioV2PinsMtlPchS.h b/Silicon/ArrowlakePkg/Include/GpioV2PinsMtlPchS.h
index 497e6200..1838e417 100644
--- a/Silicon/ArrowlakePkg/Include/GpioV2PinsMtlPchS.h
+++ b/Silicon/ArrowlakePkg/Include/GpioV2PinsMtlPchS.h
@@ -24,18 +24,14 @@
#define MTL_PCH_S_GRP_IDX_GPP_R 1
#define MTL_PCH_S_COM_IDX_GPP_J 0
#define MTL_PCH_S_GRP_IDX_GPP_J 2
-#define MTL_PCH_S_COM_IDX_VGPIO 0
-#define MTL_PCH_S_GRP_IDX_VGPIO 3
//
// Community 1
//
#define MTL_PCH_S_COM_IDX_GPP_A 1
#define MTL_PCH_S_GRP_IDX_GPP_A 0
-#define MTL_PCH_S_COM_IDX_DIR_ESPI 1
-#define MTL_PCH_S_GRP_IDX_DIR_ESPI 1
#define MTL_PCH_S_COM_IDX_GPP_B 1
-#define MTL_PCH_S_GRP_IDX_GPP_B 2
+#define MTL_PCH_S_GRP_IDX_GPP_B 1
//
// Community 2
@@ -46,18 +42,12 @@
//
// Community 3
//
-#define MTL_PCH_S_COM_IDX_SPI0 3
-#define MTL_PCH_S_GRP_IDX_SPI0 0
+
#define MTL_PCH_S_COM_IDX_GPP_C 3
-#define MTL_PCH_S_GRP_IDX_GPP_C 1
+#define MTL_PCH_S_GRP_IDX_GPP_C 0
#define MTL_PCH_S_COM_IDX_GPP_H 3
-#define MTL_PCH_S_GRP_IDX_GPP_H 2
-#define MTL_PCH_S_COM_IDX_VGPIO_3 3
-#define MTL_PCH_S_GRP_IDX_VGPIO_3 3
-#define MTL_PCH_S_COM_IDX_VGPIO_0 3
-#define MTL_PCH_S_GRP_IDX_VGPIO_0 4
-#define MTL_PCH_S_COM_IDX_VGPIO_4 3
-#define MTL_PCH_S_GRP_IDX_VGPIO_4 5
+#define MTL_PCH_S_GRP_IDX_GPP_H 1
+
//
// Community 4
@@ -76,8 +66,7 @@
//
#define MTL_PCH_S_COM_IDX_GPP_I 5
#define MTL_PCH_S_GRP_IDX_GPP_I 0
-#define MTL_PCH_S_COM_IDX_JTAG_CPU 5
-#define MTL_PCH_S_GRP_IDX_JTAG_CPU 1
+
//
// GPIO Group defines
@@ -85,16 +74,14 @@
//
// Community 0
//
-#define GPIOV2_MTL_PCH_S_GROUP_D GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_D, MTL_PCH_S_GRP_IDX_GPP_D, 0xFF)
-#define GPIOV2_MTL_PCH_S_GROUP_R GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_R, MTL_PCH_S_GRP_IDX_GPP_R, 0xFF)
-#define GPIOV2_MTL_PCH_S_GROUP_J GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_J, MTL_PCH_S_GRP_IDX_GPP_J, 0xFF)
-#define GPIOV2_MTL_PCH_S_GROUP_VGPIO GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 0xFF)
+#define GPIOV2_MTL_PCH_S_GROUP_D GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_D, MTL_PCH_S_GRP_IDX_GPP_D, 0xFF)
+#define GPIOV2_MTL_PCH_S_GROUP_R GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_R, MTL_PCH_S_GRP_IDX_GPP_R, 0xFF)
+#define GPIOV2_MTL_PCH_S_GROUP_J GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_J, MTL_PCH_S_GRP_IDX_GPP_J, 0xFF)
//
// Community 1
//
#define GPIOV2_MTL_PCH_S_GROUP_A GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_A, MTL_PCH_S_GRP_IDX_GPP_A, 0xFF)
-#define GPIOV2_MTL_PCH_S_GROUP_DIR_ESPI GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_DIR_ESPI, MTL_PCH_S_GRP_IDX_DIR_ESPI, 0xFF)
#define GPIOV2_MTL_PCH_S_GROUP_B GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_B, MTL_PCH_S_GRP_IDX_GPP_B, 0xFF)
//
@@ -105,12 +92,8 @@
//
// Community 3
//
-#define GPIOV2_MTL_PCH_S_GROUP_SPI0 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_SPI0, MTL_PCH_S_GRP_IDX_SPI0, 0xFF)
#define GPIOV2_MTL_PCH_S_GROUP_C GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_C, MTL_PCH_S_GRP_IDX_GPP_C, 0xFF)
#define GPIOV2_MTL_PCH_S_GROUP_H GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_H, MTL_PCH_S_GRP_IDX_GPP_H, 0xFF)
-#define GPIOV2_MTL_PCH_S_GROUP_VGPIO_3 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_3, MTL_PCH_S_GRP_IDX_VGPIO_3, 0xFF)
-#define GPIOV2_MTL_PCH_S_GROUP_VGPIO_0 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_0, MTL_PCH_S_GRP_IDX_VGPIO_0, 0xFF)
-#define GPIOV2_MTL_PCH_S_GROUP_VGPIO_4 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 0xFF)
//
// Community 4
@@ -124,13 +107,12 @@
// Community 5
//
#define GPIOV2_MTL_PCH_S_GROUP_I GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_I, MTL_PCH_S_GRP_IDX_GPP_I, 0xFF)
-#define GPIOV2_MTL_PCH_S_GROUP_JTAG_CPU GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_JTAG_CPU, MTL_PCH_S_GRP_IDX_JTAG_CPU, 0xFF)
//
// Group name: GPP_D
// Community index: 0
// Group index: 0
-// Number of pads: 25
+// Number of pads: 24
//
@@ -316,19 +298,12 @@
// Native function 6: IOM_GPPD_23
#define GPIOV2_MTL_PCH_S_GPP_D_23 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_D, MTL_PCH_S_GRP_IDX_GPP_D, 23)
-// Pin: GSPI3_THC1_CLK_LOOPBK ( Value: 0x18 )
-// Family: THC1_GSPI3
-// Default function: RW - 4'b0000 [padmode_value[17][0] ? 4'b0001:4'b0010]
-// Native function 1: GSPI3_CLK_LOOPBK
-// Native function 2: THC1_CLK_LOOPBK
-#define GPIOV2_MTL_PCH_S_GSPI3_THC1_CLK_LOOPBK GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_D, MTL_PCH_S_GRP_IDX_GPP_D, 24)
-
//
// Group name: GPP_R
// Community index: 0
// Group index: 1
-// Number of pads: 14
+// Number of pads: 13
//
@@ -437,18 +412,12 @@
// Native function 6: IOM_GPPR_12
#define GPIOV2_MTL_PCH_S_GPP_R_12 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_R, MTL_PCH_S_GRP_IDX_GPP_R, 12)
-// Pin: GSPI2_CLK_LOOPBK ( Value: 0x8d )
-// Family: GSPI2
-// Default function: Function 3
-// Native function 3: GSPI2_CLK_LOOPBK
-#define GPIOV2_MTL_PCH_S_GSPI2_CLK_LOOPBK GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_R, MTL_PCH_S_GRP_IDX_GPP_R, 13)
-
//
// Group name: GPP_J
// Community index: 0
// Group index: 2
-// Number of pads: 18
+// Number of pads: 17
//
@@ -571,222 +540,13 @@
// Native function 1: GLB_RST_WARN_B
#define GPIOV2_MTL_PCH_S_GPP_J_16 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_J, MTL_PCH_S_GRP_IDX_GPP_J, 16)
-// Pin: RESET_SYNCB ( Value: 0x111 )
-// Family: MiscJ
-// Default function: Function 1
-// Native function 1: RESET_SYNCB
-#define GPIOV2_MTL_PCH_S_RESET_SYNCB GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_J, MTL_PCH_S_GRP_IDX_GPP_J, 17)
-
-
-//
-// Group name: vGPIO
-// Community index: 0
-// Group index: 3
-// Number of pads: 31
-//
-
-
-// Pin: vGPIO_0 ( Value: 0x180 )
-// Family: v_CNV
-// Default function: GP-Out
-#define GPIOV2_MTL_PCH_S_VGPIO_0 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 0)
-
-// Pin: vGPIO_4 ( Value: 0x181 )
-// Family: v_CNV
-// Default function: GP-In
-#define GPIOV2_MTL_PCH_S_VGPIO_4 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 1)
-
-// Pin: vGPIO_5 ( Value: 0x182 )
-// Family: v_CNV
-// Default function: GP-Out
-#define GPIOV2_MTL_PCH_S_VGPIO_5 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 2)
-
-// Pin: vGPIO_6 ( Value: 0x183 )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 2: UART0_RXD
-// Native function 2: ISH_UART0_RXD
-#define GPIOV2_MTL_PCH_S_VGPIO_6 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 3)
-
-// Pin: vGPIO_7 ( Value: 0x184 )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 2: UART0_TXD
-// Native function 2: ISH_UART0_TXD
-#define GPIOV2_MTL_PCH_S_VGPIO_7 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 4)
-
-// Pin: vGPIO_8 ( Value: 0x185 )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 2: UART0_RTSB
-// Native function 2: ISH_UART0_RTSB
-#define GPIOV2_MTL_PCH_S_VGPIO_8 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 5)
-
-// Pin: vGPIO_9 ( Value: 0x186 )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 2: UART0_CTSB
-// Native function 2: ISH_UART0_CTSB
-#define GPIOV2_MTL_PCH_S_VGPIO_9 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 6)
-
-// Pin: vGPIO_10 ( Value: 0x187 )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 2: ISH_UART0_RXD
-// Native function 2: UART2_RXD
-#define GPIOV2_MTL_PCH_S_VGPIO_10 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 7)
-
-// Pin: vGPIO_11 ( Value: 0x188 )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 2: ISH_UART0_TXD
-// Native function 2: UART2_TXD
-#define GPIOV2_MTL_PCH_S_VGPIO_11 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 8)
-
-// Pin: vGPIO_12 ( Value: 0x189 )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 2: ISH_UART0_RTSB
-// Native function 2: UART2_RTS_B
-#define GPIOV2_MTL_PCH_S_VGPIO_12 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 9)
-
-// Pin: vGPIO_13 ( Value: 0x18a )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 2: ISH_UART0_CTSB
-// Native function 2: UART2_CTS_B
-#define GPIOV2_MTL_PCH_S_VGPIO_13 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 10)
-
-// Pin: vGPIO_18 ( Value: 0x18b )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 1: CNV_BT_UART_RXD
-#define GPIOV2_MTL_PCH_S_VGPIO_18 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 11)
-
-// Pin: vGPIO_19 ( Value: 0x18c )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 1: CNV_BT_UART_TXD
-#define GPIOV2_MTL_PCH_S_VGPIO_19 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 12)
-
-// Pin: vGPIO_20 ( Value: 0x18d )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 1: CNV_BT_UART_RTS_B
-#define GPIOV2_MTL_PCH_S_VGPIO_20 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 13)
-
-// Pin: vGPIO_21 ( Value: 0x18e )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 1: CNV_BT_UART_CTS_B
-#define GPIOV2_MTL_PCH_S_VGPIO_21 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 14)
-
-// Pin: vGPIO_22 ( Value: 0x18f )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 1: CNV_MFUART1_RXD
-#define GPIOV2_MTL_PCH_S_VGPIO_22 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 15)
-
-// Pin: vGPIO_23 ( Value: 0x190 )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 1: CNV_MFUART1_TXD
-#define GPIOV2_MTL_PCH_S_VGPIO_23 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 16)
-
-// Pin: vGPIO_24 ( Value: 0x191 )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 1: CNV_MFUART1_RTS_B
-#define GPIOV2_MTL_PCH_S_VGPIO_24 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 17)
-
-// Pin: vGPIO_25 ( Value: 0x192 )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 1: CNV_MFUART1_CTS_B
-#define GPIOV2_MTL_PCH_S_VGPIO_25 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 18)
-
-// Pin: vGPIO_30 ( Value: 0x193 )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 2: I2S0_SCLK
-// Native function 2: I2S1_SCLK
-// Native function 1: I2S2_SCLK
-#define GPIOV2_MTL_PCH_S_VGPIO_30 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 19)
-
-// Pin: vGPIO_31 ( Value: 0x194 )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 2: I2S0_SFRM
-// Native function 2: I2S1_SFRM
-// Native function 1: I2S2_SFRM
-#define GPIOV2_MTL_PCH_S_VGPIO_31 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 20)
-
-// Pin: vGPIO_32 ( Value: 0x195 )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 2: I2S0_RXD
-// Native function 2: I2S1_RXD
-// Native function 1: I2S2_RXD
-#define GPIOV2_MTL_PCH_S_VGPIO_32 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 21)
-
-// Pin: vGPIO_33 ( Value: 0x196 )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 2: I2S0_TXD
-// Native function 2: I2S1_TXD
-// Native function 1: I2S2_TXD
-#define GPIOV2_MTL_PCH_S_VGPIO_33 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 22)
-
-// Pin: vGPIO_34 ( Value: 0x197 )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 1: CNV_BT_I2S_BCLK
-#define GPIOV2_MTL_PCH_S_VGPIO_34 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 23)
-
-// Pin: vGPIO_35 ( Value: 0x198 )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 1: CNV_BT_I2S_WS_SYNC
-#define GPIOV2_MTL_PCH_S_VGPIO_35 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 24)
-
-// Pin: vGPIO_36 ( Value: 0x199 )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 1: CNV_BT_I2S_SDI
-#define GPIOV2_MTL_PCH_S_VGPIO_36 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 25)
-
-// Pin: vGPIO_37 ( Value: 0x19a )
-// Family: v_CNV
-// Default function: Function 1
-// Native function 1: CNV_BT_I2S_SDO
-#define GPIOV2_MTL_PCH_S_VGPIO_37 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 26)
-
-// Pin: vGPIO_THC0 ( Value: 0x19b )
-// Family: v_CNV
-// Default function: GP-In
-#define GPIOV2_MTL_PCH_S_VGPIO_THC0 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 27)
-
-// Pin: vGPIO_THC1 ( Value: 0x19c )
-// Family: v_CNV
-// Default function: GP-In
-#define GPIOV2_MTL_PCH_S_VGPIO_THC1 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 28)
-
-// Pin: vGPIO_THC2 ( Value: 0x19d )
-// Family: v_CNV
-// Default function: GP-In
-#define GPIOV2_MTL_PCH_S_VGPIO_THC2 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 29)
-
-// Pin: vGPIO_THC3 ( Value: 0x19e )
-// Family: v_CNV
-// Default function: GP-In
-#define GPIOV2_MTL_PCH_S_VGPIO_THC3 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO, MTL_PCH_S_GRP_IDX_VGPIO, 30)
//
// Group name: GPP_A
// Community index: 1
// Group index: 0
-// Number of pads: 15
+// Number of pads: 14
//
@@ -890,98 +650,11 @@
// Native function 6: IOM_GPPA_13
#define GPIOV2_MTL_PCH_S_GPP_A_13 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_A, MTL_PCH_S_GRP_IDX_GPP_A, 13)
-// Pin: ESPI_CLK_LOOPBK ( Value: 0x40e )
-// Family: eSPI
-// Default function: Function 1
-// Native function 1: ESPI_CLK_LOOPBK
-#define GPIOV2_MTL_PCH_S_ESPI_CLK_LOOPBK GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_A, MTL_PCH_S_GRP_IDX_GPP_A, 14)
-
-
-//
-// Group name: DIR_ESPI
-// Community index: 1
-// Group index: 1
-// Number of pads: 12
-//
-
-
-// Pin: PWRBTNB_OUT ( Value: 0x480 )
-// Family: DMI
-// Default function: Function 1
-// Native function 1: PWRBTNB_OUT
-#define GPIOV2_MTL_PCH_S_PWRBTNB_OUT GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_DIR_ESPI, MTL_PCH_S_GRP_IDX_DIR_ESPI, 0)
-
-// Pin: DMI_PERSTB ( Value: 0x481 )
-// Family: DMI
-// Default function: Function 1
-// Native function 1: DMI_PERSTB
-#define GPIOV2_MTL_PCH_S_DMI_PERSTB GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_DIR_ESPI, MTL_PCH_S_GRP_IDX_DIR_ESPI, 1)
-
-// Pin: DMI_CLKREQB ( Value: 0x482 )
-// Family: DMI
-// Default function: Function 1
-// Native function 1: DMI_CLKREQB
-#define GPIOV2_MTL_PCH_S_DMI_CLKREQB GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_DIR_ESPI, MTL_PCH_S_GRP_IDX_DIR_ESPI, 2)
-
-// Pin: DIR_ESPI_IO_0 ( Value: 0x483 )
-// Family: DIR_ESPI0
-// Default function: Function 1
-// Native function 1: DIR_ESPI_IO_0
-#define GPIOV2_MTL_PCH_S_DIR_ESPI_IO_0 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_DIR_ESPI, MTL_PCH_S_GRP_IDX_DIR_ESPI, 3)
-
-// Pin: DIR_ESPI_IO_1 ( Value: 0x484 )
-// Family: DIR_ESPI0
-// Default function: Function 1
-// Native function 1: DIR_ESPI_IO_1
-#define GPIOV2_MTL_PCH_S_DIR_ESPI_IO_1 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_DIR_ESPI, MTL_PCH_S_GRP_IDX_DIR_ESPI, 4)
-
-// Pin: DIR_ESPI_IO_2 ( Value: 0x485 )
-// Family: DIR_ESPI0
-// Default function: Function 1
-// Native function 1: DIR_ESPI_IO_2
-#define GPIOV2_MTL_PCH_S_DIR_ESPI_IO_2 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_DIR_ESPI, MTL_PCH_S_GRP_IDX_DIR_ESPI, 5)
-
-// Pin: DIR_ESPI_IO_3 ( Value: 0x486 )
-// Family: DIR_ESPI0
-// Default function: Function 1
-// Native function 1: DIR_ESPI_IO_3
-#define GPIOV2_MTL_PCH_S_DIR_ESPI_IO_3 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_DIR_ESPI, MTL_PCH_S_GRP_IDX_DIR_ESPI, 6)
-
-// Pin: DIR_ESPI_CSB ( Value: 0x487 )
-// Family: DIR_ESPI0
-// Default function: Function 1
-// Native function 1: DIR_ESPI_CSB
-#define GPIOV2_MTL_PCH_S_DIR_ESPI_CSB GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_DIR_ESPI, MTL_PCH_S_GRP_IDX_DIR_ESPI, 7)
-
-// Pin: DIR_ESPI_RESETB ( Value: 0x488 )
-// Family: DIR_ESPI0
-// Default function: Function 1
-// Native function 1: DIR_ESPI_RESETB
-#define GPIOV2_MTL_PCH_S_DIR_ESPI_RESETB GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_DIR_ESPI, MTL_PCH_S_GRP_IDX_DIR_ESPI, 8)
-
-// Pin: DIR_ESPI_CLK ( Value: 0x489 )
-// Family: DIR_ESPI0
-// Default function: Function 1
-// Native function 1: DIR_ESPI_CLK
-#define GPIOV2_MTL_PCH_S_DIR_ESPI_CLK GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_DIR_ESPI, MTL_PCH_S_GRP_IDX_DIR_ESPI, 9)
-
-// Pin: DIR_ESPI_RCLK ( Value: 0x48a )
-// Family: DIR_ESPI0
-// Default function: Function 1
-// Native function 1: DIR_ESPI_RCLK
-#define GPIOV2_MTL_PCH_S_DIR_ESPI_RCLK GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_DIR_ESPI, MTL_PCH_S_GRP_IDX_DIR_ESPI, 10)
-
-// Pin: DIR_ESPI_ALERTB ( Value: 0x48b )
-// Family: DIR_ESPI0
-// Default function: Function 1
-// Native function 1: DIR_ESPI_ALERTB
-#define GPIOV2_MTL_PCH_S_DIR_ESPI_ALERTB GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_DIR_ESPI, MTL_PCH_S_GRP_IDX_DIR_ESPI, 11)
-
//
// Group name: GPP_B
// Community index: 1
-// Group index: 2
+// Group index: 1
// Number of pads: 22
//
@@ -1156,7 +829,7 @@
// Group name: DSW
// Community index: 2
// Group index: 0
-// Number of pads: 17
+// Number of pads: 13
//
@@ -1236,98 +909,12 @@
// Default function: GP-Out
#define GPIOV2_MTL_PCH_S_GPD_12 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_DSW, MTL_PCH_S_GRP_IDX_DSW, 12)
-// Pin: SLP_LANB ( Value: 0x80d )
-// Family: DSW
-// Default function: Function 1
-// Native function 1: SLP_LANB
-#define GPIOV2_MTL_PCH_S_SLP_LANB GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_DSW, MTL_PCH_S_GRP_IDX_DSW, 13)
-
-// Pin: SLP_SUSB ( Value: 0x80e )
-// Family: DSW
-// Default function: Function 1
-// Native function 1: SLP_SUSB
-#define GPIOV2_MTL_PCH_S_SLP_SUSB GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_DSW, MTL_PCH_S_GRP_IDX_DSW, 14)
-
-// Pin: WAKEB ( Value: 0x80f )
-// Family: DSW
-// Default function: Function 1
-// Native function 1: WAKEB
-#define GPIOV2_MTL_PCH_S_WAKEB GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_DSW, MTL_PCH_S_GRP_IDX_DSW, 15)
-
-// Pin: DSW_SPARE ( Value: 0x810 )
-// Family: DSW
-// Default function: GP-In
-// Native function 1: DSW_SPARE
-#define GPIOV2_MTL_PCH_S_DSW_SPARE GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_DSW, MTL_PCH_S_GRP_IDX_DSW, 16)
-
-
-//
-// Group name: SPI0
-// Community index: 3
-// Group index: 0
-// Number of pads: 9
-//
-
-
-// Pin: SPI0_IO_2 ( Value: 0xc00 )
-// Family: SPI
-// Default function: Function 1
-// Native function 1: SPI0_IO_2
-#define GPIOV2_MTL_PCH_S_SPI0_IO_2 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_SPI0, MTL_PCH_S_GRP_IDX_SPI0, 0)
-
-// Pin: SPI0_IO_3 ( Value: 0xc01 )
-// Family: SPI
-// Default function: Function 1
-// Native function 1: SPI0_IO_3
-#define GPIOV2_MTL_PCH_S_SPI0_IO_3 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_SPI0, MTL_PCH_S_GRP_IDX_SPI0, 1)
-
-// Pin: SPI0_MOSI_IO_0 ( Value: 0xc02 )
-// Family: SPI
-// Default function: Function 1
-// Native function 1: SPI0_MOSI_IO_0
-#define GPIOV2_MTL_PCH_S_SPI0_MOSI_IO_0 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_SPI0, MTL_PCH_S_GRP_IDX_SPI0, 2)
-
-// Pin: SPI0_MISO_IO_1 ( Value: 0xc03 )
-// Family: SPI
-// Default function: Function 1
-// Native function 1: SPI0_MISO_IO_1
-#define GPIOV2_MTL_PCH_S_SPI0_MISO_IO_1 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_SPI0, MTL_PCH_S_GRP_IDX_SPI0, 3)
-
-// Pin: SPI0_TPM_CSB ( Value: 0xc04 )
-// Family: SPI
-// Default function: Function 1
-// Native function 1: SPI0_TPM_CSB
-#define GPIOV2_MTL_PCH_S_SPI0_TPM_CSB GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_SPI0, MTL_PCH_S_GRP_IDX_SPI0, 4)
-
-// Pin: SPI0_FLASH_0_CSB ( Value: 0xc05 )
-// Family: SPI
-// Default function: Function 1
-// Native function 1: SPI0_FLASH_0_CSB
-#define GPIOV2_MTL_PCH_S_SPI0_FLASH_0_CSB GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_SPI0, MTL_PCH_S_GRP_IDX_SPI0, 5)
-
-// Pin: SPI0_FLASH_1_CSB ( Value: 0xc06 )
-// Family: SPI
-// Default function: Function 1
-// Native function 1: SPI0_FLASH_1_CSB
-#define GPIOV2_MTL_PCH_S_SPI0_FLASH_1_CSB GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_SPI0, MTL_PCH_S_GRP_IDX_SPI0, 6)
-
-// Pin: SPI0_CLK ( Value: 0xc07 )
-// Family: SPI
-// Default function: Function 1
-// Native function 1: SPI0_CLK
-#define GPIOV2_MTL_PCH_S_SPI0_CLK GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_SPI0, MTL_PCH_S_GRP_IDX_SPI0, 7)
-
-// Pin: SPI0_CLK_LOOPBK ( Value: 0xc08 )
-// Family: SPI
-// Default function: Function 1
-// Native function 1: SPI0_CLK_LOOPBK
-#define GPIOV2_MTL_PCH_S_SPI0_CLK_LOOPBK GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_SPI0, MTL_PCH_S_GRP_IDX_SPI0, 8)
//
// Group name: GPP_C
// Community index: 3
-// Group index: 1
+// Group index: 0
// Number of pads: 24
//
@@ -1522,7 +1109,7 @@
//
// Group name: GPP_H
// Community index: 3
-// Group index: 2
+// Group index: 1
// Number of pads: 20
//
@@ -1671,292 +1258,6 @@
#define GPIOV2_MTL_PCH_S_GPP_H_19 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_H, MTL_PCH_S_GRP_IDX_GPP_H, 19)
-//
-// Group name: vGPIO_3
-// Community index: 3
-// Group index: 3
-// Number of pads: 4
-//
-
-
-// Pin: vGPIO_PCIE_80 ( Value: 0xd80 )
-// Family: v_PCIe
-// Default function: Function 1
-// Native function 1: CPU_PCIE_LNK_DN_0
-#define GPIOV2_MTL_PCH_S_VGPIO_PCIE_80 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_3, MTL_PCH_S_GRP_IDX_VGPIO_3, 0)
-
-// Pin: vGPIO_PCIE_81 ( Value: 0xd81 )
-// Family: v_PCIe
-// Default function: Function 1
-// Native function 1: CPU_PCIE_LNK_DN_1
-#define GPIOV2_MTL_PCH_S_VGPIO_PCIE_81 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_3, MTL_PCH_S_GRP_IDX_VGPIO_3, 1)
-
-// Pin: vGPIO_PCIE_82 ( Value: 0xd82 )
-// Family: v_PCIe
-// Default function: Function 1
-// Native function 1: CPU_PCIE_LNK_DN_2
-#define GPIOV2_MTL_PCH_S_VGPIO_PCIE_82 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_3, MTL_PCH_S_GRP_IDX_VGPIO_3, 2)
-
-// Pin: vGPIO_PCIE_83 ( Value: 0xd83 )
-// Family: v_PCIe
-// Default function: Function 1
-// Native function 1: CPU_PCIE_LNK_DN_3
-#define GPIOV2_MTL_PCH_S_VGPIO_PCIE_83 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_3, MTL_PCH_S_GRP_IDX_VGPIO_3, 3)
-
-
-//
-// Group name: vGPIO_0
-// Community index: 3
-// Group index: 4
-// Number of pads: 8
-//
-
-
-// Pin: vGPIO_USB_0 ( Value: 0xe00 )
-// Family: v_USB
-// Default function: Function 1
-// Native function 1: ESPI_USB_OCB_0
-#define GPIOV2_MTL_PCH_S_VGPIO_USB_0 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_0, MTL_PCH_S_GRP_IDX_VGPIO_0, 0)
-
-// Pin: vGPIO_USB_1 ( Value: 0xe01 )
-// Family: v_USB
-// Default function: Function 1
-// Native function 1: ESPI_USB_OCB_1
-#define GPIOV2_MTL_PCH_S_VGPIO_USB_1 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_0, MTL_PCH_S_GRP_IDX_VGPIO_0, 1)
-
-// Pin: vGPIO_USB_2 ( Value: 0xe02 )
-// Family: v_USB
-// Default function: Function 1
-// Native function 1: ESPI_USB_OCB_2
-#define GPIOV2_MTL_PCH_S_VGPIO_USB_2 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_0, MTL_PCH_S_GRP_IDX_VGPIO_0, 2)
-
-// Pin: vGPIO_USB_3 ( Value: 0xe03 )
-// Family: v_USB
-// Default function: Function 1
-// Native function 1: ESPI_USB_OCB_3
-#define GPIOV2_MTL_PCH_S_VGPIO_USB_3 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_0, MTL_PCH_S_GRP_IDX_VGPIO_0, 3)
-
-// Pin: vGPIO_USB_8 ( Value: 0xe04 )
-// Family: v_USB
-// Default function: Function 1
-// Native function 1: USB_CPU_OCB_0
-#define GPIOV2_MTL_PCH_S_VGPIO_USB_8 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_0, MTL_PCH_S_GRP_IDX_VGPIO_0, 4)
-
-// Pin: vGPIO_USB_9 ( Value: 0xe05 )
-// Family: v_USB
-// Default function: Function 1
-// Native function 1: USB_CPU_OCB_1
-#define GPIOV2_MTL_PCH_S_VGPIO_USB_9 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_0, MTL_PCH_S_GRP_IDX_VGPIO_0, 5)
-
-// Pin: vGPIO_USB_10 ( Value: 0xe06 )
-// Family: v_USB
-// Default function: Function 1
-// Native function 1: USB_CPU_OCB_2
-#define GPIOV2_MTL_PCH_S_VGPIO_USB_10 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_0, MTL_PCH_S_GRP_IDX_VGPIO_0, 6)
-
-// Pin: vGPIO_USB_11 ( Value: 0xe07 )
-// Family: v_USB
-// Default function: Function 1
-// Native function 1: USB_CPU_OCB_3
-#define GPIOV2_MTL_PCH_S_VGPIO_USB_11 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_0, MTL_PCH_S_GRP_IDX_VGPIO_0, 7)
-
-
-//
-// Group name: vGPIO_4
-// Community index: 3
-// Group index: 5
-// Number of pads: 31
-//
-
-
-// Pin: vGPIO_ISCLK_0 ( Value: 0xe80 )
-// Family: v_ISCLK
-// Default function: Function 1
-// Native function 1: ESPI_ISCLK_XTAL_CLKREQ
-#define GPIOV2_MTL_PCH_S_VGPIO_ISCLK_0 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 0)
-
-// Pin: vGPIO_ISCLK_1 ( Value: 0xe81 )
-// Family: v_ISCLK
-// Default function: Function 1
-// Native function 1: ISCLK_ESPI_XTAL_CLKACK
-#define GPIOV2_MTL_PCH_S_VGPIO_ISCLK_1 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 1)
-
-// Pin: vGPIO_SLPC_0 ( Value: 0xe82 )
-// Family: v_ISCLK
-// Default function: Function 1
-// Native function 1: ME_SLPC_FTPM_ENABLE
-#define GPIOV2_MTL_PCH_S_VGPIO_SLPC_0 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 2)
-
-// Pin: vGPIO_SLPC_1 ( Value: 0xe83 )
-// Family: v_ISCLK
-// Default function: Function 1
-// Native function 1: GP_SLPC_DTFUS_CORE_SPITPM_DIS
-#define GPIOV2_MTL_PCH_S_VGPIO_SLPC_1 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 3)
-
-// Pin: vGPIO_SLPC_2 ( Value: 0xe84 )
-// Family: v_ISCLK
-// Default function: Function 1
-// Native function 1: GP_SLPC_SPI_STRAP_TOS
-#define GPIOV2_MTL_PCH_S_VGPIO_SLPC_2 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 4)
-
-// Pin: vGPIO_SLPC_3 ( Value: 0xe85 )
-// Family: v_ISCLK
-// Default function: RW - 4'b0001 [gpio_fuse_dtfus_core_spitpm_dis?4'b0010: 4'b0001]
-// Native function 1: GP_SLPC_DTFUS_CORE_SPITPM_DIS_L0
-// Native function 2: GP_SLPC_DTFUS_CORE_SPITPM_DIS_L1
-#define GPIOV2_MTL_PCH_S_VGPIO_SLPC_3 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 5)
-
-// Pin: vGPIO_SLPC_4 ( Value: 0xe86 )
-// Family: v_ISCLK
-// Default function: RW - 4'b0001 [gpio_sstrap_spi_strap_tos?4'b0010: 4'b0001]
-// Native function 1: GP_SLPC_SPI_STRAP_TOS_L0
-// Native function 2: GP_SLPC_SPI_STRAP_TOS_L1
-#define GPIOV2_MTL_PCH_S_VGPIO_SLPC_4 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 6)
-
-// Pin: vGPIO_SLPC_5 ( Value: 0xe87 )
-// Family: v_ISCLK
-// Default function: Function 1
-// Native function 1: LPC_PRR_TS_OVR
-#define GPIOV2_MTL_PCH_S_VGPIO_SLPC_5 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 7)
-
-// Pin: vGPIO_SLPC_6 ( Value: 0xe88 )
-// Family: v_ISCLK
-// Default function: Function 1
-// Native function 1: ITSS_KU1_SHTDWN
-#define GPIOV2_MTL_PCH_S_VGPIO_SLPC_6 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 8)
-
-// Pin: vGPIO_SPARE_0 ( Value: 0xe89 )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_0
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_0 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 9)
-
-// Pin: vGPIO_SPARE_1 ( Value: 0xe8a )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_1
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_1 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 10)
-
-// Pin: vGPIO_SPARE_2 ( Value: 0xe8b )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_2
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_2 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 11)
-
-// Pin: vGPIO_SPARE_3 ( Value: 0xe8c )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_3
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_3 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 12)
-
-// Pin: vGPIO_SPARE_4 ( Value: 0xe8d )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_4
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_4 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 13)
-
-// Pin: vGPIO_SPARE_5 ( Value: 0xe8e )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_5
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_5 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 14)
-
-// Pin: vGPIO_SPARE_6 ( Value: 0xe8f )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_6
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_6 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 15)
-
-// Pin: vGPIO_SPARE_7 ( Value: 0xe90 )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_7
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_7 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 16)
-
-// Pin: vGPIO_SPARE_8 ( Value: 0xe91 )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_8
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_8 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 17)
-
-// Pin: vGPIO_SPARE_9 ( Value: 0xe92 )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_9
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_9 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 18)
-
-// Pin: vGPIO_SPARE_10 ( Value: 0xe93 )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_10
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_10 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 19)
-
-// Pin: vGPIO_SPARE_11 ( Value: 0xe94 )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_11
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_11 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 20)
-
-// Pin: vGPIO_SPARE_12 ( Value: 0xe95 )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_12
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_12 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 21)
-
-// Pin: vGPIO_SPARE_13 ( Value: 0xe96 )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_13
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_13 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 22)
-
-// Pin: vGPIO_SPARE_14 ( Value: 0xe97 )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_14
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_14 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 23)
-
-// Pin: vGPIO_SPARE_15 ( Value: 0xe98 )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_15
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_15 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 24)
-
-// Pin: vGPIO_SPARE_16 ( Value: 0xe99 )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_16
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_16 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 25)
-
-// Pin: vGPIO_SPARE_17 ( Value: 0xe9a )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_17
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_17 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 26)
-
-// Pin: vGPIO_SPARE_18 ( Value: 0xe9b )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_18
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_18 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 27)
-
-// Pin: vGPIO_SPARE_19 ( Value: 0xe9c )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_19
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_19 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 28)
-
-// Pin: vGPIO_SPARE_20 ( Value: 0xe9d )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_20
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_20 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 29)
-
-// Pin: vGPIO_SPARE_21 ( Value: 0xe9e )
-// Family: v_ISCLK
-// Default function: GP-In
-// Native function 1: VWM_SPARE_21
-#define GPIOV2_MTL_PCH_S_VGPIO_SPARE_21 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_VGPIO_4, MTL_PCH_S_GRP_IDX_VGPIO_4, 30)
-
//
// Group name: GPP_S
@@ -2036,7 +1337,7 @@
// Group name: GPP_E
// Community index: 4
// Group index: 1
-// Number of pads: 23
+// Number of pads: 22
//
@@ -2206,19 +1507,13 @@
// Native function 6: IOM_GPPE_21
#define GPIOV2_MTL_PCH_S_GPP_E_21 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_E, MTL_PCH_S_GRP_IDX_GPP_E, 21)
-// Pin: SPI1_THC0_CLK_LOOPBK ( Value: 0x1096 )
-// Family: THC0_SPI1
-// Default function: RW - 4'b0000 [padmode_value[22][0] ? 4'b0001:4'b0010]
-// Native function 1: SPI1_CLK_LOOPBK
-// Native function 2: THC0_CLK_LOOPBK
-#define GPIOV2_MTL_PCH_S_SPI1_THC0_CLK_LOOPBK GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_E, MTL_PCH_S_GRP_IDX_GPP_E, 22)
//
// Group name: GPP_K
// Community index: 4
// Group index: 2
-// Number of pads: 14
+// Number of pads: 11
//
@@ -2301,23 +1596,6 @@
// Native function 6: IOM_GPPK_10
#define GPIOV2_MTL_PCH_S_GPP_K_10 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_K, MTL_PCH_S_GRP_IDX_GPP_K, 10)
-// Pin: MISC_SPARE ( Value: 0x110b )
-// Family: SYS
-// Default function: Function 1
-// Native function 1: MISC_SPARE
-#define GPIOV2_MTL_PCH_S_MISC_SPARE GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_K, MTL_PCH_S_GRP_IDX_GPP_K, 11)
-
-// Pin: SYS_RESETB ( Value: 0x110c )
-// Family: SYS
-// Default function: Function 1
-// Native function 1: SYS_RESETB
-#define GPIOV2_MTL_PCH_S_SYS_RESETB GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_K, MTL_PCH_S_GRP_IDX_GPP_K, 12)
-
-// Pin: MLK_RSTB ( Value: 0x110d )
-// Family: SYS
-// Default function: Function 1
-// Native function 1: MLK_RSTB
-#define GPIOV2_MTL_PCH_S_MLK_RSTB GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_K, MTL_PCH_S_GRP_IDX_GPP_K, 13)
//
@@ -2551,7 +1829,7 @@
// Group name: GPP_I
// Community index: 5
// Group index: 0
-// Number of pads: 21
+// Number of pads: 17
//
@@ -2678,1680 +1956,6 @@
// Native function 1: ISH_GP_11
#define GPIOV2_MTL_PCH_S_GPP_I_16 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_I, MTL_PCH_S_GRP_IDX_GPP_I, 16)
-// Pin: GSPI0_CLK_LOOPBK ( Value: 0x1411 )
-// Family: GSPI0
-// Default function: Function 1
-// Native function 1: GSPI0_CLK_LOOPBK
-#define GPIOV2_MTL_PCH_S_GSPI0_CLK_LOOPBK GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_I, MTL_PCH_S_GRP_IDX_GPP_I, 17)
-
-// Pin: GSPI1_CLK_LOOPBK ( Value: 0x1412 )
-// Family: GSPI1
-// Default function: Function 1
-// Native function 1: GSPI1_CLK_LOOPBK
-#define GPIOV2_MTL_PCH_S_GSPI1_CLK_LOOPBK GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_I, MTL_PCH_S_GRP_IDX_GPP_I, 18)
-
-// Pin: ISH_I3C0_CLK_LOOPBK ( Value: 0x1413 )
-// Family: ISH_I2C0
-// Default function: Function 1
-// Native function 1: ISH_I3C0_CLK_LOOPBK
-#define GPIOV2_MTL_PCH_S_ISH_I3C0_CLK_LOOPBK GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_I, MTL_PCH_S_GRP_IDX_GPP_I, 19)
-
-// Pin: I3C0_CLK_LOOPBK ( Value: 0x1414 )
-// Family: I2C0
-// Default function: Function 1
-// Native function 1: I3C0_CLK_LOOPBK
-#define GPIOV2_MTL_PCH_S_I3C0_CLK_LOOPBK GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_GPP_I, MTL_PCH_S_GRP_IDX_GPP_I, 20)
-
-
-//
-// Group name: JTAG_CPU
-// Community index: 5
-// Group index: 1
-// Number of pads: 16
-//
-
-
-// Pin: JTAG_TDO ( Value: 0x1480 )
-// Family: JTAG0
-// Default function: Function 1
-// Native function 1: JTAG_TDO
-#define GPIOV2_MTL_PCH_S_JTAG_TDO GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_JTAG_CPU, MTL_PCH_S_GRP_IDX_JTAG_CPU, 0)
-
-// Pin: JTAGX ( Value: 0x1481 )
-// Family: JTAG0
-// Default function: Function 1
-// Native function 1: JTAGX
-#define GPIOV2_MTL_PCH_S_JTAGX GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_JTAG_CPU, MTL_PCH_S_GRP_IDX_JTAG_CPU, 1)
-
-// Pin: PRDYB ( Value: 0x1482 )
-// Family: JTAG2
-// Default function: Function 1
-// Native function 1: PRDYB
-#define GPIOV2_MTL_PCH_S_PRDYB GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_JTAG_CPU, MTL_PCH_S_GRP_IDX_JTAG_CPU, 2)
-
-// Pin: PREQB ( Value: 0x1483 )
-// Family: JTAG2
-// Default function: Function 1
-// Native function 1: PREQB
-#define GPIOV2_MTL_PCH_S_PREQB GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_JTAG_CPU, MTL_PCH_S_GRP_IDX_JTAG_CPU, 3)
-
-// Pin: JTAG_TDI ( Value: 0x1484 )
-// Family: JTAG0
-// Default function: Function 1
-// Native function 1: JTAG_TDI
-#define GPIOV2_MTL_PCH_S_JTAG_TDI GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_JTAG_CPU, MTL_PCH_S_GRP_IDX_JTAG_CPU, 4)
-
-// Pin: JTAG_TMS ( Value: 0x1485 )
-// Family: JTAG0
-// Default function: Function 1
-// Native function 1: JTAG_TMS
-#define GPIOV2_MTL_PCH_S_JTAG_TMS GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_JTAG_CPU, MTL_PCH_S_GRP_IDX_JTAG_CPU, 5)
-
-// Pin: JTAG_TCK ( Value: 0x1486 )
-// Family: JTAG1
-// Default function: Function 1
-// Native function 1: JTAG_TCK
-#define GPIOV2_MTL_PCH_S_JTAG_TCK GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_JTAG_CPU, MTL_PCH_S_GRP_IDX_JTAG_CPU, 6)
-
-// Pin: DBG_PMODE ( Value: 0x1487 )
-// Family: JTAG3
-// Default function: Function 1
-// Native function 1: DBG_PMODE
-#define GPIOV2_MTL_PCH_S_DBG_PMODE GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_JTAG_CPU, MTL_PCH_S_GRP_IDX_JTAG_CPU, 7)
-
-// Pin: CPU_TRSTB ( Value: 0x1488 )
-// Family: JTAG1
-// Default function: Function 1
-// Native function 1: CPU_TRSTB
-#define GPIOV2_MTL_PCH_S_CPU_TRSTB GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_JTAG_CPU, MTL_PCH_S_GRP_IDX_JTAG_CPU, 8)
-
-// Pin: CPUPWRGD ( Value: 0x1489 )
-// Family: PM1
-// Default function: Function 1
-// Native function 1: CPUPWRGD
-#define GPIOV2_MTL_PCH_S_CPUPWRGD GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_JTAG_CPU, MTL_PCH_S_GRP_IDX_JTAG_CPU, 9)
-
-// Pin: PM_SPARE0 ( Value: 0x148a )
-// Family: PM1
-// Default function: Function 1
-// Native function 1: PM_SPARE0
-#define GPIOV2_MTL_PCH_S_PM_SPARE0 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_JTAG_CPU, MTL_PCH_S_GRP_IDX_JTAG_CPU, 10)
-
-// Pin: PM_SPARE1 ( Value: 0x148b )
-// Family: PM1
-// Default function: Function 1
-// Native function 1: PM_SPARE1
-#define GPIOV2_MTL_PCH_S_PM_SPARE1 GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_JTAG_CPU, MTL_PCH_S_GRP_IDX_JTAG_CPU, 11)
-
-// Pin: CRASHLOG_TRIG_N ( Value: 0x148c )
-// Family: PM2
-// Default function: Function 1
-// Native function 1: CRASHLOG_TRIG_N
-#define GPIOV2_MTL_PCH_S_CRASHLOG_TRIG_N GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_JTAG_CPU, MTL_PCH_S_GRP_IDX_JTAG_CPU, 12)
-
-// Pin: TRIGGER_IN ( Value: 0x148d )
-// Family: TRIG
-// Default function: Function 1
-// Native function 1: TRIGGER_IN
-#define GPIOV2_MTL_PCH_S_TRIGGER_IN GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_JTAG_CPU, MTL_PCH_S_GRP_IDX_JTAG_CPU, 13)
-
-// Pin: TRIGGER_OUT ( Value: 0x148e )
-// Family: TRIG
-// Default function: Function 1
-// Native function 1: TRIGGER_OUT
-#define GPIOV2_MTL_PCH_S_TRIGGER_OUT GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_JTAG_CPU, MTL_PCH_S_GRP_IDX_JTAG_CPU, 14)
-
-// Pin: FBRK_OUT_N ( Value: 0x148f )
-// Family: PM
-// Default function: Function 1
-// Native function 1: FBRK_OUT_N
-#define GPIOV2_MTL_PCH_S_FBRK_OUT_N GPIOV2_PAD_ID (0, GPIOV2_MTL_PCH_S_CHIPSET_ID, 0, MTL_PCH_S_COM_IDX_JTAG_CPU, MTL_PCH_S_GRP_IDX_JTAG_CPU, 15)
-
-
-
-//
-// Pin muxing definitions for Group: GPP_D.
-//
-
-// Group: GPP_D, Pad: GPP_D_0, Function: 1 - SRCCLKREQB_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_0__SRCCLKREQB_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_0, 1)
-// Group: GPP_D, Pad: GPP_D_0, Function: 6 - IOM_GPPD_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_0__IOM_GPPD_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_0, 6)
-// Group: GPP_D, Pad: GPP_D_1, Function: 1 - SRCCLKREQB_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_1__SRCCLKREQB_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_1, 1)
-// Group: GPP_D, Pad: GPP_D_1, Function: 6 - IOM_GPPD_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_1__IOM_GPPD_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_1, 6)
-// Group: GPP_D, Pad: GPP_D_2, Function: 1 - SRCCLKREQB_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_2__SRCCLKREQB_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_2, 1)
-// Group: GPP_D, Pad: GPP_D_2, Function: 6 - IOM_GPPD_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_2__IOM_GPPD_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_2, 6)
-// Group: GPP_D, Pad: GPP_D_3, Function: 1 - SRCCLKREQB_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_3__SRCCLKREQB_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_3, 1)
-// Group: GPP_D, Pad: GPP_D_3, Function: 6 - IOM_GPPD_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_3__IOM_GPPD_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_3, 6)
-// Group: GPP_D, Pad: GPP_D_4, Function: 1 - SML1CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_4__SML1CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_4, 1)
-// Group: GPP_D, Pad: GPP_D_4, Function: 6 - IOM_GPPD_4
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_4__IOM_GPPD_4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_4, 6)
-// Group: GPP_D, Pad: GPP_D_5, Function: 1 - I2S2_SFRM
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_5__I2S2_SFRM GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_5, 1)
-// Group: GPP_D, Pad: GPP_D_5, Function: 2 - CNV_RF_RESET_B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_5__CNV_RF_RESET_B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_5, 2)
-// Group: GPP_D, Pad: GPP_D_5, Function: 5 - DMIC_DATA_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_5__DMIC_DATA_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_5, 5)
-// Group: GPP_D, Pad: GPP_D_5, Function: 6 - IOM_GPPD_5
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_5__IOM_GPPD_5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_5, 6)
-// Group: GPP_D, Pad: GPP_D_6, Function: 1 - I2S2_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_6__I2S2_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_6, 1)
-// Group: GPP_D, Pad: GPP_D_6, Function: 3 - CRF_CLKREQ
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_6__CRF_CLKREQ GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_6, 3)
-// Group: GPP_D, Pad: GPP_D_6, Function: 5 - DMIC_CLK_B_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_6__DMIC_CLK_B_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_6, 5)
-// Group: GPP_D, Pad: GPP_D_6, Function: 6 - IOM_GPPD_6
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_6__IOM_GPPD_6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_6, 6)
-// Group: GPP_D, Pad: GPP_D_7, Function: 1 - I2S2_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_7__I2S2_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_7, 1)
-// Group: GPP_D, Pad: GPP_D_7, Function: 5 - DMIC_DATA_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_7__DMIC_DATA_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_7, 5)
-// Group: GPP_D, Pad: GPP_D_7, Function: 6 - IOM_GPPD_7
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_7__IOM_GPPD_7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_7, 6)
-// Group: GPP_D, Pad: GPP_D_8, Function: 1 - I2S2_SCLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_8__I2S2_SCLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_8, 1)
-// Group: GPP_D, Pad: GPP_D_8, Function: 5 - DMIC_CLK_A_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_8__DMIC_CLK_A_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_8, 5)
-// Group: GPP_D, Pad: GPP_D_8, Function: 6 - IOM_GPPD_8
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_8__IOM_GPPD_8 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_8, 6)
-// Group: GPP_D, Pad: GPP_D_9, Function: 1 - SML0CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_9__SML0CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_9, 1)
-// Group: GPP_D, Pad: GPP_D_9, Function: 6 - IOM_GPPD_9
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_9__IOM_GPPD_9 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_9, 6)
-// Group: GPP_D, Pad: GPP_D_10, Function: 1 - SML0DATA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_10__SML0DATA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_10, 1)
-// Group: GPP_D, Pad: GPP_D_10, Function: 6 - IOM_GPPD_10
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_10__IOM_GPPD_10 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_10, 6)
-// Group: GPP_D, Pad: GPP_D_11, Function: 1 - SRCCLKREQB_4
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_11__SRCCLKREQB_4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_11, 1)
-// Group: GPP_D, Pad: GPP_D_11, Function: 6 - IOM_GPPD_11
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_11__IOM_GPPD_11 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_11, 6)
-// Group: GPP_D, Pad: GPP_D_12, Function: 1 - SRCCLKREQB_5
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_12__SRCCLKREQB_5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_12, 1)
-// Group: GPP_D, Pad: GPP_D_12, Function: 6 - IOM_GPPD_12
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_12__IOM_GPPD_12 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_12, 6)
-// Group: GPP_D, Pad: GPP_D_13, Function: 1 - SRCCLKREQB_6
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_13__SRCCLKREQB_6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_13, 1)
-// Group: GPP_D, Pad: GPP_D_13, Function: 6 - IOM_GPPD_13
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_13__IOM_GPPD_13 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_13, 6)
-// Group: GPP_D, Pad: GPP_D_14, Function: 1 - SRCCLKREQB_7
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_14__SRCCLKREQB_7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_14, 1)
-// Group: GPP_D, Pad: GPP_D_14, Function: 6 - IOM_GPPD_14
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_14__IOM_GPPD_14 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_14, 6)
-// Group: GPP_D, Pad: GPP_D_15, Function: 1 - SML1DATA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_15__SML1DATA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_15, 1)
-// Group: GPP_D, Pad: GPP_D_15, Function: 6 - IOM_GPPD_15
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_15__IOM_GPPD_15 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_15, 6)
-// Group: GPP_D, Pad: GPP_D_16, Function: 1 - GSPI3_CS0B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_16__GSPI3_CS0B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_16, 1)
-// Group: GPP_D, Pad: GPP_D_16, Function: 2 - THC1_SPI2_CSB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_16__THC1_SPI2_CSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_16, 2)
-// Group: GPP_D, Pad: GPP_D_16, Function: 6 - IOM_GPPD_16
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_16__IOM_GPPD_16 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_16, 6)
-// Group: GPP_D, Pad: GPP_D_17, Function: 1 - GSPI3_CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_17__GSPI3_CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_17, 1)
-// Group: GPP_D, Pad: GPP_D_17, Function: 2 - THC1_SPI2_CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_17__THC1_SPI2_CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_17, 2)
-// Group: GPP_D, Pad: GPP_D_17, Function: 6 - IOM_GPPD_17
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_17__IOM_GPPD_17 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_17, 6)
-// Group: GPP_D, Pad: GPP_D_18, Function: 1 - GSPI3_MISO
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_18__GSPI3_MISO GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_18, 1)
-// Group: GPP_D, Pad: GPP_D_18, Function: 2 - THC1_SPI2_IO_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_18__THC1_SPI2_IO_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_18, 2)
-// Group: GPP_D, Pad: GPP_D_18, Function: 6 - IOM_GPPD_18
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_18__IOM_GPPD_18 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_18, 6)
-// Group: GPP_D, Pad: GPP_D_19, Function: 1 - GSPI3_MOSI
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_19__GSPI3_MOSI GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_19, 1)
-// Group: GPP_D, Pad: GPP_D_19, Function: 2 - THC1_SPI2_IO_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_19__THC1_SPI2_IO_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_19, 2)
-// Group: GPP_D, Pad: GPP_D_19, Function: 6 - IOM_GPPD_19
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_19__IOM_GPPD_19 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_19, 6)
-// Group: GPP_D, Pad: GPP_D_20, Function: 1 - UART3_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_20__UART3_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_20, 1)
-// Group: GPP_D, Pad: GPP_D_20, Function: 2 - THC1_SPI2_IO_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_20__THC1_SPI2_IO_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_20, 2)
-// Group: GPP_D, Pad: GPP_D_20, Function: 6 - IOM_GPPD_20
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_20__IOM_GPPD_20 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_20, 6)
-// Group: GPP_D, Pad: GPP_D_21, Function: 1 - UART3_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_21__UART3_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_21, 1)
-// Group: GPP_D, Pad: GPP_D_21, Function: 2 - THC1_SPI2_IO_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_21__THC1_SPI2_IO_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_21, 2)
-// Group: GPP_D, Pad: GPP_D_21, Function: 6 - IOM_GPPD_21
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_21__IOM_GPPD_21 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_21, 6)
-// Group: GPP_D, Pad: GPP_D_22, Function: 1 - UART3_RTSB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_22__UART3_RTSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_22, 1)
-// Group: GPP_D, Pad: GPP_D_22, Function: 2 - THC1_SPI2_RSTB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_22__THC1_SPI2_RSTB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_22, 2)
-// Group: GPP_D, Pad: GPP_D_22, Function: 6 - IOM_GPPD_22
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_22__IOM_GPPD_22 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_22, 6)
-// Group: GPP_D, Pad: GPP_D_23, Function: 1 - UART3_CTSB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_23__UART3_CTSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_23, 1)
-// Group: GPP_D, Pad: GPP_D_23, Function: 2 - THC1_SPI2_INTB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_23__THC1_SPI2_INTB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_23, 2)
-// Group: GPP_D, Pad: GPP_D_23, Function: 6 - IOM_GPPD_23
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_D_23__IOM_GPPD_23 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_D_23, 6)
-// Group: GPP_D, Pad: GSPI3_THC1_CLK_LOOPBK, Function: 1 - GSPI3_CLK_LOOPBK
-#define GPIOV2_MTL_PCH_S_MUXING__GSPI3_THC1_CLK_LOOPBK__GSPI3_CLK_LOOPBK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GSPI3_THC1_CLK_LOOPBK, 1)
-// Group: GPP_D, Pad: GSPI3_THC1_CLK_LOOPBK, Function: 2 - THC1_CLK_LOOPBK
-#define GPIOV2_MTL_PCH_S_MUXING__GSPI3_THC1_CLK_LOOPBK__THC1_CLK_LOOPBK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GSPI3_THC1_CLK_LOOPBK, 2)
-
-//
-// Pin muxing definitions for Group: GPP_R.
-//
-
-// Group: GPP_R, Pad: GPP_R_0, Function: 1 - HDA_BCLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_0__HDA_BCLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_0, 1)
-// Group: GPP_R, Pad: GPP_R_0, Function: 2 - I2S0_SCLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_0__I2S0_SCLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_0, 2)
-// Group: GPP_R, Pad: GPP_R_0, Function: 4 - HDACPU_BCLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_0__HDACPU_BCLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_0, 4)
-// Group: GPP_R, Pad: GPP_R_0, Function: 5 - DMIC_CLK_A_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_0__DMIC_CLK_A_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_0, 5)
-// Group: GPP_R, Pad: GPP_R_0, Function: 6 - IOM_GPPR_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_0__IOM_GPPR_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_0, 6)
-// Group: GPP_R, Pad: GPP_R_1, Function: 1 - HDA_SYNC
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_1__HDA_SYNC GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_1, 1)
-// Group: GPP_R, Pad: GPP_R_1, Function: 2 - I2S0_SFRM
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_1__I2S0_SFRM GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_1, 2)
-// Group: GPP_R, Pad: GPP_R_1, Function: 5 - DMIC_CLK_B_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_1__DMIC_CLK_B_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_1, 5)
-// Group: GPP_R, Pad: GPP_R_1, Function: 6 - IOM_GPPR_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_1__IOM_GPPR_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_1, 6)
-// Group: GPP_R, Pad: GPP_R_2, Function: 1 - HDA_SDO
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_2__HDA_SDO GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_2, 1)
-// Group: GPP_R, Pad: GPP_R_2, Function: 2 - I2S0_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_2__I2S0_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_2, 2)
-// Group: GPP_R, Pad: GPP_R_2, Function: 4 - HDACPU_SDO
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_2__HDACPU_SDO GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_2, 4)
-// Group: GPP_R, Pad: GPP_R_2, Function: 6 - IOM_GPPR_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_2__IOM_GPPR_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_2, 6)
-// Group: GPP_R, Pad: GPP_R_3, Function: 1 - HDA_SDI_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_3__HDA_SDI_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_3, 1)
-// Group: GPP_R, Pad: GPP_R_3, Function: 2 - I2S0_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_3__I2S0_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_3, 2)
-// Group: GPP_R, Pad: GPP_R_3, Function: 4 - HDACPU_SDI
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_3__HDACPU_SDI GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_3, 4)
-// Group: GPP_R, Pad: GPP_R_3, Function: 6 - IOM_GPPR_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_3__IOM_GPPR_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_3, 6)
-// Group: GPP_R, Pad: GPP_R_4, Function: 1 - HDA_RSTB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_4__HDA_RSTB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_4, 1)
-// Group: GPP_R, Pad: GPP_R_4, Function: 6 - IOM_GPPR_4
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_4__IOM_GPPR_4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_4, 6)
-// Group: GPP_R, Pad: GPP_R_5, Function: 1 - HDA_SDI_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_5__HDA_SDI_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_5, 1)
-// Group: GPP_R, Pad: GPP_R_5, Function: 2 - I2S1_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_5__I2S1_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_5, 2)
-// Group: GPP_R, Pad: GPP_R_5, Function: 6 - IOM_GPPR_5
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_5__IOM_GPPR_5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_5, 6)
-// Group: GPP_R, Pad: GPP_R_6, Function: 2 - I2S1_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_6__I2S1_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_6, 2)
-// Group: GPP_R, Pad: GPP_R_6, Function: 6 - IOM_GPPR_6
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_6__IOM_GPPR_6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_6, 6)
-// Group: GPP_R, Pad: GPP_R_7, Function: 2 - I2S1_SFRM
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_7__I2S1_SFRM GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_7, 2)
-// Group: GPP_R, Pad: GPP_R_7, Function: 6 - IOM_GPPR_7
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_7__IOM_GPPR_7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_7, 6)
-// Group: GPP_R, Pad: GPP_R_8, Function: 2 - I2S1_SCLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_8__I2S1_SCLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_8, 2)
-// Group: GPP_R, Pad: GPP_R_8, Function: 6 - IOM_GPPR_8
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_8__IOM_GPPR_8 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_8, 6)
-// Group: GPP_R, Pad: GPP_R_9, Function: 1 - ISH_SPI_CSB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_9__ISH_SPI_CSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_9, 1)
-// Group: GPP_R, Pad: GPP_R_9, Function: 3 - GSPI2_CS0B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_9__GSPI2_CS0B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_9, 3)
-// Group: GPP_R, Pad: GPP_R_9, Function: 6 - IOM_GPPR_9
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_9__IOM_GPPR_9 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_9, 6)
-// Group: GPP_R, Pad: GPP_R_10, Function: 1 - ISH_SPI_CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_10__ISH_SPI_CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_10, 1)
-// Group: GPP_R, Pad: GPP_R_10, Function: 3 - GSPI2_CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_10__GSPI2_CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_10, 3)
-// Group: GPP_R, Pad: GPP_R_10, Function: 6 - IOM_GPPR_10
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_10__IOM_GPPR_10 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_10, 6)
-// Group: GPP_R, Pad: GPP_R_11, Function: 1 - ISH_SPI_MISO
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_11__ISH_SPI_MISO GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_11, 1)
-// Group: GPP_R, Pad: GPP_R_11, Function: 3 - GSPI2_MISO
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_11__GSPI2_MISO GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_11, 3)
-// Group: GPP_R, Pad: GPP_R_11, Function: 6 - IOM_GPPR_11
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_11__IOM_GPPR_11 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_11, 6)
-// Group: GPP_R, Pad: GPP_R_12, Function: 1 - ISH_SPI_MOSI
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_12__ISH_SPI_MOSI GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_12, 1)
-// Group: GPP_R, Pad: GPP_R_12, Function: 3 - GSPI2_MOSI
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_12__GSPI2_MOSI GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_12, 3)
-// Group: GPP_R, Pad: GPP_R_12, Function: 6 - IOM_GPPR_12
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_R_12__IOM_GPPR_12 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_R_12, 6)
-// Group: GPP_R, Pad: GSPI2_CLK_LOOPBK, Function: 3 - GSPI2_CLK_LOOPBK
-#define GPIOV2_MTL_PCH_S_MUXING__GSPI2_CLK_LOOPBK__GSPI2_CLK_LOOPBK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GSPI2_CLK_LOOPBK, 3)
-
-//
-// Pin muxing definitions for Group: GPP_J.
-//
-
-// Group: GPP_J, Pad: GPP_J_0, Function: 1 - CNV_PA_BLANKING
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_0__CNV_PA_BLANKING GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_0, 1)
-// Group: GPP_J, Pad: GPP_J_0, Function: 6 - IOM_GPPJ_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_0__IOM_GPPJ_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_0, 6)
-// Group: GPP_J, Pad: GPP_J_1, Function: 1 - CNV_BRI_DT
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_1__CNV_BRI_DT GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_1, 1)
-// Group: GPP_J, Pad: GPP_J_1, Function: 2 - UART0_RTSB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_1__UART0_RTSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_1, 2)
-// Group: GPP_J, Pad: GPP_J_1, Function: 6 - IOM_GPPJ_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_1__IOM_GPPJ_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_1, 6)
-// Group: GPP_J, Pad: GPP_J_2, Function: 1 - CNV_BRI_RSP
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_2__CNV_BRI_RSP GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_2, 1)
-// Group: GPP_J, Pad: GPP_J_2, Function: 2 - UART0_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_2__UART0_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_2, 2)
-// Group: GPP_J, Pad: GPP_J_2, Function: 6 - IOM_GPPJ_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_2__IOM_GPPJ_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_2, 6)
-// Group: GPP_J, Pad: GPP_J_3, Function: 1 - CNV_RGI_DT
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_3__CNV_RGI_DT GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_3, 1)
-// Group: GPP_J, Pad: GPP_J_3, Function: 2 - UART0_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_3__UART0_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_3, 2)
-// Group: GPP_J, Pad: GPP_J_3, Function: 6 - IOM_GPPJ_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_3__IOM_GPPJ_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_3, 6)
-// Group: GPP_J, Pad: GPP_J_4, Function: 1 - CNV_RGI_RSP
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_4__CNV_RGI_RSP GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_4, 1)
-// Group: GPP_J, Pad: GPP_J_4, Function: 2 - UART0_CTSB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_4__UART0_CTSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_4, 2)
-// Group: GPP_J, Pad: GPP_J_4, Function: 6 - IOM_GPPJ_4
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_4__IOM_GPPJ_4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_4, 6)
-// Group: GPP_J, Pad: GPP_J_5, Function: 1 - CNV_MFUART2_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_5__CNV_MFUART2_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_5, 1)
-// Group: GPP_J, Pad: GPP_J_5, Function: 6 - IOM_GPPJ_5
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_5__IOM_GPPJ_5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_5, 6)
-// Group: GPP_J, Pad: GPP_J_6, Function: 1 - CNV_MFUART2_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_6__CNV_MFUART2_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_6, 1)
-// Group: GPP_J, Pad: GPP_J_6, Function: 6 - IOM_GPPJ_6
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_6__IOM_GPPJ_6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_6, 6)
-// Group: GPP_J, Pad: GPP_J_7, Function: 1 - BOOTHALT_B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_7__BOOTHALT_B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_7, 1)
-// Group: GPP_J, Pad: GPP_J_7, Function: 6 - IOM_GPPJ_7
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_7__IOM_GPPJ_7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_7, 6)
-// Group: GPP_J, Pad: GPP_J_8, Function: 1 - RTCCLKOUT
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_8__RTCCLKOUT GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_8, 1)
-// Group: GPP_J, Pad: GPP_J_8, Function: 6 - IOM_GPPJ_8
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_8__IOM_GPPJ_8 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_8, 6)
-// Group: GPP_J, Pad: GPP_J_9, Function: 1 - BPKI3C_SDA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_9__BPKI3C_SDA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_9, 1)
-// Group: GPP_J, Pad: GPP_J_9, Function: 2 - BSSB_LS_RX
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_9__BSSB_LS_RX GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_9, 2)
-// Group: GPP_J, Pad: GPP_J_9, Function: 6 - IOM_GPPJ_9
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_9__IOM_GPPJ_9 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_9, 6)
-// Group: GPP_J, Pad: GPP_J_10, Function: 1 - BPKI3C_SCL
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_10__BPKI3C_SCL GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_10, 1)
-// Group: GPP_J, Pad: GPP_J_10, Function: 2 - BSSB_LS_TX
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_10__BSSB_LS_TX GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_10, 2)
-// Group: GPP_J, Pad: GPP_J_10, Function: 6 - IOM_GPPJ_10
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_10__IOM_GPPJ_10 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_10, 6)
-// Group: GPP_J, Pad: GPP_J_11, Function: 1 - DAM
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_11__DAM GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_11, 1)
-// Group: GPP_J, Pad: GPP_J_12, Function: 4 - HDACPU_SDI
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_12__HDACPU_SDI GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_12, 4)
-// Group: GPP_J, Pad: GPP_J_13, Function: 4 - HDACPU_SDO
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_13__HDACPU_SDO GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_13, 4)
-// Group: GPP_J, Pad: GPP_J_14, Function: 4 - HDACPU_BCLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_14__HDACPU_BCLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_14, 4)
-// Group: GPP_J, Pad: GPP_J_15, Function: 1 - AUX_PWRGD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_15__AUX_PWRGD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_15, 1)
-// Group: GPP_J, Pad: GPP_J_16, Function: 1 - GLB_RST_WARN_B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_J_16__GLB_RST_WARN_B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_J_16, 1)
-// Group: GPP_J, Pad: RESET_SYNCB, Function: 1 - RESET_SYNCB
-#define GPIOV2_MTL_PCH_S_MUXING__RESET_SYNCB__RESET_SYNCB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_RESET_SYNCB, 1)
-
-//
-// Pin muxing definitions for Group: vGPIO.
-//
-
-// Group: vGPIO, Pad: vGPIO_6, Function: 2 - UART0_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_6__UART0_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_6, 2)
-// Group: vGPIO, Pad: vGPIO_6, Function: 2 - ISH_UART0_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_6__ISH_UART0_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_6, 2)
-// Group: vGPIO, Pad: vGPIO_7, Function: 2 - UART0_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_7__UART0_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_7, 2)
-// Group: vGPIO, Pad: vGPIO_7, Function: 2 - ISH_UART0_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_7__ISH_UART0_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_7, 2)
-// Group: vGPIO, Pad: vGPIO_8, Function: 2 - UART0_RTSB
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_8__UART0_RTSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_8, 2)
-// Group: vGPIO, Pad: vGPIO_8, Function: 2 - ISH_UART0_RTSB
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_8__ISH_UART0_RTSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_8, 2)
-// Group: vGPIO, Pad: vGPIO_9, Function: 2 - UART0_CTSB
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_9__UART0_CTSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_9, 2)
-// Group: vGPIO, Pad: vGPIO_9, Function: 2 - ISH_UART0_CTSB
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_9__ISH_UART0_CTSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_9, 2)
-// Group: vGPIO, Pad: vGPIO_10, Function: 2 - ISH_UART0_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_10__ISH_UART0_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_10, 2)
-// Group: vGPIO, Pad: vGPIO_10, Function: 2 - UART2_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_10__UART2_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_10, 2)
-// Group: vGPIO, Pad: vGPIO_11, Function: 2 - ISH_UART0_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_11__ISH_UART0_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_11, 2)
-// Group: vGPIO, Pad: vGPIO_11, Function: 2 - UART2_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_11__UART2_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_11, 2)
-// Group: vGPIO, Pad: vGPIO_12, Function: 2 - ISH_UART0_RTSB
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_12__ISH_UART0_RTSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_12, 2)
-// Group: vGPIO, Pad: vGPIO_12, Function: 2 - UART2_RTS_B
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_12__UART2_RTS_B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_12, 2)
-// Group: vGPIO, Pad: vGPIO_13, Function: 2 - ISH_UART0_CTSB
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_13__ISH_UART0_CTSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_13, 2)
-// Group: vGPIO, Pad: vGPIO_13, Function: 2 - UART2_CTS_B
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_13__UART2_CTS_B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_13, 2)
-// Group: vGPIO, Pad: vGPIO_18, Function: 1 - CNV_BT_UART_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_18__CNV_BT_UART_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_18, 1)
-// Group: vGPIO, Pad: vGPIO_19, Function: 1 - CNV_BT_UART_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_19__CNV_BT_UART_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_19, 1)
-// Group: vGPIO, Pad: vGPIO_20, Function: 1 - CNV_BT_UART_RTS_B
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_20__CNV_BT_UART_RTS_B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_20, 1)
-// Group: vGPIO, Pad: vGPIO_21, Function: 1 - CNV_BT_UART_CTS_B
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_21__CNV_BT_UART_CTS_B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_21, 1)
-// Group: vGPIO, Pad: vGPIO_22, Function: 1 - CNV_MFUART1_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_22__CNV_MFUART1_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_22, 1)
-// Group: vGPIO, Pad: vGPIO_23, Function: 1 - CNV_MFUART1_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_23__CNV_MFUART1_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_23, 1)
-// Group: vGPIO, Pad: vGPIO_24, Function: 1 - CNV_MFUART1_RTS_B
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_24__CNV_MFUART1_RTS_B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_24, 1)
-// Group: vGPIO, Pad: vGPIO_25, Function: 1 - CNV_MFUART1_CTS_B
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_25__CNV_MFUART1_CTS_B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_25, 1)
-// Group: vGPIO, Pad: vGPIO_30, Function: 2 - I2S0_SCLK
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_30__I2S0_SCLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_30, 2)
-// Group: vGPIO, Pad: vGPIO_30, Function: 2 - I2S1_SCLK
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_30__I2S1_SCLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_30, 2)
-// Group: vGPIO, Pad: vGPIO_30, Function: 1 - I2S2_SCLK
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_30__I2S2_SCLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_30, 1)
-// Group: vGPIO, Pad: vGPIO_31, Function: 2 - I2S0_SFRM
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_31__I2S0_SFRM GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_31, 2)
-// Group: vGPIO, Pad: vGPIO_31, Function: 2 - I2S1_SFRM
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_31__I2S1_SFRM GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_31, 2)
-// Group: vGPIO, Pad: vGPIO_31, Function: 1 - I2S2_SFRM
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_31__I2S2_SFRM GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_31, 1)
-// Group: vGPIO, Pad: vGPIO_32, Function: 2 - I2S0_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_32__I2S0_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_32, 2)
-// Group: vGPIO, Pad: vGPIO_32, Function: 2 - I2S1_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_32__I2S1_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_32, 2)
-// Group: vGPIO, Pad: vGPIO_32, Function: 1 - I2S2_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_32__I2S2_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_32, 1)
-// Group: vGPIO, Pad: vGPIO_33, Function: 2 - I2S0_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_33__I2S0_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_33, 2)
-// Group: vGPIO, Pad: vGPIO_33, Function: 2 - I2S1_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_33__I2S1_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_33, 2)
-// Group: vGPIO, Pad: vGPIO_33, Function: 1 - I2S2_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_33__I2S2_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_33, 1)
-// Group: vGPIO, Pad: vGPIO_34, Function: 1 - CNV_BT_I2S_BCLK
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_34__CNV_BT_I2S_BCLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_34, 1)
-// Group: vGPIO, Pad: vGPIO_35, Function: 1 - CNV_BT_I2S_WS_SYNC
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_35__CNV_BT_I2S_WS_SYNC GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_35, 1)
-// Group: vGPIO, Pad: vGPIO_36, Function: 1 - CNV_BT_I2S_SDI
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_36__CNV_BT_I2S_SDI GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_36, 1)
-// Group: vGPIO, Pad: vGPIO_37, Function: 1 - CNV_BT_I2S_SDO
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_37__CNV_BT_I2S_SDO GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_37, 1)
-
-//
-// Pin muxing definitions for Group: GPP_A.
-//
-
-// Group: GPP_A, Pad: GPP_A_0, Function: 1 - ESPI_IO_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_0__ESPI_IO_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_0, 1)
-// Group: GPP_A, Pad: GPP_A_0, Function: 6 - IOM_GPPA_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_0__IOM_GPPA_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_0, 6)
-// Group: GPP_A, Pad: GPP_A_1, Function: 1 - ESPI_IO_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_1__ESPI_IO_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_1, 1)
-// Group: GPP_A, Pad: GPP_A_1, Function: 6 - IOM_GPPA_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_1__IOM_GPPA_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_1, 6)
-// Group: GPP_A, Pad: GPP_A_2, Function: 1 - ESPI_IO_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_2__ESPI_IO_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_2, 1)
-// Group: GPP_A, Pad: GPP_A_2, Function: 2 - SUSWARNB_SUSPWRDNACK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_2__SUSWARNB_SUSPWRDNACK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_2, 2)
-// Group: GPP_A, Pad: GPP_A_2, Function: 6 - IOM_GPPA_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_2__IOM_GPPA_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_2, 6)
-// Group: GPP_A, Pad: GPP_A_3, Function: 1 - ESPI_IO_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_3__ESPI_IO_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_3, 1)
-// Group: GPP_A, Pad: GPP_A_3, Function: 2 - SUSACKB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_3__SUSACKB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_3, 2)
-// Group: GPP_A, Pad: GPP_A_3, Function: 6 - IOM_GPPA_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_3__IOM_GPPA_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_3, 6)
-// Group: GPP_A, Pad: GPP_A_4, Function: 1 - ESPI_CS0B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_4__ESPI_CS0B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_4, 1)
-// Group: GPP_A, Pad: GPP_A_4, Function: 6 - IOM_GPPA_4
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_4__IOM_GPPA_4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_4, 6)
-// Group: GPP_A, Pad: GPP_A_5, Function: 1 - ESPI_CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_5__ESPI_CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_5, 1)
-// Group: GPP_A, Pad: GPP_A_5, Function: 6 - IOM_GPPA_5
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_5__IOM_GPPA_5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_5, 6)
-// Group: GPP_A, Pad: GPP_A_6, Function: 1 - ESPI_RESETB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_6__ESPI_RESETB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_6, 1)
-// Group: GPP_A, Pad: GPP_A_6, Function: 6 - IOM_GPPA_6
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_6__IOM_GPPA_6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_6, 6)
-// Group: GPP_A, Pad: GPP_A_7, Function: 1 - ESPI_CS1B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_7__ESPI_CS1B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_7, 1)
-// Group: GPP_A, Pad: GPP_A_7, Function: 6 - IOM_GPPA_7
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_7__IOM_GPPA_7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_7, 6)
-// Group: GPP_A, Pad: GPP_A_8, Function: 1 - ESPI_CS2B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_8__ESPI_CS2B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_8, 1)
-// Group: GPP_A, Pad: GPP_A_8, Function: 6 - IOM_GPPA_8
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_8__IOM_GPPA_8 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_8, 6)
-// Group: GPP_A, Pad: GPP_A_9, Function: 1 - ESPI_CS3B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_9__ESPI_CS3B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_9, 1)
-// Group: GPP_A, Pad: GPP_A_9, Function: 6 - IOM_GPPA_9
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_9__IOM_GPPA_9 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_9, 6)
-// Group: GPP_A, Pad: GPP_A_10, Function: 1 - ESPI_ALERT0B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_10__ESPI_ALERT0B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_10, 1)
-// Group: GPP_A, Pad: GPP_A_10, Function: 6 - IOM_GPPA_10
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_10__IOM_GPPA_10 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_10, 6)
-// Group: GPP_A, Pad: GPP_A_11, Function: 1 - ESPI_ALERT1B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_11__ESPI_ALERT1B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_11, 1)
-// Group: GPP_A, Pad: GPP_A_11, Function: 6 - IOM_GPPA_11
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_11__IOM_GPPA_11 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_11, 6)
-// Group: GPP_A, Pad: GPP_A_12, Function: 1 - ESPI_ALERT2B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_12__ESPI_ALERT2B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_12, 1)
-// Group: GPP_A, Pad: GPP_A_12, Function: 6 - IOM_GPPA_12
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_12__IOM_GPPA_12 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_12, 6)
-// Group: GPP_A, Pad: GPP_A_13, Function: 1 - ESPI_ALERT3B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_13__ESPI_ALERT3B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_13, 1)
-// Group: GPP_A, Pad: GPP_A_13, Function: 6 - IOM_GPPA_13
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_A_13__IOM_GPPA_13 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_A_13, 6)
-// Group: GPP_A, Pad: ESPI_CLK_LOOPBK, Function: 1 - ESPI_CLK_LOOPBK
-#define GPIOV2_MTL_PCH_S_MUXING__ESPI_CLK_LOOPBK__ESPI_CLK_LOOPBK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_ESPI_CLK_LOOPBK, 1)
-
-//
-// Pin muxing definitions for Group: DIR_ESPI.
-//
-
-// Group: DIR_ESPI, Pad: PWRBTNB_OUT, Function: 1 - PWRBTNB_OUT
-#define GPIOV2_MTL_PCH_S_MUXING__PWRBTNB_OUT__PWRBTNB_OUT GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_PWRBTNB_OUT, 1)
-// Group: DIR_ESPI, Pad: DMI_PERSTB, Function: 1 - DMI_PERSTB
-#define GPIOV2_MTL_PCH_S_MUXING__DMI_PERSTB__DMI_PERSTB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_DMI_PERSTB, 1)
-// Group: DIR_ESPI, Pad: DMI_CLKREQB, Function: 1 - DMI_CLKREQB
-#define GPIOV2_MTL_PCH_S_MUXING__DMI_CLKREQB__DMI_CLKREQB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_DMI_CLKREQB, 1)
-// Group: DIR_ESPI, Pad: DIR_ESPI_IO_0, Function: 1 - DIR_ESPI_IO_0
-#define GPIOV2_MTL_PCH_S_MUXING__DIR_ESPI_IO_0__DIR_ESPI_IO_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_DIR_ESPI_IO_0, 1)
-// Group: DIR_ESPI, Pad: DIR_ESPI_IO_1, Function: 1 - DIR_ESPI_IO_1
-#define GPIOV2_MTL_PCH_S_MUXING__DIR_ESPI_IO_1__DIR_ESPI_IO_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_DIR_ESPI_IO_1, 1)
-// Group: DIR_ESPI, Pad: DIR_ESPI_IO_2, Function: 1 - DIR_ESPI_IO_2
-#define GPIOV2_MTL_PCH_S_MUXING__DIR_ESPI_IO_2__DIR_ESPI_IO_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_DIR_ESPI_IO_2, 1)
-// Group: DIR_ESPI, Pad: DIR_ESPI_IO_3, Function: 1 - DIR_ESPI_IO_3
-#define GPIOV2_MTL_PCH_S_MUXING__DIR_ESPI_IO_3__DIR_ESPI_IO_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_DIR_ESPI_IO_3, 1)
-// Group: DIR_ESPI, Pad: DIR_ESPI_CSB, Function: 1 - DIR_ESPI_CSB
-#define GPIOV2_MTL_PCH_S_MUXING__DIR_ESPI_CSB__DIR_ESPI_CSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_DIR_ESPI_CSB, 1)
-// Group: DIR_ESPI, Pad: DIR_ESPI_RESETB, Function: 1 - DIR_ESPI_RESETB
-#define GPIOV2_MTL_PCH_S_MUXING__DIR_ESPI_RESETB__DIR_ESPI_RESETB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_DIR_ESPI_RESETB, 1)
-// Group: DIR_ESPI, Pad: DIR_ESPI_CLK, Function: 1 - DIR_ESPI_CLK
-#define GPIOV2_MTL_PCH_S_MUXING__DIR_ESPI_CLK__DIR_ESPI_CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_DIR_ESPI_CLK, 1)
-// Group: DIR_ESPI, Pad: DIR_ESPI_RCLK, Function: 1 - DIR_ESPI_RCLK
-#define GPIOV2_MTL_PCH_S_MUXING__DIR_ESPI_RCLK__DIR_ESPI_RCLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_DIR_ESPI_RCLK, 1)
-// Group: DIR_ESPI, Pad: DIR_ESPI_ALERTB, Function: 1 - DIR_ESPI_ALERTB
-#define GPIOV2_MTL_PCH_S_MUXING__DIR_ESPI_ALERTB__DIR_ESPI_ALERTB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_DIR_ESPI_ALERTB, 1)
-
-//
-// Pin muxing definitions for Group: GPP_B.
-//
-
-// Group: GPP_B, Pad: GPP_B_0, Function: 1 - PCIE_LNK_DOWN
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_0__PCIE_LNK_DOWN GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_0, 1)
-// Group: GPP_B, Pad: GPP_B_0, Function: 6 - IOM_GPPB_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_0__IOM_GPPB_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_0, 6)
-// Group: GPP_B, Pad: GPP_B_1, Function: 2 - ISH_UART0_RTSB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_1__ISH_UART0_RTSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_1, 2)
-// Group: GPP_B, Pad: GPP_B_1, Function: 2 - GSPI2_CS1B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_1__GSPI2_CS1B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_1, 2)
-// Group: GPP_B, Pad: GPP_B_1, Function: 6 - IOM_GPPB_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_1__IOM_GPPB_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_1, 6)
-// Group: GPP_B, Pad: GPP_B_2, Function: 1 - ISH_GP_8
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_2__ISH_GP_8 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_2, 1)
-// Group: GPP_B, Pad: GPP_B_2, Function: 6 - IOM_GPPB_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_2__IOM_GPPB_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_2, 6)
-// Group: GPP_B, Pad: GPP_B_3, Function: 1 - CPU_GP_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_3__CPU_GP_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_3, 1)
-// Group: GPP_B, Pad: GPP_B_3, Function: 6 - IOM_GPPB_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_3__IOM_GPPB_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_3, 6)
-// Group: GPP_B, Pad: GPP_B_4, Function: 1 - CPU_GP_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_4__CPU_GP_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_4, 1)
-// Group: GPP_B, Pad: GPP_B_4, Function: 6 - IOM_GPPB_4
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_4__IOM_GPPB_4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_4, 6)
-// Group: GPP_B, Pad: GPP_B_5, Function: 1 - SX_EXIT_HOLDOFFB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_5__SX_EXIT_HOLDOFFB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_5, 1)
-// Group: GPP_B, Pad: GPP_B_5, Function: 2 - ISH_GP_6
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_5__ISH_GP_6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_5, 2)
-// Group: GPP_B, Pad: GPP_B_5, Function: 3 - IEH_FATAL_ERR2B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_5__IEH_FATAL_ERR2B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_5, 3)
-// Group: GPP_B, Pad: GPP_B_5, Function: 6 - IOM_GPPB_5
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_5__IOM_GPPB_5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_5, 6)
-// Group: GPP_B, Pad: GPP_B_6, Function: 1 - CLKOUT_48
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_6__CLKOUT_48 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_6, 1)
-// Group: GPP_B, Pad: GPP_B_6, Function: 2 - CNV_DEBUG_00
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_6__CNV_DEBUG_00 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_6, 2)
-// Group: GPP_B, Pad: GPP_B_6, Function: 6 - IOM_GPPB_6
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_6__IOM_GPPB_6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_6, 6)
-// Group: GPP_B, Pad: GPP_B_7, Function: 1 - ISH_GP_7
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_7__ISH_GP_7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_7, 1)
-// Group: GPP_B, Pad: GPP_B_7, Function: 2 - CNV_DEBUG_01
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_7__CNV_DEBUG_01 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_7, 2)
-// Group: GPP_B, Pad: GPP_B_7, Function: 6 - IOM_GPPB_7
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_7__IOM_GPPB_7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_7, 6)
-// Group: GPP_B, Pad: GPP_B_8, Function: 1 - ISH_GP_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_8__ISH_GP_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_8, 1)
-// Group: GPP_B, Pad: GPP_B_8, Function: 2 - CNV_DEBUG_02
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_8__CNV_DEBUG_02 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_8, 2)
-// Group: GPP_B, Pad: GPP_B_8, Function: 6 - IOM_GPPB_8
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_8__IOM_GPPB_8 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_8, 6)
-// Group: GPP_B, Pad: GPP_B_9, Function: 1 - ISH_GP_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_9__ISH_GP_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_9, 1)
-// Group: GPP_B, Pad: GPP_B_9, Function: 2 - CNV_DEBUG_03
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_9__CNV_DEBUG_03 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_9, 2)
-// Group: GPP_B, Pad: GPP_B_9, Function: 6 - IOM_GPPB_9
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_9__IOM_GPPB_9 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_9, 6)
-// Group: GPP_B, Pad: GPP_B_10, Function: 1 - ISH_GP_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_10__ISH_GP_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_10, 1)
-// Group: GPP_B, Pad: GPP_B_10, Function: 2 - CNV_DEBUG_04
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_10__CNV_DEBUG_04 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_10, 2)
-// Group: GPP_B, Pad: GPP_B_10, Function: 6 - IOM_GPPB_10
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_10__IOM_GPPB_10 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_10, 6)
-// Group: GPP_B, Pad: GPP_B_11, Function: 1 - I2S_MCLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_11__I2S_MCLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_11, 1)
-// Group: GPP_B, Pad: GPP_B_11, Function: 6 - IOM_GPPB_11
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_11__IOM_GPPB_11 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_11, 6)
-// Group: GPP_B, Pad: GPP_B_12, Function: 1 - SLP_S0B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_12__SLP_S0B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_12, 1)
-// Group: GPP_B, Pad: GPP_B_12, Function: 6 - IOM_GPPB_12
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_12__IOM_GPPB_12 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_12, 6)
-// Group: GPP_B, Pad: GPP_B_13, Function: 1 - PLTRSTB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_13__PLTRSTB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_13, 1)
-// Group: GPP_B, Pad: GPP_B_13, Function: 6 - IOM_GPPB_13
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_13__IOM_GPPB_13 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_13, 6)
-// Group: GPP_B, Pad: GPP_B_14, Function: 6 - IOM_GPPB_14
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_14__IOM_GPPB_14 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_14, 6)
-// Group: GPP_B, Pad: GPP_B_15, Function: 1 - ISH_GP_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_15__ISH_GP_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_15, 1)
-// Group: GPP_B, Pad: GPP_B_15, Function: 2 - CNV_DEBUG_05
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_15__CNV_DEBUG_05 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_15, 2)
-// Group: GPP_B, Pad: GPP_B_15, Function: 6 - IOM_GPPB_15
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_15__IOM_GPPB_15 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_15, 6)
-// Group: GPP_B, Pad: GPP_B_16, Function: 1 - ISH_GP_4
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_16__ISH_GP_4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_16, 1)
-// Group: GPP_B, Pad: GPP_B_16, Function: 2 - CNV_DEBUG_06
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_16__CNV_DEBUG_06 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_16, 2)
-// Group: GPP_B, Pad: GPP_B_16, Function: 6 - IOM_GPPB_16
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_16__IOM_GPPB_16 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_16, 6)
-// Group: GPP_B, Pad: GPP_B_17, Function: 1 - ISH_GP_5
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_17__ISH_GP_5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_17, 1)
-// Group: GPP_B, Pad: GPP_B_17, Function: 2 - CNV_DEBUG_07
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_17__CNV_DEBUG_07 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_17, 2)
-// Group: GPP_B, Pad: GPP_B_17, Function: 6 - IOM_GPPB_17
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_17__IOM_GPPB_17 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_17, 6)
-// Group: GPP_B, Pad: GPP_B_18, Function: 1 - PMCALERTB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_18__PMCALERTB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_18, 1)
-// Group: GPP_B, Pad: GPP_B_18, Function: 6 - IOM_GPPB_18
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_18__IOM_GPPB_18 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_18, 6)
-// Group: GPP_B, Pad: GPP_B_19, Function: 1 - FUSA_DIAGTEST_EN
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_19__FUSA_DIAGTEST_EN GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_19, 1)
-// Group: GPP_B, Pad: GPP_B_19, Function: 6 - IOM_GPPB_19
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_19__IOM_GPPB_19 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_19, 6)
-// Group: GPP_B, Pad: GPP_B_20, Function: 1 - FUSA_DIAGTEST_MODE
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_20__FUSA_DIAGTEST_MODE GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_20, 1)
-// Group: GPP_B, Pad: GPP_B_20, Function: 6 - IOM_GPPB_20
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_20__IOM_GPPB_20 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_20, 6)
-// Group: GPP_B, Pad: GPP_B_21, Function: 1 - SML1ALERTB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_21__SML1ALERTB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_21, 1)
-// Group: GPP_B, Pad: GPP_B_21, Function: 2 - PCHHOTB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_21__PCHHOTB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_21, 2)
-// Group: GPP_B, Pad: GPP_B_21, Function: 6 - IOM_GPPB_21
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_B_21__IOM_GPPB_21 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_B_21, 6)
-
-//
-// Pin muxing definitions for Group: DSW.
-//
-
-// Group: DSW, Pad: GPD_0, Function: 1 - BATLOWB
-#define GPIOV2_MTL_PCH_S_MUXING__GPD_0__BATLOWB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPD_0, 1)
-// Group: DSW, Pad: GPD_1, Function: 1 - ACPRESENT
-#define GPIOV2_MTL_PCH_S_MUXING__GPD_1__ACPRESENT GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPD_1, 1)
-// Group: DSW, Pad: GPD_2, Function: 1 - LAN_WAKEB
-#define GPIOV2_MTL_PCH_S_MUXING__GPD_2__LAN_WAKEB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPD_2, 1)
-// Group: DSW, Pad: GPD_3, Function: 1 - PWRBTNB
-#define GPIOV2_MTL_PCH_S_MUXING__GPD_3__PWRBTNB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPD_3, 1)
-// Group: DSW, Pad: GPD_4, Function: 1 - SLP_S3B
-#define GPIOV2_MTL_PCH_S_MUXING__GPD_4__SLP_S3B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPD_4, 1)
-// Group: DSW, Pad: GPD_5, Function: 1 - SLP_S4B
-#define GPIOV2_MTL_PCH_S_MUXING__GPD_5__SLP_S4B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPD_5, 1)
-// Group: DSW, Pad: GPD_6, Function: 1 - SLP_AB
-#define GPIOV2_MTL_PCH_S_MUXING__GPD_6__SLP_AB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPD_6, 1)
-// Group: DSW, Pad: GPD_8, Function: 1 - SUSCLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPD_8__SUSCLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPD_8, 1)
-// Group: DSW, Pad: GPD_9, Function: 1 - SLP_WLANB
-#define GPIOV2_MTL_PCH_S_MUXING__GPD_9__SLP_WLANB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPD_9, 1)
-// Group: DSW, Pad: GPD_10, Function: 1 - SLP_S5B
-#define GPIOV2_MTL_PCH_S_MUXING__GPD_10__SLP_S5B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPD_10, 1)
-// Group: DSW, Pad: GPD_11, Function: 1 - LANPHYPC
-#define GPIOV2_MTL_PCH_S_MUXING__GPD_11__LANPHYPC GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPD_11, 1)
-// Group: DSW, Pad: SLP_LANB, Function: 1 - SLP_LANB
-#define GPIOV2_MTL_PCH_S_MUXING__SLP_LANB__SLP_LANB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_SLP_LANB, 1)
-// Group: DSW, Pad: SLP_SUSB, Function: 1 - SLP_SUSB
-#define GPIOV2_MTL_PCH_S_MUXING__SLP_SUSB__SLP_SUSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_SLP_SUSB, 1)
-// Group: DSW, Pad: WAKEB, Function: 1 - WAKEB
-#define GPIOV2_MTL_PCH_S_MUXING__WAKEB__WAKEB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_WAKEB, 1)
-// Group: DSW, Pad: DSW_SPARE, Function: 1 - DSW_SPARE
-#define GPIOV2_MTL_PCH_S_MUXING__DSW_SPARE__DSW_SPARE GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_DSW_SPARE, 1)
-
-//
-// Pin muxing definitions for Group: SPI0.
-//
-
-// Group: SPI0, Pad: SPI0_IO_2, Function: 1 - SPI0_IO_2
-#define GPIOV2_MTL_PCH_S_MUXING__SPI0_IO_2__SPI0_IO_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_SPI0_IO_2, 1)
-// Group: SPI0, Pad: SPI0_IO_3, Function: 1 - SPI0_IO_3
-#define GPIOV2_MTL_PCH_S_MUXING__SPI0_IO_3__SPI0_IO_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_SPI0_IO_3, 1)
-// Group: SPI0, Pad: SPI0_MOSI_IO_0, Function: 1 - SPI0_MOSI_IO_0
-#define GPIOV2_MTL_PCH_S_MUXING__SPI0_MOSI_IO_0__SPI0_MOSI_IO_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_SPI0_MOSI_IO_0, 1)
-// Group: SPI0, Pad: SPI0_MISO_IO_1, Function: 1 - SPI0_MISO_IO_1
-#define GPIOV2_MTL_PCH_S_MUXING__SPI0_MISO_IO_1__SPI0_MISO_IO_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_SPI0_MISO_IO_1, 1)
-// Group: SPI0, Pad: SPI0_TPM_CSB, Function: 1 - SPI0_TPM_CSB
-#define GPIOV2_MTL_PCH_S_MUXING__SPI0_TPM_CSB__SPI0_TPM_CSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_SPI0_TPM_CSB, 1)
-// Group: SPI0, Pad: SPI0_FLASH_0_CSB, Function: 1 - SPI0_FLASH_0_CSB
-#define GPIOV2_MTL_PCH_S_MUXING__SPI0_FLASH_0_CSB__SPI0_FLASH_0_CSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_SPI0_FLASH_0_CSB, 1)
-// Group: SPI0, Pad: SPI0_FLASH_1_CSB, Function: 1 - SPI0_FLASH_1_CSB
-#define GPIOV2_MTL_PCH_S_MUXING__SPI0_FLASH_1_CSB__SPI0_FLASH_1_CSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_SPI0_FLASH_1_CSB, 1)
-// Group: SPI0, Pad: SPI0_CLK, Function: 1 - SPI0_CLK
-#define GPIOV2_MTL_PCH_S_MUXING__SPI0_CLK__SPI0_CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_SPI0_CLK, 1)
-// Group: SPI0, Pad: SPI0_CLK_LOOPBK, Function: 1 - SPI0_CLK_LOOPBK
-#define GPIOV2_MTL_PCH_S_MUXING__SPI0_CLK_LOOPBK__SPI0_CLK_LOOPBK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_SPI0_CLK_LOOPBK, 1)
-
-//
-// Pin muxing definitions for Group: GPP_C.
-//
-
-// Group: GPP_C, Pad: GPP_C_0, Function: 1 - SMBCLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_0__SMBCLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_0, 1)
-// Group: GPP_C, Pad: GPP_C_0, Function: 6 - IOM_GPPC_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_0__IOM_GPPC_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_0, 6)
-// Group: GPP_C, Pad: GPP_C_1, Function: 1 - SMBDATA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_1__SMBDATA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_1, 1)
-// Group: GPP_C, Pad: GPP_C_1, Function: 6 - IOM_GPPC_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_1__IOM_GPPC_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_1, 6)
-// Group: GPP_C, Pad: GPP_C_2, Function: 1 - SMBALERTB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_2__SMBALERTB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_2, 1)
-// Group: GPP_C, Pad: GPP_C_2, Function: 6 - IOM_GPPC_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_2__IOM_GPPC_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_2, 6)
-// Group: GPP_C, Pad: GPP_C_3, Function: 2 - ISH_UART0_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_3__ISH_UART0_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_3, 2)
-// Group: GPP_C, Pad: GPP_C_3, Function: 2 - SML0BDATA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_3__SML0BDATA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_3, 2)
-// Group: GPP_C, Pad: GPP_C_3, Function: 3 - I2C2_SDA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_3__I2C2_SDA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_3, 3)
-// Group: GPP_C, Pad: GPP_C_3, Function: 6 - IOM_GPPC_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_3__IOM_GPPC_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_3, 6)
-// Group: GPP_C, Pad: GPP_C_4, Function: 2 - ISH_UART0_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_4__ISH_UART0_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_4, 2)
-// Group: GPP_C, Pad: GPP_C_4, Function: 2 - SML0BCLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_4__SML0BCLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_4, 2)
-// Group: GPP_C, Pad: GPP_C_4, Function: 3 - I2C2_SCL
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_4__I2C2_SCL GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_4, 3)
-// Group: GPP_C, Pad: GPP_C_4, Function: 6 - IOM_GPPC_4
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_4__IOM_GPPC_4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_4, 6)
-// Group: GPP_C, Pad: GPP_C_5, Function: 1 - SML0ALERTB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_5__SML0ALERTB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_5, 1)
-// Group: GPP_C, Pad: GPP_C_5, Function: 6 - IOM_GPPC_5
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_5__IOM_GPPC_5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_5, 6)
-// Group: GPP_C, Pad: GPP_C_6, Function: 1 - ISH_I2C2_SDA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_6__ISH_I2C2_SDA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_6, 1)
-// Group: GPP_C, Pad: GPP_C_6, Function: 2 - I2C3_SDA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_6__I2C3_SDA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_6, 2)
-// Group: GPP_C, Pad: GPP_C_6, Function: 6 - IOM_GPPC_6
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_6__IOM_GPPC_6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_6, 6)
-// Group: GPP_C, Pad: GPP_C_7, Function: 1 - ISH_I2C2_SCL
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_7__ISH_I2C2_SCL GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_7, 1)
-// Group: GPP_C, Pad: GPP_C_7, Function: 2 - I2C3_SCL
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_7__I2C3_SCL GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_7, 2)
-// Group: GPP_C, Pad: GPP_C_7, Function: 6 - IOM_GPPC_7
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_7__IOM_GPPC_7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_7, 6)
-// Group: GPP_C, Pad: GPP_C_8, Function: 2 - UART0_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_8__UART0_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_8, 2)
-// Group: GPP_C, Pad: GPP_C_8, Function: 6 - IOM_GPPC_8
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_8__IOM_GPPC_8 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_8, 6)
-// Group: GPP_C, Pad: GPP_C_9, Function: 2 - UART0_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_9__UART0_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_9, 2)
-// Group: GPP_C, Pad: GPP_C_9, Function: 6 - IOM_GPPC_9
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_9__IOM_GPPC_9 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_9, 6)
-// Group: GPP_C, Pad: GPP_C_10, Function: 2 - UART0_RTSB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_10__UART0_RTSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_10, 2)
-// Group: GPP_C, Pad: GPP_C_10, Function: 6 - IOM_GPPC_10
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_10__IOM_GPPC_10 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_10, 6)
-// Group: GPP_C, Pad: GPP_C_11, Function: 2 - UART0_CTSB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_11__UART0_CTSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_11, 2)
-// Group: GPP_C, Pad: GPP_C_11, Function: 6 - IOM_GPPC_11
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_11__IOM_GPPC_11 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_11, 6)
-// Group: GPP_C, Pad: GPP_C_12, Function: 1 - UART1_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_12__UART1_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_12, 1)
-// Group: GPP_C, Pad: GPP_C_12, Function: 2 - ISH_UART1_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_12__ISH_UART1_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_12, 2)
-// Group: GPP_C, Pad: GPP_C_12, Function: 6 - IOM_GPPC_12
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_12__IOM_GPPC_12 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_12, 6)
-// Group: GPP_C, Pad: GPP_C_13, Function: 1 - UART1_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_13__UART1_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_13, 1)
-// Group: GPP_C, Pad: GPP_C_13, Function: 2 - ISH_UART1_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_13__ISH_UART1_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_13, 2)
-// Group: GPP_C, Pad: GPP_C_13, Function: 6 - IOM_GPPC_13
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_13__IOM_GPPC_13 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_13, 6)
-// Group: GPP_C, Pad: GPP_C_14, Function: 1 - UART1_RTSB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_14__UART1_RTSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_14, 1)
-// Group: GPP_C, Pad: GPP_C_14, Function: 2 - ISH_UART1_RTSB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_14__ISH_UART1_RTSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_14, 2)
-// Group: GPP_C, Pad: GPP_C_14, Function: 6 - IOM_GPPC_14
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_14__IOM_GPPC_14 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_14, 6)
-// Group: GPP_C, Pad: GPP_C_15, Function: 1 - UART1_CTSB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_15__UART1_CTSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_15, 1)
-// Group: GPP_C, Pad: GPP_C_15, Function: 2 - ISH_UART1_CTSB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_15__ISH_UART1_CTSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_15, 2)
-// Group: GPP_C, Pad: GPP_C_15, Function: 6 - IOM_GPPC_15
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_15__IOM_GPPC_15 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_15, 6)
-// Group: GPP_C, Pad: GPP_C_16, Function: 1 - USB2_OCB_4
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_16__USB2_OCB_4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_16, 1)
-// Group: GPP_C, Pad: GPP_C_16, Function: 2 - I2C4_SDA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_16__I2C4_SDA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_16, 2)
-// Group: GPP_C, Pad: GPP_C_16, Function: 6 - IOM_GPPC_16
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_16__IOM_GPPC_16 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_16, 6)
-// Group: GPP_C, Pad: GPP_C_17, Function: 1 - USB2_OCB_5
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_17__USB2_OCB_5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_17, 1)
-// Group: GPP_C, Pad: GPP_C_17, Function: 2 - I2C4_SCL
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_17__I2C4_SCL GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_17, 2)
-// Group: GPP_C, Pad: GPP_C_17, Function: 6 - IOM_GPPC_17
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_17__IOM_GPPC_17 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_17, 6)
-// Group: GPP_C, Pad: GPP_C_18, Function: 1 - USB2_OCB_6
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_18__USB2_OCB_6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_18, 1)
-// Group: GPP_C, Pad: GPP_C_18, Function: 2 - I2C5_SDA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_18__I2C5_SDA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_18, 2)
-// Group: GPP_C, Pad: GPP_C_18, Function: 6 - IOM_GPPC_18
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_18__IOM_GPPC_18 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_18, 6)
-// Group: GPP_C, Pad: GPP_C_19, Function: 1 - USB2_OCB_7
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_19__USB2_OCB_7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_19, 1)
-// Group: GPP_C, Pad: GPP_C_19, Function: 2 - I2C5_SCL
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_19__I2C5_SCL GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_19, 2)
-// Group: GPP_C, Pad: GPP_C_19, Function: 6 - IOM_GPPC_19
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_19__IOM_GPPC_19 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_19, 6)
-// Group: GPP_C, Pad: GPP_C_20, Function: 2 - UART2_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_20__UART2_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_20, 2)
-// Group: GPP_C, Pad: GPP_C_20, Function: 3 - CNV_MFUART0_RXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_20__CNV_MFUART0_RXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_20, 3)
-// Group: GPP_C, Pad: GPP_C_20, Function: 6 - IOM_GPPC_20
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_20__IOM_GPPC_20 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_20, 6)
-// Group: GPP_C, Pad: GPP_C_21, Function: 2 - UART2_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_21__UART2_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_21, 2)
-// Group: GPP_C, Pad: GPP_C_21, Function: 3 - CNV_MFUART0_TXD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_21__CNV_MFUART0_TXD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_21, 3)
-// Group: GPP_C, Pad: GPP_C_21, Function: 6 - IOM_GPPC_21
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_21__IOM_GPPC_21 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_21, 6)
-// Group: GPP_C, Pad: GPP_C_22, Function: 1 - UART2_RTSB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_22__UART2_RTSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_22, 1)
-// Group: GPP_C, Pad: GPP_C_22, Function: 3 - CNV_MFUART0_RTS_B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_22__CNV_MFUART0_RTS_B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_22, 3)
-// Group: GPP_C, Pad: GPP_C_22, Function: 6 - IOM_GPPC_22
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_22__IOM_GPPC_22 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_22, 6)
-// Group: GPP_C, Pad: GPP_C_23, Function: 1 - UART2_CTSB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_23__UART2_CTSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_23, 1)
-// Group: GPP_C, Pad: GPP_C_23, Function: 3 - CNV_MFUART0_CTS_B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_23__CNV_MFUART0_CTS_B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_23, 3)
-// Group: GPP_C, Pad: GPP_C_23, Function: 6 - IOM_GPPC_23
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_C_23__IOM_GPPC_23 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_C_23, 6)
-
-//
-// Pin muxing definitions for Group: GPP_H.
-//
-
-// Group: GPP_H, Pad: GPP_H_0, Function: 6 - IOM_GPPH_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_0__IOM_GPPH_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_0, 6)
-// Group: GPP_H, Pad: GPP_H_1, Function: 1 - SRCCLKREQB_8
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_1__SRCCLKREQB_8 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_1, 1)
-// Group: GPP_H, Pad: GPP_H_1, Function: 6 - IOM_GPPH_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_1__IOM_GPPH_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_1, 6)
-// Group: GPP_H, Pad: GPP_H_2, Function: 1 - SRCCLKREQB_9
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_2__SRCCLKREQB_9 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_2, 1)
-// Group: GPP_H, Pad: GPP_H_2, Function: 6 - IOM_GPPH_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_2__IOM_GPPH_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_2, 6)
-// Group: GPP_H, Pad: GPP_H_3, Function: 1 - SRCCLKREQB_10
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_3__SRCCLKREQB_10 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_3, 1)
-// Group: GPP_H, Pad: GPP_H_3, Function: 6 - IOM_GPPH_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_3__IOM_GPPH_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_3, 6)
-// Group: GPP_H, Pad: GPP_H_4, Function: 1 - SRCCLKREQB_11
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_4__SRCCLKREQB_11 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_4, 1)
-// Group: GPP_H, Pad: GPP_H_4, Function: 6 - IOM_GPPH_4
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_4__IOM_GPPH_4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_4, 6)
-// Group: GPP_H, Pad: GPP_H_5, Function: 1 - USB2_OCB_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_5__USB2_OCB_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_5, 1)
-// Group: GPP_H, Pad: GPP_H_5, Function: 6 - IOM_GPPH_5
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_5__IOM_GPPH_5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_5, 6)
-// Group: GPP_H, Pad: GPP_H_6, Function: 1 - USB2_OCB_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_6__USB2_OCB_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_6, 1)
-// Group: GPP_H, Pad: GPP_H_6, Function: 6 - IOM_GPPH_6
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_6__IOM_GPPH_6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_6, 6)
-// Group: GPP_H, Pad: GPP_H_7, Function: 1 - USB2_OCB_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_7__USB2_OCB_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_7, 1)
-// Group: GPP_H, Pad: GPP_H_7, Function: 2 - GMII_MDC_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_7__GMII_MDC_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_7, 2)
-// Group: GPP_H, Pad: GPP_H_7, Function: 6 - IOM_GPPH_7
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_7__IOM_GPPH_7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_7, 6)
-// Group: GPP_H, Pad: GPP_H_8, Function: 1 - USB2_OCB_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_8__USB2_OCB_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_8, 1)
-// Group: GPP_H, Pad: GPP_H_8, Function: 2 - GMII_MDIO_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_8__GMII_MDIO_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_8, 2)
-// Group: GPP_H, Pad: GPP_H_8, Function: 6 - IOM_GPPH_8
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_8__IOM_GPPH_8 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_8, 6)
-// Group: GPP_H, Pad: GPP_H_9, Function: 1 - SML2CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_9__SML2CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_9, 1)
-// Group: GPP_H, Pad: GPP_H_9, Function: 6 - IOM_GPPH_9
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_9__IOM_GPPH_9 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_9, 6)
-// Group: GPP_H, Pad: GPP_H_10, Function: 1 - SML2DATA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_10__SML2DATA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_10, 1)
-// Group: GPP_H, Pad: GPP_H_10, Function: 6 - IOM_GPPH_10
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_10__IOM_GPPH_10 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_10, 6)
-// Group: GPP_H, Pad: GPP_H_11, Function: 1 - SML2ALERTB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_11__SML2ALERTB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_11, 1)
-// Group: GPP_H, Pad: GPP_H_11, Function: 6 - IOM_GPPH_11
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_11__IOM_GPPH_11 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_11, 6)
-// Group: GPP_H, Pad: GPP_H_12, Function: 1 - SML3CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_12__SML3CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_12, 1)
-// Group: GPP_H, Pad: GPP_H_12, Function: 6 - IOM_GPPH_12
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_12__IOM_GPPH_12 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_12, 6)
-// Group: GPP_H, Pad: GPP_H_13, Function: 1 - SML3DATA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_13__SML3DATA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_13, 1)
-// Group: GPP_H, Pad: GPP_H_13, Function: 6 - IOM_GPPH_13
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_13__IOM_GPPH_13 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_13, 6)
-// Group: GPP_H, Pad: GPP_H_14, Function: 1 - SML3ALERTB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_14__SML3ALERTB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_14, 1)
-// Group: GPP_H, Pad: GPP_H_14, Function: 6 - IOM_GPPH_14
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_14__IOM_GPPH_14 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_14, 6)
-// Group: GPP_H, Pad: GPP_H_15, Function: 1 - SML4CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_15__SML4CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_15, 1)
-// Group: GPP_H, Pad: GPP_H_15, Function: 6 - IOM_GPPH_15
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_15__IOM_GPPH_15 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_15, 6)
-// Group: GPP_H, Pad: GPP_H_16, Function: 1 - SML4DATA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_16__SML4DATA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_16, 1)
-// Group: GPP_H, Pad: GPP_H_16, Function: 6 - IOM_GPPH_16
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_16__IOM_GPPH_16 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_16, 6)
-// Group: GPP_H, Pad: GPP_H_17, Function: 1 - SML4ALERTB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_17__SML4ALERTB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_17, 1)
-// Group: GPP_H, Pad: GPP_H_17, Function: 6 - IOM_GPPH_17
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_17__IOM_GPPH_17 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_17, 6)
-// Group: GPP_H, Pad: GPP_H_18, Function: 1 - ISH_I2C1_SDA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_18__ISH_I2C1_SDA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_18, 1)
-// Group: GPP_H, Pad: GPP_H_18, Function: 2 - SMIB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_18__SMIB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_18, 2)
-// Group: GPP_H, Pad: GPP_H_18, Function: 6 - IOM_GPPH_18
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_18__IOM_GPPH_18 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_18, 6)
-// Group: GPP_H, Pad: GPP_H_19, Function: 1 - ISH_I2C1_SCL
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_19__ISH_I2C1_SCL GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_19, 1)
-// Group: GPP_H, Pad: GPP_H_19, Function: 2 - NMIB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_19__NMIB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_19, 2)
-// Group: GPP_H, Pad: GPP_H_19, Function: 6 - IOM_GPPH_19
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_H_19__IOM_GPPH_19 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_H_19, 6)
-
-//
-// Pin muxing definitions for Group: vGPIO_3.
-//
-
-// Group: vGPIO_3, Pad: vGPIO_PCIE_80, Function: 1 - CPU_PCIE_LNK_DN_0
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_PCIE_80__CPU_PCIE_LNK_DN_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_PCIE_80, 1)
-// Group: vGPIO_3, Pad: vGPIO_PCIE_81, Function: 1 - CPU_PCIE_LNK_DN_1
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_PCIE_81__CPU_PCIE_LNK_DN_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_PCIE_81, 1)
-// Group: vGPIO_3, Pad: vGPIO_PCIE_82, Function: 1 - CPU_PCIE_LNK_DN_2
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_PCIE_82__CPU_PCIE_LNK_DN_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_PCIE_82, 1)
-// Group: vGPIO_3, Pad: vGPIO_PCIE_83, Function: 1 - CPU_PCIE_LNK_DN_3
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_PCIE_83__CPU_PCIE_LNK_DN_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_PCIE_83, 1)
-
-//
-// Pin muxing definitions for Group: vGPIO_0.
-//
-
-// Group: vGPIO_0, Pad: vGPIO_USB_0, Function: 1 - ESPI_USB_OCB_0
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_USB_0__ESPI_USB_OCB_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_USB_0, 1)
-// Group: vGPIO_0, Pad: vGPIO_USB_1, Function: 1 - ESPI_USB_OCB_1
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_USB_1__ESPI_USB_OCB_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_USB_1, 1)
-// Group: vGPIO_0, Pad: vGPIO_USB_2, Function: 1 - ESPI_USB_OCB_2
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_USB_2__ESPI_USB_OCB_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_USB_2, 1)
-// Group: vGPIO_0, Pad: vGPIO_USB_3, Function: 1 - ESPI_USB_OCB_3
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_USB_3__ESPI_USB_OCB_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_USB_3, 1)
-// Group: vGPIO_0, Pad: vGPIO_USB_8, Function: 1 - USB_CPU_OCB_0
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_USB_8__USB_CPU_OCB_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_USB_8, 1)
-// Group: vGPIO_0, Pad: vGPIO_USB_9, Function: 1 - USB_CPU_OCB_1
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_USB_9__USB_CPU_OCB_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_USB_9, 1)
-// Group: vGPIO_0, Pad: vGPIO_USB_10, Function: 1 - USB_CPU_OCB_2
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_USB_10__USB_CPU_OCB_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_USB_10, 1)
-// Group: vGPIO_0, Pad: vGPIO_USB_11, Function: 1 - USB_CPU_OCB_3
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_USB_11__USB_CPU_OCB_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_USB_11, 1)
-
-//
-// Pin muxing definitions for Group: vGPIO_4.
-//
-
-// Group: vGPIO_4, Pad: vGPIO_ISCLK_0, Function: 1 - ESPI_ISCLK_XTAL_CLKREQ
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_ISCLK_0__ESPI_ISCLK_XTAL_CLKREQ GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_ISCLK_0, 1)
-// Group: vGPIO_4, Pad: vGPIO_ISCLK_1, Function: 1 - ISCLK_ESPI_XTAL_CLKACK
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_ISCLK_1__ISCLK_ESPI_XTAL_CLKACK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_ISCLK_1, 1)
-// Group: vGPIO_4, Pad: vGPIO_SLPC_0, Function: 1 - ME_SLPC_FTPM_ENABLE
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SLPC_0__ME_SLPC_FTPM_ENABLE GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SLPC_0, 1)
-// Group: vGPIO_4, Pad: vGPIO_SLPC_1, Function: 1 - GP_SLPC_DTFUS_CORE_SPITPM_DIS
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SLPC_1__GP_SLPC_DTFUS_CORE_SPITPM_DIS GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SLPC_1, 1)
-// Group: vGPIO_4, Pad: vGPIO_SLPC_2, Function: 1 - GP_SLPC_SPI_STRAP_TOS
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SLPC_2__GP_SLPC_SPI_STRAP_TOS GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SLPC_2, 1)
-// Group: vGPIO_4, Pad: vGPIO_SLPC_3, Function: 1 - GP_SLPC_DTFUS_CORE_SPITPM_DIS_L0
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SLPC_3__GP_SLPC_DTFUS_CORE_SPITPM_DIS_L0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SLPC_3, 1)
-// Group: vGPIO_4, Pad: vGPIO_SLPC_3, Function: 2 - GP_SLPC_DTFUS_CORE_SPITPM_DIS_L1
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SLPC_3__GP_SLPC_DTFUS_CORE_SPITPM_DIS_L1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SLPC_3, 2)
-// Group: vGPIO_4, Pad: vGPIO_SLPC_4, Function: 1 - GP_SLPC_SPI_STRAP_TOS_L0
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SLPC_4__GP_SLPC_SPI_STRAP_TOS_L0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SLPC_4, 1)
-// Group: vGPIO_4, Pad: vGPIO_SLPC_4, Function: 2 - GP_SLPC_SPI_STRAP_TOS_L1
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SLPC_4__GP_SLPC_SPI_STRAP_TOS_L1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SLPC_4, 2)
-// Group: vGPIO_4, Pad: vGPIO_SLPC_5, Function: 1 - LPC_PRR_TS_OVR
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SLPC_5__LPC_PRR_TS_OVR GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SLPC_5, 1)
-// Group: vGPIO_4, Pad: vGPIO_SLPC_6, Function: 1 - ITSS_KU1_SHTDWN
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SLPC_6__ITSS_KU1_SHTDWN GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SLPC_6, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_0, Function: 1 - VWM_SPARE_0
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_0__VWM_SPARE_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_0, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_1, Function: 1 - VWM_SPARE_1
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_1__VWM_SPARE_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_1, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_2, Function: 1 - VWM_SPARE_2
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_2__VWM_SPARE_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_2, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_3, Function: 1 - VWM_SPARE_3
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_3__VWM_SPARE_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_3, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_4, Function: 1 - VWM_SPARE_4
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_4__VWM_SPARE_4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_4, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_5, Function: 1 - VWM_SPARE_5
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_5__VWM_SPARE_5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_5, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_6, Function: 1 - VWM_SPARE_6
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_6__VWM_SPARE_6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_6, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_7, Function: 1 - VWM_SPARE_7
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_7__VWM_SPARE_7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_7, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_8, Function: 1 - VWM_SPARE_8
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_8__VWM_SPARE_8 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_8, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_9, Function: 1 - VWM_SPARE_9
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_9__VWM_SPARE_9 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_9, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_10, Function: 1 - VWM_SPARE_10
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_10__VWM_SPARE_10 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_10, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_11, Function: 1 - VWM_SPARE_11
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_11__VWM_SPARE_11 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_11, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_12, Function: 1 - VWM_SPARE_12
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_12__VWM_SPARE_12 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_12, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_13, Function: 1 - VWM_SPARE_13
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_13__VWM_SPARE_13 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_13, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_14, Function: 1 - VWM_SPARE_14
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_14__VWM_SPARE_14 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_14, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_15, Function: 1 - VWM_SPARE_15
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_15__VWM_SPARE_15 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_15, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_16, Function: 1 - VWM_SPARE_16
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_16__VWM_SPARE_16 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_16, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_17, Function: 1 - VWM_SPARE_17
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_17__VWM_SPARE_17 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_17, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_18, Function: 1 - VWM_SPARE_18
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_18__VWM_SPARE_18 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_18, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_19, Function: 1 - VWM_SPARE_19
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_19__VWM_SPARE_19 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_19, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_20, Function: 1 - VWM_SPARE_20
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_20__VWM_SPARE_20 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_20, 1)
-// Group: vGPIO_4, Pad: vGPIO_SPARE_21, Function: 1 - VWM_SPARE_21
-#define GPIOV2_MTL_PCH_S_MUXING__VGPIO_SPARE_21__VWM_SPARE_21 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_VGPIO_SPARE_21, 1)
-
-//
-// Pin muxing definitions for Group: GPP_S.
-//
-
-// Group: GPP_S, Pad: GPP_S_0, Function: 1 - SNDW0_CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_0__SNDW0_CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_0, 1)
-// Group: GPP_S, Pad: GPP_S_0, Function: 3 - RGMII_AUXTS_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_0__RGMII_AUXTS_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_0, 3)
-// Group: GPP_S, Pad: GPP_S_1, Function: 1 - SNDW0_DATA0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_1__SNDW0_DATA0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_1, 1)
-// Group: GPP_S, Pad: GPP_S_1, Function: 3 - RGMII_INT_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_1__RGMII_INT_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_1, 3)
-// Group: GPP_S, Pad: GPP_S_2, Function: 1 - SNDW1_CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_2__SNDW1_CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_2, 1)
-// Group: GPP_S, Pad: GPP_S_2, Function: 5 - DMIC_CLK_A_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_2__DMIC_CLK_A_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_2, 5)
-// Group: GPP_S, Pad: GPP_S_2, Function: 3 - RGMII_RESET_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_2__RGMII_RESET_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_2, 3)
-// Group: GPP_S, Pad: GPP_S_2, Function: 4 - SNDW0_DATA1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_2__SNDW0_DATA1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_2, 4)
-// Group: GPP_S, Pad: GPP_S_3, Function: 1 - SNDW1_DATA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_3__SNDW1_DATA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_3, 1)
-// Group: GPP_S, Pad: GPP_S_3, Function: 5 - DMIC_DATA_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_3__DMIC_DATA_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_3, 5)
-// Group: GPP_S, Pad: GPP_S_3, Function: 3 - RGMII_PPS_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_3__RGMII_PPS_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_3, 3)
-// Group: GPP_S, Pad: GPP_S_3, Function: 4 - SNDW0_DATA2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_3__SNDW0_DATA2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_3, 4)
-// Group: GPP_S, Pad: GPP_S_4, Function: 1 - SNDW2_CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_4__SNDW2_CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_4, 1)
-// Group: GPP_S, Pad: GPP_S_4, Function: 5 - DMIC_CLK_B_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_4__DMIC_CLK_B_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_4, 5)
-// Group: GPP_S, Pad: GPP_S_4, Function: 3 - RGMII_AUXTS_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_4__RGMII_AUXTS_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_4, 3)
-// Group: GPP_S, Pad: GPP_S_4, Function: 4 - SNDW0_DATA3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_4__SNDW0_DATA3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_4, 4)
-// Group: GPP_S, Pad: GPP_S_5, Function: 1 - SNDW2_DATA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_5__SNDW2_DATA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_5, 1)
-// Group: GPP_S, Pad: GPP_S_5, Function: 5 - DMIC_CLK_B_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_5__DMIC_CLK_B_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_5, 5)
-// Group: GPP_S, Pad: GPP_S_5, Function: 3 - RGMII_INT_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_5__RGMII_INT_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_5, 3)
-// Group: GPP_S, Pad: GPP_S_6, Function: 1 - SNDW3_CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_6__SNDW3_CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_6, 1)
-// Group: GPP_S, Pad: GPP_S_6, Function: 5 - DMIC_CLK_A_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_6__DMIC_CLK_A_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_6, 5)
-// Group: GPP_S, Pad: GPP_S_6, Function: 3 - RGMII_RESET_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_6__RGMII_RESET_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_6, 3)
-// Group: GPP_S, Pad: GPP_S_7, Function: 1 - SNDW3_DATA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_7__SNDW3_DATA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_7, 1)
-// Group: GPP_S, Pad: GPP_S_7, Function: 5 - DMIC_DATA_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_7__DMIC_DATA_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_7, 5)
-// Group: GPP_S, Pad: GPP_S_7, Function: 3 - RGMII_PPS_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_S_7__RGMII_PPS_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_S_7, 3)
-
-//
-// Pin muxing definitions for Group: GPP_E.
-//
-
-// Group: GPP_E, Pad: GPP_E_0, Function: 1 - SATAXPCIE_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_0__SATAXPCIE_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_0, 1)
-// Group: GPP_E, Pad: GPP_E_0, Function: 2 - SATAGP_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_0__SATAGP_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_0, 2)
-// Group: GPP_E, Pad: GPP_E_0, Function: 6 - IOM_GPPE_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_0__IOM_GPPE_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_0, 6)
-// Group: GPP_E, Pad: GPP_E_1, Function: 1 - SATAXPCIE_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_1__SATAXPCIE_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_1, 1)
-// Group: GPP_E, Pad: GPP_E_1, Function: 2 - SATAGP_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_1__SATAGP_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_1, 2)
-// Group: GPP_E, Pad: GPP_E_1, Function: 6 - IOM_GPPE_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_1__IOM_GPPE_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_1, 6)
-// Group: GPP_E, Pad: GPP_E_2, Function: 1 - SATAXPCIE_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_2__SATAXPCIE_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_2, 1)
-// Group: GPP_E, Pad: GPP_E_2, Function: 2 - SATAGP_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_2__SATAGP_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_2, 2)
-// Group: GPP_E, Pad: GPP_E_2, Function: 6 - IOM_GPPE_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_2__IOM_GPPE_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_2, 6)
-// Group: GPP_E, Pad: GPP_E_3, Function: 1 - CPU_GP_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_3__CPU_GP_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_3, 1)
-// Group: GPP_E, Pad: GPP_E_3, Function: 6 - IOM_GPPE_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_3__IOM_GPPE_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_3, 6)
-// Group: GPP_E, Pad: GPP_E_4, Function: 1 - SATA_DEVSLP_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_4__SATA_DEVSLP_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_4, 1)
-// Group: GPP_E, Pad: GPP_E_4, Function: 6 - IOM_GPPE_4
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_4__IOM_GPPE_4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_4, 6)
-// Group: GPP_E, Pad: GPP_E_5, Function: 1 - SATA_DEVSLP_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_5__SATA_DEVSLP_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_5, 1)
-// Group: GPP_E, Pad: GPP_E_5, Function: 6 - IOM_GPPE_5
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_5__IOM_GPPE_5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_5, 6)
-// Group: GPP_E, Pad: GPP_E_6, Function: 1 - SATA_DEVSLP_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_6__SATA_DEVSLP_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_6, 1)
-// Group: GPP_E, Pad: GPP_E_6, Function: 6 - IOM_GPPE_6
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_6__IOM_GPPE_6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_6, 6)
-// Group: GPP_E, Pad: GPP_E_7, Function: 1 - CPU_GP_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_7__CPU_GP_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_7, 1)
-// Group: GPP_E, Pad: GPP_E_7, Function: 6 - IOM_GPPE_7
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_7__IOM_GPPE_7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_7, 6)
-// Group: GPP_E, Pad: GPP_E_8, Function: 1 - SATA_LEDB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_8__SATA_LEDB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_8, 1)
-// Group: GPP_E, Pad: GPP_E_8, Function: 6 - IOM_GPPE_8
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_8__IOM_GPPE_8 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_8, 6)
-// Group: GPP_E, Pad: GPP_E_9, Function: 1 - SRCCLKREQB_12
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_9__SRCCLKREQB_12 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_9, 1)
-// Group: GPP_E, Pad: GPP_E_9, Function: 6 - IOM_GPPE_9
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_9__IOM_GPPE_9 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_9, 6)
-// Group: GPP_E, Pad: GPP_E_10, Function: 1 - SRCCLKREQB_13
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_10__SRCCLKREQB_13 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_10, 1)
-// Group: GPP_E, Pad: GPP_E_10, Function: 6 - IOM_GPPE_10
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_10__IOM_GPPE_10 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_10, 6)
-// Group: GPP_E, Pad: GPP_E_11, Function: 1 - ISH_GP_9
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_11__ISH_GP_9 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_11, 1)
-// Group: GPP_E, Pad: GPP_E_11, Function: 6 - IOM_GPPE_11
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_11__IOM_GPPE_11 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_11, 6)
-// Group: GPP_E, Pad: GPP_E_12, Function: 1 - ISH_GP_10
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_12__ISH_GP_10 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_12, 1)
-// Group: GPP_E, Pad: GPP_E_12, Function: 6 - IOM_GPPE_12
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_12__IOM_GPPE_12 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_12, 6)
-// Group: GPP_E, Pad: GPP_E_13, Function: 2 - THC0_SPI1_CSB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_13__THC0_SPI1_CSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_13, 2)
-// Group: GPP_E, Pad: GPP_E_13, Function: 3 - Serial_Blink
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_13__SERIAL_BLINK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_13, 3)
-// Group: GPP_E, Pad: GPP_E_13, Function: 4 - Blink
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_13__BLINK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_13, 4)
-// Group: GPP_E, Pad: GPP_E_13, Function: 6 - IOM_GPPE_13
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_13__IOM_GPPE_13 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_13, 6)
-// Group: GPP_E, Pad: GPP_E_14, Function: 2 - THC0_SPI1_CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_14__THC0_SPI1_CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_14, 2)
-// Group: GPP_E, Pad: GPP_E_14, Function: 3 - Serial_Blink
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_14__SERIAL_BLINK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_14, 3)
-// Group: GPP_E, Pad: GPP_E_14, Function: 4 - Blink
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_14__BLINK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_14, 4)
-// Group: GPP_E, Pad: GPP_E_14, Function: 6 - IOM_GPPE_14
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_14__IOM_GPPE_14 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_14, 6)
-// Group: GPP_E, Pad: GPP_E_15, Function: 2 - THC0_SPI1_IO_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_15__THC0_SPI1_IO_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_15, 2)
-// Group: GPP_E, Pad: GPP_E_15, Function: 3 - Serial_Blink
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_15__SERIAL_BLINK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_15, 3)
-// Group: GPP_E, Pad: GPP_E_15, Function: 4 - Blink
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_15__BLINK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_15, 4)
-// Group: GPP_E, Pad: GPP_E_15, Function: 6 - IOM_GPPE_15
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_15__IOM_GPPE_15 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_15, 6)
-// Group: GPP_E, Pad: GPP_E_16, Function: 2 - THC0_SPI1_IO_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_16__THC0_SPI1_IO_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_16, 2)
-// Group: GPP_E, Pad: GPP_E_16, Function: 3 - Serial_Blink
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_16__SERIAL_BLINK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_16, 3)
-// Group: GPP_E, Pad: GPP_E_16, Function: 4 - Blink
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_16__BLINK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_16, 4)
-// Group: GPP_E, Pad: GPP_E_16, Function: 6 - IOM_GPPE_16
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_16__IOM_GPPE_16 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_16, 6)
-// Group: GPP_E, Pad: GPP_E_17, Function: 2 - THC0_SPI1_IO_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_17__THC0_SPI1_IO_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_17, 2)
-// Group: GPP_E, Pad: GPP_E_17, Function: 6 - IOM_GPPE_17
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_17__IOM_GPPE_17 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_17, 6)
-// Group: GPP_E, Pad: GPP_E_18, Function: 2 - THC0_SPI1_IO_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_18__THC0_SPI1_IO_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_18, 2)
-// Group: GPP_E, Pad: GPP_E_18, Function: 6 - IOM_GPPE_18
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_18__IOM_GPPE_18 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_18, 6)
-// Group: GPP_E, Pad: GPP_E_19, Function: 2 - THC0_SPI1_RSTB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_19__THC0_SPI1_RSTB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_19, 2)
-// Group: GPP_E, Pad: GPP_E_19, Function: 6 - IOM_GPPE_19
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_19__IOM_GPPE_19 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_19, 6)
-// Group: GPP_E, Pad: GPP_E_20, Function: 2 - THC0_SPI1_INTB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_20__THC0_SPI1_INTB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_20, 2)
-// Group: GPP_E, Pad: GPP_E_20, Function: 6 - IOM_GPPE_20
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_20__IOM_GPPE_20 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_20, 6)
-// Group: GPP_E, Pad: GPP_E_21, Function: 2 - ISH_UART0_CTSB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_21__ISH_UART0_CTSB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_21, 2)
-// Group: GPP_E, Pad: GPP_E_21, Function: 2 - SML0BALERTB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_21__SML0BALERTB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_21, 2)
-// Group: GPP_E, Pad: GPP_E_21, Function: 6 - IOM_GPPE_21
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_E_21__IOM_GPPE_21 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_E_21, 6)
-// Group: GPP_E, Pad: SPI1_THC0_CLK_LOOPBK, Function: 1 - SPI1_CLK_LOOPBK
-#define GPIOV2_MTL_PCH_S_MUXING__SPI1_THC0_CLK_LOOPBK__SPI1_CLK_LOOPBK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_SPI1_THC0_CLK_LOOPBK, 1)
-// Group: GPP_E, Pad: SPI1_THC0_CLK_LOOPBK, Function: 2 - THC0_CLK_LOOPBK
-#define GPIOV2_MTL_PCH_S_MUXING__SPI1_THC0_CLK_LOOPBK__THC0_CLK_LOOPBK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_SPI1_THC0_CLK_LOOPBK, 2)
-
-//
-// Pin muxing definitions for Group: GPP_K.
-//
-
-// Group: GPP_K, Pad: GPP_K_0, Function: 1 - GSXDOUT
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_0__GSXDOUT GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_0, 1)
-// Group: GPP_K, Pad: GPP_K_0, Function: 3 - Serial_Blink
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_0__SERIAL_BLINK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_0, 3)
-// Group: GPP_K, Pad: GPP_K_0, Function: 4 - Blink
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_0__BLINK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_0, 4)
-// Group: GPP_K, Pad: GPP_K_0, Function: 6 - IOM_GPPK_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_0__IOM_GPPK_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_0, 6)
-// Group: GPP_K, Pad: GPP_K_1, Function: 1 - GSXSLOAD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_1__GSXSLOAD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_1, 1)
-// Group: GPP_K, Pad: GPP_K_1, Function: 6 - IOM_GPPK_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_1__IOM_GPPK_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_1, 6)
-// Group: GPP_K, Pad: GPP_K_2, Function: 1 - GSXDIN
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_2__GSXDIN GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_2, 1)
-// Group: GPP_K, Pad: GPP_K_2, Function: 6 - IOM_GPPK_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_2__IOM_GPPK_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_2, 6)
-// Group: GPP_K, Pad: GPP_K_3, Function: 1 - GSXSRESETB
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_3__GSXSRESETB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_3, 1)
-// Group: GPP_K, Pad: GPP_K_3, Function: 6 - IOM_GPPK_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_3__IOM_GPPK_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_3, 6)
-// Group: GPP_K, Pad: GPP_K_4, Function: 1 - GSXCLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_4__GSXCLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_4, 1)
-// Group: GPP_K, Pad: GPP_K_4, Function: 6 - IOM_GPPK_4
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_4__IOM_GPPK_4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_4, 6)
-// Group: GPP_K, Pad: GPP_K_5, Function: 1 - ADR_COMPLETE
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_5__ADR_COMPLETE GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_5, 1)
-// Group: GPP_K, Pad: GPP_K_5, Function: 6 - IOM_GPPK_5
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_5__IOM_GPPK_5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_5, 6)
-// Group: GPP_K, Pad: GPP_K_6, Function: 2 - FUSE_SORT_BUMP_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_6__FUSE_SORT_BUMP_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_6, 2)
-// Group: GPP_K, Pad: GPP_K_6, Function: 6 - IOM_GPPK_6
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_6__IOM_GPPK_6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_6, 6)
-// Group: GPP_K, Pad: GPP_K_7, Function: 2 - FUSE_SORT_BUMP_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_7__FUSE_SORT_BUMP_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_7, 2)
-// Group: GPP_K, Pad: GPP_K_7, Function: 6 - IOM_GPPK_7
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_7__IOM_GPPK_7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_7, 6)
-// Group: GPP_K, Pad: GPP_K_8, Function: 1 - CORE_VID_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_8__CORE_VID_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_8, 1)
-// Group: GPP_K, Pad: GPP_K_8, Function: 6 - IOM_GPPK_8
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_8__IOM_GPPK_8 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_8, 6)
-// Group: GPP_K, Pad: GPP_K_9, Function: 1 - CORE_VID_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_9__CORE_VID_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_9, 1)
-// Group: GPP_K, Pad: GPP_K_9, Function: 6 - IOM_GPPK_9
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_9__IOM_GPPK_9 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_9, 6)
-// Group: GPP_K, Pad: GPP_K_10, Function: 2 - FUSE_SORT_BUMP_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_10__FUSE_SORT_BUMP_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_10, 2)
-// Group: GPP_K, Pad: GPP_K_10, Function: 6 - IOM_GPPK_10
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_K_10__IOM_GPPK_10 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_K_10, 6)
-// Group: GPP_K, Pad: MISC_SPARE, Function: 1 - MISC_SPARE
-#define GPIOV2_MTL_PCH_S_MUXING__MISC_SPARE__MISC_SPARE GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_MISC_SPARE, 1)
-// Group: GPP_K, Pad: SYS_RESETB, Function: 1 - SYS_RESETB
-#define GPIOV2_MTL_PCH_S_MUXING__SYS_RESETB__SYS_RESETB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_SYS_RESETB, 1)
-// Group: GPP_K, Pad: MLK_RSTB, Function: 1 - MLK_RSTB
-#define GPIOV2_MTL_PCH_S_MUXING__MLK_RSTB__MLK_RSTB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_MLK_RSTB, 1)
-
-//
-// Pin muxing definitions for Group: GPP_F.
-//
-
-// Group: GPP_F, Pad: GPP_F_0, Function: 1 - SATAXPCIE_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_0__SATAXPCIE_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_0, 1)
-// Group: GPP_F, Pad: GPP_F_0, Function: 2 - SATAGP_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_0__SATAGP_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_0, 2)
-// Group: GPP_F, Pad: GPP_F_0, Function: 3 - VISA2CH1_D0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_0__VISA2CH1_D0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_0, 3)
-// Group: GPP_F, Pad: GPP_F_0, Function: 4 - PTI_TRACE_D00
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_0__PTI_TRACE_D00 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_0, 4)
-// Group: GPP_F, Pad: GPP_F_0, Function: 5 - VISAFUSECH1_D0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_0__VISAFUSECH1_D0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_0, 5)
-// Group: GPP_F, Pad: GPP_F_0, Function: 6 - IOM_GPPF_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_0__IOM_GPPF_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_0, 6)
-// Group: GPP_F, Pad: GPP_F_1, Function: 1 - SATAXPCIE_4
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_1__SATAXPCIE_4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_1, 1)
-// Group: GPP_F, Pad: GPP_F_1, Function: 2 - SATAGP_4
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_1__SATAGP_4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_1, 2)
-// Group: GPP_F, Pad: GPP_F_1, Function: 3 - VISA2CH1_D1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_1__VISA2CH1_D1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_1, 3)
-// Group: GPP_F, Pad: GPP_F_1, Function: 4 - PTI_TRACE_D01
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_1__PTI_TRACE_D01 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_1, 4)
-// Group: GPP_F, Pad: GPP_F_1, Function: 5 - VISAFUSECH1_D1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_1__VISAFUSECH1_D1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_1, 5)
-// Group: GPP_F, Pad: GPP_F_1, Function: 6 - IOM_GPPF_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_1__IOM_GPPF_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_1, 6)
-// Group: GPP_F, Pad: GPP_F_2, Function: 1 - SATAXPCIE_5
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_2__SATAXPCIE_5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_2, 1)
-// Group: GPP_F, Pad: GPP_F_2, Function: 2 - SATAGP_5
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_2__SATAGP_5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_2, 2)
-// Group: GPP_F, Pad: GPP_F_2, Function: 3 - VISA2CH1_D2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_2__VISA2CH1_D2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_2, 3)
-// Group: GPP_F, Pad: GPP_F_2, Function: 4 - PTI_TRACE_D02
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_2__PTI_TRACE_D02 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_2, 4)
-// Group: GPP_F, Pad: GPP_F_2, Function: 5 - VISAFUSECH1_D2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_2__VISAFUSECH1_D2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_2, 5)
-// Group: GPP_F, Pad: GPP_F_2, Function: 6 - IOM_GPPF_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_2__IOM_GPPF_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_2, 6)
-// Group: GPP_F, Pad: GPP_F_3, Function: 1 - SATAXPCIE_6
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_3__SATAXPCIE_6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_3, 1)
-// Group: GPP_F, Pad: GPP_F_3, Function: 2 - SATAGP_6
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_3__SATAGP_6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_3, 2)
-// Group: GPP_F, Pad: GPP_F_3, Function: 3 - VISA2CH1_D3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_3__VISA2CH1_D3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_3, 3)
-// Group: GPP_F, Pad: GPP_F_3, Function: 4 - PTI_TRACE_D03
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_3__PTI_TRACE_D03 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_3, 4)
-// Group: GPP_F, Pad: GPP_F_3, Function: 5 - VISAFUSECH1_D3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_3__VISAFUSECH1_D3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_3, 5)
-// Group: GPP_F, Pad: GPP_F_3, Function: 6 - IOM_GPPF_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_3__IOM_GPPF_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_3, 6)
-// Group: GPP_F, Pad: GPP_F_4, Function: 1 - SATAXPCIE_7
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_4__SATAXPCIE_7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_4, 1)
-// Group: GPP_F, Pad: GPP_F_4, Function: 2 - SATAGP_7
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_4__SATAGP_7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_4, 2)
-// Group: GPP_F, Pad: GPP_F_4, Function: 3 - VISA2CH1_D4
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_4__VISA2CH1_D4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_4, 3)
-// Group: GPP_F, Pad: GPP_F_4, Function: 4 - PTI_TRACE_D04
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_4__PTI_TRACE_D04 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_4, 4)
-// Group: GPP_F, Pad: GPP_F_4, Function: 5 - VISAFUSECH1_D4
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_4__VISAFUSECH1_D4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_4, 5)
-// Group: GPP_F, Pad: GPP_F_4, Function: 6 - IOM_GPPF_4
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_4__IOM_GPPF_4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_4, 6)
-// Group: GPP_F, Pad: GPP_F_5, Function: 1 - SATA_DEVSLP_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_5__SATA_DEVSLP_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_5, 1)
-// Group: GPP_F, Pad: GPP_F_5, Function: 3 - VISA2CH1_D5
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_5__VISA2CH1_D5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_5, 3)
-// Group: GPP_F, Pad: GPP_F_5, Function: 4 - PTI_TRACE_D05
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_5__PTI_TRACE_D05 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_5, 4)
-// Group: GPP_F, Pad: GPP_F_5, Function: 5 - VISAFUSECH1_D5
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_5__VISAFUSECH1_D5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_5, 5)
-// Group: GPP_F, Pad: GPP_F_5, Function: 6 - IOM_GPPF_5
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_5__IOM_GPPF_5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_5, 6)
-// Group: GPP_F, Pad: GPP_F_6, Function: 1 - SATA_DEVSLP_4
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_6__SATA_DEVSLP_4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_6, 1)
-// Group: GPP_F, Pad: GPP_F_6, Function: 3 - VISA2CH1_D6
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_6__VISA2CH1_D6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_6, 3)
-// Group: GPP_F, Pad: GPP_F_6, Function: 4 - PTI_TRACE_D06
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_6__PTI_TRACE_D06 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_6, 4)
-// Group: GPP_F, Pad: GPP_F_6, Function: 5 - VISAFUSECH1_D6
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_6__VISAFUSECH1_D6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_6, 5)
-// Group: GPP_F, Pad: GPP_F_6, Function: 6 - IOM_GPPF_6
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_6__IOM_GPPF_6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_6, 6)
-// Group: GPP_F, Pad: GPP_F_7, Function: 1 - SATA_DEVSLP_5
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_7__SATA_DEVSLP_5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_7, 1)
-// Group: GPP_F, Pad: GPP_F_7, Function: 3 - VISA2CH1_D7
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_7__VISA2CH1_D7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_7, 3)
-// Group: GPP_F, Pad: GPP_F_7, Function: 4 - PTI_TRACE_D07
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_7__PTI_TRACE_D07 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_7, 4)
-// Group: GPP_F, Pad: GPP_F_7, Function: 5 - VISAFUSECH1_D7
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_7__VISAFUSECH1_D7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_7, 5)
-// Group: GPP_F, Pad: GPP_F_7, Function: 6 - IOM_GPPF_7
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_7__IOM_GPPF_7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_7, 6)
-// Group: GPP_F, Pad: GPP_F_8, Function: 1 - SATA_DEVSLP_6
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_8__SATA_DEVSLP_6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_8, 1)
-// Group: GPP_F, Pad: GPP_F_8, Function: 3 - VISA2CH1_CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_8__VISA2CH1_CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_8, 3)
-// Group: GPP_F, Pad: GPP_F_8, Function: 4 - PTI_TRACE_CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_8__PTI_TRACE_CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_8, 4)
-// Group: GPP_F, Pad: GPP_F_8, Function: 5 - VISAFUSECH1_CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_8__VISAFUSECH1_CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_8, 5)
-// Group: GPP_F, Pad: GPP_F_8, Function: 6 - IOM_GPPF_8
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_8__IOM_GPPF_8 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_8, 6)
-// Group: GPP_F, Pad: GPP_F_9, Function: 1 - SATA_DEVSLP_7
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_9__SATA_DEVSLP_7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_9, 1)
-// Group: GPP_F, Pad: GPP_F_9, Function: 3 - VISA2CH2_D0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_9__VISA2CH2_D0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_9, 3)
-// Group: GPP_F, Pad: GPP_F_9, Function: 4 - PTI_TRACE_D08
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_9__PTI_TRACE_D08 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_9, 4)
-// Group: GPP_F, Pad: GPP_F_9, Function: 5 - DIR_ESPI_SMI
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_9__DIR_ESPI_SMI GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_9, 5)
-// Group: GPP_F, Pad: GPP_F_9, Function: 6 - IOM_GPPF_9
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_9__IOM_GPPF_9 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_9, 6)
-// Group: GPP_F, Pad: GPP_F_10, Function: 1 - SATA_SCLOCK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_10__SATA_SCLOCK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_10, 1)
-// Group: GPP_F, Pad: GPP_F_10, Function: 3 - VISA2CH2_D1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_10__VISA2CH2_D1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_10, 3)
-// Group: GPP_F, Pad: GPP_F_10, Function: 4 - PTI_TRACE_D09
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_10__PTI_TRACE_D09 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_10, 4)
-// Group: GPP_F, Pad: GPP_F_10, Function: 5 - DIR_ESPI_NMI
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_10__DIR_ESPI_NMI GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_10, 5)
-// Group: GPP_F, Pad: GPP_F_10, Function: 6 - IOM_GPPF_10
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_10__IOM_GPPF_10 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_10, 6)
-// Group: GPP_F, Pad: GPP_F_11, Function: 1 - SATA_SLOAD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_11__SATA_SLOAD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_11, 1)
-// Group: GPP_F, Pad: GPP_F_11, Function: 3 - VISA2CH2_D2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_11__VISA2CH2_D2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_11, 3)
-// Group: GPP_F, Pad: GPP_F_11, Function: 4 - PTI_TRACE_D10
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_11__PTI_TRACE_D10 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_11, 4)
-// Group: GPP_F, Pad: GPP_F_11, Function: 5 - DIR_ESPI_IRQ
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_11__DIR_ESPI_IRQ GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_11, 5)
-// Group: GPP_F, Pad: GPP_F_11, Function: 6 - IOM_GPPF_11
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_11__IOM_GPPF_11 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_11, 6)
-// Group: GPP_F, Pad: GPP_F_12, Function: 1 - SATA_SDATAOUT1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_12__SATA_SDATAOUT1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_12, 1)
-// Group: GPP_F, Pad: GPP_F_12, Function: 3 - VISA2CH2_D3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_12__VISA2CH2_D3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_12, 3)
-// Group: GPP_F, Pad: GPP_F_12, Function: 4 - PTI_TRACE_D11
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_12__PTI_TRACE_D11 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_12, 4)
-// Group: GPP_F, Pad: GPP_F_12, Function: 5 - DIR_ESPI_WAKE
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_12__DIR_ESPI_WAKE GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_12, 5)
-// Group: GPP_F, Pad: GPP_F_12, Function: 6 - IOM_GPPF_12
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_12__IOM_GPPF_12 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_12, 6)
-// Group: GPP_F, Pad: GPP_F_13, Function: 1 - SATA_SDATAOUT0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_13__SATA_SDATAOUT0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_13, 1)
-// Group: GPP_F, Pad: GPP_F_13, Function: 3 - VISA2CH2_D4
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_13__VISA2CH2_D4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_13, 3)
-// Group: GPP_F, Pad: GPP_F_13, Function: 4 - PTI_TRACE_D12
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_13__PTI_TRACE_D12 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_13, 4)
-// Group: GPP_F, Pad: GPP_F_13, Function: 5 - DIR_ESPI_SCI
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_13__DIR_ESPI_SCI GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_13, 5)
-// Group: GPP_F, Pad: GPP_F_13, Function: 6 - IOM_GPPF_13
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_13__IOM_GPPF_13 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_13, 6)
-// Group: GPP_F, Pad: GPP_F_14, Function: 3 - VISA2CH2_D5
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_14__VISA2CH2_D5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_14, 3)
-// Group: GPP_F, Pad: GPP_F_14, Function: 4 - PTI_TRACE_D13
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_14__PTI_TRACE_D13 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_14, 4)
-// Group: GPP_F, Pad: GPP_F_14, Function: 6 - IOM_GPPF_14
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_14__IOM_GPPF_14 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_14, 6)
-// Group: GPP_F, Pad: GPP_F_15, Function: 3 - VISA2CH2_D6
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_15__VISA2CH2_D6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_15, 3)
-// Group: GPP_F, Pad: GPP_F_15, Function: 4 - PTI_TRACE_D14
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_15__PTI_TRACE_D14 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_15, 4)
-// Group: GPP_F, Pad: GPP_F_15, Function: 6 - IOM_GPPF_15
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_15__IOM_GPPF_15 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_15, 6)
-// Group: GPP_F, Pad: GPP_F_16, Function: 3 - VISA2CH2_D7
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_16__VISA2CH2_D7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_16, 3)
-// Group: GPP_F, Pad: GPP_F_16, Function: 4 - PTI_TRACE_D15
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_16__PTI_TRACE_D15 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_16, 4)
-// Group: GPP_F, Pad: GPP_F_16, Function: 6 - IOM_GPPF_16
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_16__IOM_GPPF_16 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_16, 6)
-// Group: GPP_F, Pad: GPP_F_17, Function: 3 - VISA2CH2_CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_17__VISA2CH2_CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_17, 3)
-// Group: GPP_F, Pad: GPP_F_17, Function: 4 - PTI_TRACE_VLD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_17__PTI_TRACE_VLD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_17, 4)
-// Group: GPP_F, Pad: GPP_F_17, Function: 6 - IOM_GPPF_17
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_17__IOM_GPPF_17 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_17, 6)
-// Group: GPP_F, Pad: GPP_F_18, Function: 6 - IOM_GPPF_18
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_18__IOM_GPPF_18 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_18, 6)
-// Group: GPP_F, Pad: GPP_F_19, Function: 1 - DNX_FORCE_RELOAD
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_19__DNX_FORCE_RELOAD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_19, 1)
-// Group: GPP_F, Pad: GPP_F_19, Function: 6 - IOM_GPPF_19
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_19__IOM_GPPF_19 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_19, 6)
-// Group: GPP_F, Pad: GPP_F_20, Function: 1 - GMII_MDC_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_20__GMII_MDC_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_20, 1)
-// Group: GPP_F, Pad: GPP_F_20, Function: 6 - IOM_GPPF_20
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_20__IOM_GPPF_20 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_20, 6)
-// Group: GPP_F, Pad: GPP_F_21, Function: 1 - GMII_MDIO_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_21__GMII_MDIO_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_21, 1)
-// Group: GPP_F, Pad: GPP_F_21, Function: 6 - IOM_GPPF_21
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_21__IOM_GPPF_21 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_21, 6)
-// Group: GPP_F, Pad: GPP_F_22, Function: 3 - IEH_CORR_ERR0B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_22__IEH_CORR_ERR0B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_22, 3)
-// Group: GPP_F, Pad: GPP_F_22, Function: 6 - IOM_GPPF_22
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_22__IOM_GPPF_22 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_22, 6)
-// Group: GPP_F, Pad: GPP_F_23, Function: 3 - IEH_NONFATAL_ERR1B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_23__IEH_NONFATAL_ERR1B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_23, 3)
-// Group: GPP_F, Pad: GPP_F_23, Function: 6 - IOM_GPPF_23
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_F_23__IOM_GPPF_23 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_F_23, 6)
-
-//
-// Pin muxing definitions for Group: GPP_I.
-//
-
-// Group: GPP_I, Pad: GPP_I_0, Function: 1 - GSPI0_CS1B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_0__GSPI0_CS1B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_0, 1)
-// Group: GPP_I, Pad: GPP_I_0, Function: 6 - IOM_GPPI_0
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_0__IOM_GPPI_0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_0, 6)
-// Group: GPP_I, Pad: GPP_I_1, Function: 1 - GSPI1_CS1B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_1__GSPI1_CS1B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_1, 1)
-// Group: GPP_I, Pad: GPP_I_1, Function: 6 - IOM_GPPI_1
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_1__IOM_GPPI_1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_1, 6)
-// Group: GPP_I, Pad: GPP_I_2, Function: 1 - I2C0_SDA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_2__I2C0_SDA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_2, 1)
-// Group: GPP_I, Pad: GPP_I_2, Function: 2 - I3C0_SDA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_2__I3C0_SDA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_2, 2)
-// Group: GPP_I, Pad: GPP_I_2, Function: 6 - IOM_GPPI_2
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_2__IOM_GPPI_2 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_2, 6)
-// Group: GPP_I, Pad: GPP_I_3, Function: 1 - I2C0_SCL
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_3__I2C0_SCL GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_3, 1)
-// Group: GPP_I, Pad: GPP_I_3, Function: 2 - I3C0_SCL
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_3__I3C0_SCL GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_3, 2)
-// Group: GPP_I, Pad: GPP_I_3, Function: 6 - IOM_GPPI_3
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_3__IOM_GPPI_3 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_3, 6)
-// Group: GPP_I, Pad: GPP_I_4, Function: 1 - I2C1_SDA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_4__I2C1_SDA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_4, 1)
-// Group: GPP_I, Pad: GPP_I_4, Function: 6 - IOM_GPPI_4
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_4__IOM_GPPI_4 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_4, 6)
-// Group: GPP_I, Pad: GPP_I_5, Function: 1 - I2C1_SCL
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_5__I2C1_SCL GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_5, 1)
-// Group: GPP_I, Pad: GPP_I_5, Function: 6 - IOM_GPPI_5
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_5__IOM_GPPI_5 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_5, 6)
-// Group: GPP_I, Pad: GPP_I_6, Function: 1 - GSPI0_CS0B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_6__GSPI0_CS0B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_6, 1)
-// Group: GPP_I, Pad: GPP_I_6, Function: 6 - IOM_GPPI_6
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_6__IOM_GPPI_6 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_6, 6)
-// Group: GPP_I, Pad: GPP_I_7, Function: 1 - GSPI0_CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_7__GSPI0_CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_7, 1)
-// Group: GPP_I, Pad: GPP_I_7, Function: 6 - IOM_GPPI_7
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_7__IOM_GPPI_7 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_7, 6)
-// Group: GPP_I, Pad: GPP_I_8, Function: 1 - GSPI0_MISO
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_8__GSPI0_MISO GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_8, 1)
-// Group: GPP_I, Pad: GPP_I_8, Function: 6 - IOM_GPPI_8
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_8__IOM_GPPI_8 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_8, 6)
-// Group: GPP_I, Pad: GPP_I_9, Function: 1 - GSPI0_MOSI
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_9__GSPI0_MOSI GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_9, 1)
-// Group: GPP_I, Pad: GPP_I_9, Function: 6 - IOM_GPPI_9
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_9__IOM_GPPI_9 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_9, 6)
-// Group: GPP_I, Pad: GPP_I_10, Function: 1 - GSPI1_CS0B
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_10__GSPI1_CS0B GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_10, 1)
-// Group: GPP_I, Pad: GPP_I_10, Function: 6 - IOM_GPPI_10
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_10__IOM_GPPI_10 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_10, 6)
-// Group: GPP_I, Pad: GPP_I_11, Function: 1 - GSPI1_CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_11__GSPI1_CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_11, 1)
-// Group: GPP_I, Pad: GPP_I_11, Function: 2 - NFC_CLK
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_11__NFC_CLK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_11, 2)
-// Group: GPP_I, Pad: GPP_I_11, Function: 6 - IOM_GPPI_11
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_11__IOM_GPPI_11 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_11, 6)
-// Group: GPP_I, Pad: GPP_I_12, Function: 1 - GSPI1_MISO
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_12__GSPI1_MISO GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_12, 1)
-// Group: GPP_I, Pad: GPP_I_12, Function: 2 - NFC_CLKREQ
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_12__NFC_CLKREQ GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_12, 2)
-// Group: GPP_I, Pad: GPP_I_12, Function: 6 - IOM_GPPI_12
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_12__IOM_GPPI_12 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_12, 6)
-// Group: GPP_I, Pad: GPP_I_13, Function: 1 - GSPI1_MOSI
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_13__GSPI1_MOSI GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_13, 1)
-// Group: GPP_I, Pad: GPP_I_13, Function: 6 - IOM_GPPI_13
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_13__IOM_GPPI_13 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_13, 6)
-// Group: GPP_I, Pad: GPP_I_14, Function: 1 - ISH_I2C0_SDA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_14__ISH_I2C0_SDA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_14, 1)
-// Group: GPP_I, Pad: GPP_I_14, Function: 2 - ISH_I3C0_SDA
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_14__ISH_I3C0_SDA GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_14, 2)
-// Group: GPP_I, Pad: GPP_I_14, Function: 6 - IOM_GPPI_14
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_14__IOM_GPPI_14 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_14, 6)
-// Group: GPP_I, Pad: GPP_I_15, Function: 1 - ISH_I2C0_SCL
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_15__ISH_I2C0_SCL GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_15, 1)
-// Group: GPP_I, Pad: GPP_I_15, Function: 2 - ISH_I3C0_SCL
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_15__ISH_I3C0_SCL GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_15, 2)
-// Group: GPP_I, Pad: GPP_I_16, Function: 1 - ISH_GP_11
-#define GPIOV2_MTL_PCH_S_MUXING__GPP_I_16__ISH_GP_11 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GPP_I_16, 1)
-// Group: GPP_I, Pad: GSPI0_CLK_LOOPBK, Function: 1 - GSPI0_CLK_LOOPBK
-#define GPIOV2_MTL_PCH_S_MUXING__GSPI0_CLK_LOOPBK__GSPI0_CLK_LOOPBK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GSPI0_CLK_LOOPBK, 1)
-// Group: GPP_I, Pad: GSPI1_CLK_LOOPBK, Function: 1 - GSPI1_CLK_LOOPBK
-#define GPIOV2_MTL_PCH_S_MUXING__GSPI1_CLK_LOOPBK__GSPI1_CLK_LOOPBK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_GSPI1_CLK_LOOPBK, 1)
-// Group: GPP_I, Pad: ISH_I3C0_CLK_LOOPBK, Function: 1 - ISH_I3C0_CLK_LOOPBK
-#define GPIOV2_MTL_PCH_S_MUXING__ISH_I3C0_CLK_LOOPBK__ISH_I3C0_CLK_LOOPBK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_ISH_I3C0_CLK_LOOPBK, 1)
-// Group: GPP_I, Pad: I3C0_CLK_LOOPBK, Function: 1 - I3C0_CLK_LOOPBK
-#define GPIOV2_MTL_PCH_S_MUXING__I3C0_CLK_LOOPBK__I3C0_CLK_LOOPBK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_I3C0_CLK_LOOPBK, 1)
-
-//
-// Pin muxing definitions for Group: JTAG_CPU.
-//
-
-// Group: JTAG_CPU, Pad: JTAG_TDO, Function: 1 - JTAG_TDO
-#define GPIOV2_MTL_PCH_S_MUXING__JTAG_TDO__JTAG_TDO GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_JTAG_TDO, 1)
-// Group: JTAG_CPU, Pad: JTAGX, Function: 1 - JTAGX
-#define GPIOV2_MTL_PCH_S_MUXING__JTAGX__JTAGX GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_JTAGX, 1)
-// Group: JTAG_CPU, Pad: PRDYB, Function: 1 - PRDYB
-#define GPIOV2_MTL_PCH_S_MUXING__PRDYB__PRDYB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_PRDYB, 1)
-// Group: JTAG_CPU, Pad: PREQB, Function: 1 - PREQB
-#define GPIOV2_MTL_PCH_S_MUXING__PREQB__PREQB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_PREQB, 1)
-// Group: JTAG_CPU, Pad: JTAG_TDI, Function: 1 - JTAG_TDI
-#define GPIOV2_MTL_PCH_S_MUXING__JTAG_TDI__JTAG_TDI GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_JTAG_TDI, 1)
-// Group: JTAG_CPU, Pad: JTAG_TMS, Function: 1 - JTAG_TMS
-#define GPIOV2_MTL_PCH_S_MUXING__JTAG_TMS__JTAG_TMS GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_JTAG_TMS, 1)
-// Group: JTAG_CPU, Pad: JTAG_TCK, Function: 1 - JTAG_TCK
-#define GPIOV2_MTL_PCH_S_MUXING__JTAG_TCK__JTAG_TCK GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_JTAG_TCK, 1)
-// Group: JTAG_CPU, Pad: DBG_PMODE, Function: 1 - DBG_PMODE
-#define GPIOV2_MTL_PCH_S_MUXING__DBG_PMODE__DBG_PMODE GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_DBG_PMODE, 1)
-// Group: JTAG_CPU, Pad: CPU_TRSTB, Function: 1 - CPU_TRSTB
-#define GPIOV2_MTL_PCH_S_MUXING__CPU_TRSTB__CPU_TRSTB GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_CPU_TRSTB, 1)
-// Group: JTAG_CPU, Pad: CPUPWRGD, Function: 1 - CPUPWRGD
-#define GPIOV2_MTL_PCH_S_MUXING__CPUPWRGD__CPUPWRGD GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_CPUPWRGD, 1)
-// Group: JTAG_CPU, Pad: PM_SPARE0, Function: 1 - PM_SPARE0
-#define GPIOV2_MTL_PCH_S_MUXING__PM_SPARE0__PM_SPARE0 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_PM_SPARE0, 1)
-// Group: JTAG_CPU, Pad: PM_SPARE1, Function: 1 - PM_SPARE1
-#define GPIOV2_MTL_PCH_S_MUXING__PM_SPARE1__PM_SPARE1 GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_PM_SPARE1, 1)
-// Group: JTAG_CPU, Pad: CRASHLOG_TRIG_N, Function: 1 - CRASHLOG_TRIG_N
-#define GPIOV2_MTL_PCH_S_MUXING__CRASHLOG_TRIG_N__CRASHLOG_TRIG_N GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_CRASHLOG_TRIG_N, 1)
-// Group: JTAG_CPU, Pad: TRIGGER_IN, Function: 1 - TRIGGER_IN
-#define GPIOV2_MTL_PCH_S_MUXING__TRIGGER_IN__TRIGGER_IN GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_TRIGGER_IN, 1)
-// Group: JTAG_CPU, Pad: TRIGGER_OUT, Function: 1 - TRIGGER_OUT
-#define GPIOV2_MTL_PCH_S_MUXING__TRIGGER_OUT__TRIGGER_OUT GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_TRIGGER_OUT, 1)
-// Group: JTAG_CPU, Pad: FBRK_OUT_N, Function: 1 - FBRK_OUT_N
-#define GPIOV2_MTL_PCH_S_MUXING__FBRK_OUT_N__FBRK_OUT_N GPIOV2_PAD_SET_NATIVE_FUNCTION (GPIOV2_MTL_PCH_S_FBRK_OUT_N, 1)
#endif // _GPIOV2_PINS_MTL_PCH_S_H_
diff --git a/Silicon/ArrowlakePkg/Include/GpioV2PinsMtlSoc.h b/Silicon/ArrowlakePkg/Include/GpioV2PinsMtlSoc.h
index f9225bf6..ceae5e3a 100644
--- a/Silicon/ArrowlakePkg/Include/GpioV2PinsMtlSoc.h
+++ b/Silicon/ArrowlakePkg/Include/GpioV2PinsMtlSoc.h
@@ -19,7 +19,6 @@
// GPIO community indexes in controller
//
// Com 0
-#define MTL_M_GPIO_PAD_COM_IDX_CPU 0
#define MTL_M_GPIO_PAD_COM_IDX_GPP_V 0
#define MTL_M_GPIO_PAD_COM_IDX_GPP_C 0
// Com 1
@@ -28,44 +27,36 @@
// Com 3
#define MTL_M_GPIO_PAD_COM_IDX_GPP_H 2
#define MTL_M_GPIO_PAD_COM_IDX_GPP_F 2
-#define MTL_M_GPIO_PAD_COM_IDX_SPI_SYS 2
-#define MTL_M_GPIO_PAD_COM_IDX_USB_THC 2
// Com 4
#define MTL_M_GPIO_PAD_COM_IDX_GPP_S 3
-#define MTL_M_GPIO_PAD_COM_IDX_JTAG 3
// Com 5
#define MTL_M_GPIO_PAD_COM_IDX_GPP_B 4
#define MTL_M_GPIO_PAD_COM_IDX_GPP_D 4
-#define MTL_M_GPIO_PAD_COM_IDX_VGPIO 4
//
// GPIO group indexes in communities
//
// Com 0
-#define MTL_M_GPIO_PAD_GRP_IDX_CPU 0
-#define MTL_M_GPIO_PAD_GRP_IDX_GPP_V 1
-#define MTL_M_GPIO_PAD_GRP_IDX_GPP_C 2
+#define MTL_M_GPIO_PAD_GRP_IDX_GPP_V 0
+#define MTL_M_GPIO_PAD_GRP_IDX_GPP_C 1
// Com 1
#define MTL_M_GPIO_PAD_GRP_IDX_GPP_A 0
#define MTL_M_GPIO_PAD_GRP_IDX_GPP_E 1
// Com 3
#define MTL_M_GPIO_PAD_GRP_IDX_GPP_H 0
#define MTL_M_GPIO_PAD_GRP_IDX_GPP_F 1
-#define MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS 2
-#define MTL_M_GPIO_PAD_GRP_IDX_USB_THC 3
+
// Com 4
#define MTL_M_GPIO_PAD_GRP_IDX_GPP_S 0
-#define MTL_M_GPIO_PAD_GRP_IDX_JTAG 1
+
// Com 5
#define MTL_M_GPIO_PAD_GRP_IDX_GPP_B 0
#define MTL_M_GPIO_PAD_GRP_IDX_GPP_D 1
-#define MTL_M_GPIO_PAD_GRP_IDX_VGPIO 2
//
// GPIO Group defines
//
// Com 0
-#define GPIOV2_MTL_SOC_M_GROUP_CPU GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_CPU, MTL_M_GPIO_PAD_GRP_IDX_CPU, 0xFF)
#define GPIOV2_MTL_SOC_M_GROUP_V GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_V, MTL_M_GPIO_PAD_GRP_IDX_GPP_V, 0xFF)
#define GPIOV2_MTL_SOC_M_GROUP_C GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_C, MTL_M_GPIO_PAD_GRP_IDX_GPP_C, 0xFF)
// Com 1
@@ -74,26 +65,16 @@
// Com 3
#define GPIOV2_MTL_SOC_M_GROUP_H GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_H, MTL_M_GPIO_PAD_GRP_IDX_GPP_H, 0xFF)
#define GPIOV2_MTL_SOC_M_GROUP_F GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_F, MTL_M_GPIO_PAD_GRP_IDX_GPP_F, 0xFF)
-#define GPIOV2_MTL_SOC_M_GROUP_SPI GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 0xFF)
-#define GPIOV2_MTL_SOC_M_GROUP_USB GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 0xFF)
// Com 4
#define GPIOV2_MTL_SOC_M_GROUP_S GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_S, MTL_M_GPIO_PAD_GRP_IDX_GPP_S, 0xFF)
-#define GPIOV2_MTL_SOC_M_GROUP_MBPB GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 0xFF)
// Com 5
#define GPIOV2_MTL_SOC_M_GROUP_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_B, MTL_M_GPIO_PAD_GRP_IDX_GPP_B, 0xFF)
#define GPIOV2_MTL_SOC_M_GROUP_D GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_D, MTL_M_GPIO_PAD_GRP_IDX_GPP_D, 0xFF)
-#define GPIOV2_MTL_SOC_M_GROUP_VGPIO GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0xFF)
//
// GPIO PAD defines
//
// Com 0
-#define GPIOV2_MTL_SOC_M_CPU_PECI GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_CPU, MTL_M_GPIO_PAD_GRP_IDX_CPU, 0)
-#define GPIOV2_MTL_SOC_M_CPU_RESET_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_CPU, MTL_M_GPIO_PAD_GRP_IDX_CPU, 1)
-#define GPIOV2_MTL_SOC_M_CPU_SOUT GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_CPU, MTL_M_GPIO_PAD_GRP_IDX_CPU, 2)
-#define GPIOV2_MTL_SOC_M_CPU_SCK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_CPU, MTL_M_GPIO_PAD_GRP_IDX_CPU, 3)
-#define GPIOV2_MTL_SOC_M_CPU_ALERT_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_CPU, MTL_M_GPIO_PAD_GRP_IDX_CPU, 4)
-
#define GPIOV2_MTL_SOC_M_GPP_V0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_V, MTL_M_GPIO_PAD_GRP_IDX_GPP_V, 0)
#define GPIOV2_MTL_SOC_M_GPP_V1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_V, MTL_M_GPIO_PAD_GRP_IDX_GPP_V, 1)
#define GPIOV2_MTL_SOC_M_GPP_V2 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_V, MTL_M_GPIO_PAD_GRP_IDX_GPP_V, 2)
@@ -169,7 +150,6 @@
#define GPIOV2_MTL_SOC_M_GPP_A21 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_A, MTL_M_GPIO_PAD_GRP_IDX_GPP_A, 21)
#define GPIOV2_MTL_SOC_M_GPP_A22 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_A, MTL_M_GPIO_PAD_GRP_IDX_GPP_A, 22)
#define GPIOV2_MTL_SOC_M_GPP_A23 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_A, MTL_M_GPIO_PAD_GRP_IDX_GPP_A, 23)
-#define GPIOV2_MTL_SOC_M_ESPI_CLK_LOOPBK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_A, MTL_M_GPIO_PAD_GRP_IDX_GPP_A, 24)
#define GPIOV2_MTL_SOC_M_GPP_E0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_E, MTL_M_GPIO_PAD_GRP_IDX_GPP_E, 0)
#define GPIOV2_MTL_SOC_M_GPP_E1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_E, MTL_M_GPIO_PAD_GRP_IDX_GPP_E, 1)
@@ -195,7 +175,6 @@
#define GPIOV2_MTL_SOC_M_GPP_E21 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_E, MTL_M_GPIO_PAD_GRP_IDX_GPP_E, 21)
#define GPIOV2_MTL_SOC_M_GPP_E22 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_E, MTL_M_GPIO_PAD_GRP_IDX_GPP_E, 22)
#define GPIOV2_MTL_SOC_M_GPP_E23 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_E, MTL_M_GPIO_PAD_GRP_IDX_GPP_E, 23)
-#define GPIOV2_MTL_SOC_M_THC0_GPSI0_CLK_LOOPBK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_E, MTL_M_GPIO_PAD_GRP_IDX_GPP_E, 24)
// Com 3
#define GPIOV2_MTL_SOC_M_GPP_H0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_H, MTL_M_GPIO_PAD_GRP_IDX_GPP_H, 0)
@@ -221,9 +200,6 @@
#define GPIOV2_MTL_SOC_M_GPP_H20 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_H, MTL_M_GPIO_PAD_GRP_IDX_GPP_H, 20)
#define GPIOV2_MTL_SOC_M_GPP_H21 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_H, MTL_M_GPIO_PAD_GRP_IDX_GPP_H, 21)
#define GPIOV2_MTL_SOC_M_GPP_H22 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_H, MTL_M_GPIO_PAD_GRP_IDX_GPP_H, 22)
-#define GPIOV2_MTL_SOC_M_GPP_H23 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_H, MTL_M_GPIO_PAD_GRP_IDX_GPP_H, 23)
-#define GPIOV2_MTL_SOC_M_LPI3C1_CLK_LOOPBK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_H, MTL_M_GPIO_PAD_GRP_IDX_GPP_H, 24)
-#define GPIOV2_MTL_SOC_M_LPI3C0_CLK_LOOPBK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_H, MTL_M_GPIO_PAD_GRP_IDX_GPP_H, 25)
#define GPIOV2_MTL_SOC_M_GPP_F0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_F, MTL_M_GPIO_PAD_GRP_IDX_GPP_F, 0)
#define GPIOV2_MTL_SOC_M_GPP_F1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_F, MTL_M_GPIO_PAD_GRP_IDX_GPP_F, 1)
@@ -249,39 +225,6 @@
#define GPIOV2_MTL_SOC_M_GPP_F21 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_F, MTL_M_GPIO_PAD_GRP_IDX_GPP_F, 21)
#define GPIOV2_MTL_SOC_M_GPP_F22 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_F, MTL_M_GPIO_PAD_GRP_IDX_GPP_F, 22)
#define GPIOV2_MTL_SOC_M_GPP_F23 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_F, MTL_M_GPIO_PAD_GRP_IDX_GPP_F, 23)
-#define GPIOV2_MTL_SOC_M_THC1_GSPI1_CLK_LOOPBK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_F, MTL_M_GPIO_PAD_GRP_IDX_GPP_F, 24)
-#define GPIOV2_MTL_SOC_M_GSPI0A_CLK_LOOPBK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_F, MTL_M_GPIO_PAD_GRP_IDX_GPP_F, 25)
-
-#define GPIOV2_MTL_SOC_M_SPI0_IO2 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 0)
-#define GPIOV2_MTL_SOC_M_SPI0_IO3 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 1)
-#define GPIOV2_MTL_SOC_M_SPI0_MOSI_IO_0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 2)
-#define GPIOV2_MTL_SOC_M_SPI0_MISO_IO_0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 3)
-#define GPIOV2_MTL_SOC_M_SPI0_TPM_CS_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 4)
-#define GPIOV2_MTL_SOC_M_SPI0_FLASH_0_CS_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 5)
-#define GPIOV2_MTL_SOC_M_SPI0_FLASH_1_CS_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 6)
-#define GPIOV2_MTL_SOC_M_SPI0_CLK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 7)
-#define GPIOV2_MTL_SOC_M_BKLTEN GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 8)
-#define GPIOV2_MTL_SOC_M_BKLTCTL GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 9)
-#define GPIOV2_MTL_SOC_M_VDDEN GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 10)
-#define GPIOV2_MTL_SOC_M_SYS_PWROK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 11)
-#define GPIOV2_MTL_SOC_M_SYS_RESET_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 12)
-#define GPIOV2_MTL_SOC_M_MLK_RST_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 13)
-#define GPIOV2_MTL_SOC_M_SPI0_CLK_LOOPBK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_SPI_SYS, MTL_M_GPIO_PAD_GRP_IDX_SPI_SYS, 14)
-
-#define GPIOV2_MTL_SOC_M_USB_0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 0)
-#define GPIOV2_MTL_SOC_M_USB_1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 1)
-#define GPIOV2_MTL_SOC_M_USB_2 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 2)
-#define GPIOV2_MTL_SOC_M_USB_3 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 3)
-#define GPIOV2_MTL_SOC_M_USB_4 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 4)
-#define GPIOV2_MTL_SOC_M_USB_5 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 5)
-#define GPIOV2_MTL_SOC_M_USB_6 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 6)
-#define GPIOV2_MTL_SOC_M_USB_7 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 7)
-#define GPIOV2_MTL_SOC_M_TS_0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 8)
-#define GPIOV2_MTL_SOC_M_TS_1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 9)
-#define GPIOV2_MTL_SOC_M_THC_0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 10)
-#define GPIOV2_MTL_SOC_M_THC_1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 11)
-#define GPIOV2_MTL_SOC_M_THC_2 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 12)
-#define GPIOV2_MTL_SOC_M_THC_3 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_USB_THC, MTL_M_GPIO_PAD_GRP_IDX_USB_THC, 13)
// Com 4
#define GPIOV2_MTL_SOC_M_GPP_S0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_S, MTL_M_GPIO_PAD_GRP_IDX_GPP_S, 0)
@@ -293,19 +236,6 @@
#define GPIOV2_MTL_SOC_M_GPP_S6 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_S, MTL_M_GPIO_PAD_GRP_IDX_GPP_S, 6)
#define GPIOV2_MTL_SOC_M_GPP_S7 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_S, MTL_M_GPIO_PAD_GRP_IDX_GPP_S, 7)
-#define GPIOV2_MTL_SOC_M_MBPB0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 0)
-#define GPIOV2_MTL_SOC_M_MBPB1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 1)
-#define GPIOV2_MTL_SOC_M_MBPB2 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 2)
-#define GPIOV2_MTL_SOC_M_MBPB3 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 3)
-#define GPIOV2_MTL_SOC_M_JTAG_TDO GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 4)
-#define GPIOV2_MTL_SOC_M_PRDY_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 5)
-#define GPIOV2_MTL_SOC_M_PREQ_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 6)
-#define GPIOV2_MTL_SOC_M_JTAG_TDI GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 7)
-#define GPIOV2_MTL_SOC_M_JTAG_TMS GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 8)
-#define GPIOV2_MTL_SOC_M_JTAG_TCK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 9)
-#define GPIOV2_MTL_SOC_M_DBG_PMODE GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 10)
-#define GPIOV2_MTL_SOC_M_JTAG_TRST_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_JTAG, MTL_M_GPIO_PAD_GRP_IDX_JTAG, 11)
-
// Com 5
#define GPIOV2_MTL_SOC_M_GPP_B0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_B, MTL_M_GPIO_PAD_GRP_IDX_GPP_B, 0)
#define GPIOV2_MTL_SOC_M_GPP_B1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_B, MTL_M_GPIO_PAD_GRP_IDX_GPP_B, 1)
@@ -331,7 +261,6 @@
#define GPIOV2_MTL_SOC_M_GPP_B21 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_B, MTL_M_GPIO_PAD_GRP_IDX_GPP_B, 21)
#define GPIOV2_MTL_SOC_M_GPP_B22 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_B, MTL_M_GPIO_PAD_GRP_IDX_GPP_B, 22)
#define GPIOV2_MTL_SOC_M_GPP_B23 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_B, MTL_M_GPIO_PAD_GRP_IDX_GPP_B, 23)
-#define GPIOV2_MTL_SOC_M_ISHI3C0_CLK_LOOPBK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_B, MTL_M_GPIO_PAD_GRP_IDX_GPP_B, 24)
#define GPIOV2_MTL_SOC_M_GPP_D0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_D, MTL_M_GPIO_PAD_GRP_IDX_GPP_D, 0)
#define GPIOV2_MTL_SOC_M_GPP_D1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_D, MTL_M_GPIO_PAD_GRP_IDX_GPP_D, 1)
@@ -357,86 +286,28 @@
#define GPIOV2_MTL_SOC_M_GPP_D21 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_D, MTL_M_GPIO_PAD_GRP_IDX_GPP_D, 21)
#define GPIOV2_MTL_SOC_M_GPP_D22 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_D, MTL_M_GPIO_PAD_GRP_IDX_GPP_D, 22)
#define GPIOV2_MTL_SOC_M_GPP_D23 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_D, MTL_M_GPIO_PAD_GRP_IDX_GPP_D, 23)
-#define GPIOV2_MTL_SOC_M_BOOTHALT_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_GPP_D, MTL_M_GPIO_PAD_GRP_IDX_GPP_D, 24)
-#define GPIOV2_MTL_SOC_M_VGPIO0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x00)
-#define GPIOV2_MTL_SOC_M_VGPIO4 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x01)
-#define GPIOV2_MTL_SOC_M_VGPIO5 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x02)
-#define GPIOV2_MTL_SOC_M_VGPIO6 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x03)
-#define GPIOV2_MTL_SOC_M_VGPIO7 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x04)
-#define GPIOV2_MTL_SOC_M_VGPIO8 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x05)
-#define GPIOV2_MTL_SOC_M_VGPIO9 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x06)
-#define GPIOV2_MTL_SOC_M_VGPIO10 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x07)
-#define GPIOV2_MTL_SOC_M_VGPIO11 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x08)
-#define GPIOV2_MTL_SOC_M_VGPIO12 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x09)
-#define GPIOV2_MTL_SOC_M_VGPIO13 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x0A)
-#define GPIOV2_MTL_SOC_M_VGPIO18 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x0B)
-#define GPIOV2_MTL_SOC_M_VGPIO19 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x0C)
-#define GPIOV2_MTL_SOC_M_VGPIO20 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x0D)
-#define GPIOV2_MTL_SOC_M_VGPIO21 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x0E)
-#define GPIOV2_MTL_SOC_M_VGPIO22 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x0F)
-#define GPIOV2_MTL_SOC_M_VGPIO23 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x10)
-#define GPIOV2_MTL_SOC_M_VGPIO24 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x11)
-#define GPIOV2_MTL_SOC_M_VGPIO25 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x12)
-#define GPIOV2_MTL_SOC_M_VGPIO30 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x13)
-#define GPIOV2_MTL_SOC_M_VGPIO31 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x14)
-#define GPIOV2_MTL_SOC_M_VGPIO32 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x15)
-#define GPIOV2_MTL_SOC_M_VGPIO33 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x16)
-#define GPIOV2_MTL_SOC_M_VGPIO34 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x17)
-#define GPIOV2_MTL_SOC_M_VGPIO35 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x18)
-#define GPIOV2_MTL_SOC_M_VGPIO36 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x19)
-#define GPIOV2_MTL_SOC_M_VGPIO37 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x1A)
-#define GPIOV2_MTL_SOC_M_VGPIO40 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x1B)
-#define GPIOV2_MTL_SOC_M_VGPIO41 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x1C)
-#define GPIOV2_MTL_SOC_M_VGPIO42 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x1D)
-#define GPIOV2_MTL_SOC_M_VGPIO43 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x1E)
-#define GPIOV2_MTL_SOC_M_VGPIO44 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x1F)
-#define GPIOV2_MTL_SOC_M_VGPIO45 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x20)
-#define GPIOV2_MTL_SOC_M_VGPIO46 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x21)
-#define GPIOV2_MTL_SOC_M_VGPIO47 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_M_CHIPSET_ID, 0, MTL_M_GPIO_PAD_COM_IDX_VGPIO, MTL_M_GPIO_PAD_GRP_IDX_VGPIO, 0x22)
// Com 0
-#define MTL_S_GPIO_PAD_COM_IDX_GPP_A 0
-#define MTL_S_GPIO_PAD_COM_IDX_VGPIO_0 0
-#define MTL_S_GPIO_PAD_COM_IDX_GPP_C 0
-// Com 1
-#define MTL_S_GPIO_PAD_COM_IDX_GPP_B 1
-#define MTL_S_GPIO_PAD_COM_IDX_VGPIO_3 1
-#define MTL_S_GPIO_PAD_COM_IDX_GPP_D 1
-// Com 2
-// Com 3
-#define MTL_S_GPIO_PAD_COM_IDX_JTAG 2
-#define MTL_S_GPIO_PAD_COM_IDX_VGPIO_4 2
+#define MTL_S_GPIO_PAD_COM_IDX_GPP_A 0
+#define MTL_S_GPIO_PAD_GRP_IDX_GPP_A 0
-// Com 0
-#define MTL_S_GPIO_PAD_GRP_IDX_GPP_A 0
-#define MTL_S_GPIO_PAD_GRP_IDX_VGPIO_0 1
-#define MTL_S_GPIO_PAD_GRP_IDX_GPP_C 2
// Com 1
-#define MTL_S_GPIO_PAD_GRP_IDX_GPP_B 0
-#define MTL_S_GPIO_PAD_GRP_IDX_VGPIO_3 1
-#define MTL_S_GPIO_PAD_GRP_IDX_GPP_D 2
-// Com 2
-// Com 3
-#define MTL_S_GPIO_PAD_GRP_IDX_JTAG 0
-#define MTL_S_GPIO_PAD_GRP_IDX_VGPIO_4 1
+#define MTL_S_GPIO_PAD_COM_IDX_GPP_B 1
+#define MTL_S_GPIO_PAD_GRP_IDX_GPP_B 0
+#define MTL_S_GPIO_PAD_COM_IDX_GPP_D 1
+#define MTL_S_GPIO_PAD_GRP_IDX_GPP_D 1
+
//
// GPIO Group defines
//
// Com 0
#define GPIOV2_MTL_SOC_S_GROUP_A GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_A, MTL_S_GPIO_PAD_GRP_IDX_GPP_A, 0xFF)
-#define GPIOV2_MTL_SOC_S_GROUP_VGPIO0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_0, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_0, 0xFF)
-#define GPIOV2_MTL_SOC_S_GROUP_C GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 0xFF)
// Com 1
#define GPIOV2_MTL_SOC_S_GROUP_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_B, MTL_S_GPIO_PAD_GRP_IDX_GPP_B, 0xFF)
-#define GPIOV2_MTL_SOC_S_GROUP_VGPIO3 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_3, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_3, 0xFF)
#define GPIOV2_MTL_SOC_S_GROUP_D GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_D, MTL_S_GPIO_PAD_GRP_IDX_GPP_D, 0xFF)
-// Com 3
-#define GPIOV2_MTL_SOC_S_GROUP_JTAG GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 0xFF)
-#define GPIOV2_MTL_SOC_S_GROUP_VGPIO4 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_4, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_4, 0xFF)
-
//
// MTL SoC-S GPIO pins
@@ -466,46 +337,6 @@
#define GPIOV2_MTL_SOC_S_GPP_A21 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_A, MTL_S_GPIO_PAD_GRP_IDX_GPP_A, 21)
#define GPIOV2_MTL_SOC_S_GPP_A22 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_A, MTL_S_GPIO_PAD_GRP_IDX_GPP_A, 22)
#define GPIOV2_MTL_SOC_S_GPP_A23 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_A, MTL_S_GPIO_PAD_GRP_IDX_GPP_A, 23)
-#define GPIOV2_MTL_SOC_S_RTCCLKIN GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_A, MTL_S_GPIO_PAD_GRP_IDX_GPP_A, 24)
-#define GPIOV2_MTL_SOC_S_RESET_SYNC_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_A, MTL_S_GPIO_PAD_GRP_IDX_GPP_A, 25)
-#define GPIOV2_MTL_SOC_S_PCH_PWROK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_A, MTL_S_GPIO_PAD_GRP_IDX_GPP_A, 26)
-#define GPIOV2_MTL_SOC_S_ESPI_CLK_LOOPBACK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_A, MTL_S_GPIO_PAD_GRP_IDX_GPP_A, 27)
-
-#define GPIOV2_MTL_SOC_S_VGPIO_LPC_0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_0, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_0, 0)
-#define GPIOV2_MTL_SOC_S_VGPIO_LPC_1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_0, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_0, 1)
-#define GPIOV2_MTL_SOC_S_VGPIO_LPC_2 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_0, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_0, 2)
-#define GPIOV2_MTL_SOC_S_VGPIO_LPC_3 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_0, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_0, 3)
-#define GPIOV2_MTL_SOC_S_VGPIO_LPC_4 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_0, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_0, 4)
-#define GPIOV2_MTL_SOC_S_VGPIO_EC_SCI GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_0, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_0, 5)
-#define GPIOV2_MTL_SOC_S_VGPIO_EC_SCI1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_0, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_0, 6)
-
-#define GPIOV2_MTL_SOC_S_GPP_C0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 0)
-#define GPIOV2_MTL_SOC_S_GPP_C1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 1)
-#define GPIOV2_MTL_SOC_S_GPP_C2 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 2)
-#define GPIOV2_MTL_SOC_S_GPP_C3 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 3)
-#define GPIOV2_MTL_SOC_S_GPP_C4 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 4)
-#define GPIOV2_MTL_SOC_S_GPP_C5 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 5)
-#define GPIOV2_MTL_SOC_S_GPP_C6 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 6)
-#define GPIOV2_MTL_SOC_S_GPP_C7 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 7)
-#define GPIOV2_MTL_SOC_S_GPP_C8 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 8)
-#define GPIOV2_MTL_SOC_S_GPP_C9 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 9)
-#define GPIOV2_MTL_SOC_S_GPP_C10 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 10)
-#define GPIOV2_MTL_SOC_S_GPP_C11 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 11)
-#define GPIOV2_MTL_SOC_S_GPP_C12 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 12)
-#define GPIOV2_MTL_SOC_S_GPP_C13 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 13)
-#define GPIOV2_MTL_SOC_S_GPP_C14 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 14)
-#define GPIOV2_MTL_SOC_S_GPP_C15 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 15)
-#define GPIOV2_MTL_SOC_S_GPP_C16 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 16)
-#define GPIOV2_MTL_SOC_S_GPP_C17 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 17)
-#define GPIOV2_MTL_SOC_S_GPP_C18 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 18)
-#define GPIOV2_MTL_SOC_S_GPP_C19 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 19)
-#define GPIOV2_MTL_SOC_S_GPP_C20 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 20)
-#define GPIOV2_MTL_SOC_S_GPP_C21 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 21)
-#define GPIOV2_MTL_SOC_S_GPP_C22 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 22)
-#define GPIOV2_MTL_SOC_S_GPP_C23 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 23)
-#define GPIOV2_MTL_SOC_S_GPP_C24 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 24)
-#define GPIOV2_MTL_SOC_S_GPP_C25 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 25)
-#define GPIOV2_MTL_SOC_S_GPP_C26 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_C, MTL_S_GPIO_PAD_GRP_IDX_GPP_C, 26)
// COM1
#define GPIOV2_MTL_SOC_S_GPP_B0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_B, MTL_S_GPIO_PAD_GRP_IDX_GPP_B, 0)
@@ -529,14 +360,6 @@
#define GPIOV2_MTL_SOC_S_GPP_B18 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_B, MTL_S_GPIO_PAD_GRP_IDX_GPP_B, 18)
#define GPIOV2_MTL_SOC_S_GPP_B19 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_B, MTL_S_GPIO_PAD_GRP_IDX_GPP_B, 19)
-#define GPIOV2_MTL_SOC_S_VGPIO_USB_0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_3, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_3, 0)
-#define GPIOV2_MTL_SOC_S_VGPIO_USB_1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_3, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_3, 1)
-#define GPIOV2_MTL_SOC_S_VGPIO_USB_2 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_3, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_3, 2)
-#define GPIOV2_MTL_SOC_S_VGPIO_USB_3 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_3, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_3, 3)
-#define GPIOV2_MTL_SOC_S_VGPIO_PCIE_80 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_3, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_3, 4)
-#define GPIOV2_MTL_SOC_S_VGPIO_TS_0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_3, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_3, 5)
-#define GPIOV2_MTL_SOC_S_VGPIO_TS_1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_3, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_3, 6)
-
#define GPIOV2_MTL_SOC_S_GPP_D0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_D, MTL_S_GPIO_PAD_GRP_IDX_GPP_D, 0)
#define GPIOV2_MTL_SOC_S_GPP_D1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_D, MTL_S_GPIO_PAD_GRP_IDX_GPP_D, 1)
#define GPIOV2_MTL_SOC_S_GPP_D2 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_D, MTL_S_GPIO_PAD_GRP_IDX_GPP_D, 2)
@@ -562,28 +385,6 @@
#define GPIOV2_MTL_SOC_S_GPP_D22 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_D, MTL_S_GPIO_PAD_GRP_IDX_GPP_D, 22)
#define GPIOV2_MTL_SOC_S_GPP_D23 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_GPP_D, MTL_S_GPIO_PAD_GRP_IDX_GPP_D, 23)
-// COM2
-// COM3
-#define GPIOV2_MTL_SOC_S_PECI GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 0)
-#define GPIOV2_MTL_SOC_S_VIDSOUT GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 1)
-#define GPIOV2_MTL_SOC_S_VIDSCK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 2)
-#define GPIOV2_MTL_SOC_S_VIDALERT_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 3)
-#define GPIOV2_MTL_SOC_S_JTAG_MBPB_0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 4)
-#define GPIOV2_MTL_SOC_S_JTAG_MBPB_1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 5)
-#define GPIOV2_MTL_SOC_S_JTAG_MBPB_2 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 6)
-#define GPIOV2_MTL_SOC_S_JTAG_MBPB_3 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 7)
-#define GPIOV2_MTL_SOC_S_JTAG_TDO GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 8)
-#define GPIOV2_MTL_SOC_S_PRDY_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 9)
-#define GPIOV2_MTL_SOC_S_PREQ_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 10)
-#define GPIOV2_MTL_SOC_S_JTAG_TDI GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 11)
-#define GPIOV2_MTL_SOC_S_JTAG_TMS GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 12)
-#define GPIOV2_MTL_SOC_S_JTAG_TCK GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 13)
-#define GPIOV2_MTL_SOC_S_JTAG_PMODE GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 14)
-#define GPIOV2_MTL_SOC_S_JTAG_TRST_B GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_JTAG, MTL_S_GPIO_PAD_GRP_IDX_JTAG, 15)
-
-#define GPIOV2_MTL_SOC_S_VGPIO_ISCLK0 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_4, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_4, 0)
-#define GPIOV2_MTL_SOC_S_VGPIO_ISCLK1 GPIOV2_PAD_ID(0, GPIOV2_MTL_SOC_S_CHIPSET_ID, 0, MTL_S_GPIO_PAD_COM_IDX_VGPIO_4, MTL_S_GPIO_PAD_GRP_IDX_VGPIO_4, 1)
-
//*********************************************************************
// MTL-SOC-S Pins End *
diff --git a/Silicon/ArrowlakePkg/Include/Library/MtlPchGpioTopologyLib.h b/Silicon/ArrowlakePkg/Include/Library/MtlPchGpioTopologyLib.h
deleted file mode 100644
index 3af158cd..00000000
--- a/Silicon/ArrowlakePkg/Include/Library/MtlPchGpioTopologyLib.h
+++ /dev/null
@@ -1,86 +0,0 @@
-
-/** @file
- Header file for common part for Gpio V2 Controller PEI and DXE modules
-
- Copyright (c) 2024, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-#ifndef _GPIOV2_TOPOLOGY_MTL_PCH_H_
-#define _GPIOV2_TOPOLOGY_MTL_PCH_H_
-
-//#include
-#include
-#include
-
-
-/**
-This procedure retrieves number of communities for PCH with index 'PchIndex'
-
-@param[in] PchIndex MTL SOC/PCH index
-
-@retval Number of communities on requested PCH
-**/
-UINT32
-MtlPchGpioGetCommunitiesNum (
- IN UINT32 PchIndex
-);
-
-/**
-This procedure retrieves pointer to array of communities for PCH with index 'PchIndex'
-
-@param[in] PchIndex MTL SOC/PCH index
-
-@retval pointer to array of communities on requested PCH
-**/
-GPIOV2_COMMUNITY*
-MtlPchGpioGetCommunities (
- IN UINT32 PchIndex
-);
-
-GPIOV2_GROUP
-MtlPchGpioGetGroups (
- IN UINT32 CommunityIndex,
- IN UINT32 GroupIndex
-);
-
-/**
- This procedure retrieves number of native signals for LNL SOC
-
- @retval Number of native signals on LNL SOC
-**/
-UINT32
-MtlPchGpioGetNativeSignalsNum (
- VOID
- );
-
-/**
- This procedure retrieves pointer to array of native signals for LNL SOC
-
- @retval pointer to array of native signals on LNL SOC
-**/
-GPIOV2_NATIVE_SIGNAL_DATA *
-MtlPchGpioGetNativeSignals (
- VOID
- );
-
-/**
- This procedure retrieves register offset for given Gpio Pad
- @param[in] GpioPad Gpio Pad. Please refer to GpioPinsYYY.h - where YYY name of the platform (eg. MTL, EBG, ...)
- @param[in] Register Register for which user want to retrieve offset. Please refer to GpioV2Pad.h
- @param[out] RegisterOffset Pointer to a buffer for register offset
- @retval EFI_SUCCESS The function completed successfully
- @retval EFI_INVALID_PARAMETER Invalid group or pad number
-**/
-EFI_STATUS
-MtlPchGpioGetRegOffset (
- IN GPIOV2_PAD GpioPad,
- IN GPIOV2_REGISTER Register,
- OUT UINT32 *RegisterOffset
- );
-
-EFI_STATUS
-MtlPchInstallCommunityAccess (
- OUT P2SB_SIDEBAND_REGISTER_ACCESS *CommunityAccess
-);
-#endif //_GPIOV2_TOPOLOGY_MTL_PCH_H_
diff --git a/Silicon/ArrowlakePkg/Include/Library/MtlPchPcieRpLib.h b/Silicon/ArrowlakePkg/Include/Library/MtlPchPcieRpLib.h
index 146b1c49..09da3827 100644
--- a/Silicon/ArrowlakePkg/Include/Library/MtlPchPcieRpLib.h
+++ b/Silicon/ArrowlakePkg/Include/Library/MtlPchPcieRpLib.h
@@ -9,32 +9,6 @@
#ifndef _MTL_PCH_PCIE_RP_LIB_
#define _MTL_PCH_PCIE_RP_LIB_
-#include
-
-/**
- Translate RpIndex to controller index.
-
- @param[in] RpIndex Root port index
-
- @return ControllerIndex
- @retval 0xFF Failed to lookup controller index.
-**/
-UINT32
-MtlPchRpIndexToControllerIndex (
- IN UINT32 RpIndex
- );
-
-/**
- Get the FID number of the PCIe root port.
-
- @param[in] RpIndex Index of the root port
-
- @return FID number to use when sending SBI msg
-**/
-UINT16
-MtlPchPcieRpGetSbiFid (
- IN UINT32 RpIndex
- );
/**
Get MTL SoC Pcie Root Port Device and Function Number by Root Port physical Number
@@ -47,34 +21,12 @@ MtlPchPcieRpGetSbiFid (
@retval EFI_INVALID_PARAMETER RpNumber is invalid
**/
EFI_STATUS
+EFIAPI
MtlPchGetPcieRpDevFun (
IN UINT32 RpNumber,
OUT UINT16 *RpDev,
OUT UINT16 *RpFun
);
-/**
- This function returns PID according to PCIe controller index
-
- @param[in] ControllerIndex PCIe controller index
-
- @retval P2SB_PID Returns PID for SBI Access
-**/
-P2SB_PID
-MtlPchGetPcieControllerSbiPid (
- IN UINT32 ControllerIndex
- );
-
-/**
- This function returns PID according to Root Port Number
-
- @param[in] RpIndex Root Port Index (0-based)
-
- @retval P2SB_PID Returns PID for SBI Access
-**/
-P2SB_PID
-MtlPchGetRpSbiPid (
- IN UINT32 RpIndex
- );
#endif
\ No newline at end of file
diff --git a/Silicon/ArrowlakePkg/Include/Library/MtlSocGpioTopologyLib.h b/Silicon/ArrowlakePkg/Include/Library/MtlSocGpioTopologyLib.h
deleted file mode 100644
index 618465af..00000000
--- a/Silicon/ArrowlakePkg/Include/Library/MtlSocGpioTopologyLib.h
+++ /dev/null
@@ -1,93 +0,0 @@
-
-/** @file
-Header file for common part for Gpio V2 Controller PEI and DXE modules
-
- Copyright (c) 2024, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-@par Specification Reference:
-**/
-
-#ifndef _GPIOV2_CONTROLLER_INIT_MTL_H_
-#define _GPIOV2_CONTROLLER_INIT_MTL_H_
-
-#include
-#include
-#include
-#include
-#include
-
-
-/**
-This procedure retrieves number of communities for PCH with index 'PchIndex'
-
-@param[in] PchIndex MTL SOC/PCH index
-
-@retval Number of communities on requested PCH
-**/
-UINT32
-MtlSocGpioGetCommunitiesNum(
- IN UINT32 PchIndex
-);
-
-/**
-This procedure retrieves pointer to array of communities for PCH with index 'PchIndex'
-
-@param[in] PchIndex MTL SOC/PCH index
-
-@retval pointer to array of communities on requested PCH
-**/
-GPIOV2_COMMUNITY*
-MtlSocGpioGetCommunities(
- IN UINT32 PchIndex
-);
-
-GPIOV2_COMMUNITY*
-MtlSocGpioGetCommunity (
- IN UINT32 CommunityIndex
-);
-
-GPIOV2_GROUP
-MtlSocGpioGetGroups (
- IN UINT32 CommunityIndex,
- IN UINT32 GroupIndex
-);
-
-EFI_STATUS
-MtlSocGetP2SbController (
- IN OUT P2SB_CONTROLLER *P2SbController
-);
-
-EFI_STATUS
-MtlSocInstallCommunityAccess (
- //IN UINT32 CommunityIndex,
- OUT P2SB_SIDEBAND_REGISTER_ACCESS *CommunityAccess
-);
-
-/* GPIOV2_UNLOCK_GROUP_DATA*
-MtlSocGpioUnlockData (
- IN UINT32 CommunityIndex
-); */
-
-/* P2SB_SIDEBAND_REGISTER_ACCESS
-MtlSocGetCommunityAccess (
- IN UINT32 CommunityIndex
-); */
-
-/**
- This procedure retrieves register offset for given Gpio Pad
-
- @param[in] GpioPad Gpio Pad. Please refer to GpioPinsYYY.h - where YYY name of the platform (eg. MTL, EBG, ...)
- @param[in] Register Register for which user want to retrieve offset. Please refer to GpioV2Pad.h
- @param[out] RegisterOffset Pointer to a buffer for register offset
-
- @retval EFI_SUCCESS The function completed successfully
- @retval EFI_INVALID_PARAMETER Invalid group or pad number
-**/
-EFI_STATUS
-MtlSocGpioGetRegOffset (
- IN GPIOV2_PAD GpioPad,
- IN GPIOV2_REGISTER Register,
- OUT UINT32 *RegisterOffset
- );
-#endif //_GPIOV2_CONTROLLER_INIT_MTL_H_
diff --git a/Silicon/ArrowlakePkg/Include/Library/MtlSocPcieRpLib.h b/Silicon/ArrowlakePkg/Include/Library/MtlSocPcieRpLib.h
index 952d07a0..7fea2863 100644
--- a/Silicon/ArrowlakePkg/Include/Library/MtlSocPcieRpLib.h
+++ b/Silicon/ArrowlakePkg/Include/Library/MtlSocPcieRpLib.h
@@ -9,34 +9,6 @@
#ifndef _MTL_SOC_PCIE_RP_LIB_H_
#define _MTL_SOC_PCIE_RP_LIB_H_
-//#include
-#include
-
-/**
- Translate RpIndex to controller index.
-
- @param[in] RpIndex Root port index
-
- @return ControllerIndex
- @retval 0xFF Failed to lookup controller index.
-**/
-UINT32
-MtlSocRpIndexToControllerIndex (
- IN UINTN RpIndex
- );
-
-/**
- Get the FID number of the PCIe root port.
-
- @param[in] RpIndex Index of the root port
-
- @return FID number to use when sending SBI msg
-**/
-UINT16
-MtlSocPcieRpGetSbiFid (
- IN UINTN RpIndex
- );
-
/**
Get MTL SoC Pcie Root Port Device and Function Number by Root Port physical Number
@@ -48,58 +20,11 @@ MtlSocPcieRpGetSbiFid (
@retval EFI_INVALID_PARAMETER RpNumber is invalid
**/
EFI_STATUS
+EFIAPI
MtlSocGetPcieRpDevFun (
IN UINTN RpNumber,
OUT UINT16 *RpDev,
OUT UINT16 *RpFun
);
-/**
- This function returns PID according to PCIe controller index
-
- @param[in] ControllerIndex PCIe controller index
-
- @retval P2SB_PID Returns PID for SBI Access
-**/
-P2SB_PID
-MtlSocGetPcieControllerSbiPid (
- IN UINT32 ControllerIndex
- );
-
-/**
- This function returns PID according to Root Port Number
-
- @param[in] RpIndex Root Port Index (0-based)
-
- @retval P2SB_PID Returns PID for SBI Access
-**/
-P2SB_PID
-MtlSocGetRpSbiPid (
- IN UINTN RpIndex
- );
-
-/**
- Checks whether RpIndex is located on IOE die.
-
- @param[in] RpIndex Root port index.
-
- @return TRUE if root port is located on IOE die.
-**/
-BOOLEAN
-MtlSocIsRpOnIoeDie (
- IN UINT32 RpIndex
- );
-
-/**
- Checks if root port is decoded by IOC.
-
- @param[in] RpIndex Root port index.
-
- @return TRUE if root port is IOC decoded.
-**/
-BOOLEAN
-MtlSocIsRpIocDecoded (
- IN UINT32 RpIndex
- );
-
#endif
diff --git a/Silicon/ArrowlakePkg/Include/P2SbSidebandAccessLib.h b/Silicon/ArrowlakePkg/Include/P2SbSidebandAccessLib.h
deleted file mode 100644
index 232c515a..00000000
--- a/Silicon/ArrowlakePkg/Include/P2SbSidebandAccessLib.h
+++ /dev/null
@@ -1,359 +0,0 @@
-/** @file
- Header for P2SbSidebandAccessLib
-
- Copyright (c) 2024, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef _P2SB_SIDEBAND_ACCESS_LIB_H_
-#define _P2SB_SIDEBAND_ACCESS_LIB_H_
-
-#include "RegisterAccess.h"
-#include "P2SbController.h"
-#include "PcrDefine.h"
-#include
-
-#define P2SB_REGISTER_ACCESS_INIT {P2SbSidebandRead8, P2SbSidebandWrite8, P2SbSidebandOr8, P2SbSidebandAnd8, P2SbSidebandAndThenOr8, \
- P2SbSidebandRead16, P2SbSidebandWrite16, P2SbSidebandOr16, P2SbSidebandAnd16, P2SbSidebandAndThenOr16,\
- P2SbSidebandRead32, P2SbSidebandWrite32, P2SbSidebandOr32, P2SbSidebandAnd32, P2SbSidebandAndThenOr32}
-
-typedef enum {
- P2SbMemory = 0,
- P2SbPciConfig,
- P2SbPrivateConfig
-} P2SB_REGISTER_SPACE;
-
-typedef enum {
- P2SbMmioAccess = 0,
- P2SbMsgAccess
-} P2SB_SIDEBAND_ACCESS_METHOD;
-
-
-/**
- REGISTER_ACCESS for P2SB device to support access to sideband registers.
- Be sure to keep first member of this structure as REGISTER_ACCESS to allow
- for correct casting between caller who sees this structure as REGISTER_ACCESS
- and calle who will cast it to P2SB_SIDEBAND_REGISTER_ACCESS.
-**/
-typedef struct {
- REGISTER_ACCESS Access;
- P2SB_SIDEBAND_ACCESS_METHOD AccessMethod;
- P2SB_PID P2SbPid;
- UINT16 Fid;
- P2SB_REGISTER_SPACE RegisterSpace;
- BOOLEAN PostedWrites;
- P2SB_CONTROLLER *P2SbCtrl;
- UINT32 Offset;
-} P2SB_SIDEBAND_REGISTER_ACCESS;
-
-/**
- Reads an 8-bit register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
-
- @return The 8-bit register value specified by Offset
-**/
-UINT8
-P2SbSidebandRead8 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset
- );
-
-/**
- Writes an 8-bit register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] Value Value to write to register
-
- @return The 8-bit register value written to register
-**/
-UINT8
-P2SbSidebandWrite8 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT8 Value
- );
-
-/**
- Performs an 8-bit or on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] OrData Data with which register should be OR-ed
-
- @return The 8-bit register value written to register
-**/
-UINT8
-P2SbSidebandOr8 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT8 OrData
- );
-
-/**
- Performs an 8-bit and on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] AndData Data with which register should be AND-ed
-
- @return The 8-bit register value written to register
-**/
-UINT8
-P2SbSidebandAnd8 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT8 AndData
- );
-
-/**
- Performs an 8-bit and then or on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] AndData Data with which register should be AND-ed
- @param[in] OrData Data with which register should be OR-ed
-
- @return The 8-bit register value written to register
-**/
-UINT8
-P2SbSidebandAndThenOr8 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT8 AndData,
- IN UINT8 OrData
- );
-
-/**
- Reads a 16-bit register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
-
- @return The 16-bit register value specified by Offset
-**/
-UINT16
-P2SbSidebandRead16 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset
- );
-
-/**
- Writes a 16-bit register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] Value Value to write to register
-
- @return The 16-bit register value written to register
-**/
-UINT16
-P2SbSidebandWrite16 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT16 Value
- );
-
-/**
- Performs a 16-bit or on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] OrData Data with which register should be OR-ed
-
- @return The 16-bit register value written to register
-**/
-UINT16
-P2SbSidebandOr16 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT16 OrData
- );
-
-/**
- Performs a 16-bit and on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] AndData Data with which register should be AND-ed
-
- @return The 16-bit register value written to register
-**/
-UINT16
-P2SbSidebandAnd16 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT16 AndData
- );
-
-/**
- Performs a 16-bit and then or on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] AndData Data with which register should be AND-ed
- @param[in] OrData Data with which register should be OR-ed
-
- @return The 16-bit register value written to register
-**/
-UINT16
-P2SbSidebandAndThenOr16 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT16 AndData,
- IN UINT16 OrData
- );
-
-/**
- Reads a 32-bit register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
-
- @return The 32-bit register value specified by Offset
-**/
-UINT32
-P2SbSidebandRead32 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset
- );
-
-/**
- Writes a 32-bit register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] Value Value to write to register
-
- @return The 32-bit register value written to register
-**/
-UINT32
-P2SbSidebandWrite32 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT32 Value
- );
-
-/**
- Performs a 32-bit or on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] OrData Data with which register should be OR-ed
-
- @return The 32-bit register value written to register
-**/
-UINT32
-P2SbSidebandOr32 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT32 OrData
- );
-
-/**
- Performs a 32-bit and on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] AndData Data with which register should be AND-ed
-
- @return The 32-bit register value written to register
-**/
-UINT32
-P2SbSidebandAnd32 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT32 AndData
- );
-
-/**
- Performs a 32-bit and then or on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] AndData Data with which register should be AND-ed
- @param[in] OrData Data with which register should be OR-ed
-
- @return The 32-bit register value written to register
-**/
-UINT32
-P2SbSidebandAndThenOr32 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT32 AndData,
- IN UINT32 OrData
- );
-
-/**
- Builds P2SB sideband access.
-
- @param[in] P2SbController Pointer to P2SB controller implementing the sideband
- @param[in] P2SbPid Port id
- @param[in] Fid Function id
- @param[in] RegisterSpace Target register space
- @param[in] AccessMethod Access method
- @param[in] PostedWrites If TRUE writes sent through sideband msg will be posted
- @param[out] P2SbSidebandAccess On output an initialized sideband access descriptor
-
- @retval TRUE Access initialized successfuly
- @retval FALSE Failed to initialize access
-**/
-BOOLEAN
-BuildP2SbSidebandAccess (
- IN P2SB_CONTROLLER *P2sbController,
- IN P2SB_PID P2SbPid,
- IN UINT16 Fid,
- IN P2SB_REGISTER_SPACE RegisterSpace,
- IN P2SB_SIDEBAND_ACCESS_METHOD AccessMethod,
- IN BOOLEAN PostedWrites,
- OUT P2SB_SIDEBAND_REGISTER_ACCESS *P2SbSidebandAccess
- );
-
-/**
- Builds P2SB sideband access using offset to config space.
- This offset will be added to every register offset, when access callbacks are used.
- Some IPs, like for example DMI, implement multiple register banks in the same register space.
- For instance sideband register space can contain both PCR registers,
- starting from the beginning of the register space,
- and PCI config registers starting from the offset in the same register space.
-
- @param[in] P2SbController Pointer to P2SB controller implementing the sideband
- @param[in] P2SbPid Port id
- @param[in] Fid Function id
- @param[in] RegisterSpace Target register space
- @param[in] AccessMethod Access method
- @param[in] PostedWrites If TRUE writes sent through sideband msg will be posted
- @param[in] Offset Register space offset that will be added to register offset
- @param[out] P2SbSidebandAccess An initialized sideband access descriptor containing register space offset
-
- @retval TRUE Access initialized successfuly
- @retval FALSE Failed to initialize access
-**/
-BOOLEAN
-BuildP2SbSidebandAccessEx (
- IN P2SB_CONTROLLER *P2SbController,
- IN P2SB_PID P2SbPid,
- IN UINT16 Fid,
- IN P2SB_REGISTER_SPACE RegisterSpace,
- IN P2SB_SIDEBAND_ACCESS_METHOD AccessMethod,
- IN BOOLEAN PostedWrites,
- IN UINT32 Offset,
- OUT P2SB_SIDEBAND_REGISTER_ACCESS *P2SbSidebandAccess
- );
-
-/**
- Get P2SB instance for MTL PCH
-
- @param[in, out] P2SbController P2SB controller pointer
-
- @retval EFI_SUCCESS - Completed successfully
- EFI_INVALID_PARAMETER - P2SbController NULL
-**/
-EFI_STATUS
-MtlPchGetP2SbController (
- IN OUT P2SB_CONTROLLER *P2SbController
- );
-#endif
diff --git a/Silicon/ArrowlakePkg/Include/PchReservedResources.h b/Silicon/ArrowlakePkg/Include/PchReservedResources.h
index 32ecc5e4..7bb1d150 100644
--- a/Silicon/ArrowlakePkg/Include/PchReservedResources.h
+++ b/Silicon/ArrowlakePkg/Include/PchReservedResources.h
@@ -59,9 +59,6 @@
#define PCH_TRACE_HUB_MTB_MMIO_SIZE 0x00100000 ///< 1MB
#define PCH_TRACE_HUB_FW_BASE_ADDRESS 0xFE200000 ///< TraceHub FW MMIO base address
-#define PCH_PCR_BASE_ADDRESS 0xE0000000 ///< SBREG MMIO base address
-#define PCH_PCR_MMIO_SIZE 0x01000000 ///< 16MB
-
#define IOE_PCR_ABOVE_4G_BASE_ADDRESS 0x3FFF0000000 ///< IOE P2SB above 4G base address (PhysicalAddressBits - SIZE_256M
#endif
diff --git a/Silicon/ArrowlakePkg/Include/PcrDefine.h b/Silicon/ArrowlakePkg/Include/PcrDefine.h
deleted file mode 100644
index 9a5b9143..00000000
--- a/Silicon/ArrowlakePkg/Include/PcrDefine.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/** @file
- Private Control Register definitions
-
- Copyright (c) 2024, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-#ifndef _PCR_DEFINE_H_
-#define _PCR_DEFINE_H_
-
-#include "PchReservedResources.h"
-
-/**
- Definition for PCR address
- The PCR address is used to the PCR MMIO programming
-
- SBREG_BAR_20BITADDRESS is configured by SoC
-
- SBREG_BAR_20BITADDRESS=1, the format has included 16b addressing.
- +---------------------------------------------------------------------------------------------+
- | Addr[63:28] | Addr[27:24] | Addr[23:16] | Addr[15:2] | Addr[1:0] |
- +----------------+-----------------------+-----------------+----------------------------------+
- | REG_BAR[63:28] | TargetRegister[19:16] | TargetPort[7:0] | TargetRegister[15:2] |
- +---------------------------------------------------------------------------------------------+
-
- SBREG_BAR_20BITADDRESS=0
- +---------------------------------------------------------------------------------------------+
- | Addr[63:24] | Addr[27:24] | Addr[23:16] | Addr[15:2] | Addr[1:0] |
- +----------------+-----------------------+-----------------+----------------------------------+
- | REG_BAR[63:24] | REG_BAR[27:24] | TargetPort[7:0] | TargetRegister[15:2] |
- +---------------------------------------------------------------------------------------------+
-**/
-#define PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_ADDRESS | (UINT32) (((Offset) & 0x0F0000) << 8) | ((UINT8)(Pid) << 16) | (UINT16) ((Offset) & 0xFFFF))
-
-/**
- PCH PCR boot script accessing macro
- Those macros are only available for DXE phase.
-**/
-#define PCH_PCR_BOOT_SCRIPT_WRITE(Width, Pid, Offset, Count, Buffer) \
- S3BootScriptSaveMemWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), Count, Buffer); \
-
-#define PCH_PCR_BOOT_SCRIPT_READ_WRITE(Width, Pid, Offset, DataOr, DataAnd) \
- S3BootScriptSaveMemReadWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), DataOr, DataAnd); \
-
-#define PCH_PCR_BOOT_SCRIPT_READ(Width, Pid, Offset, BitMask, BitValue) \
- S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), BitMask, BitValue, 1, 1);
-
-typedef UINT8 P2SB_PID;
-
-typedef union {
- UINT16 Pid16bit;
- struct {
- P2SB_PID LocalPid;
- UINT8 SegmentId;
- } PortId;
-} P2SB_PORT_16_ID;
-
-#define GET_P2SB_LOCAL_PID(id) ((id) & 0xFF)
-
-#endif // _PCR_DEFINE_H_
diff --git a/Silicon/ArrowlakePkg/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf b/Silicon/ArrowlakePkg/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf
index 7fc89e48..7a8341c1 100644
--- a/Silicon/ArrowlakePkg/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf
+++ b/Silicon/ArrowlakePkg/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf
@@ -28,4 +28,3 @@
IoLib
DebugLib
PcieRpSocLib
- P2SbSocLib
\ No newline at end of file
diff --git a/Silicon/ArrowlakePkg/Library/FirmwareUpdateLib/FirmwareUpdateLib.c b/Silicon/ArrowlakePkg/Library/FirmwareUpdateLib/FirmwareUpdateLib.c
index 67b0a112..2e3554f3 100644
--- a/Silicon/ArrowlakePkg/Library/FirmwareUpdateLib/FirmwareUpdateLib.c
+++ b/Silicon/ArrowlakePkg/Library/FirmwareUpdateLib/FirmwareUpdateLib.c
@@ -18,7 +18,6 @@
#include
#include
#include
-#include
#include
#include
#include
diff --git a/Silicon/ArrowlakePkg/Library/PchP2sbLib/PchP2sbLib.c b/Silicon/ArrowlakePkg/Library/PchP2sbLib/PchP2sbLib.c
deleted file mode 100644
index 09866c1f..00000000
--- a/Silicon/ArrowlakePkg/Library/PchP2sbLib/PchP2sbLib.c
+++ /dev/null
@@ -1,976 +0,0 @@
-/** @file
- P2SB sideband access lib
-
- Copyright (c) 2024, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#define P2SB_PCR_ADDRESS(MmioBase, Pid, Offset) ((UINTN) MmioBase | (UINT32) (((Offset) & 0x0F0000) << 8) | ((UINT8)(Pid) << 16) | (UINT16) ((Offset) & 0xFFFF))
-
-#define SA_SEG_NUM 0x00
-
-//
-// MMIOs above 4G
-//
-#define MTL_PCH_P2SB_MMIO64_OFFSET 0x00000000 ///< P2SB MMIO base address
-
-/**
- Full function for executing P2SB SBI message
- Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
- It will clash with POST time SBI programming when SMI happen.
- Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI
- to prevent from racing condition.
- This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access
- needed, it's better to unhide the P2SB before calling and hide it back after done.
-
- When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been
- SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information
- when needed.
-
- @param[in] P2sbBase P2SB PCI config base
- @param[in] Pid Port ID of the SBI message
- @param[in] Offset Offset of the SBI message
- @param[in] Opcode Opcode
- @param[in] Posted Posted message
- @param[in] Fbe First byte enable
- @param[in] Bar Bar
- @param[in] Fid Function ID
- @param[in, out] Data32 Read/Write data
- @param[out] Response Response
-
- @retval EFI_SUCCESS Successfully completed.
- @retval EFI_DEVICE_ERROR Transaction fail
- @retval EFI_INVALID_PARAMETER Invalid parameter
- @retval EFI_TIMEOUT Timeout while waiting for response
-**/
-EFI_STATUS
-P2SbSbiExecutionEx (
- IN UINT64 P2sbBase,
- IN P2SB_PID Pid,
- IN UINT64 Offset,
- IN PCH_SBI_OPCODE Opcode,
- IN BOOLEAN Posted,
- IN UINT16 Fbe,
- IN UINT16 Bar,
- IN UINT16 Fid,
- IN OUT UINT32 *Data32,
- OUT UINT8 *Response
- )
-{
- INT32 Timeout;
- UINT16 SbiStat;
-
- //
- // Check opcode valid
- //
- switch (Opcode) {
- case MemoryRead:
- case MemoryWrite:
- case PciConfigRead:
- case PciConfigWrite:
- case PrivateControlRead:
- case PrivateControlWrite:
- case GpioLockUnlock:
- break;
- default:
- return EFI_INVALID_PARAMETER;
- break;
- }
-
- if (PciSegmentRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
- ASSERT (FALSE);
- return EFI_DEVICE_ERROR;
- }
- ///
- /// BWG Section 2.2.1
- /// 1. Poll P2SB PCI offset D8h[0] = 0b
- /// Make sure the previous opeartion is completed.
- ///
- Timeout = 0xFFFFFFF;
- SbiStat = 0;
- while (Timeout > 0) {
- SbiStat = PciSegmentRead16 (P2sbBase + R_P2SB_CFG_SBISTAT_V2);
- if ((SbiStat & B_P2SB_CFG_SBISTAT_INITRDY) == 0) {
- break;
- }
- Timeout--;
- }
- if (Timeout == 0) {
- return EFI_TIMEOUT;
- }
- //
- // Initial Response status
- //
- *Response = SBI_INVALID_RESPONSE;
- ///
- /// 2. Write P2SB PCI offset D0h[31:0] with Address and Destination Port ID
- ///
- PciSegmentWrite32 (P2sbBase + R_P2SB_CFG_SBIADDR_V2, (UINT32) ((Pid << 24) | (UINT16) Offset));
- ///
- /// 3. Write P2SB PCI offset DCh[31:0] with extended address, which is expected to be 0 in CNL PCH.
- ///
- PciSegmentWrite32 (P2sbBase + R_P2SB_CFG_SBIEXTADDR_V2, (UINT32) RShiftU64 (Offset, 16));
- ///
- /// 5. Set P2SB PCI offset D8h[15:8] = 00000110b for read
- /// Set P2SB PCI offset D8h[15:8] = 00000111b for write
- //
- // Set SBISTAT[15:8] to the opcode passed in
- // Set SBISTAT[7] to the posted passed in
- //
- PciSegmentAndThenOr16 (
- (P2sbBase + R_P2SB_CFG_SBISTAT_V2),
- (UINT16) ~(B_P2SB_CFG_SBISTAT_OPCODE_V2 | B_P2SB_CFG_SBISTAT_POSTED),
- (UINT16) ((Opcode << 8) | (Posted << 7))
- );
- ///
- /// 6. Write P2SB PCI offset DAh[15:0] = F000h
- ///
- //
- // Set RID[15:0] = Fbe << 12 | Bar << 8 | Fid
- //
- PciSegmentWrite16 (
- (P2sbBase + R_P2SB_CFG_SBIRID_V2),
- (((Fbe & 0x000F) << 12) | ((Bar & 0x0007) << 8) | (Fid & 0x00FF))
- );
-
- switch (Opcode) {
- case MemoryWrite:
- case PciConfigWrite:
- case PrivateControlWrite:
- case GpioLockUnlock:
- ///
- /// 4. Write P2SB PCI offset D4h[31:0] with the intended data accordingly
- ///
- PciSegmentWrite32 ((P2sbBase + R_P2SB_CFG_SBIDATA_V2), *Data32);
- break;
- default:
- ///
- /// 4. Write P2SB PCI offset D4h[31:0] with dummy data such as 0,
- /// because all D0-DFh register range must be touched in CNL PCH
- /// for a successful SBI transaction.
- ///
- PciSegmentWrite32 ((P2sbBase + R_P2SB_CFG_SBIDATA_V2), 0);
- break;
- }
- ///
- /// 7. Set P2SB PCI offset D8h[0] = 1b, Poll P2SB PCI offset D8h[0] = 0b
- ///
- //
- // Set SBISTAT[0] = 1b, trigger the SBI operation
- //
- PciSegmentOr16 (P2sbBase + R_P2SB_CFG_SBISTAT_V2, (UINT16) B_P2SB_CFG_SBISTAT_INITRDY);
- //
- // Poll SBISTAT[0] = 0b, Polling for Busy bit
- //
- Timeout = 0xFFFFFFF;
- while (Timeout > 0) {
- SbiStat = PciSegmentRead16 (P2sbBase + R_P2SB_CFG_SBISTAT_V2);
- if ((SbiStat & B_P2SB_CFG_SBISTAT_INITRDY) == 0) {
- break;
- }
- Timeout--;
- }
- if (Timeout == 0) {
- //
- // If timeout, it's fatal error.
- //
- return EFI_TIMEOUT;
- } else {
- ///
- /// 8. Check if P2SB PCI offset D8h[2:1] = 00b for successful transaction
- ///
- *Response = (UINT8) ((SbiStat & B_P2SB_CFG_SBISTAT_RESPONSE_V2) >> N_P2SB_CFG_SBISTAT_RESPONSE);
- if (*Response == SBI_SUCCESSFUL) {
- switch (Opcode) {
- case MemoryRead:
- case PciConfigRead:
- case PrivateControlRead:
- ///
- /// 9. Read P2SB PCI offset D4h[31:0] for SBI data
- ///
- *Data32 = PciSegmentRead32 (P2sbBase + R_P2SB_CFG_SBIDATA_V2);
- break;
- default:
- break;
- }
- return EFI_SUCCESS;
- } else if (*Response == SBI_POWERDOWN) {
- return EFI_NO_RESPONSE;
- } else {
- return EFI_DEVICE_ERROR;
- }
- }
-}
-
-/**
- Execute P2SB SBI message
- Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
- It will clash with POST time SBI programming when SMI happen.
- Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI
- to prevent from racing condition.
- This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access
- needed, it's better to unhide the P2SB before calling and hide it back after done.
-
- When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been
- SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information
- when needed.
-
- @param[in] P2sbBase P2SB PCI config base
- @param[in] Pid Port ID of the SBI message
- @param[in] Offset Offset of the SBI message
- @param[in] Opcode Opcode
- @param[in] Posted Posted message
- @param[in, out] Data32 Read/Write data
- @param[out] Response Response
-
- @retval EFI_SUCCESS Successfully completed.
- @retval EFI_DEVICE_ERROR Transaction fail
- @retval EFI_INVALID_PARAMETER Invalid parameter
- @retval EFI_TIMEOUT Timeout while waiting for response
-**/
-EFI_STATUS
-P2SbSbiExecution (
- IN UINT64 P2sbBase,
- IN P2SB_PID Pid,
- IN UINT64 Offset,
- IN PCH_SBI_OPCODE Opcode,
- IN BOOLEAN Posted,
- IN OUT UINT32 *Data32,
- OUT UINT8 *Response
- )
-{
- return P2SbSbiExecutionEx (
- P2sbBase,
- Pid,
- Offset,
- Opcode,
- Posted,
- 0x000F,
- 0x0000,
- 0x0000,
- Data32,
- Response
- );
-}
-
-#ifndef MDEPKG_NDEBUG
-/**
- Checks if the offset is valid for a given memory access width. Offset must align to width size.
-
- @param[in] Offset Offset of a register
- @param[in] Size Size of memory access in bytes
-
- @retval FALSE Offset is not valid for a given memory access
- @retval TRUE Offset is valid
-**/
-STATIC
-BOOLEAN
-P2SbIsPcrOffsetValid (
- IN UINT32 Offset,
- IN UINTN Size
- )
-{
- if (!IsP2sb20bPcrSupported ()) {
- if (((Offset & (Size - 1)) != 0) || (Offset > 0xFFFF)) {
- DEBUG ((DEBUG_WARN, "PCR offset error. Invalid Offset: %x Size: %x", Offset, Size));
- return FALSE;
- } else {
- return TRUE;
- }
- } else {
- if (((Offset & (Size - 1)) != 0) || (Offset > 0xFFFFF)) {
- DEBUG ((DEBUG_WARN, "PCR offset error. Invalid Offset: %x Size: %x", Offset, Size));
- return FALSE;
- } else {
- return TRUE;
- }
- }
-}
-#endif
-
-/**
- Convert register space enum into SBI opcode.
-
- @param[in] RegisterSpace To which register space is the msg addressed
- @param[in] Write TRUE if this is a write operation
-
- @return P2SB_SBI_OPCODE to address given register space
-**/
-STATIC
-PCH_SBI_OPCODE
-P2SbOpcodeFromRegisterSpace (
- IN P2SB_REGISTER_SPACE RegisterSpace,
- IN BOOLEAN Write
- )
-{
- switch (RegisterSpace) {
- case P2SbMemory:
- return Write ? MemoryWrite : MemoryRead;
- case P2SbPciConfig:
- return Write ? PciConfigWrite : PciConfigRead;
- case P2SbPrivateConfig:
- default:
- return Write ? PrivateControlWrite : PrivateControlRead;
- }
-}
-
-/**
- Reads an 8-bit register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
-
- @return The 8-bit register value specified by Offset
-**/
-UINT8
-P2SbSidebandRead8 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset
- )
-{
- P2SB_SIDEBAND_REGISTER_ACCESS *Private;
- UINT32 AlignedOffset;
- UINT32 Value;
-
- Private = (P2SB_SIDEBAND_REGISTER_ACCESS *) This;
-
- switch (Private->AccessMethod) {
- case P2SbMmioAccess:
- Offset = Offset + Private->Offset;
- ASSERT (0xE0000000);
- return MmioRead8 (P2SB_PCR_ADDRESS (0xE0000000, Private->P2SbPid, Offset));
- case P2SbMsgAccess:
- //
- // P2SB msg only supports DWORD access. To make 8-bit wide read work we align the
- // address to neares DWORD and read that. Later on we mask the value we got from DWORD to only
- // read what we need. Care needs to be taken for 8-bit registers for which there are registers
- // in the neighborhood there are other registers for which read has side effects.
- //
- AlignedOffset = Offset - (Offset % 4);
- Value = P2SbSidebandRead32 (This, AlignedOffset);
- return (UINT8) (Value >> (8 * (Offset % 4)));
- default:
- DEBUG ((DEBUG_ERROR, "P2SB: Incorrect access method %d\n", Private->AccessMethod));
- return 0xFF;
- }
-}
-
-/**
- Writes an 8-bit register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] Value Value to write to register
-
- @return The 8-bit register value written to register
-**/
-UINT8
-P2SbSidebandWrite8 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT8 Value
- )
-{
- P2SB_SIDEBAND_REGISTER_ACCESS *Private;
- UINT32 AlignedOffset;
-
- Private = (P2SB_SIDEBAND_REGISTER_ACCESS *) This;
-
-
- switch (Private->AccessMethod) {
- case P2SbMmioAccess:
- Offset = Offset + Private->Offset;
- ASSERT (0xE0000000);
- MmioWrite8 (P2SB_PCR_ADDRESS (0xE0000000, Private->P2SbPid, Offset), Value);
- //
- // Readback to flush the write cycle and ensure ordering with primary
- //
- return MmioRead8 (P2SB_PCR_ADDRESS (0xE0000000, Private->P2SbPid, Offset));
- case P2SbMsgAccess:
- //
- // P2SB msg only supports DWORD access to make it work with 16-bit width
- // we align the offset to the nearest DWORD and use the AndThenOr32 method to
- // only modify required fields in 16-bit register. Care needs to be taken when
- // one wish to modify a 16-bit register for which nearest 32-bit aligned register
- // contains write once fields.
- //
- AlignedOffset = Offset - (Offset % 4);
- P2SbSidebandAndThenOr32 (
- This,
- AlignedOffset,
- ~(0xFF << (8 * (Offset % 4))),
- Value << (8 * (Offset % 4))
- );
- return Value;
- default:
- DEBUG ((DEBUG_ERROR, "P2SB: Incorrect access method %d\n", Private->AccessMethod));
- return 0xFF;
- }
-}
-
-/**
- Performs an 8-bit or on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] OrData Data with which register should be OR-ed
-
- @return The 8-bit register value written to register
-**/
-UINT8
-P2SbSidebandOr8 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT8 OrData
- )
-{
- UINT8 Value;
-
- Value = P2SbSidebandRead8 (This, Offset);
- Value |= OrData;
- return P2SbSidebandWrite8 (This, Offset, Value);
-}
-
-/**
- Performs an 8-bit and on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] AndData Data with which register should be AND-ed
-
- @return The 8-bit register value written to register
-**/
-UINT8
-P2SbSidebandAnd8 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT8 AndData
- )
-{
- UINT8 Value;
-
- Value = P2SbSidebandRead8 (This, Offset);
- Value &= AndData;
- return P2SbSidebandWrite8 (This, Offset, Value);
-}
-
-/**
- Performs an 8-bit and then or on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] AndData Data with which register should be AND-ed
- @param[in] OrData Data with which register should be OR-ed
-
- @return The 8-bit register value written to register
-**/
-UINT8
-P2SbSidebandAndThenOr8 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT8 AndData,
- IN UINT8 OrData
- )
-{
- UINT8 Value;
-
- Value = P2SbSidebandRead8 (This, Offset);
- Value &= AndData;
- Value |= OrData;
- return P2SbSidebandWrite8 (This, Offset, Value);
-}
-
-/**
- Reads a 16-bit register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
-
- @return The 16-bit register value specified by Offset
-**/
-UINT16
-P2SbSidebandRead16 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset
- )
-{
- P2SB_SIDEBAND_REGISTER_ACCESS *Private;
- UINT32 AlignedOffset;
- UINT32 Value;
-
-#ifndef MDEPKG_NDEBUG
- ASSERT (P2SbIsPcrOffsetValid (Offset, 2));
-#endif
-
- Private = (P2SB_SIDEBAND_REGISTER_ACCESS *) This;
-
- switch (Private->AccessMethod) {
- case P2SbMmioAccess:
- Offset = Offset + Private->Offset;
- ASSERT (0xE0000000);
- return MmioRead16 (P2SB_PCR_ADDRESS (0xE0000000, Private->P2SbPid, Offset));
- case P2SbMsgAccess:
- //
- // P2SB msg only supports DWORD access. To make 8-bit wide read work we align the
- // address to neares DWORD and read that. Later on we mask the value we got from DWORD to only
- // read what we need. Care needs to be taken for 8-bit registers for which there are registers
- // in the neighborhood there are other registers for which read has side effects.
- //
- AlignedOffset = Offset - (Offset % 4);
- Value = P2SbSidebandRead32 (This, AlignedOffset);
- return (UINT16) (Value >> (8 * (Offset % 4)));
- default:
- DEBUG ((DEBUG_ERROR, "P2SB: Incorrect access method %d\n", Private->AccessMethod));
- return 0xFFFF;
- }
-}
-
-/**
- Writes a 16-bit register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] Value Value to write to register
-
- @return The 16-bit register value written to register
-**/
-UINT16
-P2SbSidebandWrite16 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT16 Value
- )
-{
- P2SB_SIDEBAND_REGISTER_ACCESS *Private;
- UINT32 AlignedOffset;
-
-#ifndef MDEPKG_NDEBUG
- ASSERT (P2SbIsPcrOffsetValid (Offset, 2));
-#endif
-
- Private = (P2SB_SIDEBAND_REGISTER_ACCESS *) This;
-
- switch (Private->AccessMethod) {
- case P2SbMmioAccess:
- Offset = Offset + Private->Offset;
- ASSERT (0xE0000000);
- MmioWrite16 (P2SB_PCR_ADDRESS (0xE0000000, Private->P2SbPid, Offset), Value);
- //
- // Readback to flush the write cycle and ensure ordering with primary
- //
- return MmioRead16 (P2SB_PCR_ADDRESS (0xE0000000, Private->P2SbPid, Offset));
- case P2SbMsgAccess:
- //
- // P2SB msg only supports DWORD access to make it work with 16-bit width
- // we align the offset to the nearest DWORD and use the AndThenOr32 method to
- // only modify required fields in 16-bit register. Care needs to be taken when
- // one wish to modify a 16-bit register for which nearest 32-bit aligned register
- // contains write once fields.
- //
- AlignedOffset = Offset - (Offset % 4);
- P2SbSidebandAndThenOr32 (
- This,
- AlignedOffset,
- ~(0xFFFF << (8 * (Offset % 4))),
- Value << (8 * (Offset % 4))
- );
- return Value;
- default:
- DEBUG ((DEBUG_ERROR, "P2SB: Incorrect access method %d\n", Private->AccessMethod));
- return 0xFFFF;
- }
-}
-
-/**
- Performs a 16-bit or on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] OrData Data with which register should be OR-ed
-
- @return The 16-bit register value written to register
-**/
-UINT16
-P2SbSidebandOr16 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT16 OrData
- )
-{
- UINT16 Value;
-
- Value = P2SbSidebandRead16 (This, Offset);
- Value |= OrData;
- return P2SbSidebandWrite16 (This, Offset, Value);
-}
-
-/**
- Performs a 16-bit and on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] AndData Data with which register should be AND-ed
-
- @return The 16-bit register value written to register
-**/
-UINT16
-P2SbSidebandAnd16 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT16 AndData
- )
-{
- UINT16 Value;
-
- Value = P2SbSidebandRead16 (This, Offset);
- Value &= AndData;
- return P2SbSidebandWrite16 (This, Offset, Value);
-}
-
-/**
- Performs a 16-bit and then or on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] AndData Data with which register should be AND-ed
- @param[in] OrData Data with which register should be OR-ed
-
- @return The 16-bit register value written to register
-**/
-UINT16
-P2SbSidebandAndThenOr16 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT16 AndData,
- IN UINT16 OrData
- )
-{
- UINT16 Value;
-
- Value = P2SbSidebandRead16 (This, Offset);
- Value &= AndData;
- Value |= OrData;
- return P2SbSidebandWrite16 (This, Offset, Value);
-}
-
-/**
- Check if currently run in HFPGA environment or not.
-
- @retval TRUE Run in HFPGA environment
- @retval FALSE Not run in HFPGA environment
-**/
-BOOLEAN
-IsHfpgaEnvironment (
- VOID
- )
-{
- UINT8 PlatformId;
-
- PlatformId = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_MC_SIM_RECOGNITION_OFFSET));
-
- return (PlatformId == V_SA_MC_SIM_RECOGNITION_PLATFORM_HFPGA);
-}
-
-/**
- Check if currently run in Simics environment or not.
-
- @retval TRUE Run in Simics environment
- @retval FALSE Not run in Simics environment
-**/
-BOOLEAN
-IsSimicsEnvironment (
- VOID
- )
-{
- UINT8 PlatformId;
-
- PlatformId = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_MC_SIM_RECOGNITION_OFFSET));
-
- return (PlatformId == V_SA_MC_SIM_RECOGNITION_PLATFORM_SIMICS);
-}
-
-/**
- Reads a 32-bit register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
-
- @return The 32-bit register value specified by Offset
-**/
-UINT32
-P2SbSidebandRead32 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset
- )
-{
- P2SB_SIDEBAND_REGISTER_ACCESS *Private;
- EFI_STATUS Status;
- UINT32 Value;
- UINT8 Response;
-
- Private = (P2SB_SIDEBAND_REGISTER_ACCESS *) This;
- Offset = Offset + Private->Offset;
-
- switch (Private->AccessMethod) {
- case P2SbMmioAccess:
-#ifndef MDEPKG_NDEBUG
- ASSERT (P2SbIsPcrOffsetValid (Offset, 4));
-#endif
- ASSERT (0xE0000000);
- return MmioRead32 (P2SB_PCR_ADDRESS (0xE0000000, Private->P2SbPid, Offset));
- case P2SbMsgAccess:
- Status = P2SbSbiExecutionEx (
- 0x80F9000,
- Private->P2SbPid,
- Offset,
- P2SbOpcodeFromRegisterSpace (Private->RegisterSpace, FALSE),
- FALSE,
- 0xF,
- 0,
- Private->Fid,
- &Value,
- &Response
- );
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "P2SB: MSG failed %r, %d\n", Status, Response));
- return 0xFFFFFFFF;
- } else {
- return Value;
- }
- default:
- DEBUG ((DEBUG_ERROR, "P2SB: Incorrect access method %d\n", Private->AccessMethod));
- return 0xFFFFFFFF;
- }
-}
-
-/**
- Writes a 32-bit register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] Value Value to write to register
-
- @return The 32-bit register value written to register
-**/
-UINT32
-P2SbSidebandWrite32 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT32 Value
- )
-{
- P2SB_SIDEBAND_REGISTER_ACCESS *Private;
- EFI_STATUS Status;
- UINT8 Response;
-
- Private = (P2SB_SIDEBAND_REGISTER_ACCESS *) This;
- Offset = Offset + Private->Offset;
-
- switch (Private->AccessMethod) {
- case P2SbMmioAccess:
-#ifndef MDEPKG_NDEBUG
- ASSERT (P2SbIsPcrOffsetValid (Offset, 4));
-#endif
- ASSERT (0xE0000000);
- MmioWrite32 (P2SB_PCR_ADDRESS (0xE0000000, Private->P2SbPid, Offset), Value);
- //
- // Readback to flush the write cycle and ensure ordering with primary
- //
- return MmioRead32 (P2SB_PCR_ADDRESS (0xE0000000, Private->P2SbPid, Offset));
- case P2SbMsgAccess:
- Status = P2SbSbiExecutionEx (
- 0x80F9000,
- Private->P2SbPid,
- Offset,
- P2SbOpcodeFromRegisterSpace (Private->RegisterSpace, TRUE),
- Private->PostedWrites,
- 0xF,
- 0,
- Private->Fid,
- &Value,
- &Response
- );
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "P2SB: MSG failed %r, %d\n", Status, Response));
- return 0xFFFFFFFF;
- } else {
- return Value;
- }
- default:
- DEBUG ((DEBUG_ERROR, "P2SB: Incorrect access method %d\n", Private->AccessMethod));
- return 0xFFFFFFFF;
- }
-}
-
-/**
- Performs a 32-bit or on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] OrData Data with which register should be OR-ed
-
- @return The 32-bit register value written to register
-**/
-UINT32
-P2SbSidebandOr32 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT32 OrData
- )
-{
- UINT32 Value;
-
- Value = P2SbSidebandRead32 (This, Offset);
- Value |= OrData;
- return P2SbSidebandWrite32 (This, Offset, Value);
-}
-
-/**
- Performs a 32-bit and on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] AndData Data with which register should be AND-ed
-
- @return The 32-bit register value written to register
-**/
-UINT32
-P2SbSidebandAnd32 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT32 AndData
- )
-{
- UINT32 Value;
-
- Value = P2SbSidebandRead32 (This, Offset);
- Value &= AndData;
- return P2SbSidebandWrite32 (This, Offset, Value);
-}
-
-/**
- Performs a 32-bit and then or on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] AndData Data with which register should be AND-ed
- @param[in] OrData Data with which register should be OR-ed
-
- @return The 32-bit register value written to register
-**/
-UINT32
-P2SbSidebandAndThenOr32 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT32 AndData,
- IN UINT32 OrData
- )
-{
- UINT32 Value;
-
- Value = P2SbSidebandRead32 (This, Offset);
- Value &= AndData;
- Value |= OrData;
- return P2SbSidebandWrite32 (This, Offset, Value);
-}
-
-/**
- Builds P2SB sideband access.
-
- @param[in] P2SbController Pointer to P2SB controller implementing the sideband
- @param[in] P2SbPid Port id
- @param[in] Fid Function id
- @param[in] RegisterSpace Target register space
- @param[in] AccessMethod Access method
- @param[in] PostedWrites If TRUE writes sent through sideband msg will be posted
- @param[out] P2SbSidebandAccess On output an initialized sideband access descriptor
-
- @retval TRUE Access initialized successfuly
- @retval FALSE Failed to initialize access
-**/
-BOOLEAN
-BuildP2SbSidebandAccess (
- IN P2SB_CONTROLLER *P2SbController,
- IN P2SB_PID P2SbPid,
- IN UINT16 Fid,
- IN P2SB_REGISTER_SPACE RegisterSpace,
- IN P2SB_SIDEBAND_ACCESS_METHOD AccessMethod,
- IN BOOLEAN PostedWrites,
- OUT P2SB_SIDEBAND_REGISTER_ACCESS *P2SbSidebandAccess
- )
-{
- P2SbSidebandAccess->Access.Read8 = P2SbSidebandRead8;
- P2SbSidebandAccess->Access.Write8 = P2SbSidebandWrite8;
- P2SbSidebandAccess->Access.Or8 = P2SbSidebandOr8;
- P2SbSidebandAccess->Access.And8 = P2SbSidebandAnd8;
- P2SbSidebandAccess->Access.AndThenOr8 = P2SbSidebandAndThenOr8;
- P2SbSidebandAccess->Access.Read16 = P2SbSidebandRead16;
- P2SbSidebandAccess->Access.Write16 = P2SbSidebandWrite16;
- P2SbSidebandAccess->Access.Or16 = P2SbSidebandOr16;
- P2SbSidebandAccess->Access.And16 = P2SbSidebandAnd16;
- P2SbSidebandAccess->Access.AndThenOr16 = P2SbSidebandAndThenOr16;
- P2SbSidebandAccess->Access.Read32 = P2SbSidebandRead32;
- P2SbSidebandAccess->Access.Write32 = P2SbSidebandWrite32;
- P2SbSidebandAccess->Access.Or32 = P2SbSidebandOr32;
- P2SbSidebandAccess->Access.And32 = P2SbSidebandAnd32;
- P2SbSidebandAccess->Access.AndThenOr32 = P2SbSidebandAndThenOr32;
-
- P2SbSidebandAccess->AccessMethod = AccessMethod;
- P2SbSidebandAccess->P2SbPid = P2SbPid;
- P2SbSidebandAccess->Fid = Fid;
- P2SbSidebandAccess->RegisterSpace = RegisterSpace;
- P2SbSidebandAccess->PostedWrites = PostedWrites;
- P2SbSidebandAccess->P2SbCtrl = P2SbController;
- P2SbSidebandAccess->Offset = 0;
-
- return TRUE;
-}
-
-/**
- Get P2SB instance for MTL PCH
-
- @param[in, out] P2SbController P2SB controller pointer
-
- @retval EFI_SUCCESS - Completed successfully
- EFI_INVALID_PARAMETER - P2SbController NULL
-**/
-EFI_STATUS
-MtlPchGetP2SbController (
- IN OUT P2SB_CONTROLLER *P2SbController
- )
-{
- UINT8 SegmentNumber;
- UINT64 ReservedMmio64Base;
-
- if (P2SbController == NULL) {
- return EFI_INVALID_PARAMETER;
- }
- SegmentNumber = 0;
- ReservedMmio64Base = 0x5FF0000000;
-
- ZeroMem (P2SbController, sizeof (P2SB_CONTROLLER));
- P2SbController->PciCfgBaseAddr = PCI_SEGMENT_LIB_ADDRESS (
- SegmentNumber,
- 128,
- 31,
- 1,
- 0);
- P2SbController->Mmio = ReservedMmio64Base + MTL_PCH_P2SB_MMIO64_OFFSET;
- P2SbController->HpetMmio = 0;
-
- return EFI_SUCCESS;
-}
diff --git a/Silicon/ArrowlakePkg/Library/PciExpressHelpersLibrary/PciExpressHelpersLibrary.inf b/Silicon/ArrowlakePkg/Library/PciExpressHelpersLibrary/PciExpressHelpersLibrary.inf
index e2ee7bfe..1b0a1ef6 100644
--- a/Silicon/ArrowlakePkg/Library/PciExpressHelpersLibrary/PciExpressHelpersLibrary.inf
+++ b/Silicon/ArrowlakePkg/Library/PciExpressHelpersLibrary/PciExpressHelpersLibrary.inf
@@ -24,13 +24,10 @@
[LibraryClasses]
IoLib
DebugLib
- PchPcrLib
- PchInfoLib
- GpioLib
- TimerLib
- BasePchPciBdfLib
- BasePcieHelperLib
PcieRpLib
+ PchInfoLib
+ TimerLib
+ BasePcieHelperLib
[Packages]
Silicon/ArrowlakePkg/ArrowlakePkg.dec
diff --git a/Silicon/ArrowlakePkg/Library/PcieRpLib/PcieRpLib.inf b/Silicon/ArrowlakePkg/Library/PcieRpLib/PcieRpLib.inf
index 5065a45e..5c94d140 100644
--- a/Silicon/ArrowlakePkg/Library/PcieRpLib/PcieRpLib.inf
+++ b/Silicon/ArrowlakePkg/Library/PcieRpLib/PcieRpLib.inf
@@ -25,12 +25,9 @@
[LibraryClasses]
IoLib
DebugLib
- PchPcrLib
PchInfoLib
- GpioLib
TimerLib
BasePcieHelperLib
- PchPciBdfLib
[Packages]
MdePkg/MdePkg.dec
diff --git a/Silicon/ArrowlakePkg/Library/PlatformHookLib/PlatformHookLib.c b/Silicon/ArrowlakePkg/Library/PlatformHookLib/PlatformHookLib.c
index ed1b9166..d479a4f5 100644
--- a/Silicon/ArrowlakePkg/Library/PlatformHookLib/PlatformHookLib.c
+++ b/Silicon/ArrowlakePkg/Library/PlatformHookLib/PlatformHookLib.c
@@ -10,14 +10,12 @@
#include
#include
#include
-#include
#include
#include
#include
#include
#include
#include
-#include
#include
#include
#include
diff --git a/Silicon/ArrowlakePkg/Library/PlatformHookLib/PlatformHookLibArlp.c b/Silicon/ArrowlakePkg/Library/PlatformHookLib/PlatformHookLibArlp.c
index 0db317fb..21c00b36 100644
--- a/Silicon/ArrowlakePkg/Library/PlatformHookLib/PlatformHookLibArlp.c
+++ b/Silicon/ArrowlakePkg/Library/PlatformHookLib/PlatformHookLibArlp.c
@@ -10,14 +10,12 @@
#include
#include
#include
-#include
#include
#include
#include
#include
#include
#include
-#include
#include
#include
#include
diff --git a/Silicon/CommonSocPkg/Include/Library/P2SbSidebandAccessLib.h b/Silicon/CommonSocPkg/Include/Library/P2SbSidebandAccessLib.h
deleted file mode 100644
index 8bb590db..00000000
--- a/Silicon/CommonSocPkg/Include/Library/P2SbSidebandAccessLib.h
+++ /dev/null
@@ -1,391 +0,0 @@
-/** @file
- Header for P2SbSidebandAccessLib
-
- Copyright (c) 2023, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef _P2SB_SIDEBAND_ACCESS_LIB_H_
-#define _P2SB_SIDEBAND_ACCESS_LIB_H_
-
-#include "Library/RegisterAccess.h"
-#include
-#include "Library/P2SbController.h"
-#include "Library/PcrDefine.h"
-#include
-//#include "PchSbiAccessV2Lib.h"
-
-#define P2SB_REGISTER_ACCESS_INIT {P2SbSidebandRead8, P2SbSidebandWrite8, P2SbSidebandOr8, P2SbSidebandAnd8, P2SbSidebandAndThenOr8, \
- P2SbSidebandRead16, P2SbSidebandWrite16, P2SbSidebandOr16, P2SbSidebandAnd16, P2SbSidebandAndThenOr16,\
- P2SbSidebandRead32, P2SbSidebandWrite32, P2SbSidebandOr32, P2SbSidebandAnd32, P2SbSidebandAndThenOr32}
-
-typedef enum {
- P2SbMemory = 0,
- P2SbPciConfig,
- P2SbPrivateConfig
-} P2SB_REGISTER_SPACE;
-
-typedef enum {
- P2SbMmioAccess = 0,
- P2SbMsgAccess
-} P2SB_SIDEBAND_ACCESS_METHOD;
-
-
-/**
- REGISTER_ACCESS for P2SB device to support access to sideband registers.
- Be sure to keep first member of this structure as REGISTER_ACCESS to allow
- for correct casting between caller who sees this structure as REGISTER_ACCESS
- and calle who will cast it to P2SB_SIDEBAND_REGISTER_ACCESS.
-**/
-typedef struct {
- REGISTER_ACCESS Access;
- P2SB_SIDEBAND_ACCESS_METHOD AccessMethod;
- P2SB_PID P2SbPid;
- UINT16 Fid;
- P2SB_REGISTER_SPACE RegisterSpace;
- BOOLEAN PostedWrites;
- P2SB_CONTROLLER P2SbCtrl;
- UINT32 Offset;
-} P2SB_SIDEBAND_REGISTER_ACCESS;
-
-/**
- Reads an 8-bit register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
-
- @return The 8-bit register value specified by Offset
-**/
-UINT8
-P2SbSidebandRead8 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset
- );
-
-/**
- Writes an 8-bit register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] Value Value to write to register
-
- @return The 8-bit register value written to register
-**/
-UINT8
-P2SbSidebandWrite8 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT8 Value
- );
-
-/**
- Performs an 8-bit or on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] OrData Data with which register should be OR-ed
-
- @return The 8-bit register value written to register
-**/
-UINT8
-P2SbSidebandOr8 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT8 OrData
- );
-
-/**
- Performs an 8-bit and on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] AndData Data with which register should be AND-ed
-
- @return The 8-bit register value written to register
-**/
-UINT8
-P2SbSidebandAnd8 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT8 AndData
- );
-
-/**
- Performs an 8-bit and then or on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] AndData Data with which register should be AND-ed
- @param[in] OrData Data with which register should be OR-ed
-
- @return The 8-bit register value written to register
-**/
-UINT8
-P2SbSidebandAndThenOr8 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT8 AndData,
- IN UINT8 OrData
- );
-
-/**
- Reads a 16-bit register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
-
- @return The 16-bit register value specified by Offset
-**/
-UINT16
-P2SbSidebandRead16 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset
- );
-
-/**
- Writes a 16-bit register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] Value Value to write to register
-
- @return The 16-bit register value written to register
-**/
-UINT16
-P2SbSidebandWrite16 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT16 Value
- );
-
-/**
- Performs a 16-bit or on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] OrData Data with which register should be OR-ed
-
- @return The 16-bit register value written to register
-**/
-UINT16
-P2SbSidebandOr16 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT16 OrData
- );
-
-/**
- Performs a 16-bit and on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] AndData Data with which register should be AND-ed
-
- @return The 16-bit register value written to register
-**/
-UINT16
-P2SbSidebandAnd16 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT16 AndData
- );
-
-/**
- Performs a 16-bit and then or on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] AndData Data with which register should be AND-ed
- @param[in] OrData Data with which register should be OR-ed
-
- @return The 16-bit register value written to register
-**/
-UINT16
-P2SbSidebandAndThenOr16 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT16 AndData,
- IN UINT16 OrData
- );
-
-/**
- Reads a 32-bit register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
-
- @return The 32-bit register value specified by Offset
-**/
-UINT32
-P2SbSidebandRead32 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset
- );
-
-/**
- Writes a 32-bit register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] Value Value to write to register
-
- @return The 32-bit register value written to register
-**/
-UINT32
-P2SbSidebandWrite32 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT32 Value
- );
-
-/**
- Performs a 32-bit or on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] OrData Data with which register should be OR-ed
-
- @return The 32-bit register value written to register
-**/
-UINT32
-P2SbSidebandOr32 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT32 OrData
- );
-
-/**
- Performs a 32-bit and on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] AndData Data with which register should be AND-ed
-
- @return The 32-bit register value written to register
-**/
-UINT32
-P2SbSidebandAnd32 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT32 AndData
- );
-
-/**
- Performs a 32-bit and then or on the register
-
- @param[in] This Pointer to REGISTER_ACCESS
- @param[in] Offset Offset of the register in the register bank
- @param[in] AndData Data with which register should be AND-ed
- @param[in] OrData Data with which register should be OR-ed
-
- @return The 32-bit register value written to register
-**/
-UINT32
-P2SbSidebandAndThenOr32 (
- IN REGISTER_ACCESS *This,
- IN UINT32 Offset,
- IN UINT32 AndData,
- IN UINT32 OrData
- );
-
-/**
- Full function for executing P2SB SBI message
- Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
- It will clash with POST time SBI programming when SMI happen.
- Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI
- to prevent from racing condition.
- This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access
- needed, it's better to unhide the P2SB before calling and hide it back after done.
-
- When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been
- SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information
- when needed.
-
- @param[in] P2sbBase P2SB PCI config base
- @param[in] Pid Port ID of the SBI message
- @param[in] Offset Offset of the SBI message
- @param[in] Opcode Opcode
- @param[in] Posted Posted message
- @param[in] Fbe First byte enable
- @param[in] Bar Bar
- @param[in] Fid Function ID
- @param[in, out] Data32 Read/Write data
- @param[out] Response Response
-
- @retval EFI_SUCCESS Successfully completed.
- @retval EFI_DEVICE_ERROR Transaction fail
- @retval EFI_INVALID_PARAMETER Invalid parameter
- @retval EFI_TIMEOUT Timeout while waiting for response
-**/
-EFI_STATUS
-P2SbSbiExecutionEx (
- IN UINT64 P2sbBase,
- IN P2SB_PID Pid,
- IN UINT64 Offset,
- IN PCH_SBI_OPCODE Opcode,
- IN BOOLEAN Posted,
- IN UINT16 Fbe,
- IN UINT16 Bar,
- IN UINT16 Fid,
- IN OUT UINT32 *Data32,
- OUT UINT8 *Response
- );
-
-/**
- Builds P2SB sideband access.
-
- @param[in] P2SbController Pointer to P2SB controller implementing the sideband
- @param[in] P2SbPid Port id
- @param[in] Fid Function id
- @param[in] RegisterSpace Target register space
- @param[in] AccessMethod Access method
- @param[in] PostedWrites If TRUE writes sent through sideband msg will be posted
- @param[out] P2SbSidebandAccess On output an initialized sideband access descriptor
-
- @retval TRUE Access initialized successfuly
- @retval FALSE Failed to initialize access
-**/
-BOOLEAN
-BuildP2SbSidebandAccess (
- IN P2SB_PID P2SbPid,
- IN UINT16 Fid,
- IN P2SB_REGISTER_SPACE RegisterSpace,
- IN P2SB_SIDEBAND_ACCESS_METHOD AccessMethod,
- IN BOOLEAN PostedWrites,
- OUT P2SB_SIDEBAND_REGISTER_ACCESS *P2SbSidebandAccess
- );
-
-/**
- Builds P2SB sideband access using offset to config space.
- This offset will be added to every register offset, when access callbacks are used.
- Some IPs, like for example DMI, implement multiple register banks in the same register space.
- For instance sideband register space can contain both PCR registers,
- starting from the beginning of the register space,
- and PCI config registers starting from the offset in the same register space.
-
- @param[in] P2SbController Pointer to P2SB controller implementing the sideband
- @param[in] P2SbPid Port id
- @param[in] Fid Function id
- @param[in] RegisterSpace Target register space
- @param[in] AccessMethod Access method
- @param[in] PostedWrites If TRUE writes sent through sideband msg will be posted
- @param[in] Offset Register space offset that will be added to register offset
- @param[out] P2SbSidebandAccess An initialized sideband access descriptor containing register space offset
-
- @retval TRUE Access initialized successfuly
- @retval FALSE Failed to initialize access
-**/
-BOOLEAN
-BuildP2SbSidebandAccessEx (
- IN P2SB_CONTROLLER *P2SbController,
- IN P2SB_PID P2SbPid,
- IN UINT16 Fid,
- IN P2SB_REGISTER_SPACE RegisterSpace,
- IN P2SB_SIDEBAND_ACCESS_METHOD AccessMethod,
- IN BOOLEAN PostedWrites,
- IN UINT32 Offset,
- OUT P2SB_SIDEBAND_REGISTER_ACCESS *P2SbSidebandAccess
- );
-
-#endif
diff --git a/Silicon/CommonSocPkg/Library/PchPcrLib/PchPcrLib.inf b/Silicon/CommonSocPkg/Library/PchPcrLib/PchPcrLib.inf
index 7b91cbdf..d3f2d94d 100644
--- a/Silicon/CommonSocPkg/Library/PchPcrLib/PchPcrLib.inf
+++ b/Silicon/CommonSocPkg/Library/PchPcrLib/PchPcrLib.inf
@@ -32,6 +32,5 @@
IoLib
DebugLib
PchInfoLib
- GpioSiLib
[Pcd]