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  • 4e8e97a22a cores/spi/spi_bone: Cosmetic cleanups on FSM (rename states). Florent Kermarrec 2022-10-19 11:40:12 +02:00
  • bdfb032be9 cores/spi/spi_bone: More cosmetic cleanups. Florent Kermarrec 2022-10-19 11:21:33 +02:00
  • 0b05abb44f cores/spi/spi_bone: Rename self.wishbone to self.bus/bus. Florent Kermarrec 2022-10-19 11:10:21 +02:00
  • b6b3ab4f11 cores/spi/spi_bone: Move Clk edges detection and rename signals (rising -> posedge, falling -> negedge). Florent Kermarrec 2022-10-19 11:02:43 +02:00
  • 710a1958a4 cores/spi/spi_bone: Separate SPI IOs handling from Signals. Florent Kermarrec 2022-10-19 10:55:44 +02:00
  • 2a15ab554a cores/spi/spi_bone: Remove some duplicated code between 2 and 3 wires cases. Florent Kermarrec 2022-10-19 10:53:26 +02:00
  • eabdc0b7e9 cores/spi/spi_bone: Cosmetic cleanup pass (and remove unreachable ValueErrors). Florent Kermarrec 2022-10-19 10:48:13 +02:00
  • 296fc7add0 cores/spi/spi_bone: Spi -> SPI and rename SpiWishboneBridge to SPIBone. Florent Kermarrec 2022-10-19 10:37:11 +02:00
  • b6069a4d62 soc/cores/spi/spi_master: Remove SPISlave. Florent Kermarrec 2022-10-18 18:22:33 +02:00
  • 9f52ed1207 soc/cores/spi: Integrate SPIWishboneBridge from https://github.com/xobs/spibone. Sean Cross 2022-10-18 18:17:42 +02:00
  • f5c9425e14 soc/cores/spi: Create spi directory and split spi.py in spi_master/spi_slave. Florent Kermarrec 2022-10-18 18:15:17 +02:00
  • f7e05b1953 interconnect/axi: Add 8-bit/16-bit data-widths. Florent Kermarrec 2022-10-18 14:15:08 +02:00
  • 838a30f148 interconnect/stream/Monitor: Add reset/latch control from logic. Florent Kermarrec 2022-10-18 09:21:00 +02:00
  • 7bd0311947 interconnect/stream/Monitor: Fix packet support and cleanup. Florent Kermarrec 2022-10-17 18:42:34 +02:00
  • b990b90c0e soc/interconnect/stream/Monitor: Add Packets count (with configurable delimiter: first or last). Florent Kermarrec 2022-10-14 20:04:48 +02:00
  • a03013e427 ci: Bump to ubuntu 20.04. Florent Kermarrec 2022-10-14 18:21:19 +02:00
  • 24cfbd8d67 build/efinity: Update to 2022.1.226. Florent Kermarrec 2022-10-14 10:25:44 +02:00
  • 84db6a0b3a interconnect/axi: Add AXI version to AXIInterface (default to AXI4) and handle AXI3/AXI4 differences. Florent Kermarrec 2022-10-13 11:04:00 +02:00
  • a8070051b5 cpu/microwatt: Switch to VHD2VConverter to simplify code. Florent Kermarrec 2022-10-13 09:23:20 +02:00
  • 3e23ad3cff build/vhd2v_converter: Fix add_sources (to make it similar to platform.add_sources). Florent Kermarrec 2022-10-13 09:12:58 +02:00
  • 808cf1a466 Merge pull request #1460 from enjoy-digital/neorv32_params enjoy-digital 2022-10-12 21:18:14 +02:00
  • 74ae18ddaa cpu/neorv32/core: Avoid configure_litex_core_complex by passing params to new VHD2VConverter. Florent Kermarrec 2022-10-12 14:47:28 +02:00
  • efdc9ecef9 build/vhd2v_converter: Always do params -> constants translation. Florent Kermarrec 2022-10-12 14:35:43 +02:00
  • 03a5f16d70 build/vhd2v_converter: Add list of things to check. Florent Kermarrec 2022-10-12 12:07:41 +02:00
  • 00f29a3497 build: Rename VHDLWrapper to VHD2VConverter (more explicit). Florent Kermarrec 2022-10-12 11:57:21 +02:00
  • 848245bf59 build/sim/verilator: Add missing support_mixed_language property. Florent Kermarrec 2022-10-12 11:49:42 +02:00
  • c700f9d0ef Merge pull request #1453 from trabucayre/vhdl_wrapper enjoy-digital 2022-10-12 11:42:51 +02:00
  • bf1349bd17 Merge pull request #1458 from antmicro/rowhammer-etherbone-retry enjoy-digital 2022-10-12 11:27:43 +02:00
  • ac3699770c interconnect/stream/ClockDomainCrossing: Expose buffered parameter. Florent Kermarrec 2022-10-06 18:30:02 +02:00
  • 75bf668883 Merge pull request #1450 from tpwrules/improve-intel-pll-calculation enjoy-digital 2022-10-06 12:06:58 +02:00
  • b47ebf2ce7 Merge pull request #1449 from tpwrules/fix-quartus-clock-constraints enjoy-digital 2022-10-06 11:59:31 +02:00
  • 536e24f715 soc/cores/cpu/neorv32: convert to VHDLWrapper Gwenhael Goavec-Merou 2022-09-23 19:39:53 +02:00
  • 8eef2cda0d build/VHDLWrapper: adding a class to factorize VHDL handling Gwenhael Goavec-Merou 2022-09-23 19:34:25 +02:00
  • aa17c27eb9 interconnect/axi/axi_stream: Add clock_domain parameters. Florent Kermarrec 2022-10-05 11:06:52 +02:00
  • fea73d932e soc/cores/clock/intel: speed up PLL config computation Thomas Watson 2022-10-01 13:04:16 -05:00
  • b7ef989963 soc/cores/clock/intel_*: respect PFD input frequency Thomas Watson 2022-10-01 12:37:23 -05:00
  • d89d6dfd0a soc/cores/clock/intel_common: cleanup Thomas Watson 2022-10-01 12:28:32 -05:00
  • d531a07719 build/altera: fix clock constraints Thomas Watson 2022-09-30 23:33:52 -05:00
  • d27d6fca62 soc/cores/video: fix framebuffer color output Thomas Watson 2022-09-30 19:15:56 -05:00
  • 3836e8a36c Merge pull request #1447 from enjoy-digital/naxriscv-merge Dolu1990 2022-09-30 16:21:23 +02:00
  • 43699f2768 interconnect/axi/axi_common: Add missing param signals from connect_to_pads. Florent Kermarrec 2022-09-30 14:36:46 +02:00
  • c9f669d4ec Merge branch 'master' into naxriscv-merge Dolu1990 2022-09-30 13:37:03 +02:00
  • 79392e6eb8 soc/cores/jtag/Efinix: Cosmetic cleanups and rename EFINIX_JTAG to EfinixJTAG. Florent Kermarrec 2022-09-30 13:34:00 +02:00
  • b5b820b27f Merge pull request #1446 from enjoy-digital/vexriscv-smp-merge enjoy-digital 2022-09-30 13:17:13 +02:00
  • 622a35fd4e Improve naxriscv peripheral latency Dolu1990 2022-09-30 11:52:14 +02:00
  • cb0e9c23d3 Add Efinix JTAG support, with vexriscv-smp binding function Dolu1990 2022-09-30 11:48:07 +02:00
  • af58237203 software/demo: Add comments for Nix specific changes (To ease future maintenance and avoid breaking it). Florent Kermarrec 2022-09-29 17:29:53 +02:00
  • 1fb1cf19e5 Merge pull request #1434 from tpwrules/fix-bare-metal-demo enjoy-digital 2022-09-29 17:20:12 +02:00
  • c5eaac9c3e build/xilinx/vivado: Cosmetic cleanup. Florent Kermarrec 2022-09-29 17:16:16 +02:00
  • 28fb3962df Merge pull request #1444 from cklarhorst/more_vivado_options enjoy-digital 2022-09-29 17:12:44 +02:00
  • ad8b7da63d Merge pull request #1442 from trabucayre/video_swap_blue_red enjoy-digital 2022-09-29 17:04:09 +02:00
  • 8ffdc535d1 Vivado: Make directives configurable via argparser + add option to limit vivado threads Christian Klarhorst 2022-09-29 15:42:15 +02:00
  • dc0a4ea40b soc/cores/video: swap red and blue channel Gwenhael Goavec-Merou 2022-09-27 08:07:31 +02:00
  • c717e4c824 Merge pull request #1440 from cklarhorst/naxriscv Dolu1990 2022-09-26 12:48:47 +02:00
  • 9c43fe85c6 cpu/naxriscv: Add --no-netlist-cache Christian Klarhorst 2022-09-25 21:00:03 +02:00
  • 7795fba3cf cpu/naxriscv: Add --update-repo option & check for update errors Christian Klarhorst 2022-09-25 20:41:54 +02:00
  • 759530f272 build/generic_platform, generic_toolchain, yosys_nextpnr_wrapper: introduce the information about ability to do synthesis with mixed languages Gwenhael Goavec-Merou 2022-09-23 18:43:22 +02:00
  • b8e22fcd79 interconnect/axi: Simplify/Fix IOs generation. (Param signals were missing for AXIFull). Florent Kermarrec 2022-09-22 09:54:00 +02:00
  • 162a0a4c1e cpu/rocket: fix variant typos Gabriel Somlo 2022-09-20 09:29:46 -04:00
  • cb8e0193fc Added retransmission logic for EtherBone UDP reads. Maciej Kurc 2022-09-15 17:27:42 +02:00
  • e12af4f050 interconnect/axi/axi_stream: Fix get_ios and base it on length of created Endpoint's signals. Florent Kermarrec 2022-09-20 09:07:27 +02:00
  • 23db2e65f4 Merge pull request #1437 from trabucayre/yosys_nextpnr_refactor_args enjoy-digital 2022-09-19 19:29:34 +02:00
  • e9f6642d8f build/yosys,nextpnr, lattice: refactor args Gwenhael Goavec-Merou 2022-09-19 19:08:25 +02:00
  • 32272ba855 axi/axi_stream: Set default keep_width to None and automatically set it to data_width//8 when not specified. Florent Kermarrec 2022-09-19 13:26:36 +02:00
  • 860c757f33 Merge pull request #1435 from gsomlo/gls-yosys-flow3 enjoy-digital 2022-09-19 09:18:00 +02:00
  • 441042bef4 yosys_nextpnr_toolchain: add flow3 option to abc9 mode Gabriel Somlo 2022-09-18 08:25:32 -04:00
  • d7837f8751 demo: fix minor build issues Thomas Watson 2022-09-17 19:05:45 -05:00
  • c24bbedb68 interconnect/axi/axi_full: Fix AXIUpConverter compilation. Florent Kermarrec 2022-09-16 14:06:22 +02:00
  • 1e1e75dba7 software/bios/boot: Fix missing CONFIG_BIOS_NO_DELAYS update. Florent Kermarrec 2022-09-16 14:05:45 +02:00
  • fa902281aa integration/common/get_mem_data: Allow filemane_or_regions to be None and add endianness assertion. Florent Kermarrec 2022-09-16 14:05:20 +02:00
  • d36f98bf45 axi/axi_full: Simplify by switching AXI channels to AXIStreamInterface. Florent Kermarrec 2022-09-15 15:52:03 +02:00
  • bc385c7358 interconnect/axi/axi_stream: Simplify by always adding id/dest/user to endpoints and add layout/name parameters for more flexibility. Florent Kermarrec 2022-09-15 15:25:59 +02:00
  • 3cd4a3830c cores/dma/WishboneDMAWriter: Add ready_on_idle parameter and set it to 1 by default. Florent Kermarrec 2022-09-14 10:02:07 +02:00
  • 0adb604c97 Merge pull request #1423 from zyp/improve_dma enjoy-digital 2022-09-14 09:57:43 +02:00
  • 89bb688500 Merge pull request #1426 from enjoy-digital/naxriscv-merge Dolu1990 2022-09-12 23:25:47 +02:00
  • 0a380b9c3b cpu/NaxRiscv improve peripheral read/write speed by staying 32 bits Dolu1990 2022-09-12 19:19:35 +02:00
  • 8e7fd9bc1f Merge branch 'master' into naxriscv-merge Dolu1990 2022-09-12 19:18:12 +02:00
  • 23f529a313 soc/builder: Propagate data_width to get_mem_data. Florent Kermarrec 2022-09-12 16:46:20 +02:00
  • 481234de91 integration/common/get_mem_data: Add data_width support. Florent Kermarrec 2022-09-12 16:45:33 +02:00
  • a7cc1af416 soc: Propagate main bus address_width to the different interfaces dynamically created. Florent Kermarrec 2022-09-12 16:13:45 +02:00
  • 95bed6de5c interconnect/wishbone: Allow passing address_width (In byte addressing). Florent Kermarrec 2022-09-12 16:12:52 +02:00
  • 91c521a22a Changes: Prepare for next release changes. Florent Kermarrec 2022-09-12 11:08:50 +02:00
  • ded3bad178 cpu/naxriscv: Minor cleanups on recent changes. Florent Kermarrec 2022-09-12 11:01:39 +02:00
  • f2a088bfcc Merge pull request #1355 from cklarhorst/master Dolu1990 2022-09-12 10:18:22 +02:00
  • fa0c2df687 CHANGES: Update and release. Florent Kermarrec 2022-09-12 09:00:36 +02:00
  • 3c4c12a72f cores/dma: End transfer when the last flag is set. Vegard Storheil Eriksen 2022-09-10 10:15:23 +02:00
  • 6ad6d1e414 cores/dma: Don’t drop data while idle. Vegard Storheil Eriksen 2022-09-10 10:13:18 +02:00
  • 6367fc6cab update naxriscv comments Christian Klarhorst 2022-09-09 13:19:36 +02:00
  • 15f72174ce interconnect/axi/axi_full: Add region signal to aw/ar and optional user signal to aw/w/b/ar/r channels. Florent Kermarrec 2022-09-09 12:46:31 +02:00
  • 14160ce7e3 cpu/NaxRiscv update nax with peripheral memory region Dolu1990 2022-09-09 11:23:24 +02:00
  • b7e2d24f37 interconnect/wishbone/DownConverter: Avoid FSM and Idle cycle. Florent Kermarrec 2022-09-08 17:41:24 +02:00
  • a04f20880f Change naxriscv memory-region format Christian Klarhorst 2022-09-08 17:33:20 +02:00
  • e5de4b356a interconnect/axi/axi_lite: Add prot signal. Florent Kermarrec 2022-09-08 12:06:35 +02:00
  • 3b714c8145 test: Add minimal test_axi_stream test (Just syntax check for now). Florent Kermarrec 2022-09-08 11:53:05 +02:00
  • afc89c9350 interconnect/axi/axi_stream: Add ID/Dest support and minor cleanup. Florent Kermarrec 2022-09-08 11:51:55 +02:00
  • 5b8d3651a9 software/liblitedram: Enable ECP5DDRPHY features on GW2DDRPHY (since very similar). Florent Kermarrec 2022-09-07 16:27:54 +02:00
  • ee536f9cd5 CONTRIBUTORS: Update. Florent Kermarrec 2022-09-07 10:13:17 +02:00
  • 85e8aab5ae tools/litex_contributors: Sort contributors by names. Florent Kermarrec 2022-09-07 10:07:12 +02:00
  • 0bd19fd026 tools/litex_contributors: Rename authors to contributors. Florent Kermarrec 2022-09-07 09:49:26 +02:00
  • 0144612751 tools/litex_contributors: Add RapidSilicon to companies. Florent Kermarrec 2022-09-07 09:46:59 +02:00