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  • 860ca8673e json2renode: Use opensbi->base for bios binary Mateusz Karlic 2022-09-22 13:25:45 +02:00
  • ca63d12509 json2renode: Add support for multicore builds Mateusz Karlic 2022-09-22 12:32:31 +02:00
  • 240b24b7ff gen/fhdl/hierarchy: Use [] for BlackBoxes. Florent Kermarrec 2022-11-08 15:07:58 +01:00
  • b32d694ae4 interconnect/axi: Do not expose dest on AXI-Full (Only present for on AXI-Stream). Florent Kermarrec 2022-11-08 14:51:37 +01:00
  • f617e823b9 Merge pull request #1495 from Icenowy/openc906-debug enjoy-digital 2022-11-08 14:01:40 +01:00
  • 85273ffe99 cpu/openc906: add debug variant that connects CPU DM to main bus Icenowy Zheng 2022-11-07 11:53:40 +08:00
  • 9493338c68 cpu/openc906: fix the semantics of self.reset Icenowy Zheng 2022-11-07 11:51:38 +08:00
  • ff3bd11de1 Merge pull request #1494 from trabucayre/parset_fix_target_group enjoy-digital 2022-11-07 21:03:37 +01:00
  • 98912f45e0 litex/build/parser: check if self._target_group is not None before calling add_argument Gwenhael Goavec-Merou 2022-11-07 20:40:09 +01:00
  • 3269d12a27 gen/fhdl/hierarchy: Use ** for BlackBox for black/white consoles. Florent Kermarrec 2022-11-07 19:19:14 +01:00
  • f43b92103a build/sim/core/Makefile: Add -Wno-COMBDLY and -Wno-CASEINCOMPLETE flags to disable more these warnings (thanks @suarezvictor). Florent Kermarrec 2022-11-07 15:26:35 +01:00
  • 3c52d440a6 build/parser: Fix CPU listing when invalid one is provided and simplify. Florent Kermarrec 2022-11-07 13:34:09 +01:00
  • 1ce3271efe build/parser: Add LiteXSoCArgumentParser compatibility and switch to it in integration/soc. Florent Kermarrec 2022-11-07 13:16:24 +01:00
  • a2cb04b218 LICENSE: Update. - Update project description. - Add plain text BSD 2-Clause License for Github detection. - Add LiteX developers to copyrights (similar to README). - Add "moral" conditions for use of the project. Florent Kermarrec 2022-11-07 10:00:59 +01:00
  • 9ccf08e22d build/parser: Rename soc_core_argdict to soc_argdict. Florent Kermarrec 2022-11-07 08:45:24 +01:00
  • 2e46a81bf6 tools/litex_sim: hack to allow memory base other than 0x40000000 Icenowy Zheng 2022-11-04 22:19:20 +08:00
  • 3b4bb083d4 build/parser: Fix CPU's args_read. Florent Kermarrec 2022-11-06 21:51:29 +01:00
  • 621c5cc187 build/argument_parser: Rename to parser to simplify name/imports. Florent Kermarrec 2022-11-06 21:36:00 +01:00
  • 6b541fb4fb build/nextpnr/yosys_wrapper: -x. Florent Kermarrec 2022-11-06 21:21:15 +01:00
  • c62306d57e build/argument_parser: Minor styles changes. Florent Kermarrec 2022-11-06 21:19:17 +01:00
  • 8040c83268 build/xilinx/platform: serie7 -> 7series. Florent Kermarrec 2022-11-06 21:16:43 +01:00
  • b9b165d25d Merge pull request #1418 from trabucayre/rework_toolchain_args enjoy-digital 2022-11-06 21:15:36 +01:00
  • ad7ded9358 litex/litex/build: adding argument_parser (LiteXArgumentParser) to factorize toolchain aspects and common args Gwenhael Goavec-Merou 2022-11-04 21:05:04 +01:00
  • d061e9b9cf build/xxx/platform: adding methods to return toolchains list by device, and args by toolchain Gwenhael Goavec-Merou 2022-09-03 23:15:11 +02:00
  • 38ee44a85a axi/axi_full: size/lock width are different on AXI3 and AXI4. Florent Kermarrec 2022-11-04 12:35:09 +01:00
  • 8f459a27dd integration/common/get_mem_data: Remove dead code (thanks @Rongronggg9). Florent Kermarrec 2022-11-04 10:21:12 +01:00
  • adea7879d7 gen/fhdl/verilog: Add Verilog Timescale generation. Florent Kermarrec 2022-11-04 08:15:36 +01:00
  • 2ae445018a Merge pull request #1489 from shenki/crc-pie-fix enjoy-digital 2022-11-04 07:52:45 +01:00
  • 3a5a2b5c7d Merge pull request #1488 from Icenowy/wide-soc enjoy-digital 2022-11-04 07:49:27 +01:00
  • a253d7addc Merge pull request #1487 from Icenowy/c906-ethmac-map enjoy-digital 2022-11-04 07:42:56 +01:00
  • dd0918e9cc Do not build software as PIE Joel Stanley 2022-11-04 16:19:02 +10:30
  • 879f1b38bc integration/soc/add_sdram: connect to main bus with its data width Icenowy Zheng 2022-11-03 20:22:15 +08:00
  • 5ff23066b7 integration/common/get_mem_data: add support for wider data widths Icenowy Zheng 2022-11-03 20:20:52 +08:00
  • dd6e4868f2 cpu/openc906: add ethmac to memory map and misc changes Icenowy Zheng 2022-11-03 15:44:09 +08:00
  • b107d4a6fe Make keep attribute for add_period_constraint optional. Vivado 2019 barfs upon IDELAYCTRL automatically replicated and it's refclk set to dont_touch. Vamsi Vytla 2022-11-03 21:26:28 -07:00
  • eb2e9a371d Merge pull request #1485 from Icenowy/64bit-systembus-csr-fix enjoy-digital 2022-11-03 21:27:19 +01:00
  • b8e007540c Merge pull request #1486 from alanvgreen/terms enjoy-digital 2022-11-03 21:25:48 +01:00
  • 61be01ebd4 litex/soc: update API to avoid unfortunate terms Alan Green 2022-11-04 04:09:16 +11:00
  • 21e46b6b6c tools/litex_sim: Avoid use of SoCCore.add_memory_region/add_wb_slave. Florent Kermarrec 2022-11-03 19:22:26 +01:00
  • 964c82e4e8 soc_core: Move methods that are no longer recommended to compat_soc_core and add compat_notice to them. Florent Kermarrec 2022-11-03 19:10:31 +01:00
  • f64dc2b799 gen/fhdl/hierachy: Improve and give names to unnamed modules. Florent Kermarrec 2022-11-03 16:20:07 +01:00
  • 9321380f48 litex/gen/fhdl: Add initial LiteXHierarchyExplorer and use it to display hierarchy when building SoC. Florent Kermarrec 2022-11-03 10:57:40 +01:00
  • 507ffb72b5 colorer: Avoid duplication and move it to litex/gen. Florent Kermarrec 2022-11-03 09:49:51 +01:00
  • 3986a5b27e Merge pull request #1484 from cklarhorst/i2c_addr enjoy-digital 2022-11-03 09:25:41 +01:00
  • 0c705537af soc/interconnect/csr: Fix CSR on 64-bit SoC bus width Icenowy Zheng 2022-11-02 23:30:40 +08:00
  • fa3b4a1f1f soc/software: Support non 8bit i2c memory addresses Christian Klarhorst 2022-11-02 12:42:08 +01:00
  • f71bda1c61 Merge pull request #1482 from Icenowy/openc906-fix enjoy-digital 2022-11-02 08:36:33 +01:00
  • 0f097fd4c7 cpu/openc906: misc fixes/enhancements related to L1$ Icenowy Zheng 2022-11-01 16:10:46 +08:00
  • cd2805b422 soc/SoCBusHandler: Set default _interconnect to None. Florent Kermarrec 2022-10-31 09:40:36 +01:00
  • c71db5159b Merge pull request #1448 from tpwrules/fix-framebuffer-colors enjoy-digital 2022-10-30 21:26:10 +01:00
  • 9497b0cdf5 Merge pull request #1481 from alanvgreen/with-cxx enjoy-digital 2022-10-30 21:25:37 +01:00
  • 3704e36c7e Merge pull request #1476 from shenki/riscv-toolchain enjoy-digital 2022-10-30 21:25:18 +01:00
  • 7142d25e98 Merge pull request #1475 from shenki/vhd2v-ghdl enjoy-digital 2022-10-30 21:24:44 +01:00
  • 59d10b8672 Merge pull request #1480 from Icenowy/axifull-downconv-fix enjoy-digital 2022-10-30 21:17:10 +01:00
  • 57a35d7a70 soc/software/demo/Makefile: define WITH_CXX Alan Green 2022-10-31 06:10:06 +11:00
  • 5240d28817 cpu/openc906: fixes to get it work again Icenowy Zheng 2022-10-30 19:55:36 +08:00
  • ab4880c97e interconnect/axi/axi_full: Fix AXIDownConverter compilation. Icenowy Zheng 2022-10-30 17:24:32 +08:00
  • 0e2a1b54a4 riscv: Fix compilation with new binutils Joel Stanley 2022-10-28 14:48:02 +10:30
  • deafbf5efe vhd2v: Use GHDL directly Joel Stanley 2022-10-28 10:21:53 +10:30
  • e3c33191b0 Merge pull request #1474 from trabucayre/f4pga_edalize enjoy-digital 2022-10-29 12:46:17 +02:00
  • 0855612b6d build/lattice/icestorm: use PNR getter to fill edalize dict Gwenhael Goavec-Merou 2022-10-29 11:16:55 +02:00
  • 50ffd0cd02 build/{nextpnr_wrapper, yosys_nextpnr_toolchain}: adding getter to retrieve pnr configuration Gwenhael Goavec-Merou 2022-10-29 11:15:52 +02:00
  • 50cf037bef build/xilinx/f4pga: adding edalize backend support Gwenhael Goavec-Merou 2022-10-29 09:14:49 +02:00
  • 949f262ce9 build/xilinx/f4pga: XDC -> xdc Gwenhael Goavec-Merou 2022-10-29 09:14:05 +02:00
  • 79cc3698b8 build/generic_toolchain, build/lattice/icestorm: tool_options is now a dict {key, value} (with value can be a dict) => edaflow compat Gwenhael Goavec-Merou 2022-10-29 09:12:51 +02:00
  • ab6bb331fd build/generic_toolchain: space before = Gwenhael Goavec-Merou 2022-10-29 09:08:19 +02:00
  • 2086cced22 soc/interconnect/csr_eventmanager: Also switch to new Reduce. Florent Kermarrec 2022-10-28 19:38:45 +02:00
  • 2829ca93f7 litex/gen: Move LiteXModule to gen/fhdl/module.py. Florent Kermarrec 2022-10-28 19:38:24 +02:00
  • e3e99c527c soc/cores/interconnect: Switch most of the cores to new Reduce. Florent Kermarrec 2022-10-28 19:31:33 +02:00
  • a10b1fd1e6 gen/common/Reduce: Add ADD support. Florent Kermarrec 2022-10-28 19:13:27 +02:00
  • 5106fd43fc gen/common: Add Reduction function (To avoid using Python's reduction directly which is messy/confusing). Florent Kermarrec 2022-10-28 15:09:29 +02:00
  • 13448b8260 soc/SoCBusHandler: Integrate interconnect code since avoid duplication and simplify reuse. Florent Kermarrec 2022-10-28 12:43:00 +02:00
  • 3603e90ed8 integration/soc/SoC: Add collection of CSRs described in Main Module (ie Top-Level). Florent Kermarrec 2022-10-28 10:01:33 +02:00
  • 1f2d4f017a integration/soc: Switch to LiteXModule and from self.submodules/self.clock_domains to self. Florent Kermarrec 2022-10-27 16:03:01 +02:00
  • f8702d744f gen/common/LiteXModule: Also inherit from AutoDoc. Florent Kermarrec 2022-10-27 15:52:21 +02:00
  • a71fd1d31b gen/common: Introduce LiteXModule class to simplify Modules creation and avoid common mistakes. Florent Kermarrec 2022-10-27 15:27:57 +02:00
  • e570b612b2 Merge pull request #1470 from shenki/update-microwatt Tim 'mithro' Ansell 2022-10-26 21:10:32 -07:00
  • 4ccf9f487d microwatt: Fix irq variant Joel Stanley 2022-10-26 17:27:15 +10:30
  • d45d3532fe microwatt: Update to latest Joel Stanley 2022-10-26 16:34:18 +10:30
  • f95cf6ab2d vhd2v: Fix mixed langauge support Joel Stanley 2022-10-26 16:29:53 +10:30
  • 611b84ccee build/sim/Verilator: Skip .hex in sources. Florent Kermarrec 2022-10-24 18:21:10 +02:00
  • af445e93dd build/vendor/common: Minor style cleanup. Florent Kermarrec 2022-10-24 09:33:22 +02:00
  • 88d89773ef interconnect/csr: Sort by DUID even with sort=False (for retro-compatibility). Florent Kermarrec 2022-10-22 09:21:37 +02:00
  • 50acdf73a4 interconnect/csr_bus: Add missing part of the previous fix... Florent Kermarrec 2022-10-21 23:06:25 +02:00
  • 76d3a77cf3 interconnect/csr_bus: Fix build with custom get_csrs/get_constants from cores. Florent Kermarrec 2022-10-21 22:01:34 +02:00
  • d30f780a87 fhdl/verilog: Switch tab to 4 spaces. Florent Kermarrec 2022-10-21 19:49:04 +02:00
  • 84c3e9c50e fhdl/verilog: Make tab configurable. Florent Kermarrec 2022-10-21 19:47:28 +02:00
  • 1f58ce3c31 gen/fhdl/verilog: Improve _print_signal to align signals definition. Florent Kermarrec 2022-10-21 19:39:02 +02:00
  • b6e672a060 fhdl/verilog: Move inline verilog attribute to previous line to improve readability of the generated verilog. Florent Kermarrec 2022-10-21 19:19:28 +02:00
  • 096f2184e6 soc/interconnect/csr: Replace level with sort and fix targets compilation. Florent Kermarrec 2022-10-21 18:54:12 +02:00
  • 14b2829a5f Merge pull request #1467 from enjoy-digital/csr_mapping enjoy-digital 2022-10-21 18:36:26 +02:00
  • a60a51c52f interconnect/csr: Only sort gathered items at Module level. Florent Kermarrec 2022-10-21 16:04:23 +02:00
  • a57f0640cc soc/interconnect/csr: Add optional support fixed CSR mapping. Florent Kermarrec 2022-10-21 14:45:46 +02:00
  • 804a1a5b26 soc/add_uart: Improve error message for unsupported UART. Florent Kermarrec 2022-10-21 09:03:25 +02:00
  • 73d70cf594 build/sim/platform: Remove add_csr calls no longer required. Florent Kermarrec 2022-10-21 08:43:51 +02:00
  • 525bbd19a9 Merge pull request #1465 from mohamedElbouazzati/cv32e41p_interrupts enjoy-digital 2022-10-20 16:00:39 +02:00
  • 85e9881f45 Fix IRQS for cv32e41p mohamedElbouazzati 2022-10-19 17:48:36 +02:00
  • da8d3d10aa tools/litex_read_verilog: Add proc step before exporting to .json since now seems to be required for some verilog designs. Florent Kermarrec 2022-10-19 15:29:00 +02:00
  • 89670e5938 soc/cores/spi: Add SPIBone import. Florent Kermarrec 2022-10-19 15:21:31 +02:00
  • 519b411954 core/spi/spi_bone: Update header. Florent Kermarrec 2022-10-19 11:40:51 +02:00