enjoy-digital
ffcf2fca49
Merge branch 'master' into cva5
2022-05-25 15:18:17 +02:00
Florent Kermarrec
3e388a5b58
cores/cpu: Improve address readability with underscores.
2022-05-25 11:40:35 +02:00
Florent Kermarrec
e1c132809e
cpu/cva6: Only keep AXI<->AXI-Lite conversion.
2022-05-25 11:28:32 +02:00
Florent Kermarrec
808f29ed2e
cpu/cva6/core: Cleanup/Simplify integration.
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- Cosmetic changes and increase similarities with other CPUs.
- Simplification.
- Allow converting AXI to Wishbone or AXI-Lite (Still keep wishbone as default).
- Connect reset from SoC.
- Reorder AXI signals by channels.
- Move JTAG integration to add_jtag method.
2022-05-25 10:20:09 +02:00
Florent Kermarrec
69451fad09
test/test_cpu: Disable test_cva6 for now since seems to be failing.
2022-05-25 09:32:30 +02:00
Florent Kermarrec
db407b973c
litex_setup: Switch CVA6 to litex-hub and order CPU list per ISA.
2022-05-25 09:29:23 +02:00
Florent Kermarrec
73c76c6126
tools/litex_sim: Add pre-definied commented config flags.
2022-05-25 09:17:36 +02:00
Florent Kermarrec
7028745829
bios/main: Add CONFIG_BIOS_NO_CRC to disable CRC Check (Useful in simulation).
2022-05-25 09:16:48 +02:00
Florent Kermarrec
de6f9e7e83
soc/bios: Cleanup bios manual config flags.
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- CONFIG_WITH_BUILD_TIME -> CONFIG_BIOS_NO_BUILD_TIME.
- CONFIG_SIM_DISABLE_PROMPT -> CONFIG_BIOS_NO_PROMPT.
- CONFIG_DISABLE_DELAYS -> CONFIG_BIOS_NO_DELAYS.
2022-05-25 09:03:45 +02:00
enjoy-digital
b033d91738
Merge pull request #1294 from suppamax/cva6
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add cva6 cpu
2022-05-24 19:28:57 +02:00
Florent Kermarrec
a67cd6e442
build/osfpga: Add include_path support.
2022-05-24 17:33:03 +02:00
Florent Kermarrec
3bf5c11928
build/osfpga: Add test_soc.py to test simple SoC builds.
2022-05-24 17:33:00 +02:00
Florent Kermarrec
5140668c31
build/osfpga: Rename blinky.py to test_blinky.py.
2022-05-24 17:32:54 +02:00
Florent Kermarrec
5bdc0cbc63
build/osfpga: Add macros dict and use it for now to derivate macro from device.
2022-05-24 17:32:49 +02:00
enjoy-digital
c2e9125d05
Merge pull request #1309 from jevinskie/jev/bug/intel-clocking-indent
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Intel Clocking: compute_config() fix indent causing PLL config error
2022-05-24 09:31:54 +02:00
Jevin Sweval
68fe6a30fd
Intel Clocking: compute_config() fix indent causing PLL config error
2022-05-23 12:12:32 -07:00
enjoy-digital
6e42082128
Merge pull request #1307 from jevinskie/jev/feat/altera_reset_pretty_names
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AlteraAsyncResetSynchronizer: prettify instance names
2022-05-23 10:00:16 +02:00
enjoy-digital
90840ff953
Merge pull request #1305 from jevinskie/jev/feat/platform_request_remaining
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Add request_remaining("name") that returns unallocated pins.
2022-05-23 09:57:29 +02:00
enjoy-digital
b510157b2f
Merge pull request #1304 from jevinskie/jev/bug/quartus-error-bailout
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Quartus build: bail out on error
2022-05-23 09:56:32 +02:00
Jevin Sweval
7d1c9a9001
AlteraAsyncResetSynchronizer: prettify instance names
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This makes debugging e.g. conflicting drivers easier since the errors will display the clock domain name.
2022-05-21 16:22:41 -07:00
Jevin Sweval
0b9ffb6adb
Add request_remaining("name") that returns unallocated pins.
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Improve error reporting on request_all().
2022-05-21 16:03:56 -07:00
Jevin Sweval
9f7028e088
Quartus build: bail out on error
2022-05-21 16:02:25 -07:00
Florent Kermarrec
a426ec9e2f
cpu/vexriscv_smp/core: Only use Linux variant (Since similar to standard).
2022-05-20 18:52:46 +02:00
enjoy-digital
9ee9eb16a4
Merge pull request #1302 from tonymcdowell-rs/master
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litex_setup: fix path reference for python3 binary on non-Linux hosts
2022-05-20 12:12:27 +02:00
Tony McDowell
2e9b0331db
litex_setup: fix path reference for python3 binary on non-Linux hosts
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the python binary is stored in the "Program Files" directory. without
delimiting the path the calls to the binary will fail on Windows hosts.
2022-05-19 12:50:50 -06:00
