Florent Kermarrec
557ebcedfb
liblitesata/sata_init: Always reinitialize core on call (Even when already ready).
2022-04-15 13:53:18 +02:00
Florent Kermarrec
ceb25445d2
wishbone/sram/burst: First review/Minor cleanups.
2022-04-15 09:03:12 +02:00
enjoy-digital
9c4778b2c1
Merge pull request #1267 from antmicro/wb-sram-inc-burst
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soc/interconnect/wishbone: Add incrementing address burst mode to SRAM
2022-04-15 08:47:42 +02:00
Florent Kermarrec
8b2fc201cf
soc/cores/uart: Add assert data_width == address_width to prevent building broken logic and pass data_width/address_width to Wishbone.
2022-04-15 08:39:45 +02:00
enjoy-digital
fac39c8210
Merge pull request #1275 from fjullien/efinix_ifacewriter_add_gpio_options
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Efinix ifacewriter add gpio options
2022-04-15 08:19:57 +02:00
enjoy-digital
08cd4803f3
Merge pull request #1274 from fjullien/fix_efinix_pll
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Fix efinix pll
2022-04-15 08:19:18 +02:00
Franck Jullien
e86c06c9ff
efinix:clock: improve logging informations
2022-04-14 10:48:51 +02:00
Franck Jullien
25b4eb7b0b
efinix: dont print info in get_pll_resource
2022-04-14 10:48:51 +02:00
Franck Jullien
5f9d943d36
efinix: get_free_pll_resource needs to call get_pll_resource
2022-04-14 10:48:51 +02:00
Franck Jullien
66e49249cc
efinix:ifacewriter: add out_clk_inv and in_clk_inv to gpio block
2022-04-14 10:42:55 +02:00
Franck Jullien
78c35365e8
efinix:ifacewriter: add in_reg and out_reg to gpio block
2022-04-14 10:42:48 +02:00
Florent Kermarrec
63356b8187
cpu/naxriscv: Minor cleanups.
2022-04-14 10:12:45 +02:00
Florent Kermarrec
0a738002e0
openocd/jtag: Add JTAG-UART/JTABBone support to Zynq7000/ZynqMPSoC and define all Xilinx IRs for USERX.
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Thanks @smunaut for the initial investigation/implementation. The changes have been minimized to:
- Adding an optional delay in TDI: On Zynq devices, TDI is delayed by 1 TCK to bypass the PS tap.
- Avoiding OpenOCD's -endstate DRPAUSE on Xilinx that does not seem required.
2022-04-14 09:51:03 +02:00
Dolu1990
be43ef6424
cpu/NaxRiscv: Now support reset from the jtag
2022-04-12 19:38:36 +02:00
Rafal Kolucki
8c1bc139ab
soc/interconnect/wishbone: Cleanup in burst cycles support logic
2022-04-12 15:32:29 +02:00
Rafal Kolucki
ad46a57403
test/test_wishbone: Add test for Wishbone SRAM constant address burst cycle
2022-04-12 14:06:22 +02:00
Rafal Kolucki
cdd216f692
test/test_wishbone: Add basic test for SRAM with burst cycles support
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Tests incrementing address burst cycle with linear and wrapped increments.
Only 4-beat wrap burst is tested in `test_sram_burst_wrap` test.
2022-04-12 14:06:22 +02:00
Rafal Kolucki
c00ca99ea9
soc/interconnect/wishbone: Add burst params to Interface test functions
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This commit also replaces hardcoded CTI signal values with constants.
2022-04-12 14:06:22 +02:00
Rafal Kolucki
83ea56aeee
soc/interconnect/wishbone: Move burst cycles support option to SoCBusHandler/SoC classes
2022-04-12 14:06:22 +02:00
Rafal Kolucki
ca78f799e1
soc/integration/soc_core: Add SRAM/ROM burst cycles support switch
2022-04-12 14:06:22 +02:00
Rafal Kolucki
54f897f446
soc/interconnect/wishbone: Make burst cycles support in SRAM optional
2022-04-12 14:06:22 +02:00
Rafal Kolucki
8ef51a00ee
soc/interconnect/wishbone: Add incrementing burst cycles support to SRAM
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This commit adds support for incrementing burst cycles in SRAM peripheral.
By default it's enabled, but can be disabled by passing `burst=False`
to the class while initializing, if it won't be useful for created design
(e.g. no Wishbone bus masters with burst support).
2022-04-12 14:06:22 +02:00
Florent Kermarrec
7416943f9c
cores/usb_fifo: Re-implement FT245PHYSynchronous, passing simple tests on FT601/LimeSDRMini-V2.0.
2022-04-11 19:23:58 +02:00
Florent Kermarrec
7187ac22e4
interconnect/axi: Add AXSIZE dict definition.
2022-04-11 19:20:22 +02:00
Florent Kermarrec
1989d85b91
software/libbase/i2c/i2c_poll: Also test for write when polling since some I2C devices do not respond to read or require a specific protocol.
2022-04-11 09:52:00 +02:00
