Florent Kermarrec
924da55ea0
stream/AsyncFIFO: Add a minimum of 2 buffers on Efinix FPGAs to fix issues on hardware.
...
Root cause still need to be understand, but when testing with another AsyncFIFO (from verilog axis),
the behavior was similar. So is it an Efinity issue? Constraint issue?
2023-07-27 13:29:05 +02:00
Florent Kermarrec
72a1592bee
litex/gen: Add initial/minimal LiteXContext to easily get build context from modules.
...
Still a PoC and need to think a bit more about it, but will allow fixing AsyncFIFO issue
on Efinix FPGAs.
2023-07-27 13:27:15 +02:00
Florent Kermarrec
20ce982da2
software/bios: Fix missing CSR_SDCARD_CORE_BASE update.
2023-07-26 16:30:52 +02:00
Florent Kermarrec
66b44ecd60
soc/add_uart: Fix stub behavior (sink/source swap), thanks @zyp.
2023-07-26 12:26:16 +02:00
Florent Kermarrec
0f1fdea893
build/xilinx/vivado: Also generate design checkpoint after synthesis and placement.
...
This help exploring/constraining complex designs by using Vivado GUI and design checkpoint.
2023-07-21 19:53:28 +02:00
Florent Kermarrec
35cd744adc
CHANGES: Update.
2023-07-21 15:16:42 +02:00
Florent Kermarrec
330d61d2bd
soc/add_pcie: Remove MSI workaround on Ultrascale(+) now that root cause is understood/fixed (thanks @smunaut).
2023-07-21 14:50:38 +02:00
Florent Kermarrec
aae15737cd
CHANGES: Update.
2023-07-20 16:30:48 +02:00
Florent Kermarrec
c00f61d9d7
tools: Update to new sdcard core name.
2023-07-20 16:29:05 +02:00
Florent Kermarrec
6693a723d1
software: Update to new sdcard core name.
2023-07-20 16:28:51 +02:00
Florent Kermarrec
0152e7de8e
soc/add_sata: Use name parameter to allow multiple sdcard instances.
2023-07-20 16:28:22 +02:00
Florent Kermarrec
e364316814
soc/add_sata: Use name parameter to allow multiple sata instances.
2023-07-20 16:02:03 +02:00
Florent Kermarrec
f995d74e55
soc/add_uartbone: Rename name parameter to uart_name to allow multiple uartbone (also for consistency with other cores) and other minor cleanups.
2023-07-20 15:42:03 +02:00
Florent Kermarrec
6e78db6767
soc/add_bus_master: Use name where possible to avoid automatic naming and improve log readability.
2023-07-20 15:15:44 +02:00
Florent Kermarrec
f6da67fb38
soc/add_pcie: Add optional data_width parameter.
2023-07-20 10:35:10 +02:00
Florent Kermarrec
69c6fa11d2
build/lattice/common/lattice_ecp5_trellis_special_overrides: Add missing DifferentialOutput.
2023-07-17 17:08:35 +02:00
Florent Kermarrec
6ab156e225
soc/cores: Fix regressions.
2023-07-17 11:48:39 +02:00
Florent Kermarrec
79a82dc732
tools/litex_json2dts_linux: Remove duplicated clock definition.
...
Keep clock definition introduced by 9b67898e99
2023-07-17 11:27:07 +02:00
Florent Kermarrec
3d101b9749
integration/export: When csr_base is specified, make CSR regions definition relative to it.
...
Useful for PCIe based systems when internal CSR base is automatically added by the logic.
2023-07-17 11:14:33 +02:00
Florent Kermarrec
3fc16f54f1
soc/cores/cpu: Switch to LiteXModule.
2023-07-17 09:26:58 +02:00
Florent Kermarrec
39ff69ade7
cores/spi: Switch to LiteXModule.
2023-07-17 09:14:47 +02:00
Florent Kermarrec
028f7eb72f
cores/ram: Switch to LiteXModule.
2023-07-17 09:12:25 +02:00
Florent Kermarrec
b35c6580e8
soc/cores/clock: Switch to LiteXModule.
2023-07-15 21:54:07 +02:00
Florent Kermarrec
8103cf7851
soc/cores: Switch cores to LiteXModule (still need to do cpu, ram, clk, spi).
2023-07-14 22:19:14 +02:00
Florent Kermarrec
6e46710678
gen/fhdl/module: Fix CSR clock domain renaming to cores converted to LiteXModule, thanks @smunaut.
2023-07-14 10:01:32 +02:00
