stream/AsyncFIFO: Add a minimum of 2 buffers on Efinix FPGAs to fix issues on hardware.

Root cause still need to be understand, but when testing with another AsyncFIFO (from verilog axis),
the behavior was similar. So is it an Efinity issue? Constraint issue?

litex/soc/interconnect/stream.py

@@ -13,6 +13,8 @@ from migen.util.misc import xdir
 from migen.genlib import fifo
 from migen.genlib.cdc import MultiReg, PulseSynchronizer, AsyncResetSynchronizer
 
+from litex.gen import LiteXContext
+
 from litex.soc.interconnect.csr import *
 
 # Endpoint -----------------------------------------------------------------------------------------
@@ -234,10 +236,19 @@ class AsyncFIFO(_FIFOWrapper):
     def __init__(self, layout, depth=None, buffered=False):
         depth = 4 if depth is None else depth
         assert depth >= 4
+        nbuffers = 0
+        if buffered:
+            nbuffers = 1
+        from litex.build.efinix import EfinixPlatform
+        if isinstance(LiteXContext.platform, EfinixPlatform):
+            nbuffers = 2 # Minimum of 2 buffers required on Efinix FPGAs.
         _FIFOWrapper.__init__(self,
-            fifo_class = fifo.AsyncFIFOBuffered if buffered else fifo.AsyncFIFO,
+            fifo_class = fifo.AsyncFIFOBuffered if nbuffers > 0 else fifo.AsyncFIFO,
             layout     = layout,
-            depth      = depth)
+            depth      = depth
+        )
+        if nbuffers > 1:
+            ClockDomainsRenamer("read")(BufferizeEndpoints({"source": DIR_SOURCE})(self))
 
 # ClockDomainCrossing ------------------------------------------------------------------------------