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KabylakeOpenBoardPkg/AspireVn7Dash572G: Duplicate KabylakeRvp3 directory

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This makes diffing the follow-up board changes easier.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
This commit is contained in:
Benjamin Doron
2021-08-18 11:48:57 -07:00
committed by Nate DeSimone
parent 4659ef048a
commit cf57743b49
55 changed files with 8384 additions and 0 deletions
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115
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c Normal file
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/** @file
This file is SampleCode of the library for Intel PCH PEI Policy initialization.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "PeiPchPolicyUpdate.h"
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/HobLib.h>
#include <Guid/GlobalVariable.h>
#include <Library/PchGbeLib.h>
#include <Library/PchInfoLib.h>
#include <Library/PchPcrLib.h>
#include <Library/PchHsioLib.h>
#include <Library/PchSerialIoLib.h>
#include <Library/PchPcieRpLib.h>
#include <GpioConfig.h>
#include <GpioPinsSklH.h>
#include <Library/DebugLib.h>
#include <Library/PchGbeLib.h>
#define PCI_CLASS_NETWORK 0x02
#define PCI_CLASS_NETWORK_ETHERNET 0x00
#define PCI_CLASS_NETWORK_OTHER 0x80
GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = {
//
// Intel PRO/Wireless
//
{ 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
//
// Intel WiMAX/WiFi Link
//
{ 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
//
// Intel Crane Peak WLAN NIC
//
{ 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
//
// Intel Crane Peak w/BT WLAN NIC
//
{ 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
//
// Intel Kelsey Peak WiFi, WiMax
//
{ 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
//
// Intel Centrino Wireless-N 105
//
{ 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
//
// Intel Centrino Wireless-N 135
//
{ 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
//
// Intel Centrino Wireless-N 2200
//
{ 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
//
// Intel Centrino Wireless-N 2230
//
{ 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
//
// Intel Centrino Wireless-N 6235
//
{ 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
//
// Intel CampPeak 2 Wifi
//
{ 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
{ 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
//
// Intel WilkinsPeak 1 Wifi
//
{ 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
{ 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
//
// Intel Wilkins Peak 2 Wifi
//
{ 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
{ 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
//
// Intel Wilkins Peak PF Wifi
//
{ 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
//
// End of Table
//
{ 0 }
};

87
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c Normal file
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/** @file
Implementation of Fsp Misc UPD Initialization.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiPei.h>
#include <Library/DebugLib.h>
#include <Library/PeiLib.h>
#include <Library/ConfigBlockLib.h>
#include <FspEas.h>
#include <FspmUpd.h>
#include <FspsUpd.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/DebugPrintErrorLevelLib.h>
#include <Library/PciLib.h>
#include <Guid/MemoryOverwriteControl.h>
#include <PchAccess.h>
/**
Performs FSP Misc UPD initialization.
@param[in][out] FspmUpd Pointer to FSPM_UPD Data.
@retval EFI_SUCCESS FSP UPD Data is updated.
**/
EFI_STATUS
EFIAPI
PeiFspMiscUpdUpdatePreMem (
IN OUT FSPM_UPD *FspmUpd
)
{
EFI_STATUS Status;
UINTN VariableSize;
VOID *MemorySavedData;
UINT8 MorControl;
VOID *MorControlPtr;
//
// Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths.
//
VariableSize = 0;
MemorySavedData = NULL;
Status = PeiGetVariable (
L"MemoryConfig",
&gFspNonVolatileStorageHobGuid,
&MemorySavedData,
&VariableSize
);
DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHobGuid - %r\n", Status));
DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize));
FspmUpd->FspmArchUpd.NvsBufferPtr = MemorySavedData;
if (FspmUpd->FspmArchUpd.NvsBufferPtr != NULL) {
//
// Set the DISB bit in PCH (DRAM Initialization Scratchpad Bit - GEN_PMCON_A[23]),
// after memory Data is saved to NVRAM.
//
PciOr32 ((UINTN)PCI_LIB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PCH_PMC_GEN_PMCON_A), B_PCH_PMC_GEN_PMCON_A_DISB);
}
//
// MOR
//
MorControl = 0;
MorControlPtr = &MorControl;
VariableSize = sizeof (MorControl);
Status = PeiGetVariable (
MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME,
&gEfiMemoryOverwriteControlDataGuid,
&MorControlPtr,
&VariableSize
);
DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status));
if (MOR_CLEAR_MEMORY_VALUE (MorControl)) {
FspmUpd->FspmConfig.CleanMemory = (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK);
}
return EFI_SUCCESS;
}

186
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c Normal file
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/** @file
Provide FSP wrapper platform related function.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiPei.h>
#include <Library/PcdLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/FspWrapperApiLib.h>
#include <Library/SiliconPolicyUpdateLib.h>
#include <FspEas.h>
#include <FspmUpd.h>
#include <FspsUpd.h>
/**
Performs FSP Misc UPD initialization.
@param[in][out] FspmUpd Pointer to FSPM_UPD Data.
@retval EFI_SUCCESS FSP UPD Data is updated.
**/
EFI_STATUS
EFIAPI
PeiFspMiscUpdUpdatePreMem (
IN OUT FSPM_UPD *FspmUpd
);
/**
Performs FSP PCH PEI Policy pre mem initialization.
@param[in][out] FspmUpd Pointer to FSP UPD Data.
@retval EFI_SUCCESS FSP UPD Data is updated.
@retval EFI_NOT_FOUND Fail to locate required PPI.
@retval Other FSP UPD Data update process fail.
**/
EFI_STATUS
EFIAPI
PeiFspPchPolicyUpdatePreMem (
IN OUT FSPM_UPD *FspmUpd
);
/**
Performs FSP PCH PEI Policy initialization.
@param[in][out] FspsUpd Pointer to FSP UPD Data.
@retval EFI_SUCCESS FSP UPD Data is updated.
@retval EFI_NOT_FOUND Fail to locate required PPI.
@retval Other FSP UPD Data update process fail.
**/
EFI_STATUS
EFIAPI
PeiFspPchPolicyUpdate (
IN OUT FSPS_UPD *FspsUpd
);
/**
Performs FSP SA PEI Policy initialization in pre-memory.
@param[in][out] FspmUpd Pointer to FSP UPD Data.
@retval EFI_SUCCESS FSP UPD Data is updated.
@retval EFI_NOT_FOUND Fail to locate required PPI.
@retval Other FSP UPD Data update process fail.
**/
EFI_STATUS
EFIAPI
PeiFspSaPolicyUpdatePreMem (
IN OUT FSPM_UPD *FspmUpd
);
/**
Performs FSP SA PEI Policy initialization.
@param[in][out] FspsUpd Pointer to FSP UPD Data.
@retval EFI_SUCCESS FSP UPD Data is updated.
@retval EFI_NOT_FOUND Fail to locate required PPI.
@retval Other FSP UPD Data update process fail.
**/
EFI_STATUS
EFIAPI
PeiFspSaPolicyUpdate (
IN OUT FSPS_UPD *FspsUpd
);
VOID
InternalPrintVariableData (
IN UINT8 *Data8,
IN UINTN DataSize
)
{
UINTN Index;
for (Index = 0; Index < DataSize; Index++) {
if (Index % 0x10 == 0) {
DEBUG ((DEBUG_INFO, "\n%08X:", Index));
}
DEBUG ((DEBUG_INFO, " %02X", *Data8++));
}
DEBUG ((DEBUG_INFO, "\n"));
}
/**
Performs silicon pre-mem policy update.
The meaning of Policy is defined by silicon code.
It could be the raw data, a handle, a PPI, etc.
The input Policy must be returned by SiliconPolicyDonePreMem().
1) In FSP path, the input Policy should be FspmUpd.
A platform may use this API to update the FSPM UPD policy initialized
by the silicon module or the default UPD data.
The output of FSPM UPD data from this API is the final UPD data.
2) In non-FSP path, the board may use additional way to get
the silicon policy data field based upon the input Policy.
@param[in, out] Policy Pointer to policy.
@return the updated policy.
**/
VOID *
EFIAPI
SiliconPolicyUpdatePreMem (
IN OUT VOID *FspmUpd
)
{
FSPM_UPD *FspmUpdDataPtr;
FspmUpdDataPtr = FspmUpd;
PeiFspSaPolicyUpdatePreMem (FspmUpdDataPtr);
PeiFspPchPolicyUpdatePreMem (FspmUpdDataPtr);
PeiFspMiscUpdUpdatePreMem (FspmUpdDataPtr);
InternalPrintVariableData ((VOID *)FspmUpdDataPtr, sizeof(FSPM_UPD));
return FspmUpd;
}
/**
Performs silicon post-mem policy update.
The meaning of Policy is defined by silicon code.
It could be the raw data, a handle, a PPI, etc.
The input Policy must be returned by SiliconPolicyDonePostMem().
1) In FSP path, the input Policy should be FspsUpd.
A platform may use this API to update the FSPS UPD policy initialized
by the silicon module or the default UPD data.
The output of FSPS UPD data from this API is the final UPD data.
2) In non-FSP path, the board may use additional way to get
the silicon policy data field based upon the input Policy.
@param[in, out] Policy Pointer to policy.
@return the updated policy.
**/
VOID *
EFIAPI
SiliconPolicyUpdatePostMem (
IN OUT VOID *FspsUpd
)
{
FSPS_UPD *FspsUpdDataPtr;
FspsUpdDataPtr = FspsUpd;
PeiFspSaPolicyUpdate (FspsUpdDataPtr);
PeiFspPchPolicyUpdate (FspsUpdDataPtr);
InternalPrintVariableData ((VOID *)FspsUpdDataPtr, sizeof(FSPS_UPD));
return FspsUpd;
}

153
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c Normal file
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/** @file
This file is SampleCode of the library for Intel PCH PEI Policy initialization.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "PeiPchPolicyUpdate.h"
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/HobLib.h>
#include <Guid/GlobalVariable.h>
#include <Library/PchGbeLib.h>
#include <Library/PchInfoLib.h>
#include <Library/PchPcrLib.h>
#include <Library/PchHsioLib.h>
#include <Library/PchSerialIoLib.h>
#include <Library/PchPcieRpLib.h>
#include <GpioConfig.h>
#include <GpioPinsSklH.h>
#include <Library/DebugLib.h>
#include <Library/PchGbeLib.h>
extern PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[];
/**
Add verb table helper function.
This function calculates verbtable number and shows verb table information.
@param[in,out] VerbTableEntryNum Input current VerbTable number and output the number after adding new table
@param[in,out] VerbTableArray Pointer to array of VerbTable
@param[in] VerbTable VerbTable which is going to add into array
**/
STATIC
VOID
InternalAddVerbTable (
IN OUT UINT8 *VerbTableEntryNum,
IN OUT UINT32 *VerbTableArray,
IN HDAUDIO_VERB_TABLE *VerbTable
)
{
if (VerbTable == NULL) {
DEBUG ((DEBUG_ERROR, "InternalAddVerbTable wrong input: VerbTable == NULL\n"));
return;
}
VerbTableArray[*VerbTableEntryNum] = (UINT32) VerbTable;
*VerbTableEntryNum += 1;
DEBUG ((DEBUG_INFO,
"Add verb table for vendor = 0x%04X devId = 0x%04X (size = %d DWords)\n",
VerbTable->Header.VendorId,
VerbTable->Header.DeviceId,
VerbTable->Header.DataDwords)
);
}
enum HDAUDIO_CODEC_SELECT {
PchHdaCodecPlatformOnboard = 0,
PchHdaCodecExternalKit = 1
};
/**
Add verb table function.
This function update the verb table number and verb table ptr of policy.
@param[in] HdAudioConfig HDAudie config block
@param[in] CodecType Platform codec type indicator
@param[in] AudioConnectorType Platform audio connector type
**/
STATIC
VOID
InternalAddPlatformVerbTables (
IN OUT FSPS_UPD *FspsUpd,
IN UINT8 CodecType,
IN UINT8 AudioConnectorType
)
{
UINT8 VerbTableEntryNum;
UINT32 VerbTableArray[32];
UINT32 *VerbTablePtr;
VerbTableEntryNum = 0;
InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdDisplayAudioHdaVerbTable));
if (CodecType == PchHdaCodecPlatformOnboard) {
DEBUG ((DEBUG_INFO, "HDA Policy: Onboard codec selected\n"));
if ((VOID *) (UINTN) PcdGet32 (PcdExtHdaVerbTable) != NULL) {
if (AudioConnectorType == 0) { //Type-C Audio connector selected in Bios Setup menu
InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdExtHdaVerbTable));
InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL);
InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL);
DEBUG ((DEBUG_INFO, "HDA: Type-C Audio connector selected!\n"));
} else { //Stacked Jack Audio connector selected in Bios Setup menu
InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable));
InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable2));
InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL);
DEBUG ((DEBUG_INFO, "HDA: Stacked-Jack Audio connector selected!\n"));
}
} else {
InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable));
InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable2));
InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL);
}
} else {
DEBUG ((DEBUG_INFO, "HDA Policy: External codec kit selected\n"));
InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable1));
InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable2));
InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable3));
}
FspsUpd->FspsConfig.PchHdaVerbTableEntryNum = VerbTableEntryNum;
VerbTablePtr = (UINT32 *) AllocateZeroPool (sizeof (UINT32) * VerbTableEntryNum);
CopyMem (VerbTablePtr, VerbTableArray, sizeof (UINT32) * VerbTableEntryNum);
FspsUpd->FspsConfig.PchHdaVerbTablePtr = (UINT32) VerbTablePtr;
}
/**
Performs FSP PCH PEI Policy initialization.
@param[in][out] FspsUpd Pointer to FSP UPD Data.
@retval EFI_SUCCESS FSP UPD Data is updated.
@retval EFI_NOT_FOUND Fail to locate required PPI.
@retval Other FSP UPD Data update process fail.
**/
EFI_STATUS
EFIAPI
PeiFspPchPolicyUpdate (
IN OUT FSPS_UPD *FspsUpd
)
{
FspsUpd->FspsConfig.PchSubSystemVendorId = V_PCH_INTEL_VENDOR_ID;
FspsUpd->FspsConfig.PchSubSystemId = V_PCH_DEFAULT_SID;
FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr = (UINT32) mPcieDeviceTable;
InternalAddPlatformVerbTables (FspsUpd, PchHdaCodecPlatformOnboard, PcdGet8 (PcdAudioConnector));
DEBUG_CODE_BEGIN();
if ((PcdGet8 (PcdSerialIoUartDebugEnable) == 1) &&
FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (PcdSerialIoUartNumber)] == PchSerialIoDisabled ) {
FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (PcdSerialIoUartNumber)] = PchSerialIoLegacyUart;
}
DEBUG_CODE_END();
return EFI_SUCCESS;
}

27
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h Normal file
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/** @file
Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _PEI_PCH_POLICY_UPDATE_H_
#define _PEI_PCH_POLICY_UPDATE_H_
//
// External include files do NOT need to be explicitly specified in real EDKII
// environment
//
#include <PiPei.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/PciLib.h>
#include <Ppi/SiPolicy.h>
#include <Library/MmPciLib.h>
#include <FspEas.h>
#include <FspmUpd.h>
#include <FspsUpd.h>
#endif

248
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c Normal file
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/** @file
This file is SampleCode of the library for Intel PCH PEI Policy initialization.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "PeiPchPolicyUpdate.h"
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/HobLib.h>
#include <Guid/GlobalVariable.h>
#include <Library/PchInfoLib.h>
#include <Library/PchPcrLib.h>
#include <Library/PchHsioLib.h>
#include <Library/PchPcieRpLib.h>
#include <PchHsioPtssTables.h>
#include <Library/DebugLib.h>
VOID
InstallPlatformHsioPtssTable (
IN OUT FSPM_UPD *FspmUpd
)
{
HSIO_PTSS_TABLES *UnknowPtssTables;
HSIO_PTSS_TABLES *SpecificPtssTables;
HSIO_PTSS_TABLES *PtssTables;
UINT8 PtssTableIndex;
UINT32 UnknowTableSize;
UINT32 SpecificTableSize;
UINT32 TableSize;
UINT32 Entry;
UINT8 LaneNum;
UINT8 Index;
UINT8 MaxSataPorts;
UINT8 MaxPciePorts;
UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PciePort;
UINTN RpBase;
UINTN RpDevice;
UINTN RpFunction;
UINT32 StrapFuseCfg;
UINT8 PcieControllerCfg;
EFI_STATUS Status;
UnknowPtssTables = NULL;
UnknowTableSize = 0;
SpecificPtssTables = NULL;
SpecificTableSize = 0;
if (GetPchGeneration () == SklPch) {
switch (PchStepping ()) {
case PchLpB0:
case PchLpB1:
UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable1);
UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable1Size);
SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable1);
SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable1Size);
break;
case PchLpC0:
case PchLpC1:
UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable2);
UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable2Size);
SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable2);
SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable2Size);
break;
case PchHB0:
case PchHC0:
UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable1);
UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable1Size);
SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable1);
SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable1Size);
break;
case PchHD0:
case PchHD1:
UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2);
UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size);
SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2);
SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size);
break;
default:
UnknowPtssTables = NULL;
UnknowTableSize = 0;
SpecificPtssTables = NULL;
SpecificTableSize = 0;
DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));
}
} else {
switch (PchStepping ()) {
case KblPchHA0:
UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2);
UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size);
SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2);
SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size);
break;
default:
UnknowPtssTables = NULL;
UnknowTableSize = 0;
SpecificPtssTables = NULL;
SpecificTableSize = 0;
DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));
}
}
PtssTableIndex = 0;
MaxSataPorts = GetPchMaxSataPortNum ();
MaxPciePorts = GetPchMaxPciePortNum ();
ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal));
//Populate PCIe topology based on lane configuration
for (PciePort = 0; PciePort < MaxPciePorts; PciePort += 4) {
Status = GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction);
ASSERT_EFI_ERROR (Status);
RpBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction);
StrapFuseCfg = MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG);
PcieControllerCfg = (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC);
DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value = %d\n", PciePort, PcieControllerCfg));
}
for (Index = 0; Index < MaxPciePorts; Index++) {
DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology = %d\n", Index, PcieTopologyReal[Index]));
}
//Case 1: BoardId is known, Topology is known/unknown
//Case 1a: SATA
PtssTables = SpecificPtssTables;
TableSize = SpecificTableSize;
for (Index = 0; Index < MaxSataPorts; Index++) {
if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
for (Entry = 0; Entry < TableSize; Entry++) {
if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
(PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA)
)
{
PtssTableIndex++;
if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) &&
(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = TRUE;
FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
} else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8)) {
if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) {
FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = TRUE;
FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);
}
if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) {
FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = TRUE;
FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);
}
} else {
ASSERT (FALSE);
}
}
}
}
}
//Case 1b: PCIe
for (Index = 0; Index < MaxPciePorts; Index++) {
if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
for (Entry = 0; Entry < TableSize; Entry++) {
if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
(PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
(PcieTopologyReal[Index] == PtssTables[Entry].Topology)) {
PtssTableIndex++;
if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) &&
(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = TRUE;
FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);
} else {
ASSERT (FALSE);
}
}
}
}
}
//Case 2: BoardId is unknown, Topology is known/unknown
if (PtssTableIndex == 0) {
DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be applied\n"));
PtssTables = UnknowPtssTables;
TableSize = UnknowTableSize;
for (Index = 0; Index < MaxSataPorts; Index++) {
if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
for (Entry = 0; Entry < TableSize; Entry++) {
if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
(PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA)
)
{
if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) &&
(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = TRUE;
FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
} else if (PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8) {
if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) {
FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = TRUE;
FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);
}
if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) {
FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = TRUE;
FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);
}
} else {
ASSERT (FALSE);
}
}
}
}
}
for (Index = 0; Index < MaxPciePorts; Index++) {
if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
for (Entry = 0; Entry < TableSize; Entry++) {
if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
(PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
(PcieTopologyReal[Index] == PtssTables[Entry].Topology)) {
if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) &&
(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = TRUE;
FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);
} else {
ASSERT (FALSE);
}
}
}
}
}
}
}
/**
Performs FSP PCH PEI Policy pre mem initialization.
@param[in][out] FspmUpd Pointer to FSP UPD Data.
@retval EFI_SUCCESS FSP UPD Data is updated.
@retval EFI_NOT_FOUND Fail to locate required PPI.
@retval Other FSP UPD Data update process fail.
**/
EFI_STATUS
EFIAPI
PeiFspPchPolicyUpdatePreMem (
IN OUT FSPM_UPD *FspmUpd
)
{
InstallPlatformHsioPtssTable (FspmUpd);
return EFI_SUCCESS;
}

84
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c Normal file
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/** @file
Do Platform Stage System Agent initialization.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "PeiSaPolicyUpdate.h"
#include <Guid/MemoryTypeInformation.h>
#include <Library/HobLib.h>
#include <PchAccess.h>
#include <SaAccess.h>
#include <Pi/PiFirmwareFile.h>
#include <Pi/PiPeiCis.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PeiSaPolicyLib.h>
#include <Library/PeiLib.h>
/**
Performs FSP SA PEI Policy initialization.
@param[in][out] FspsUpd Pointer to FSP UPD Data.
@retval EFI_SUCCESS FSP UPD Data is updated.
@retval EFI_NOT_FOUND Fail to locate required PPI.
@retval Other FSP UPD Data update process fail.
**/
EFI_STATUS
EFIAPI
PeiFspSaPolicyUpdate (
IN OUT FSPS_UPD *FspsUpd
)
{
VOID *Buffer;
VOID *MemBuffer;
UINT32 Size;
DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));
FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1;
Size = 0;
Buffer = NULL;
PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size);
if (Buffer == NULL) {
DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
} else {
MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
if ((MemBuffer != NULL) && (Buffer != NULL)) {
CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
FspsUpd->FspsConfig.GraphicsConfigPtr = (UINT32)(UINTN)MemBuffer;
} else {
DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n"));
FspsUpd->FspsConfig.GraphicsConfigPtr = 0;
}
}
DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.GraphicsConfigPtr));
DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size));
Size = 0;
Buffer = NULL;
PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, &Size);
if (Buffer == NULL) {
DEBUG((DEBUG_WARN, "Could not locate Logo\n"));
} else {
MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
if ((MemBuffer != NULL) && (Buffer != NULL)) {
CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
FspsUpd->FspsConfig.LogoPtr = (UINT32)(UINTN)MemBuffer;
FspsUpd->FspsConfig.LogoSize = Size;
} else {
DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n"));
FspsUpd->FspsConfig.LogoPtr = 0;
FspsUpd->FspsConfig.LogoSize = 0;
}
}
DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.LogoPtr));
DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.LogoSize));
return EFI_SUCCESS;
}

30
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h Normal file
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/** @file
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _PEI_SA_POLICY_UPDATE_H_
#define _PEI_SA_POLICY_UPDATE_H_
//
// External include files do NOT need to be explicitly specified in real EDKII
// environment
//
#include <SaPolicyCommon.h>
#include <Library/DebugPrintErrorLevelLib.h>
#include <CpuRegs.h>
#include <Library/CpuPlatformLib.h>
#include "PeiPchPolicyUpdate.h"
#include <Library/PcdLib.h>
#include <CpuAccess.h>
#include <FspEas.h>
#include <FspmUpd.h>
#include <FspsUpd.h>
extern EFI_GUID gTianoLogoGuid;
#endif

79
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c Normal file
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/** @file
Do Platform Stage System Agent initialization.
Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "PeiSaPolicyUpdate.h"
#include <CpuRegs.h>
#include <Library/CpuPlatformLib.h>
#include <Guid/MemoryTypeInformation.h>
#include <Guid/MemoryOverwriteControl.h>
#include <Library/HobLib.h>
#include <PchAccess.h>
#include <SaAccess.h>
#include <Library/CpuMailboxLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PeiSaPolicyLib.h>
#include <Library/GpioLib.h>
#include <GpioPinsSklH.h>
/**
Performs FSP SA PEI Policy initialization in pre-memory.
@param[in][out] FspmUpd Pointer to FSP UPD Data.
@retval EFI_SUCCESS FSP UPD Data is updated.
@retval EFI_NOT_FOUND Fail to locate required PPI.
@retval Other FSP UPD Data update process fail.
**/
EFI_STATUS
EFIAPI
PeiFspSaPolicyUpdatePreMem (
IN OUT FSPM_UPD *FspmUpd
)
{
VOID *Buffer;
//
// If SpdAddressTable are not all 0, it means DIMM slots implemented and
// MemorySpdPtr* already updated by reading SPD from DIMM in SiliconPolicyInitPreMem.
//
// If SpdAddressTable all 0, this is memory down design and hardcoded SpdData
// should be applied to MemorySpdPtr*.
//
if ((PcdGet8 (PcdMrcSpdAddressTable0) == 0) && (PcdGet8 (PcdMrcSpdAddressTable1) == 0)
&& (PcdGet8 (PcdMrcSpdAddressTable2) == 0) && (PcdGet8 (PcdMrcSpdAddressTable3) == 0)) {
DEBUG((DEBUG_INFO, "Override MemorySpdPtr...\n"));
CopyMem((VOID *)(UINTN)FspmUpd->FspmConfig.MemorySpdPtr00, (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize));
CopyMem((VOID *)(UINTN)FspmUpd->FspmConfig.MemorySpdPtr10, (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize));
}
DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n"));
Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap);
if (Buffer) {
CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12);
CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) Buffer + 12, 12);
}
Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram);
if (Buffer) {
CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, 8);
CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, (UINT8*) Buffer + 8, 8);
}
DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp Target Settings...\n"));
Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor);
if (Buffer) {
CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6);
}
Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget);
if (Buffer) {
CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10);
}
return EFI_SUCCESS;
}

150
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf Normal file
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## @file
# Provide FSP wrapper platform related function.
#
# Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
################################################################################
#
# Defines Section - statements that will be processed to create a Makefile.
#
################################################################################
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = SiliconPolicyUpdateLibFsp
FILE_GUID = 4E83003B-49A9-459E-AAA6-1CA3C6D04FB2
MODULE_TYPE = PEIM
VERSION_STRING = 1.0
LIBRARY_CLASS = SiliconPolicyUpdateLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
################################################################################
#
# Sources Section - list of files that are required for the build to succeed.
#
################################################################################
[Sources]
PeiFspPolicyUpdateLib.c
PeiPchPolicyUpdatePreMem.c
PeiPchPolicyUpdate.c
PeiSaPolicyUpdatePreMem.c
PeiSaPolicyUpdate.c
PeiFspMiscUpdUpdateLib.c
PcieDeviceTable.c
################################################################################
#
# Package Dependency Section - list of Package files that are required for
# this module.
#
################################################################################
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
IntelFsp2Pkg/IntelFsp2Pkg.dec
IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
IntelSiliconPkg/IntelSiliconPkg.dec
KabylakeSiliconPkg/SiPkg.dec
KabylakeFspBinPkg/KabylakeFspBinPkg.dec
KabylakeOpenBoardPkg/OpenBoardPkg.dec
MinPlatformPkg/MinPlatformPkg.dec
[LibraryClasses.IA32]
FspWrapperApiLib
OcWdtLib
PchResetLib
FspWrapperPlatformLib
BaseMemoryLib
CpuPlatformLib
DebugLib
HobLib
IoLib
PcdLib
PostCodeLib
SmbusLib
MmPciLib
ConfigBlockLib
PeiSaPolicyLib
PchGbeLib
PchInfoLib
PchHsioLib
PchPcieRpLib
MemoryAllocationLib
CpuMailboxLib
DebugPrintErrorLevelLib
SiPolicyLib
PchGbeLib
TimerLib
GpioLib
PeiLib
[Pcd]
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES
# SPD Address Table
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES
gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES
gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable2
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdExtHdaVerbTable
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable1
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable2
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable3
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDisplayAudioHdaVerbTable
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAudioConnector
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid
[Guids]
gFspNonVolatileStorageHobGuid ## CONSUMES
gTianoLogoGuid ## CONSUMES
gEfiMemoryOverwriteControlDataGuid
[Depex]
gEdkiiVTdInfoPpiGuid

46
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/EcCommands.h Normal file
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/** @file
Definition for supported EC commands.
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef EC_COMMANDS_H_
#define EC_COMMANDS_H_
//
// Timeout if EC command/data fails
//
#define EC_TIME_OUT 0x20000
//
// The EC implements an embedded controller interface at ports 0x60/0x64 and a ACPI compliant
// system management controller at ports 0x62/0x66. Port 0x66 is the command and status port,
// port 0x62 is the data port.
//
#define EC_D_PORT 0x62
#define EC_C_PORT 0x66
//
// Status Port 0x62
//
#define EC_S_OVR_TMP 0x80 // Current CPU temperature exceeds the threshold
#define EC_S_SMI_EVT 0x40 // SMI event is pending
#define EC_S_SCI_EVT 0x20 // SCI event is pending
#define EC_S_BURST 0x10 // EC is in burst mode or normal mode
#define EC_S_CMD 0x08 // Byte in data register is command/data
#define EC_S_IGN 0x04 // Ignored
#define EC_S_IBF 0x02 // Input buffer is full/empty
#define EC_S_OBF 0x01 // Output buffer is full/empty
//
// EC commands that are issued to the EC through the command port (0x66).
// New commands and command parameters should only be written by the host when IBF=0.
// Data read from the EC data port is valid only when OBF=1.
//
#define EC_C_FAB_ID 0x0D // Get the board fab ID in the lower 3 bits
#define EC_C_ACPI_READ 0x80 // Read a byte of EC RAM
#define EC_C_ACPI_WRITE 0x81 // Write a byte of EC RAM
#endif // EC_COMMANDS_H_

48
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/FlashMapInclude.fdf Normal file
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## @file
# FDF file for the KabylakeRvp3 board.
#
# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
#=================================================================================#
# 8 M BIOS - for FSP wrapper
#=================================================================================#
DEFINE FLASH_BASE = 0xFF800000 #
DEFINE FLASH_SIZE = 0x00800000 #
DEFINE FLASH_BLOCK_SIZE = 0x00010000 #
DEFINE FLASH_NUM_BLOCKS = 0x00000080 #
#=================================================================================#
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000 # Flash addr (0xFF800000)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize = 0x00040000 #
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = 0x00000000 # Flash addr (0xFF800000)
SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0001E000 #
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = 0x0001E000 # Flash addr (0xFF81E000)
SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = 0x00002000 #
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = 0x00020000 # Flash addr (0xFF820000)
SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = 0x00020000 #
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00040000 # Flash addr (0xFF840000)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = 0x00050000 #
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x00090000 # Flash addr (0xFF890000)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00070000 #
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = 0x00100000 # Flash addr (0xFF900000)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00090000 #
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = 0x00190000 # Flash addr (0xFF990000)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x001E0000 #
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = 0x00370000 # Flash addr (0xFFB70000)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00180000 #
SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = 0x004F0000 # Flash addr (0xFFCF0000)
SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = 0x000A0000 #
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = 0x00590000 # Flash addr (0xFFD90000)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = 0x00060000 #
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = 0x005F0000 # Flash addr (0xFFDF0000)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize = 0x000BC000 #
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = 0x006AC000 # Flash addr (0xFFEAC000)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize = 0x00014000 #
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset = 0x006C0000 # Flash addr (0xFFEC0000)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize = 0x00010000 #
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = 0x006D0000 # Flash addr (0xFFED0000)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = 0x00130000 #

662
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.c Normal file
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51
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.inf Normal file
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### @file
# Platform Hook Library instance for Kaby Lake RVP3.
#
# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
###
[Defines]
INF_VERSION = 0x00010017
BASE_NAME = BasePlatformHookLib
FILE_GUID = E22ADCC6-ED90-4A90-9837-C8E7FF9E963D
VERSION_STRING = 1.0
MODULE_TYPE = BASE
LIBRARY_CLASS = PlatformHookLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
[LibraryClasses]
BaseLib
IoLib
MmPciLib
PciLib
PchCycleDecodingLib
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
MinPlatformPkg/MinPlatformPkg.dec
KabylakeOpenBoardPkg/OpenBoardPkg.dec
KabylakeSiliconPkg/SiPkg.dec
[Pcd]
gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataDefaultPort ## CONSUMES
[FixedPcd]
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES
[Sources]
BasePlatformHookLib.c

36
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c Normal file
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@@ -0,0 +1,36 @@
/** @file
Kaby Lake RVP 3 Board ACPI library
Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Base.h>
#include <Uefi.h>
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include <Library/BoardAcpiTableLib.h>
#include <Library/PcdLib.h>
#include <Library/DebugLib.h>
EFI_STATUS
EFIAPI
KabylakeRvp3BoardUpdateAcpiTable (
IN OUT EFI_ACPI_COMMON_HEADER *Table,
IN OUT EFI_ACPI_TABLE_VERSION *Version
);
EFI_STATUS
EFIAPI
BoardUpdateAcpiTable (
IN OUT EFI_ACPI_COMMON_HEADER *Table,
IN OUT EFI_ACPI_TABLE_VERSION *Version
)
{
KabylakeRvp3BoardUpdateAcpiTable (Table, Version);
return EFI_SUCCESS;
}

48
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf Normal file
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### @file
# Kaby Lake RVP 3 Board ACPI library
#
# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
###
[Defines]
INF_VERSION = 0x00010017
BASE_NAME = DxeBoardAcpiTableLib
FILE_GUID = 6562E0AE-90D8-4D41-8C97-81286B4BE7D2
VERSION_STRING = 1.0
MODULE_TYPE = BASE
LIBRARY_CLASS = BoardAcpiTableLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
[LibraryClasses]
BaseLib
IoLib
PciLib
AslUpdateLib
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
MinPlatformPkg/MinPlatformPkg.dec
KabylakeOpenBoardPkg/OpenBoardPkg.dec
KabylakeSiliconPkg/SiPkg.dec
BoardModulePkg/BoardModulePkg.dec
[Pcd]
gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress
[Sources]
DxeKabylakeRvp3AcpiTableLib.c
DxeBoardAcpiTableLib.c

76
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeKabylakeRvp3AcpiTableLib.c Normal file
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/** @file
Kaby Lake RVP 3 Board ACPI Library
Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Base.h>
#include <Uefi.h>
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include <Library/BoardAcpiTableLib.h>
#include <Library/PcdLib.h>
#include <Library/DebugLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/AslUpdateLib.h>
#include <Protocol/GlobalNvsArea.h>
#include <PlatformBoardId.h>
GLOBAL_REMOVE_IF_UNREFERENCED EFI_GLOBAL_NVS_AREA_PROTOCOL mGlobalNvsArea;
VOID
KabylakeRvp3UpdateGlobalNvs (
VOID
)
{
//
// Allocate and initialize the NVS area for SMM and ASL communication.
//
mGlobalNvsArea.Area = (VOID *)(UINTN)PcdGet64 (PcdAcpiGnvsAddress);
//
// Update global NVS area for ASL and SMM init code to use
//
//
// Enable PowerState
//
mGlobalNvsArea.Area->PowerState = 1; // AC =1; for mobile platform, will update this value in SmmPlatform.c
mGlobalNvsArea.Area->NativePCIESupport = PcdGet8 (PcdPciExpNative);
//
// Enable APIC
//
mGlobalNvsArea.Area->ApicEnable = GLOBAL_NVS_DEVICE_ENABLE;
//
// Low Power S0 Idle - Enabled/Disabled
//
mGlobalNvsArea.Area->LowPowerS0Idle = PcdGet8 (PcdLowPowerS0Idle);
mGlobalNvsArea.Area->Ps2MouseEnable = FALSE;
mGlobalNvsArea.Area->Ps2KbMsEnable = PcdGet8 (PcdPs2KbMsEnable);
mGlobalNvsArea.Area->BoardId = (UINT8) LibPcdGetSku ();
}
EFI_STATUS
EFIAPI
KabylakeRvp3BoardUpdateAcpiTable (
IN OUT EFI_ACPI_COMMON_HEADER *Table,
IN OUT EFI_ACPI_TABLE_VERSION *Version
)
{
if (Table->Signature == EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {
KabylakeRvp3UpdateGlobalNvs ();
}
return EFI_SUCCESS;
}

43
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c Normal file
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@@ -0,0 +1,43 @@
/** @file
Kaby Lake RVP 3 Multi-Board ACPI Support library
Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Base.h>
#include <Uefi.h>
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include <Library/BoardAcpiTableLib.h>
#include <Library/MultiBoardAcpiSupportLib.h>
#include <Library/PcdLib.h>
#include <Library/DebugLib.h>
#include <PlatformBoardId.h>
EFI_STATUS
EFIAPI
KabylakeRvp3BoardUpdateAcpiTable (
IN OUT EFI_ACPI_COMMON_HEADER *Table,
IN OUT EFI_ACPI_TABLE_VERSION *Version
);
BOARD_ACPI_TABLE_FUNC mKabylakeRvp3BoardAcpiTableFunc = {
KabylakeRvp3BoardUpdateAcpiTable
};
EFI_STATUS
EFIAPI
DxeKabylakeRvp3MultiBoardAcpiSupportLibConstructor (
VOID
)
{
if ((LibPcdGetSku () == BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSku () == BoardIdSkylakeRvp3)) {
return RegisterBoardAcpiTableFunc (&mKabylakeRvp3BoardAcpiTableFunc);
}
return EFI_SUCCESS;
}

49
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf Normal file
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### @file
# Kaby Lake RVP 3 Multi-Board ACPI Support library
#
# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
###
[Defines]
INF_VERSION = 0x00010017
BASE_NAME = DxeKabylakeRvp3MultiBoardAcpiTableLib
FILE_GUID = 8E6A3B38-53E0-48C0-970F-058F380FCB80
VERSION_STRING = 1.0
MODULE_TYPE = BASE
LIBRARY_CLASS = NULL
CONSTRUCTOR = DxeKabylakeRvp3MultiBoardAcpiSupportLibConstructor
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
[LibraryClasses]
BaseLib
IoLib
PciLib
AslUpdateLib
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
MinPlatformPkg/MinPlatformPkg.dec
KabylakeOpenBoardPkg/OpenBoardPkg.dec
KabylakeSiliconPkg/SiPkg.dec
BoardModulePkg/BoardModulePkg.dec
[Pcd]
gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress
[Sources]
DxeKabylakeRvp3AcpiTableLib.c
DxeMultiBoardAcpiSupportLib.c

62
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c Normal file
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/** @file
Kaby Lake RVP 3 SMM Board ACPI Enable library
Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Base.h>
#include <Uefi.h>
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include <Library/BoardAcpiEnableLib.h>
#include <Library/PcdLib.h>
#include <Library/DebugLib.h>
EFI_STATUS
EFIAPI
KabylakeRvp3BoardEnableAcpi (
IN BOOLEAN EnableSci
);
EFI_STATUS
EFIAPI
KabylakeRvp3BoardDisableAcpi (
IN BOOLEAN DisableSci
);
EFI_STATUS
EFIAPI
SiliconEnableAcpi (
IN BOOLEAN EnableSci
);
EFI_STATUS
EFIAPI
SiliconDisableAcpi (
IN BOOLEAN DisableSci
);
EFI_STATUS
EFIAPI
BoardEnableAcpi (
IN BOOLEAN EnableSci
)
{
SiliconEnableAcpi (EnableSci);
return KabylakeRvp3BoardEnableAcpi (EnableSci);
}
EFI_STATUS
EFIAPI
BoardDisableAcpi (
IN BOOLEAN DisableSci
)
{
SiliconDisableAcpi (DisableSci);
return KabylakeRvp3BoardDisableAcpi (DisableSci);
}

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