From cf57743b49489bcf84e5a74bac80d71bfdaa9da2 Mon Sep 17 00:00:00 2001 From: Benjamin Doron Date: Wed, 18 Aug 2021 11:48:57 -0700 Subject: [PATCH] KabylakeOpenBoardPkg/AspireVn7Dash572G: Duplicate KabylakeRvp3 directory This makes diffing the follow-up board changes easier. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Isaac Oram Cc: Michael Kubacki Signed-off-by: Benjamin Doron Reviewed-by: Nate DeSimone Reviewed-by: Michael Kubacki --- .../PcieDeviceTable.c | 115 +++ .../PeiFspMiscUpdUpdateLib.c | 87 +++ .../PeiFspPolicyUpdateLib.c | 186 +++++ .../PeiPchPolicyUpdate.c | 153 ++++ .../PeiPchPolicyUpdate.h | 27 + .../PeiPchPolicyUpdatePreMem.c | 248 ++++++ .../PeiSaPolicyUpdate.c | 84 ++ .../PeiSaPolicyUpdate.h | 30 + .../PeiSaPolicyUpdatePreMem.c | 79 ++ .../PeiSiliconPolicyUpdateLibFsp.inf | 150 ++++ .../AspireVn7Dash572G/Include/EcCommands.h | 46 ++ .../Include/Fdf/FlashMapInclude.fdf | 48 ++ .../BasePlatformHookLib/BasePlatformHookLib.c | 662 ++++++++++++++++ .../BasePlatformHookLib.inf | 51 ++ .../BoardAcpiLib/DxeBoardAcpiTableLib.c | 36 + .../BoardAcpiLib/DxeBoardAcpiTableLib.inf | 48 ++ .../DxeKabylakeRvp3AcpiTableLib.c | 76 ++ .../DxeMultiBoardAcpiSupportLib.c | 43 ++ .../DxeMultiBoardAcpiSupportLib.inf | 49 ++ .../BoardAcpiLib/SmmBoardAcpiEnableLib.c | 62 ++ .../BoardAcpiLib/SmmBoardAcpiEnableLib.inf | 47 ++ .../SmmKabylakeRvp3AcpiEnableLib.c | 39 + .../SmmMultiBoardAcpiSupportLib.c | 81 ++ .../SmmMultiBoardAcpiSupportLib.inf | 48 ++ .../BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 168 ++++ .../BoardInitLib/KabylakeRvp3GpioTable.c | 381 ++++++++++ .../BoardInitLib/KabylakeRvp3HdaVerbTables.c | 232 ++++++ .../BoardInitLib/KabylakeRvp3HsioPtssTables.c | 105 +++ .../BoardInitLib/KabylakeRvp3SpdTable.c | 541 +++++++++++++ .../BoardInitLib/PeiBoardInitPostMemLib.c | 39 + .../BoardInitLib/PeiBoardInitPostMemLib.inf | 54 ++ .../BoardInitLib/PeiBoardInitPreMemLib.c | 108 +++ .../BoardInitLib/PeiBoardInitPreMemLib.inf | 135 ++++ .../BoardInitLib/PeiKabylakeRvp3Detect.c | 124 +++ .../BoardInitLib/PeiKabylakeRvp3InitLib.h | 44 ++ .../PeiKabylakeRvp3InitPostMemLib.c | 208 +++++ .../PeiKabylakeRvp3InitPreMemLib.c | 339 +++++++++ .../PeiMultiBoardInitPostMemLib.c | 40 + .../PeiMultiBoardInitPostMemLib.inf | 56 ++ .../BoardInitLib/PeiMultiBoardInitPreMemLib.c | 82 ++ .../PeiMultiBoardInitPreMemLib.inf | 137 ++++ .../AspireVn7Dash572G/OpenBoardPkg.dsc | 521 +++++++++++++ .../AspireVn7Dash572G/OpenBoardPkg.fdf | 715 ++++++++++++++++++ .../OpenBoardPkgBuildOption.dsc | 151 ++++ .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 464 ++++++++++++ .../DxeGopPolicyInit.c | 175 +++++ .../DxeGopPolicyInit.h | 39 + .../DxeSaPolicyInit.h | 64 ++ .../DxeSaPolicyUpdate.c | 66 ++ .../DxeSiliconPolicyUpdateLib.c | 53 ++ .../DxeSiliconPolicyUpdateLib.inf | 51 ++ .../PeiSiliconPolicyUpdateLib.c | 601 +++++++++++++++ .../PeiSiliconPolicyUpdateLib.inf | 92 +++ .../AspireVn7Dash572G/build_board.py | 68 ++ .../AspireVn7Dash572G/build_config.cfg | 36 + 55 files changed, 8384 insertions(+) create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/EcCommands.h create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/FlashMapInclude.fdf create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.inf create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeKabylakeRvp3AcpiTableLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmKabylakeRvp3AcpiEnableLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/KabylakeRvp3GpioTable.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/KabylakeRvp3HdaVerbTables.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/KabylakeRvp3HsioPtssTables.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/KabylakeRvp3SpdTable.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.inf create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiKabylakeRvp3Detect.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiKabylakeRvp3InitLib.h create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiKabylakeRvp3InitPostMemLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.fdf create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgBuildOption.dsc create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_board.py create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.cfg diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c new file mode 100644 index 00000000..155dfdaf --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c @@ -0,0 +1,115 @@ +/** @file + This file is SampleCode of the library for Intel PCH PEI Policy initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PeiPchPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCI_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x00 +#define PCI_CLASS_NETWORK_OTHER 0x80 + +GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = { + // + // Intel PRO/Wireless + // + { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel WiMAX/WiFi Link + // + { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Crane Peak WLAN NIC + // + { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Crane Peak w/BT WLAN NIC + // + { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Kelsey Peak WiFi, WiMax + // + { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 105 + // + { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 135 + // + { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 2200 + // + { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 2230 + // + { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 6235 + // + { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel CampPeak 2 Wifi + // + { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel WilkinsPeak 1 Wifi + // + { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 }, + { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 }, + // + // Intel Wilkins Peak 2 Wifi + // + { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 }, + { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 }, + // + // Intel Wilkins Peak PF Wifi + // + { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + + // + // End of Table + // + { 0 } +}; + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c new file mode 100644 index 00000000..d8aff196 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c @@ -0,0 +1,87 @@ +/** @file + Implementation of Fsp Misc UPD Initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/** + Performs FSP Misc UPD initialization. + + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. +**/ +EFI_STATUS +EFIAPI +PeiFspMiscUpdUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + UINTN VariableSize; + VOID *MemorySavedData; + UINT8 MorControl; + VOID *MorControlPtr; + + // + // Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths. + // + VariableSize = 0; + MemorySavedData = NULL; + Status = PeiGetVariable ( + L"MemoryConfig", + &gFspNonVolatileStorageHobGuid, + &MemorySavedData, + &VariableSize + ); + DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHobGuid - %r\n", Status)); + DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize)); + FspmUpd->FspmArchUpd.NvsBufferPtr = MemorySavedData; + + if (FspmUpd->FspmArchUpd.NvsBufferPtr != NULL) { + // + // Set the DISB bit in PCH (DRAM Initialization Scratchpad Bit - GEN_PMCON_A[23]), + // after memory Data is saved to NVRAM. + // + PciOr32 ((UINTN)PCI_LIB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PCH_PMC_GEN_PMCON_A), B_PCH_PMC_GEN_PMCON_A_DISB); + } + + // + // MOR + // + MorControl = 0; + MorControlPtr = &MorControl; + VariableSize = sizeof (MorControl); + Status = PeiGetVariable ( + MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME, + &gEfiMemoryOverwriteControlDataGuid, + &MorControlPtr, + &VariableSize + ); + DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status)); + if (MOR_CLEAR_MEMORY_VALUE (MorControl)) { + FspmUpd->FspmConfig.CleanMemory = (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK); + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c new file mode 100644 index 00000000..55be1626 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c @@ -0,0 +1,186 @@ +/** @file + Provide FSP wrapper platform related function. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/** + Performs FSP Misc UPD initialization. + + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. +**/ +EFI_STATUS +EFIAPI +PeiFspMiscUpdUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP PCH PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP PCH PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyUpdate ( + IN OUT FSPS_UPD *FspsUpd + ); + +/** + Performs FSP SA PEI Policy initialization in pre-memory. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP SA PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyUpdate ( + IN OUT FSPS_UPD *FspsUpd + ); + +VOID +InternalPrintVariableData ( + IN UINT8 *Data8, + IN UINTN DataSize + ) +{ + UINTN Index; + + for (Index = 0; Index < DataSize; Index++) { + if (Index % 0x10 == 0) { + DEBUG ((DEBUG_INFO, "\n%08X:", Index)); + } + DEBUG ((DEBUG_INFO, " %02X", *Data8++)); + } + DEBUG ((DEBUG_INFO, "\n")); +} + +/** + Performs silicon pre-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The input Policy must be returned by SiliconPolicyDonePreMem(). + + 1) In FSP path, the input Policy should be FspmUpd. + A platform may use this API to update the FSPM UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPM UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePreMem ( + IN OUT VOID *FspmUpd + ) +{ + FSPM_UPD *FspmUpdDataPtr; + + FspmUpdDataPtr = FspmUpd; + PeiFspSaPolicyUpdatePreMem (FspmUpdDataPtr); + PeiFspPchPolicyUpdatePreMem (FspmUpdDataPtr); + PeiFspMiscUpdUpdatePreMem (FspmUpdDataPtr); + + InternalPrintVariableData ((VOID *)FspmUpdDataPtr, sizeof(FSPM_UPD)); + + return FspmUpd; +} + +/** + Performs silicon post-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The input Policy must be returned by SiliconPolicyDonePostMem(). + + 1) In FSP path, the input Policy should be FspsUpd. + A platform may use this API to update the FSPS UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPS UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePostMem ( + IN OUT VOID *FspsUpd + ) +{ + FSPS_UPD *FspsUpdDataPtr; + + FspsUpdDataPtr = FspsUpd; + PeiFspSaPolicyUpdate (FspsUpdDataPtr); + PeiFspPchPolicyUpdate (FspsUpdDataPtr); + + InternalPrintVariableData ((VOID *)FspsUpdDataPtr, sizeof(FSPS_UPD)); + + return FspsUpd; +} + + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c new file mode 100644 index 00000000..b469720a --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c @@ -0,0 +1,153 @@ +/** @file + This file is SampleCode of the library for Intel PCH PEI Policy initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PeiPchPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[]; + +/** + Add verb table helper function. + This function calculates verbtable number and shows verb table information. + + @param[in,out] VerbTableEntryNum Input current VerbTable number and output the number after adding new table + @param[in,out] VerbTableArray Pointer to array of VerbTable + @param[in] VerbTable VerbTable which is going to add into array +**/ +STATIC +VOID +InternalAddVerbTable ( + IN OUT UINT8 *VerbTableEntryNum, + IN OUT UINT32 *VerbTableArray, + IN HDAUDIO_VERB_TABLE *VerbTable + ) +{ + if (VerbTable == NULL) { + DEBUG ((DEBUG_ERROR, "InternalAddVerbTable wrong input: VerbTable == NULL\n")); + return; + } + + VerbTableArray[*VerbTableEntryNum] = (UINT32) VerbTable; + *VerbTableEntryNum += 1; + + DEBUG ((DEBUG_INFO, + "Add verb table for vendor = 0x%04X devId = 0x%04X (size = %d DWords)\n", + VerbTable->Header.VendorId, + VerbTable->Header.DeviceId, + VerbTable->Header.DataDwords) + ); +} + +enum HDAUDIO_CODEC_SELECT { + PchHdaCodecPlatformOnboard = 0, + PchHdaCodecExternalKit = 1 +}; + +/** + Add verb table function. + This function update the verb table number and verb table ptr of policy. + + @param[in] HdAudioConfig HDAudie config block + @param[in] CodecType Platform codec type indicator + @param[in] AudioConnectorType Platform audio connector type +**/ +STATIC +VOID +InternalAddPlatformVerbTables ( + IN OUT FSPS_UPD *FspsUpd, + IN UINT8 CodecType, + IN UINT8 AudioConnectorType + ) +{ + UINT8 VerbTableEntryNum; + UINT32 VerbTableArray[32]; + UINT32 *VerbTablePtr; + + VerbTableEntryNum = 0; + + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdDisplayAudioHdaVerbTable)); + + if (CodecType == PchHdaCodecPlatformOnboard) { + DEBUG ((DEBUG_INFO, "HDA Policy: Onboard codec selected\n")); + if ((VOID *) (UINTN) PcdGet32 (PcdExtHdaVerbTable) != NULL) { + if (AudioConnectorType == 0) { //Type-C Audio connector selected in Bios Setup menu + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdExtHdaVerbTable)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); + DEBUG ((DEBUG_INFO, "HDA: Type-C Audio connector selected!\n")); + } else { //Stacked Jack Audio connector selected in Bios Setup menu + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable2)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); + DEBUG ((DEBUG_INFO, "HDA: Stacked-Jack Audio connector selected!\n")); + } + } else { + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable2)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); + } + } else { + DEBUG ((DEBUG_INFO, "HDA Policy: External codec kit selected\n")); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable1)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable2)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable3)); + } + + FspsUpd->FspsConfig.PchHdaVerbTableEntryNum = VerbTableEntryNum; + + VerbTablePtr = (UINT32 *) AllocateZeroPool (sizeof (UINT32) * VerbTableEntryNum); + CopyMem (VerbTablePtr, VerbTableArray, sizeof (UINT32) * VerbTableEntryNum); + FspsUpd->FspsConfig.PchHdaVerbTablePtr = (UINT32) VerbTablePtr; +} + +/** + Performs FSP PCH PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyUpdate ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + + FspsUpd->FspsConfig.PchSubSystemVendorId = V_PCH_INTEL_VENDOR_ID; + FspsUpd->FspsConfig.PchSubSystemId = V_PCH_DEFAULT_SID; + + FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr = (UINT32) mPcieDeviceTable; + + InternalAddPlatformVerbTables (FspsUpd, PchHdaCodecPlatformOnboard, PcdGet8 (PcdAudioConnector)); + +DEBUG_CODE_BEGIN(); +if ((PcdGet8 (PcdSerialIoUartDebugEnable) == 1) && + FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (PcdSerialIoUartNumber)] == PchSerialIoDisabled ) { + FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (PcdSerialIoUartNumber)] = PchSerialIoLegacyUart; + } +DEBUG_CODE_END(); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h new file mode 100644 index 00000000..30d2f99e --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h @@ -0,0 +1,27 @@ +/** @file + +Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PEI_PCH_POLICY_UPDATE_H_ +#define _PEI_PCH_POLICY_UPDATE_H_ + +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#endif diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c new file mode 100644 index 00000000..f6390ee1 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c @@ -0,0 +1,248 @@ +/** @file + This file is SampleCode of the library for Intel PCH PEI Policy initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PeiPchPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +InstallPlatformHsioPtssTable ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + HSIO_PTSS_TABLES *UnknowPtssTables; + HSIO_PTSS_TABLES *SpecificPtssTables; + HSIO_PTSS_TABLES *PtssTables; + UINT8 PtssTableIndex; + UINT32 UnknowTableSize; + UINT32 SpecificTableSize; + UINT32 TableSize; + UINT32 Entry; + UINT8 LaneNum; + UINT8 Index; + UINT8 MaxSataPorts; + UINT8 MaxPciePorts; + UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PciePort; + UINTN RpBase; + UINTN RpDevice; + UINTN RpFunction; + UINT32 StrapFuseCfg; + UINT8 PcieControllerCfg; + EFI_STATUS Status; + + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + + if (GetPchGeneration () == SklPch) { + switch (PchStepping ()) { + case PchLpB0: + case PchLpB1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable1); + UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable1Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable1); + SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable1Size); + break; + case PchLpC0: + case PchLpC1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable2Size); + break; + case PchHB0: + case PchHC0: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable1); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable1Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable1); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable1Size); + break; + case PchHD0: + case PchHD1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size); + break; + default: + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); + } + } else { + switch (PchStepping ()) { + case KblPchHA0: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size); + break; + default: + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); + } + } + + PtssTableIndex = 0; + MaxSataPorts = GetPchMaxSataPortNum (); + MaxPciePorts = GetPchMaxPciePortNum (); + ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal)); + + //Populate PCIe topology based on lane configuration + for (PciePort = 0; PciePort < MaxPciePorts; PciePort += 4) { + Status = GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction); + ASSERT_EFI_ERROR (Status); + + RpBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction); + StrapFuseCfg = MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG); + PcieControllerCfg = (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC); + DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value = %d\n", PciePort, PcieControllerCfg)); + } + for (Index = 0; Index < MaxPciePorts; Index++) { + DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology = %d\n", Index, PcieTopologyReal[Index])); + } + + //Case 1: BoardId is known, Topology is known/unknown + //Case 1a: SATA + PtssTables = SpecificPtssTables; + TableSize = SpecificTableSize; + for (Index = 0; Index < MaxSataPorts; Index++) { + if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA) + ) + { + PtssTableIndex++; + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) { + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; + } else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8)) { + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) { + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); + } + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) { + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); + } + } else { + ASSERT (FALSE); + } + } + } + } + } + //Case 1b: PCIe + for (Index = 0; Index < MaxPciePorts; Index++) { + if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) && + (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) { + PtssTableIndex++; + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) { + FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); + } else { + ASSERT (FALSE); + } + } + } + } + } + //Case 2: BoardId is unknown, Topology is known/unknown + if (PtssTableIndex == 0) { + DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be applied\n")); + + PtssTables = UnknowPtssTables; + TableSize = UnknowTableSize; + + for (Index = 0; Index < MaxSataPorts; Index++) { + if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA) + ) + { + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) { + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; + } else if (PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8) { + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) { + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); + } + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) { + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); + } + } else { + ASSERT (FALSE); + } + } + } + } + } + for (Index = 0; Index < MaxPciePorts; Index++) { + if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) && + (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) { + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) { + FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); + } else { + ASSERT (FALSE); + } + } + } + } + } + } +} + +/** + Performs FSP PCH PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + InstallPlatformHsioPtssTable (FspmUpd); + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c new file mode 100644 index 00000000..d6ec3e38 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c @@ -0,0 +1,84 @@ +/** @file +Do Platform Stage System Agent initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PeiSaPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Performs FSP SA PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyUpdate ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + VOID *Buffer; + VOID *MemBuffer; + UINT32 Size; + + DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); + + FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1; + + Size = 0; + Buffer = NULL; + PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size); + if (Buffer == NULL) { + DEBUG((DEBUG_WARN, "Could not locate VBT\n")); + } else { + MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); + if ((MemBuffer != NULL) && (Buffer != NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + FspsUpd->FspsConfig.GraphicsConfigPtr = (UINT32)(UINTN)MemBuffer; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n")); + FspsUpd->FspsConfig.GraphicsConfigPtr = 0; + } + } + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.GraphicsConfigPtr)); + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size)); + + Size = 0; + Buffer = NULL; + PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, &Size); + if (Buffer == NULL) { + DEBUG((DEBUG_WARN, "Could not locate Logo\n")); + } else { + MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); + if ((MemBuffer != NULL) && (Buffer != NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + FspsUpd->FspsConfig.LogoPtr = (UINT32)(UINTN)MemBuffer; + FspsUpd->FspsConfig.LogoSize = Size; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n")); + FspsUpd->FspsConfig.LogoPtr = 0; + FspsUpd->FspsConfig.LogoSize = 0; + } + } + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.LogoPtr)); + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.LogoSize)); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h new file mode 100644 index 00000000..3abf3fc8 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h @@ -0,0 +1,30 @@ +/** @file + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PEI_SA_POLICY_UPDATE_H_ +#define _PEI_SA_POLICY_UPDATE_H_ + +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#include +#include +#include +#include +#include "PeiPchPolicyUpdate.h" +#include +#include + +#include +#include +#include + +extern EFI_GUID gTianoLogoGuid; + +#endif + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c new file mode 100644 index 00000000..f95f82a2 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c @@ -0,0 +1,79 @@ +/** @file +Do Platform Stage System Agent initialization. + +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PeiSaPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/** + Performs FSP SA PEI Policy initialization in pre-memory. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + VOID *Buffer; + + // + // If SpdAddressTable are not all 0, it means DIMM slots implemented and + // MemorySpdPtr* already updated by reading SPD from DIMM in SiliconPolicyInitPreMem. + // + // If SpdAddressTable all 0, this is memory down design and hardcoded SpdData + // should be applied to MemorySpdPtr*. + // + if ((PcdGet8 (PcdMrcSpdAddressTable0) == 0) && (PcdGet8 (PcdMrcSpdAddressTable1) == 0) + && (PcdGet8 (PcdMrcSpdAddressTable2) == 0) && (PcdGet8 (PcdMrcSpdAddressTable3) == 0)) { + DEBUG((DEBUG_INFO, "Override MemorySpdPtr...\n")); + CopyMem((VOID *)(UINTN)FspmUpd->FspmConfig.MemorySpdPtr00, (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize)); + CopyMem((VOID *)(UINTN)FspmUpd->FspmConfig.MemorySpdPtr10, (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize)); + } + + DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n")); + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12); + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) Buffer + 12, 12); + } + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, 8); + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, (UINT8*) Buffer + 8, 8); + } + + DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp Target Settings...\n")); + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6); + } + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10); + } + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf new file mode 100644 index 00000000..f8bec0c8 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf @@ -0,0 +1,150 @@ +## @file +# Provide FSP wrapper platform related function. +# +# Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SiliconPolicyUpdateLibFsp + FILE_GUID = 4E83003B-49A9-459E-AAA6-1CA3C6D04FB2 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconPolicyUpdateLib + + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 +# + +################################################################################ +# +# Sources Section - list of files that are required for the build to succeed. +# +################################################################################ + +[Sources] + PeiFspPolicyUpdateLib.c + PeiPchPolicyUpdatePreMem.c + PeiPchPolicyUpdate.c + PeiSaPolicyUpdatePreMem.c + PeiSaPolicyUpdate.c + PeiFspMiscUpdUpdateLib.c + PcieDeviceTable.c + +################################################################################ +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +################################################################################ + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + KabylakeSiliconPkg/SiPkg.dec + KabylakeFspBinPkg/KabylakeFspBinPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[LibraryClasses.IA32] + FspWrapperApiLib + OcWdtLib + PchResetLib + FspWrapperPlatformLib + BaseMemoryLib + CpuPlatformLib + DebugLib + HobLib + IoLib + PcdLib + PostCodeLib + SmbusLib + MmPciLib + ConfigBlockLib + PeiSaPolicyLib + PchGbeLib + PchInfoLib + PchHsioLib + PchPcieRpLib + MemoryAllocationLib + CpuMailboxLib + DebugPrintErrorLevelLib + SiPolicyLib + PchGbeLib + TimerLib + GpioLib + PeiLib + +[Pcd] + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES + + # SPD Address Table + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 ## CONSUMES + + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES + + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size + + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdExtHdaVerbTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDisplayAudioHdaVerbTable + + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAudioConnector + + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid + +[Guids] + gFspNonVolatileStorageHobGuid ## CONSUMES + gTianoLogoGuid ## CONSUMES + gEfiMemoryOverwriteControlDataGuid + +[Depex] + gEdkiiVTdInfoPpiGuid + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/EcCommands.h b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/EcCommands.h new file mode 100644 index 00000000..a4ab192d --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/EcCommands.h @@ -0,0 +1,46 @@ +/** @file + Definition for supported EC commands. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef EC_COMMANDS_H_ +#define EC_COMMANDS_H_ + +// +// Timeout if EC command/data fails +// +#define EC_TIME_OUT 0x20000 + +// +// The EC implements an embedded controller interface at ports 0x60/0x64 and a ACPI compliant +// system management controller at ports 0x62/0x66. Port 0x66 is the command and status port, +// port 0x62 is the data port. +// +#define EC_D_PORT 0x62 +#define EC_C_PORT 0x66 + +// +// Status Port 0x62 +// +#define EC_S_OVR_TMP 0x80 // Current CPU temperature exceeds the threshold +#define EC_S_SMI_EVT 0x40 // SMI event is pending +#define EC_S_SCI_EVT 0x20 // SCI event is pending +#define EC_S_BURST 0x10 // EC is in burst mode or normal mode +#define EC_S_CMD 0x08 // Byte in data register is command/data +#define EC_S_IGN 0x04 // Ignored +#define EC_S_IBF 0x02 // Input buffer is full/empty +#define EC_S_OBF 0x01 // Output buffer is full/empty + +// +// EC commands that are issued to the EC through the command port (0x66). +// New commands and command parameters should only be written by the host when IBF=0. +// Data read from the EC data port is valid only when OBF=1. +// +#define EC_C_FAB_ID 0x0D // Get the board fab ID in the lower 3 bits +#define EC_C_ACPI_READ 0x80 // Read a byte of EC RAM +#define EC_C_ACPI_WRITE 0x81 // Write a byte of EC RAM + +#endif // EC_COMMANDS_H_ diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/FlashMapInclude.fdf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/FlashMapInclude.fdf new file mode 100644 index 00000000..b5e3f66c --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/FlashMapInclude.fdf @@ -0,0 +1,48 @@ +## @file +# FDF file for the KabylakeRvp3 board. +# +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +#=================================================================================# +# 8 M BIOS - for FSP wrapper +#=================================================================================# +DEFINE FLASH_BASE = 0xFF800000 # +DEFINE FLASH_SIZE = 0x00800000 # +DEFINE FLASH_BLOCK_SIZE = 0x00010000 # +DEFINE FLASH_NUM_BLOCKS = 0x00000080 # +#=================================================================================# + +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000 # Flash addr (0xFF800000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize = 0x00040000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = 0x00000000 # Flash addr (0xFF800000) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0001E000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = 0x0001E000 # Flash addr (0xFF81E000) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = 0x00002000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = 0x00020000 # Flash addr (0xFF820000) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = 0x00020000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00040000 # Flash addr (0xFF840000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = 0x00050000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x00090000 # Flash addr (0xFF890000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00070000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = 0x00100000 # Flash addr (0xFF900000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00090000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = 0x00190000 # Flash addr (0xFF990000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x001E0000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = 0x00370000 # Flash addr (0xFFB70000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00180000 # +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = 0x004F0000 # Flash addr (0xFFCF0000) +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = 0x000A0000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = 0x00590000 # Flash addr (0xFFD90000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = 0x00060000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = 0x005F0000 # Flash addr (0xFFDF0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize = 0x000BC000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = 0x006AC000 # Flash addr (0xFFEAC000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize = 0x00014000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset = 0x006C0000 # Flash addr (0xFFEC0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize = 0x00010000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = 0x006D0000 # Flash addr (0xFFED0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = 0x00130000 # diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.c new file mode 100644 index 00000000..c7fc6986 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.c @@ -0,0 +1,662 @@ +/** @file + Platform Hook Library instances + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define COM1_BASE 0x3f8 +#define COM2_BASE 0x2f8 + +#define SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS 0x0690 + +#define LPC_SIO_INDEX_DEFAULT_PORT_2 0x2E +#define LPC_SIO_DATA_DEFAULT_PORT_2 0x2F +#define LPC_SIO_GPIO_REGISTER_ADDRESS_2 0x0A20 + +#define LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT 0x2E +#define LEGACY_DAUGHTER_CARD_SIO_DATA_PORT 0x2F +#define LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT 0x4E +#define LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT 0x4F + +typedef struct { + UINT8 Register; + UINT8 Value; +} EFI_SIO_TABLE; + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTable[] = { + {0x002, 0x88}, // Power On UARTs + {0x024, COM1_BASE >> 2}, + {0x025, COM2_BASE >> 2}, + {0x028, 0x043}, // IRQ of UARTs, UART2 IRQ=3,UART1 IRQ=4, + {0x029, 0x080}, // SIRQ_CLKRUN_EN + {0x02A, 0x000}, + {0x02B, 0x0DE}, + {0x00A, 0x040}, + {0x00C, 0x00E}, + {0x02c, 0x002}, + {0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4}, + {0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8}, + {0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff}, + {0x03a, 0x00A}, // LPC Docking Enabling + {0x031, 0x01f}, + {0x032, 0x000}, + {0x033, 0x004}, + {0x038, 0x0FB}, + {0x035, 0x0FE}, + {0x036, 0x000}, + {0x037, 0x0FF}, + {0x039, 0x000}, + {0x034, 0x001}, + {0x012, FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & 0xFF}, // Relocate configuration ports base address + {0x013, (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) >> 8) & 0xFF} // to ensure SIO config address can be accessed in OS +}; + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableSmsc1000[] = { + {0x002, 0x88}, // Power On UARTs + {0x007, 0x00}, + {0x024, COM1_BASE >> 2}, + {0x025, COM2_BASE >> 2}, + {0x028, 0x043}, // IRQ of UARTs, UART2 IRQ=3,UART1 IRQ=4, + {0x029, 0x080}, // SIRQ_CLKRUN_EN + {0x02A, 0x000}, + {0x02B, 0x0DE}, + {0x00A, 0x040}, + {0x00C, 0x00E}, + {0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4}, + {0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8}, + {0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff}, + {0x03a, 0x00A}, // LPC Docking Enabling + {0x031, 0x01f}, + {0x032, 0x000}, + {0x033, 0x004}, + {0x038, 0x0FB}, + {0x035, 0x0FE}, + {0x036, 0x000}, + {0x037, 0x0FE}, + {0x039, 0x000}, + {0x034, 0x001} +}; + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWpcn381u[] = { + {0x29, 0x0A0}, // Enable super I/O clock and set to 48MHz + {0x22, 0x003}, // + {0x07, 0x003}, // Select UART0 device + {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB + {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB + {0x70, 0x004}, // Set to IRQ4 + {0x30, 0x001}, // Enable it with Activation bit + {0x07, 0x002}, // Select UART1 device + {0x60, (COM2_BASE >> 8)}, // Set Base Address MSB + {0x61, (COM2_BASE & 0x00FF)}, // Set Base Address LSB + {0x70, 0x003}, // Set to IRQ3 + {0x30, 0x001}, // Enable it with Activation bit + {0x07, 0x007}, // Select GPIO device + {0x60, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 >> 8)}, // Set Base Address MSB + {0x61, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 & 0x00FF)}, // Set Base Address LSB + {0x30, 0x001}, // Enable it with Activation bit + {0x21, 0x001}, // Global Device Enable + {0x26, 0x000} // Fast Enable UART 0 & 1 as their enable & activation bit +}; + +// +// National PC8374L +// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mDesktopSioTable[] = { + {0x007, 0x03}, // Select Com1 + {0x061, 0xF8}, // 0x3F8 + {0x060, 0x03}, // 0x3F8 + {0x070, 0x04}, // IRQ4 + {0x030, 0x01} // Active +}; + +// +// IT8628 +// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableSerialPort[] = { + {0x023, 0x09}, // Clock Selection register + {0x007, 0x01}, // Com1 Logical Device Number select + {0x061, 0xF8}, // Serial Port 1 Base Address MSB Register + {0x060, 0x03}, // Serial Port 1 Base Address LSB Register + {0x070, 0x04}, // Serial Port 1 Interrupt Level Select + {0x030, 0x01}, // Serial Port 1 Activate + {0x007, 0x02}, // Com1 Logical Device Number select + {0x061, 0xF8}, // Serial Port 2 Base Address MSB Register + {0x060, 0x02}, // Serial Port 2 Base Address MSB Register + {0x070, 0x03}, // Serial Port 2 Interrupt Level Select + {0x030, 0x01} // Serial Port 2 Activate +}; + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableParallelPort[] = { + {0x007, 0x03}, // Parallel Port Logical Device Number select + {0x030, 0x00}, // Parallel port Activate + {0x061, 0x78}, // Parallel Port Base Address 1 MSB Register + {0x060, 0x03}, // Parallel Port Base Address 1 LSB Register + {0x063, 0x78}, // Parallel Port Base Address 2 MSB Register + {0x062, 0x07}, // Parallel Port Base Address 1 LSB Register + {0x0F0, 0x03} // Special Configuration register +}; + + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWinbondX374[] = { + {0x07, 0x03}, // Select UART0 device + {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB + {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB + {0x70, 0x04}, // Set to IRQ4 + {0x30, 0x01} // Enable it with Activation bit +}; + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTablePilot3[] = { + {0x07, 0x02}, // Set logical device SP Serial port Com0 + {0x61, 0xF8}, // Write Base Address LSB register 0x3F8 + {0x60, 0x03}, // Write Base Address MSB register 0x3F8 + {0x70, 0x04}, // Write IRQ1 value (IRQ 1) keyboard + {0x30, 0x01} // Enable serial port with Activation bit +}; + +/** + Detect if a National 393 SIO is docked. If yes, enable the docked SIO + and its serial port, and disable the onboard serial port. + + @retval EFI_SUCCESS Operations performed successfully. +**/ +STATIC +VOID +CheckNationalSio ( + VOID + ) +{ + UINT8 Data8; + + // + // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f). + // We use (0x2e, 0x2f) which is determined by BADD default strapping + // + + // + // Read the Pc87393 signature + // + IoWrite8 (0x2e, 0x20); + Data8 = IoRead8 (0x2f); + + if (Data8 == 0xea) { + // + // Signature matches - National PC87393 SIO is docked + // + + // + // Enlarge the LPC decode scope to accommodate the Docking LPC Switch + // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated at + // SIO_BASE_ADDRESS + 0x10) + // + PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & (UINT16)~0x7F), 0x20); + + // + // Enable port switch + // + IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06); + + // + // Turn on docking power + // + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c); + + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c); + + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc); + + // + // Enable port switch + // + IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7); + + // + // GPIO setting + // + IoWrite8 (0x2e, 0x24); + IoWrite8 (0x2f, 0x29); + + // + // Enable chip clock + // + IoWrite8 (0x2e, 0x29); + IoWrite8 (0x2f, 0x1e); + + + // + // Enable serial port + // + + // + // Select com1 + // + IoWrite8 (0x2e, 0x7); + IoWrite8 (0x2f, 0x3); + + // + // Base address: 0x3f8 + // + IoWrite8 (0x2e, 0x60); + IoWrite8 (0x2f, 0x03); + IoWrite8 (0x2e, 0x61); + IoWrite8 (0x2f, 0xf8); + + // + // Interrupt: 4 + // + IoWrite8 (0x2e, 0x70); + IoWrite8 (0x2f, 0x04); + + // + // Enable bank selection + // + IoWrite8 (0x2e, 0xf0); + IoWrite8 (0x2f, 0x82); + + // + // Activate + // + IoWrite8 (0x2e, 0x30); + IoWrite8 (0x2f, 0x01); + + // + // Disable onboard serial port + // + IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55); + + // + // Power Down UARTs + // + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2); + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00); + + // + // Dissable COM1 decode + // + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24); + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); + + // + // Disable COM2 decode + // + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25); + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); + + // + // Disable interrupt + // + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28); + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0); + + IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA); + + // + // Enable floppy + // + + // + // Select floppy + // + IoWrite8 (0x2e, 0x7); + IoWrite8 (0x2f, 0x0); + + // + // Base address: 0x3f0 + // + IoWrite8 (0x2e, 0x60); + IoWrite8 (0x2f, 0x03); + IoWrite8 (0x2e, 0x61); + IoWrite8 (0x2f, 0xf0); + + // + // Interrupt: 6 + // + IoWrite8 (0x2e, 0x70); + IoWrite8 (0x2f, 0x06); + + // + // DMA 2 + // + IoWrite8 (0x2e, 0x74); + IoWrite8 (0x2f, 0x02); + + // + // Activate + // + IoWrite8 (0x2e, 0x30); + IoWrite8 (0x2f, 0x01); + + } else { + + // + // No National pc87393 SIO is docked, turn off dock power and + // disable port switch + // + // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf); + // IoWrite8 (0x690, 0); + + // + // If no National pc87393, just return + // + return; + } +} + + +/** +Check whether the IT8628 SIO present on LPC. If yes, enable its serial +ports, parallel port, and port 80. + +@retval EFI_SUCCESS Operations performed successfully. +**/ +STATIC +VOID +It8628SioSerialPortInit ( + VOID + ) +{ + UINT8 ChipId0 = 0; + UINT8 ChipId1 = 0; + UINT16 LpcIoDecondeRangeSet = 0; + UINT16 LpcIoDecoodeSet = 0; + UINT8 Index; + UINTN LpcBaseAddr; + + + // + // Enable I/O decoding for COM1 (3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh. + // + LpcBaseAddr = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + + LpcIoDecondeRangeSet = (UINT16) MmioRead16 (LpcBaseAddr + R_PCH_LPC_IOD); + LpcIoDecoodeSet = (UINT16) MmioRead16 (LpcBaseAddr + R_PCH_LPC_IOE); + MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOD), (LpcIoDecondeRangeSet | ((V_PCH_LPC_IOD_COMB_2F8 << 4) | V_PCH_LPC_IOD_COMA_3F8))); + MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOE), (LpcIoDecoodeSet | (B_PCH_LPC_IOE_SE | B_PCH_LPC_IOE_CBE | B_PCH_LPC_IOE_CAE))); + + // + // Enter MB PnP Mode + // + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x87); + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x01); + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55); + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55); + + // + // Read Chip Id of SIO IT8628 (registers 0x20 and 0x21) + // + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x20); + ChipId0 = IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2); + + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x21); + ChipId1 = IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2); + + // + // Enable Serial Port 1, Port 2 + // + if ((ChipId0 == 0x86) && (ChipId1 == 0x28)) { + for (Index = 0; Index < sizeof (mSioIt8628TableSerialPort) / sizeof (EFI_SIO_TABLE); Index++) { + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Index].Register); + IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Index].Value); + } + } + + // + // Exit MB PnP Mode + // + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x02); + IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, 0x02); + + return; +} + + +/** + Performs platform specific initialization required for the CPU to access + the hardware associated with a SerialPortLib instance. This function does + not initialize the serial port hardware itself. Instead, it initializes + hardware devices that are required for the CPU to access the serial port + hardware. This function may be called more than once. + + @retval RETURN_SUCCESS The platform specific initialization succeeded. + @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed. + +**/ +RETURN_STATUS +EFIAPI +PlatformHookSerialPortInitialize ( + VOID + ) +{ + UINT16 ConfigPort; + UINT16 IndexPort; + UINT16 DataPort; + UINT16 DeviceId; + UINT8 Index; + UINT16 AcpiBase; + + // + // Set the ICH ACPI Base Address (Reg#40h) and ACPI Enable bit + // in ACPI Controll (Reg#44h bit7) for PrePpiStall function use. + // + IndexPort = 0; + DataPort = 0; + Index = 0; + AcpiBase = 0; + PchAcpiBaseGet (&AcpiBase); + if (AcpiBase == 0) { + PchAcpiBaseSet (PcdGet16 (PcdAcpiBaseAddress)); + } + + // + // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h. + // + PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange)); + PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding)); + + // Configure Sio IT8628 + It8628SioSerialPortInit (); + + DeviceId = MmioRead16 (MmPciBase (SA_MC_BUS, 0, 0) + R_SA_MC_DEVICE_ID); + if (IS_SA_DEVICE_ID_MOBILE (DeviceId)) { + // + // if no EC, it is SV Bidwell Bar board + // + if ((IoRead8 (0x66) != 0xFF) && (IoRead8 (0x62) != 0xFF)) { + // + // Super I/O initialization for SMSC SI1007 + // + ConfigPort = FixedPcdGet16 (PcdLpcSioConfigDefaultPort); + DataPort = PcdGet16 (PcdLpcSioDataDefaultPort); + IndexPort = PcdGet16 (PcdLpcSioIndexDefaultPort); + + // + // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF; + // + PchLpcGenIoRangeSet (FixedPcdGet16 (PcdSioBaseAddress) & (~0x7F), 0x10); + + // + // Program and Enable Default Super IO Configuration Port Addresses and range + // + PchLpcGenIoRangeSet (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x10); + + // + // Enter Config Mode + // + IoWrite8 (ConfigPort, 0x55); + + // + // Check for SMSC SIO1007 + // + IoWrite8 (IndexPort, 0x0D); // SMSC SIO1007 Device ID register is 0x0D + if (IoRead8 (DataPort) == 0x20) { // SMSC SIO1007 Device ID is 0x20 + // + // Configure SIO + // + for (Index = 0; Index < sizeof (mSioTable) / sizeof (EFI_SIO_TABLE); Index++) { + IoWrite8 (IndexPort, mSioTable[Index].Register); + IoWrite8 (DataPort, mSioTable[Index].Value); + } + + // + // Exit Config Mode + // + IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA); + + // + // GPIO 15-17:IN 10-14:OUT Enable RS232 ref: Page42 of CRB_SCH + // + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0c, 0x1f); + } + + // + // Check if a National Pc87393 SIO is docked + // + CheckNationalSio (); + + // + // Super I/O initialization for SMSC SIO1000 + // + ConfigPort = PcdGet16 (PcdLpcSioIndexPort); + IndexPort = PcdGet16 (PcdLpcSioIndexPort); + DataPort = PcdGet16 (PcdLpcSioDataPort); + + // + // Enter Config Mode + // + IoWrite8 (ConfigPort, 0x55); + + // + // Check for SMSC SIO1000 + // + if (IoRead8 (ConfigPort) != 0xFF) { + // + // Configure SIO + // + for (Index = 0; Index < sizeof (mSioTableSmsc1000) / sizeof (EFI_SIO_TABLE); Index++) { + IoWrite8 (IndexPort, mSioTableSmsc1000[Index].Register); + IoWrite8 (DataPort, mSioTableSmsc1000[Index].Value); + } + + // + // Exit Config Mode + // + IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA); + } + + // + // Super I/O initialization for Winbond WPCN381U + // + IndexPort = LPC_SIO_INDEX_DEFAULT_PORT_2; + DataPort = LPC_SIO_DATA_DEFAULT_PORT_2; + + // + // Check for Winbond WPCN381U + // + IoWrite8 (IndexPort, 0x20); // Winbond WPCN381U Device ID register is 0x20 + if (IoRead8 (DataPort) == 0xF4) { // Winbond WPCN381U Device ID is 0xF4 + // + // Configure SIO + // + for (Index = 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI_SIO_TABLE); Index++) { + IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register); + IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value); + } + } + } //EC is not exist, skip mobile board detection for SV board + + // + //add for SV Bidwell Bar board + // + if (IoRead8 (COM1_BASE) == 0xFF) { + // + // Super I/O initialization for Winbond WPCD374 (LDC2) and 8374 (LDC) + // Looking for LDC2 card first + // + IoWrite8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT, 0x55); + if (IoRead8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT) == 0x55) { + IndexPort = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT; + DataPort = LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT; + } else { + IndexPort = LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT; + DataPort = LEGACY_DAUGHTER_CARD_SIO_DATA_PORT; + } + + IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID register is 0x20 + if (IoRead8 (DataPort) == 0xF1) { // Winbond x374 Device ID is 0xF1 + for (Index = 0; Index < sizeof (mSioTableWinbondX374) / sizeof (EFI_SIO_TABLE); Index++) { + IoWrite8 (IndexPort, mSioTableWinbondX374[Index].Register); + IoWrite8 (DataPort, mSioTableWinbondX374[Index].Value); + } + } + }// end of Bidwell Bar SIO initialization + } else if (IS_SA_DEVICE_ID_DESKTOP (DeviceId) || IS_SA_DEVICE_ID_SERVER (DeviceId)) { + // + // If we are in debug mode, we will allow serial status codes + // + + // + // National PC8374 SIO & Winbond WPCD374 (LDC2) + // + IndexPort = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT; + + IoWrite8 (IndexPort, 0x55); + if (IoRead8 (IndexPort) == 0x55) { + IndexPort = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT; + DataPort = LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT; + } else { + IndexPort = LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT; + DataPort = LEGACY_DAUGHTER_CARD_SIO_DATA_PORT; + } + + // + // Configure SIO + // + IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID register is 0x20 + if (IoRead8 (DataPort) == 0xF1) { // Winbond x374 Device ID is 0xF1 + for (Index = 0; Index < sizeof (mDesktopSioTable) / sizeof (EFI_SIO_TABLE); Index++) { + IoWrite8 (IndexPort, mDesktopSioTable[Index].Register); + //PrePpiStall (200); + IoWrite8 (DataPort, mDesktopSioTable[Index].Value); + //PrePpiStall (200); + } + return RETURN_SUCCESS; + } + // + // Configure Pilot3 SIO + // + IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_UNLOCK); //Enter config mode. + IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_CHIP_ID_REG); // Pilot3 SIO Device ID register is 0x20. + if (IoRead8 (PILOTIII_SIO_DATA_PORT) == PILOTIII_CHIP_ID) { // Pilot3 SIO Device ID register is 0x03. + // + // Configure SIO + // + for (Index = 0; Index < sizeof (mSioTablePilot3) / sizeof (EFI_SIO_TABLE); Index++) { + IoWrite8 (PILOTIII_SIO_INDEX_PORT, mSioTablePilot3[Index].Register); + IoWrite8 (PILOTIII_SIO_DATA_PORT, mSioTablePilot3[Index].Value); + } + } + IoWrite8 (PILOTIII_SIO_INDEX_PORT , PILOTIII_LOCK); //Exit config mode. + } + + + return RETURN_SUCCESS; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.inf new file mode 100644 index 00000000..7a5e2906 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.inf @@ -0,0 +1,51 @@ +### @file +# Platform Hook Library instance for Kaby Lake RVP3. +# +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = BasePlatformHookLib + FILE_GUID = E22ADCC6-ED90-4A90-9837-C8E7FF9E963D + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = PlatformHookLib +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + MmPciLib + PciLib + PchCycleDecodingLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + KabylakeSiliconPkg/SiPkg.dec + +[Pcd] + gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataDefaultPort ## CONSUMES + +[FixedPcd] + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES + +[Sources] + BasePlatformHookLib.c diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c new file mode 100644 index 00000000..8699f8d4 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c @@ -0,0 +1,36 @@ +/** @file + Kaby Lake RVP 3 Board ACPI library + +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +KabylakeRvp3BoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ); + +EFI_STATUS +EFIAPI +BoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +{ + KabylakeRvp3BoardUpdateAcpiTable (Table, Version); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf new file mode 100644 index 00000000..e0bf5823 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf @@ -0,0 +1,48 @@ +### @file +# Kaby Lake RVP 3 Board ACPI library +# +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = DxeBoardAcpiTableLib + FILE_GUID = 6562E0AE-90D8-4D41-8C97-81286B4BE7D2 + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = BoardAcpiTableLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + AslUpdateLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + KabylakeSiliconPkg/SiPkg.dec + BoardModulePkg/BoardModulePkg.dec + +[Pcd] + gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress + +[Sources] + DxeKabylakeRvp3AcpiTableLib.c + DxeBoardAcpiTableLib.c + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeKabylakeRvp3AcpiTableLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeKabylakeRvp3AcpiTableLib.c new file mode 100644 index 00000000..d66283f7 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeKabylakeRvp3AcpiTableLib.c @@ -0,0 +1,76 @@ +/** @file + Kaby Lake RVP 3 Board ACPI Library + +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_GLOBAL_NVS_AREA_PROTOCOL mGlobalNvsArea; + +VOID +KabylakeRvp3UpdateGlobalNvs ( + VOID + ) +{ + + // + // Allocate and initialize the NVS area for SMM and ASL communication. + // + mGlobalNvsArea.Area = (VOID *)(UINTN)PcdGet64 (PcdAcpiGnvsAddress); + + // + // Update global NVS area for ASL and SMM init code to use + // + + // + // Enable PowerState + // + mGlobalNvsArea.Area->PowerState = 1; // AC =1; for mobile platform, will update this value in SmmPlatform.c + + mGlobalNvsArea.Area->NativePCIESupport = PcdGet8 (PcdPciExpNative); + + // + // Enable APIC + // + mGlobalNvsArea.Area->ApicEnable = GLOBAL_NVS_DEVICE_ENABLE; + + // + // Low Power S0 Idle - Enabled/Disabled + // + mGlobalNvsArea.Area->LowPowerS0Idle = PcdGet8 (PcdLowPowerS0Idle); + + mGlobalNvsArea.Area->Ps2MouseEnable = FALSE; + mGlobalNvsArea.Area->Ps2KbMsEnable = PcdGet8 (PcdPs2KbMsEnable); + + mGlobalNvsArea.Area->BoardId = (UINT8) LibPcdGetSku (); +} + +EFI_STATUS +EFIAPI +KabylakeRvp3BoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +{ + if (Table->Signature == EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) { + KabylakeRvp3UpdateGlobalNvs (); + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c new file mode 100644 index 00000000..dfb1b028 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c @@ -0,0 +1,43 @@ +/** @file + Kaby Lake RVP 3 Multi-Board ACPI Support library + +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +KabylakeRvp3BoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ); + +BOARD_ACPI_TABLE_FUNC mKabylakeRvp3BoardAcpiTableFunc = { + KabylakeRvp3BoardUpdateAcpiTable +}; + +EFI_STATUS +EFIAPI +DxeKabylakeRvp3MultiBoardAcpiSupportLibConstructor ( + VOID + ) +{ + if ((LibPcdGetSku () == BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSku () == BoardIdSkylakeRvp3)) { + return RegisterBoardAcpiTableFunc (&mKabylakeRvp3BoardAcpiTableFunc); + } + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf new file mode 100644 index 00000000..e5de9268 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf @@ -0,0 +1,49 @@ +### @file +# Kaby Lake RVP 3 Multi-Board ACPI Support library +# +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = DxeKabylakeRvp3MultiBoardAcpiTableLib + FILE_GUID = 8E6A3B38-53E0-48C0-970F-058F380FCB80 + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = NULL + CONSTRUCTOR = DxeKabylakeRvp3MultiBoardAcpiSupportLibConstructor + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + AslUpdateLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + KabylakeSiliconPkg/SiPkg.dec + BoardModulePkg/BoardModulePkg.dec + +[Pcd] + gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress + +[Sources] + DxeKabylakeRvp3AcpiTableLib.c + DxeMultiBoardAcpiSupportLib.c + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c new file mode 100644 index 00000000..e89624ea --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c @@ -0,0 +1,62 @@ +/** @file + Kaby Lake RVP 3 SMM Board ACPI Enable library + +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +KabylakeRvp3BoardEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +KabylakeRvp3BoardDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +BoardEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + SiliconEnableAcpi (EnableSci); + return KabylakeRvp3BoardEnableAcpi (EnableSci); +} + +EFI_STATUS +EFIAPI +BoardDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + SiliconDisableAcpi (DisableSci); + return KabylakeRvp3BoardDisableAcpi (DisableSci); +} + + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf new file mode 100644 index 00000000..46a714dc --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf @@ -0,0 +1,47 @@ +### @file +# Kaby Lake RVP 3 SMM Board ACPI Enable library +# +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = SmmBoardAcpiEnableLib + FILE_GUID = 549E69AE-D3B3-485B-9C17-AF16E20A58AD + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = BoardAcpiEnableLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + MmPciLib + PchCycleDecodingLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + KabylakeSiliconPkg/SiPkg.dec + +[Pcd] + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES + +[Protocols] + +[Sources] + SmmKabylakeRvp3AcpiEnableLib.c + SmmSiliconAcpiEnableLib.c + SmmBoardAcpiEnableLib.c + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmKabylakeRvp3AcpiEnableLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmKabylakeRvp3AcpiEnableLib.c new file mode 100644 index 00000000..54755dd1 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmKabylakeRvp3AcpiEnableLib.c @@ -0,0 +1,39 @@ +/** @file + Kaby Lake RVP 3 SMM Board ACPI Enable library + +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +KabylakeRvp3BoardEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + // enable additional board register + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +KabylakeRvp3BoardDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + // enable additional board register + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c new file mode 100644 index 00000000..fb678a19 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c @@ -0,0 +1,81 @@ +/** @file + Kaby Lake RVP 3 SMM Multi-Board ACPI Support library + +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +KabylakeRvp3BoardEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +KabylakeRvp3BoardDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +KabylakeRvp3MultiBoardEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + SiliconEnableAcpi (EnableSci); + return KabylakeRvp3BoardEnableAcpi (EnableSci); +} + +EFI_STATUS +EFIAPI +KabylakeRvp3MultiBoardDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + SiliconDisableAcpi (DisableSci); + return KabylakeRvp3BoardDisableAcpi (DisableSci); +} + +BOARD_ACPI_ENABLE_FUNC mKabylakeRvp3BoardAcpiEnableFunc = { + KabylakeRvp3MultiBoardEnableAcpi, + KabylakeRvp3MultiBoardDisableAcpi, +}; + +EFI_STATUS +EFIAPI +SmmKabylakeRvp3MultiBoardAcpiSupportLibConstructor ( + VOID + ) +{ + if ((LibPcdGetSku () == BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSku () == BoardIdSkylakeRvp3)) { + return RegisterBoardAcpiEnableFunc (&mKabylakeRvp3BoardAcpiEnableFunc); + } + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf new file mode 100644 index 00000000..fca63c83 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf @@ -0,0 +1,48 @@ +### @file +# Kaby Lake RVP 3 SMM Multi-Board ACPI Support library +# +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = SmmKabylakeRvp3MultiBoardAcpiSupportLib + FILE_GUID = 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5 + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = NULL + CONSTRUCTOR = SmmKabylakeRvp3MultiBoardAcpiSupportLibConstructor + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + MmPciLib + PchCycleDecodingLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + KabylakeSiliconPkg/SiPkg.dec + +[Pcd] + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES + +[Protocols] + +[Sources] + SmmKabylakeRvp3AcpiEnableLib.c + SmmSiliconAcpiEnableLib.c + SmmMultiBoardAcpiSupportLib.c + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c new file mode 100644 index 00000000..7f63a12b --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c @@ -0,0 +1,168 @@ +/** @file + Kaby Lake RVP 3 SMM Silicon ACPI Enable library + +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Clear Port 80h + + SMI handler to enable ACPI mode + + Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI + + Disables the SW SMI Timer. + ACPI events are disabled and ACPI event status is cleared. + SCI mode is then enabled. + + Clear SLP SMI status + Enable SLP SMI + + Disable SW SMI Timer + + Clear all ACPI event status and disable all ACPI events + + Disable PM sources except power button + Clear status bits + + Disable GPE0 sources + Clear status bits + + Disable GPE1 sources + Clear status bits + + Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) + + Enable SCI +**/ +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + UINT32 OutputValue; + UINT32 SmiEn; + UINT32 SmiSts; + UINT32 ULKMC; + UINTN LpcBaseAddress; + UINT16 AcpiBaseAddr; + UINT32 Pm1Cnt; + + LpcBaseAddress = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + + // + // Get the ACPI Base Address + // + PchAcpiBaseGet (&AcpiBaseAddr); + + // + // BIOS must also ensure that CF9GR is cleared and locked before handing control to the + // OS in order to prevent the host from issuing global resets and resetting ME + // + // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Reset + // MmioWrite32 ( + // PmcBaseAddress + R_PCH_PMC_ETR3), + // PmInit); + + // + // Clear Port 80h + // + IoWrite8 (0x80, 0); + + // + // Disable SW SMI Timer and clean the status + // + SmiEn = IoRead32 (AcpiBaseAddr + R_PCH_SMI_EN); + SmiEn &= ~(B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB); + IoWrite32 (AcpiBaseAddr + R_PCH_SMI_EN, SmiEn); + + SmiSts = IoRead32 (AcpiBaseAddr + R_PCH_SMI_STS); + SmiSts |= B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB; + IoWrite32 (AcpiBaseAddr + R_PCH_SMI_STS, SmiSts); + + // + // Disable port 60/64 SMI trap if they are enabled + // + ULKMC = MmioRead32 (LpcBaseAddress + R_PCH_LPC_ULKMC) & ~(B_PCH_LPC_ULKMC_60REN | B_PCH_LPC_ULKMC_60WEN | B_PCH_LPC_ULKMC_64REN | B_PCH_LPC_ULKMC_64WEN | B_PCH_LPC_ULKMC_A20PASSEN); + MmioWrite32 (LpcBaseAddress + R_PCH_LPC_ULKMC, ULKMC); + + // + // Disable PM sources except power button + // + IoWrite16 (AcpiBaseAddr + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN); + + // + // Clear PM status except Power Button status for RapidStart Resume + // + IoWrite16 (AcpiBaseAddr + R_PCH_ACPI_PM1_STS, 0xFEFF); + + // + // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) + // + IoWrite8 (R_PCH_RTC_INDEX_ALT, R_PCH_RTC_REGD); + IoWrite8 (R_PCH_RTC_TARGET_ALT, 0x0); + + // + // Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#) + // + OutputValue = IoRead32 (AcpiBaseAddr + 0x38); + OutputValue = OutputValue & ~(1 << (UINTN) PcdGet8 (PcdSmcExtSmiBitPosition)); + IoWrite32 (AcpiBaseAddr + 0x38, OutputValue); + + + // + // Enable SCI + // + if (EnableSci) { + Pm1Cnt = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT); + Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN; + IoWrite32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt); + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + UINT16 AcpiBaseAddr; + UINT32 Pm1Cnt; + + // + // Get the ACPI Base Address + // + PchAcpiBaseGet (&AcpiBaseAddr); + + // + // Disable SCI + // + if (DisableSci) { + Pm1Cnt = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT); + Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SCI_EN; + IoWrite32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt); + } + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/KabylakeRvp3GpioTable.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/KabylakeRvp3GpioTable.c new file mode 100644 index 00000000..2439c6bc --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/KabylakeRvp3GpioTable.c @@ -0,0 +1,381 @@ +/** @file + GPIO definition table for KabylakeRvp3 + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _KABYLAKE_RVP3_GPIO_TABLE_H_ +#define _KABYLAKE_RVP3_GPIO_TABLE_H_ + +#include +#include +#include +#include +#include + + +#define END_OF_GPIO_TABLE 0xFFFFFFFF + +GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] = +{ +//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//H_RCIN_N +//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0 +//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1 +//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2 +//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3 +//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N +//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ + {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S0ix_R_N +// skip for PM_CLKRUN_N {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N +//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK +// skip for PCH_CLK_PCI_TPM {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM + {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR + {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N +//skip for SUS_PWR_ACK_R {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R +//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N +//skip for SUSACK_R_N {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N + {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_SEL + {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_EN_N + {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0_SENSOR + {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1_SENSOR + {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2_SENSOR + {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHUB_IRQ + {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_N + {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//FPS_DRDY + {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID0 + {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID1 + {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALERTB + {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}},//TCH_PAD_INTR_R_N + {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KILL_N + {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N + // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT1_N + // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N + // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N + // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N + // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WLAN_N + {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT_PWR_GATEB + {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_S0_N + {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_N + {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_PWREN + // {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_DFU, NOT OWNED BY BIOS + {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N + {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//TBT_CIO_PLUG_EVENT_N + {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N + {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSPI1_CS_R1_N + {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1 + {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1 + {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1 + {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N + {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK + {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DATA + {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N + {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK + {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DATA + {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N + {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK, OWNED BY ME + {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_DATA, OWNED BY ME + {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RXD + {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_TXD + {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RTS_N + {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_CTS_N + {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD + {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD + {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N + {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N + {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SDA + {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SCL + {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SDA + {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SCL + {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD + {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD + {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RTS_N + {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_CTS_N + {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CS_N + {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CLK + {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MISO + {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MOSI + {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLASH_STROBE + {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SDA + {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SCL + {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SDA + {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SCL + {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//HOME_BTN + {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SCREEN_LOCK_PCH + {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_UP_PCH + {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_DOWN_PCH + {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA + {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK + {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RTS_N + {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N + {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_1 + {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DMIC_DATA_1 + {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_0 + {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DMIC_DATA_0 + {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO2 + {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO3 + {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK + {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N + {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD_PRSNT_N + {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N + {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_DFU_N + {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_RESET + {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R + // {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R, NOT OWNED BY BIOS + {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA_LED_N + {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0_WP1_OTG_N + {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1_WP4_N + {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N + // {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_IRQ, NOT OWNED BY BIOS + {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD_Q + {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD_Q + {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N + {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//SMC_RUNTIME_SCI_R_N + {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD + {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTRL_CLK + {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_CTRL_DATA + {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTRL_CLK + {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_CTRL_DATA + {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ + {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_RST_N + {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCLK + {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFRM + {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD + {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD + {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA + {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL + {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA + {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL + {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA + {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL + {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA + {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL + {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD + {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0 + {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1 + {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2 + {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3 + {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4 + {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5 + {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6 + {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7 + {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK + {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK + {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET + {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD + {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0 + {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1 + {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2 + {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3 + {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB + {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK + {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP + {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N + {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R + {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N + {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_N + {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N + {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N + {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N + {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N + {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK + {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N + {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N + {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENABLE + {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table +}; + +UINT16 mGpioTableLpDdr3Rvp3Size = sizeof (mGpioTableLpDdr3Rvp3) / sizeof (GPIO_INIT_CONFIG) - 1; + +GPIO_INIT_CONFIG mGpioTableKabyLakeYLpddr3Rvp3[] = +{ + { GPIO_SKL_LP_GPP_A12, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResumeReset, GpioTermNone } },//REALSENSE_ISH_WAKE + { GPIO_SKL_LP_GPP_A20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone } },//IRIS_PROXI_INTR + { GPIO_SKL_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N + { GPIO_SKL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone } },//SD_CARD_WAKE + { GPIO_SKL_LP_GPP_D11, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone } },//TYPEC_P1_DCI_CLK + { GPIO_SKL_LP_GPP_D12, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone } },//TYPEC_P1_DCI_DATA +}; + +UINT16 mGpioTableKabyLakeYLpddr3Rvp3Size = sizeof (mGpioTableKabyLakeYLpddr3Rvp3) / sizeof (GPIO_INIT_CONFIG); + +GPIO_INIT_CONFIG mGpioTableLpddr3Rvp3UcmcDevice[] = +{ + { GPIO_SKL_LP_GPP_B0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone } }, //GPP_B0 + { GPIO_SKL_LP_GPP_B1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone } }, //GPP_B1 +}; + +UINT16 mGpioTableLpddr3Rvp3UcmcDeviceSize = sizeof (mGpioTableLpddr3Rvp3UcmcDevice) / sizeof (GPIO_INIT_CONFIG); + +GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3Touchpanel = + {GPIO_SKL_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}}; + +GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3SdhcSidebandCardDetect = + {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntBothEdge, GpioHostDeepReset, GpioTermNone}}; //SD_CDB D3 + +//IO Expander Table for SKL RVP7, RVP13 and RVP15 +IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[] = +{ + {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//DGPU_PRSNT_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SW_GFX_PWERGD_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26 + {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27 + {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N + {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N + {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED}//M.2_WIGIG_PWREN_IOEXP +}; + +UINT16 mGpioTableIoExpanderSize = sizeof (mGpioTableIoExpander) / sizeof (IO_EXPANDER_GPIO_CONFIG); + +//IO Expander Table for KBL -Refresh +IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeRDdr4[] = +{ + {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//Unused pin + {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RTD3_USB_PD1_PWR_EN + {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//HRESET_PD1_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N + //{IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_RST_CNTRL_R + // We want the initial state to be high. + {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_RST_CNTRL_R + {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_WAKE_CTRL_R_N + // Turn off WWAN power and will turn it on later. + {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N + {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD + {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD + {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N + {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP +}; +UINT16 mGpioTableIoExpanderSizeKabylakeRDdr4 = sizeof (mGpioTableIoExpanderKabylakeRDdr4) / sizeof (IO_EXPANDER_GPIO_CONFIG); + +//IO Expander Table for KBL -kc +IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeKcDdr3[] = +{ + {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD + {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD + {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26 + {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27 + {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N + {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N + {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FPS_LOCK_N + {IO_EXPANDER_1, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_FLEX_PWREN + {IO_EXPANDER_1, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB_UART_SEL + {IO_EXPANDER_1, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_DOCK_PWREN_IOEXP_R +}; +UINT16 mGpioTableIoExpanderSizeKabylakeKcDdr3 = sizeof (mGpioTableIoExpanderKabylakeKcDdr3) / sizeof (IO_EXPANDER_GPIO_CONFIG); +//IO Expander Table Full table for KBL RVP3 +IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeRvp3[] = +{ + {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//DGPU_PRSNT_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED },//SW_GFX_DGPU_SEL (KBL_RVP3_BOARD) +//{IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP (SKL_RVP3_BOARD) + {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SW_GFX_PWERGD_IOEXP + {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N + {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26 + {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27 + {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N + {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED },//Not Connected (KBK_RVP3_BOARD) +//{IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP (SKL_RVP3_BOARD) + {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N + {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP + {IO_EXPANDER_1, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN (KBL_RVP3_BOARD) + {IO_EXPANDER_1, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FPS_LOCK_N (KBL_RVP3_BOARD) +}; + +UINT16 mGpioTableIoExpanderKabylakeRvp3Size = sizeof (mGpioTableIoExpanderKabylakeRvp3) / sizeof (IO_EXPANDER_GPIO_CONFIG); + +#endif // _KABYLAKE_RVP3_GPIO_TABLE_H_ diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/KabylakeRvp3HdaVerbTables.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/KabylakeRvp3HdaVerbTables.c new file mode 100644 index 00000000..92afcbab --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/KabylakeRvp3HdaVerbTables.c @@ -0,0 +1,232 @@ +/** @file + HDA Verb table for KabylakeRvp3 + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _KABYLAKE_RVP3_HDA_VERB_TABLES_H_ +#define _KABYLAKE_RVP3_HDA_VERB_TABLES_H_ + +#include + +HDAUDIO_VERB_TABLE HdaVerbTableAlc286Rvp3 = HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC286) for RVP3 + // Revision ID = 0xff + // Codec Verb Table for SKL PCH boards + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0286 + // + 0x10EC, 0x0286, + 0xFF, 0xFF, + //=================================================================================================== + // + // Realtek Semiconductor Corp. + // + //=================================================================================================== + + //Realtek High Definition Audio Configuration - Version : 5.0.2.9 + //Realtek HD Audio Codec : ALC286 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0286&SUBSYS_10EC108E + //The number of verb command block : 16 + + // NID 0x12 : 0x411111F0 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x9017011F + // NID 0x17 : 0x90170110 + // NID 0x18 : 0x03A11040 + // NID 0x19 : 0x411111F0 + // NID 0x1A : 0x411111F0 + // NID 0x1D : 0x4066A22D + // NID 0x1E : 0x411111F0 + // NID 0x21 : 0x03211020 + + + //===== HDA Codec Subsystem ID Verb-table ===== + //HDA Codec Subsystem ID : 0x10EC108E + 0x0017208E, + 0x00172110, + 0x001722EC, + 0x00172310, + + //===== Pin Widget Verb-table ===== + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271CF0, + 0x01271D11, + 0x01271E11, + 0x01271F41, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - SPEAKER-OUT (Port-D) + 0x01771C1F, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x17 - I2S-OUT + 0x01771C10, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - MIC1 (Port-B) + 0x01871C40, + 0x01871D10, + 0x01871EA1, + 0x01871F03, + //Pin widget 0x19 - I2S-IN + 0x01971CF0, + 0x01971D11, + 0x01971E11, + 0x01971F41, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C2D, + 0x01D71DA2, + 0x01D71E66, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x21 - HP-OUT (Port-A) + 0x02171C20, + 0x02171D10, + 0x02171E21, + 0x02171F03, + //Widget node 0x20 : + 0x02050071, + 0x02040014, + 0x02050010, + 0x02040C22, + //Widget node 0x20 - 1 : + 0x0205004F, + 0x02045029, + 0x0205004F, + 0x02045029, + //Widget node 0x20 - 2 : + 0x0205002B, + 0x02040DD0, + 0x0205002D, + 0x02047020, + //Widget node 0x20 - 3 : + 0x0205000E, + 0x02046C80, + 0x01771F90, + 0x01771F90, + //TI AMP settings : + 0x02050022, + 0x0204004C, + 0x02050023, + 0x02040000, + 0x02050025, + 0x02040000, + 0x02050026, + 0x0204B010, + + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + + 0x02050022, + 0x0204004C, + 0x02050023, + 0x02040002, + 0x02050025, + 0x02040011, + 0x02050026, + 0x0204B010, + + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + + 0x02050022, + 0x0204004C, + 0x02050023, + 0x0204000D, + 0x02050025, + 0x02040010, + 0x02050026, + 0x0204B010, + + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + + 0x02050022, + 0x0204004C, + 0x02050023, + 0x02040025, + 0x02050025, + 0x02040008, + 0x02050026, + 0x0204B010, + + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + + 0x02050022, + 0x0204004C, + 0x02050023, + 0x02040002, + 0x02050025, + 0x02040000, + 0x02050026, + 0x0204B010, + + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + + 0x02050022, + 0x0204004C, + 0x02050023, + 0x02040003, + 0x02050025, + 0x02040000, + 0x02050026, + 0x0204B010 +); + +#endif // _KABYLAKE_RVP3_HDA_VERB_TABLES_H_ diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/KabylakeRvp3HsioPtssTables.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/KabylakeRvp3HsioPtssTables.c new file mode 100644 index 00000000..8a9048fa --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/KabylakeRvp3HsioPtssTables.c @@ -0,0 +1,105 @@ +/** @file + KabylakeRvp3 HSIO PTSS H File + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef KABYLAKE_RVP3_HSIO_PTSS_H_ +#define KABYLAKE_RVP3_HSIO_PTSS_H_ + +#include + +#ifndef HSIO_PTSS_TABLE_SIZE +#define HSIO_PTSS_TABLE_SIZE(A) A##_Size = sizeof (A) / sizeof (HSIO_PTSS_TABLES) +#endif + +//BoardId KabylakeRvp3 +HSIO_PTSS_TABLES PchLpHsioPtss_Cx_KabylakeRvp3[] = { + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoM2}, + {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoM2}, + {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4}, + {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) ~0x3F000000}, PchSataTopoDirectConnect}, + {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoM2}, + {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4}, + {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4}, + {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{12, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{13, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{14, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{15, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4}, + {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoM2}, + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopox1}, + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00322900, (UINT32) ~0x3F3F00}, PchSataTopoM2}, + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00382C00, (UINT32) ~0x3F3F00}, PchSataTopoDirectConnect}, + {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoM2}, + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopox1}, + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, + {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, + {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown} +}; + +UINT16 PchLpHsioPtss_Cx_KabylakeRvp3_Size = sizeof(PchLpHsioPtss_Cx_KabylakeRvp3) / sizeof(HSIO_PTSS_TABLES); + +HSIO_PTSS_TABLES PchLpHsioPtss_Bx_KabylakeRvp3[] = { + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchPcieTopoUnknown}, + {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4}, + {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) ~0x3F000000}, PchSataTopoDirectConnect}, + {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4}, + {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4}, + {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{12, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{13, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{14, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown}, + {{15, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4}, + {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopox1}, + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00322900, (UINT32) ~0x3F3F00}, PchPcieTopoUnknown}, + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00382C00, (UINT32) ~0x3F3F00}, PchSataTopoDirectConnect}, + {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopox1}, + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown}, + {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, + {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, + {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}, +}; + +UINT16 PchLpHsioPtss_Bx_KabylakeRvp3_Size = sizeof(PchLpHsioPtss_Bx_KabylakeRvp3) / sizeof(HSIO_PTSS_TABLES); + +#endif // KABYLAKE_RVP3_HSIO_PTSS_H_ diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/KabylakeRvp3SpdTable.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/KabylakeRvp3SpdTable.c new file mode 100644 index 00000000..e4ad785b --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/KabylakeRvp3SpdTable.c @@ -0,0 +1,541 @@ +/** @file + GPIO definition table for KabylakeRvp3 + +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _KABYLAKE_RVP3_SPD_TABLE_H_ +#define _KABYLAKE_RVP3_SPD_TABLE_H_ + +// +// DQByteMap[0] - ClkDQByteMap: +// If clock is per rank, program to [0xFF, 0xFF] +// If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF] +// If clock is shared by 2 ranks but does not go to all bytes, +// Entry[i] defines which DQ bytes Group i services +// DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is CmdN/CAB +// DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is CmdS/CAB +// DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE /CAB +// For DDR, DQByteMap[3:1] = [0xFF, 0] +// DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we have 1 CTL / rank +// Variable only exists to make the code easier to use +// DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we have 1 CA Vref +// Variable only exists to make the code easier to use +// +// +// DQ byte mapping to CMD/CTL/CLK, from the CPU side - for SKL RVP3, SKL SDS - used by SKL/KBL MRC +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqByteMapSklRvp3[2][6][2] = { + // Channel 0: + { + { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4] + { 0x00, 0xF0 }, // CmdN does not have CAA, CAB goes to Bytes[7:4] + { 0x0F, 0xF0 }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4] + { 0x0F, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB + { 0xFF, 0x00 }, // CTL (CS) goes to all bytes + { 0xFF, 0x00 } // CA Vref is one for all bytes + }, + // Channel 1: + { + { 0x33, 0xCC }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4] + { 0x00, 0xCC }, // CmdN does not have CAA, CAB goes to Bytes[7:4] + { 0x33, 0xCC }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4] + { 0x33, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB + { 0xFF, 0x00 }, // CTL (CS) goes to all bytes + { 0xFF, 0x00 } // CA Vref is one for all bytes + } +}; + +// +// DQS byte swizzling between CPU and DRAM - for SKL DOE RVP +// + +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqsMapCpu2DramSklRvp3[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, // Channel 0 + { 1, 0, 4, 5, 2, 3, 6, 7 } // Channel 1 +}; + +// Samsung K4E6E304ED-EGCF 178b QDP LPDDR3, 4Gb die (256Mx16), x16 +// or Hynix H9CCNNNBLTALAR-NUD +// or similar +// 1867, 14-17-17-40 +// 2 ranks per channel, 2 SDRAMs per rank, 8x4Gb = 4GB total per channel +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp16Spd[] = { + 0x24, ///< 0 Number of Serial PD Bytes Written / SPD Device Size + 0x20, ///< 1 SPD Revision + 0x0F, ///< 2 DRAM Device Type + 0x0E, ///< 3 Module Type + 0x14, ///< 4 SDRAM Density and Banks: 8 Banks, 4 Gb SDRAM density + 0x12, ///< 5 SDRAM Addressing: 14 Rows, 11 Columns + 0xB5, ///< 6 SDRAM Package Type: QDP, 1 Channel per die, Signal Loading Matrix 1 + 0x00, ///< 7 SDRAM Optional Features + 0x00, ///< 8 SDRAM Thermal and Refresh Options + 0x00, ///< 9 Other SDRAM Optional Features + 0x00, ///< 10 Reserved - must be coded as 0x00 + 0x03, ///< 11 Module Nominal Voltage, VDD + 0x0A, ///< 12 Module Organization, SDRAM width: 16 bits, 2 Ranks + 0x23, ///< 13 Module Memory Bus Width: 2 channels, 64 bit channel bus width + 0x00, ///< 14 Module Thermal Sensor + 0x00, ///< 15 Extended Module Type + 0x00, ///< 16 Reserved - must be coded as 0x00 + 0x00, ///< 17 Timebases + 0x09, ///< 18 SDRAM Minimum Cycle Time (tCKmin): tCKmin = 1.071ns (LPDDR3-1867) + 0xFF, ///< 19 SDRAM Minimum Cycle Time (tCKmax) + 0xD4, ///< 20 CAS Latencies Supported, First Byte (tCK): 14, 12, 10, 8 + 0x00, ///< 21 CAS Latencies Supported, Second Byte + 0x00, ///< 22 CAS Latencies Supported, Third Byte + 0x00, ///< 23 CAS Latencies Supported, Fourth Byte + 0x78, ///< 24 Minimum CAS Latency Time (tAAmin) = 14.994 ns + 0x00, ///< 25 Read and Write Latency Set Options + 0x90, ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin) + 0xA8, ///< 27 Minimum Row Precharge Delay Time for all banks (tRPab) + 0x90, ///< 28 Minimum Row Precharge Delay Time per bank (tRPpb) + 0x10, ///< 29 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Least Significant Byte + 0x04, ///< 30 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Most Significant Byte + 0xE0, ///< 31 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Least Significant Byte + 0x01, ///< 32 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Most Significant Byte + 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bit Mapping + 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bit Mapping + 0, 0, ///< 78 - 79 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119 + 0x00, ///< 120 Fine Offset for Minimum Row Precharge Delay Time per bank (tRPpb) + 0x00, ///< 121 Fine Offset for Minimum Row Precharge Delay Time for all banks (tRPab) + 0x00, ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) + 0xFA, ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin): 14.994 ns (LPDDR3-1867) + 0x7F, ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax): 32.002 ns + 0xCA, ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin): 1.071 ns (LPDDR-1867) + 0x00, ///< 126 CRC A + 0x00, ///< 127 CRC B + 0, 0, ///< 128 - 129 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319 + 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte + 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte + 0x00, ///< 322 Module Manufacturing Location + 0x00, ///< 323 Module Manufacturing Date Year + 0x00, ///< 324 Module Manufacturing Date Week + 0x55, ///< 325 Module Serial Number A + 0x00, ///< 326 Module Serial Number B + 0x00, ///< 327 Module Serial Number C + 0x00, ///< 328 Module Serial Number D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20) + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number + 0x00, ///< 349 Module Revision Code + 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte + 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte + 0x00, ///< 352 DRAM Stepping + 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509 + 0, 0 ///< 510 - 511 +}; + +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp16SpdSize = sizeof (mSkylakeRvp16Spd); + +//Hynix H9CCNNNBJTMLAR-NUD, DDP, LPDDR3, 8Gb die +//1867 +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp3Spd110[] = { + 0x91, ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2 + 0x20, ///< 1 SPD Revision + 0xF1, ///< 2 DRAM Device Type + 0x03, ///< 3 Module Type + 0x05, ///< 4 SDRAM Density and Banks, 8Gb + 0x19, ///< 5 SDRAM Addressing: 15 Rows, 10 Columns + 0x05, ///< 6 Module Nominal Voltage + 0x0B, ///< 7 Module Organization: 32 bits, 2 Ranks + 0x03, ///< 8 Module Memory Bus Width + 0x11, ///< 9 Fine Timebase (FTB) Dividend / Divisor + 0x01, ///< 10 Medium Timebase (MTB) Dividend + 0x08, ///< 11 Medium Timebase (MTB) Divisor + 0x09, ///< 12 SDRAM Minimum Cycle Time (tCKmin): tCKmin = 1.071 ns (LPDDR3-1867) + 0x00, ///< 13 Reserved0 + 0x50, ///< 14 CAS Latencies supported (tCK): 14, 12, 10, 8 (LSB) + 0x05, ///< 15 CAS Latencies supported (tCK): 14, 12, 10, 8 (LSB) + 0x78, ///< 16 Minimum CAS Latency (tAAmin) = 14.994 ns + 0x78, ///< 17 Minimum Write Recovery Time (tWRmin) + 0x90, ///< 18 Minimum RAS# to CAS# Delay Time (tRCDmin) + 0x50, ///< 19 Minimum Row Active to Row Active Delay Time (tRRDmin) + 0x90, ///< 20 Minimum Row Precharge Delay Time (tRPmin) + 0x11, ///< 21 Upper Nibbles for tRAS and tRC + 0x50, ///< 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte + 0xE0, ///< 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte + 0x90, ///< 24 Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte + 0x06, ///< 25 Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte + 0x3C, ///< 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) + 0x3C, ///< 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) + 0x01, ///< 28 Upper Nibble for tFAW + 0x90, ///< 29 Minimum Four Activate Window Delay Time (tFAWmin) + 0x00, ///< 30 SDRAM Optional Features + 0x00, ///< 31 SDRAMThermalAndRefreshOptions + 0x00, ///< 32 ModuleThermalSensor + 0x00, ///< 33 SDRAM Device Type + 0xCA, ///< 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin): 1.071 ns (LPDDR3-1867) + 0xFA, ///< 35 Fine Offset for Minimum CAS Latency Time (tAAmin): 14.994 ns (LPDDR3-1867) + 0x00, ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) + 0x00, ///< 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) + 0x00, ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) + 0xA8, ///< 39 Row precharge time for all banks (tRPab) + 0x00, ///< 40 FTB for Row precharge time for all banks (tRPab) + 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 41 - 49 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 + 0, 0, ///< 60 - 61 + 0x00, ///< 62 Reference Raw Card Used + 0x00, ///< 63 Address Mapping from Edge Connector to DRAM + 0x00, ///< 64 ThermalHeatSpreaderSolution + 0, 0, 0, 0, 0, ///< 65 - 69 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 + 0, 0, 0, 0, 0, 0, 0, ///< 110 - 116 + 0x00, ///< 117 Module Manufacturer ID Code, Least Significant Byte + 0x00, ///< 118 Module Manufacturer ID Code, Most Significant Byte + 0x00, ///< 119 Module Manufacturing Location + 0x00, ///< 120 Module Manufacturing Date Year + 0x00, ///< 121 Module Manufacturing Date creation work week + 0x55, ///< 122 Module Serial Number A + 0x00, ///< 123 Module Serial Number B + 0x00, ///< 124 Module Serial Number C + 0x00, ///< 125 Module Serial Number D + 0x00, ///< 126 CRC A + 0x00 ///< 127 CRC B +}; + +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp3Spd110Size = sizeof (mSkylakeRvp3Spd110); + +// +// Micron MT52L512M32D2PF 78b DDP LPDDR3, 8Gb die (256Mx32), x32 +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mKblRSpdLpddr32133[] = { + 0x91, ///< 0 128 SPD bytes used, 256 total, CRC covers 0..116 + 0x20, ///< 1 SPD Revision 2.0 + 0xF1, ///< 2 DRAM Type: LPDDR3 SDRAM + 0x03, ///< 3 Module Type: SO-DIMM + 0x05, ///< 4 8 Banks, 8 Gb SDRAM density + 0x19, ///< 5 SDRAM Addressing: 15 Rows, 10 Columns + 0x05, ///< 6 Module Nominal Voltage VDD: 1.2v + 0x0B, ///< 7 SDRAM width: 32 bits, 2 Ranks + 0x03, ///< 8 SDRAM bus width: 64 bits, no ECC + 0x11, ///< 9 Fine Timebase (FTB) granularity: 1 ps + 0x01, ///< 10 Medium Timebase (MTB) : 0.125 ns + 0x08, ///< 11 Medium Timebase Divisor + 0x08, ///< 12 tCKmin = 0.938 ns (LPDDR3-2133) + 0x00, ///< 13 Reserved + 0x50, ///< 14 CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (LSB) + 0x15, ///< 15 CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (MSB) + 0x78, ///< 16 Minimum CAS Latency (tAAmin) = 15.008 ns + 0x78, ///< 17 tWR = 15 ns + 0x90, ///< 18 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns + 0x50, ///< 19 tRRD = 10 ns + 0x90, ///< 20 Minimum row precharge time (tRPmin) = 18 ns + 0x11, ///< 21 Upper nibbles for tRAS and tRC + 0x50, ///< 22 tRASmin = 42 ns + 0xE0, ///< 23 tRCmin = (tRASmin + tRPmin) = 60 ns + 0x90, ///< 24 tRFCmin = (tRFCab) = 210 ns (8Gb) + 0x06, ///< 25 tRFCmin MSB + 0x3C, ///< 26 tWTRmin = 7.5 ns + 0x3C, ///< 27 tRTPmin = 7.5 ns + 0x01, ///< 28 tFAWmin upper nibble + 0x90, ///< 29 tFAWmin = 50 ns + 0x00, ///< 30 SDRAM Optional Features - none + 0x00, ///< 31 SDRAM Thermal / Refresh options - none + 0x00, ///< 32 ModuleThermalSensor + 0x00, ///< 33 SDRAM Device Type + 0xC2, ///< 34 FTB for tCKmin = 0.938 ns (LPDDR3-2133) + 0x08, ///< 35 FTB for tAAmin = 15.008 ns (LPDDR3-2133) + 0x00, ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) + 0x00, ///< 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) + 0x00, ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) + 0xA8, ///< 39 Row precharge time for all banks (tRPab)= 21 ns + 0x00, ///< 40 FTB for Row precharge time for all banks (tRPab) = 0 + 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 41 - 49 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 + 0, 0, ///< 60 - 61 + 0x00, ///< 62 Reference Raw Card Used + 0x00, ///< 63 Rank1 Mapping: Standard + 0x00, ///< 64 ThermalHeatSpreaderSolution + 0, 0, 0, 0, 0, ///< 65 - 69 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 + 0, 0, 0, 0, 0, 0, 0, ///< 110 - 116 + 0x00, ///< 117 Module Manufacturer ID Code, Least Significant Byte + 0x00, ///< 118 Module Manufacturer ID Code, Most Significant Byte + 0x00, ///< 119 Module Manufacturing Location + 0x00, ///< 120 Module Manufacturing Date Year + 0x00, ///< 121 Module Manufacturing Date creation work week + 0x55, ///< 122 Module ID: Module Serial Number + 0x00, ///< 123 Module Serial Number B + 0x00, ///< 124 Module Serial Number C + 0x00, ///< 125 Module Serial Number D + 0x00, ///< 126 CRC A + 0x00 ///< 127 CRC B +}; +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mKblRSpdLpddr32133Size = sizeof (mKblRSpdLpddr32133); + +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSpdLpddr32133[] = { + 0x24, ///< 0 Number of Serial PD Bytes Written / SPD Device Size + 0x01, ///< 1 SPD Revision + 0x0F, ///< 2 DRAM Device Type + 0x0E, ///< 3 Module Type + 0x15, ///< 4 SDRAM Density and Banks: 8 Banks, 8 Gb SDRAM density + 0x19, ///< 5 SDRAM Addressing: 15 Rows, 10 Columns + 0x90, ///< 6 SDRAM Package Type: QDP, 1 Channel per die, Signal Loading Matrix 1 + 0x00, ///< 7 SDRAM Optional Features + 0x00, ///< 8 SDRAM Thermal and Refresh Options + 0x00, ///< 9 Other SDRAM Optional Features + 0x00, ///< 10 Reserved - must be coded as 0x00 + 0x0B, ///< 11 Module Nominal Voltage, VDD + 0x0B, ///< 12 Module Organization, SDRAM width: 32 bits, 2 Ranks + 0x03, ///< 13 Module Memory Bus Width: 2 channels, 64 bit channel bus width + 0x00, ///< 14 Module Thermal Sensor + 0x00, ///< 15 Extended Module Type + 0x00, ///< 16 Reserved - must be coded as 0x00 + 0x00, ///< 17 Timebases + 0x08, ///< 18 SDRAM Minimum Cycle Time (tCKmin) + 0xFF, ///< 19 SDRAM Minimum Cycle Time (tCKmax) + 0xD4, ///< 20 CAS Latencies Supported, First Byte + 0x01, ///< 21 CAS Latencies Supported, Second Byte + 0x00, ///< 22 CAS Latencies Supported, Third Byte + 0x00, ///< 23 CAS Latencies Supported, Fourth Byte + 0x78, ///< 24 Minimum CAS Latency Time (tAAmin) + 0x00, ///< 25 Read and Write Latency Set Options + 0x90, ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin) + 0xA8, ///< 27 Minimum Row Precharge Delay Time for all banks (tRPab) + 0x90, ///< 28 Minimum Row Precharge Delay Time per bank (tRPpb) + 0x90, ///< 29 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Least Significant Byte + 0x06, ///< 30 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Most Significant Byte + 0xD0, ///< 31 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Least Significant Byte + 0x02, ///< 32 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Most Significant Byte + 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bit Mapping + 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bit Mapping + 0, 0, ///< 78 - 79 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119 + 0x00, ///< 120 Fine Offset for Minimum Row Precharge Delay Time per bank (tRPpb) + 0x00, ///< 121 Fine Offset for Minimum Row Precharge Delay Time for all banks (tRPab) + 0x00, ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) + 0x08, ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin) + 0x7F, ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax) + 0xC2, ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) + 0x00, ///< 126 CRC A + 0x00, ///< 127 CRC B + 0, 0, ///< 128 - 129 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319 + 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte + 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte + 0x00, ///< 322 Module Manufacturing Location + 0x00, ///< 323 Module Manufacturing Date Year + 0x00, ///< 324 Module Manufacturing Date Week + 0x55, ///< 325 Module Serial Number A + 0x00, ///< 326 Module Serial Number B + 0x00, ///< 327 Module Serial Number C + 0x00, ///< 328 Module Serial Number D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20) + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number + 0x00, ///< 349 Module Revision Code + 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte + 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte + 0x00, ///< 352 DRAM Stepping + 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509 + 0, 0 ///< 510 - 511 +}; +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSpdLpddr32133Size = sizeof (mSpdLpddr32133); + +/** + Hynix H9CCNNN8JTMLAR-NTM_178b_DDP LPDDR3, 4Gb die (128Mx32), x32 + or Elpida EDF8132A1MC-GD-F + or Samsung K4E8E304EB-EGCE + 1600, 12-15-15-34 + 2 rank per channel, 2 SDRAMs per rank, 4x4Gb = 2GB total per channel +**/ +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp3Spd[] = { + 0x24, ///< 0 Number of Serial PD Bytes Written / SPD Device Size + 0x20, ///< 1 SPD Revision + 0x0F, ///< 2 DRAM Device Type + 0x0E, ///< 3 Module Type + 0x14, ///< 4 SDRAM Density and Banks: 8 Banks, 4 Gb SDRAM density + 0x11, ///< 5 SDRAM Addressing: 14 Rows, 10 Columns + 0x95, ///< 6 SDRAM Package Type: DDP, 1 Channel per die, Signal Loading Matrix 1 + 0x00, ///< 7 SDRAM Optional Features + 0x00, ///< 8 SDRAM Thermal and Refresh Options + 0x00, ///< 9 Other SDRAM Optional Features + 0x00, ///< 10 Reserved - must be coded as 0x00 + 0x03, ///< 11 Module Nominal Voltage, VDD + 0x0B, ///< 12 Module Organization, SDRAM width: 32 bits, 2 Ranks + 0x23, ///< 13 Module Memory Bus Width: 2 channels, 64 bit channel bus width + 0x00, ///< 14 Module Thermal Sensor + 0x00, ///< 15 Extended Module Type + 0x00, ///< 16 Reserved - must be coded as 0x00 + 0x00, ///< 17 Timebases + 0x0A, ///< 18 SDRAM Minimum Cycle Time (tCKmin) + 0xFF, ///< 19 SDRAM Minimum Cycle Time (tCKmax) + 0x54, ///< 20 CAS Latencies Supported, First Byte (tCk): 12 10 8 + 0x00, ///< 21 CAS Latencies Supported, Second Byte + 0x00, ///< 22 CAS Latencies Supported, Third Byte + 0x00, ///< 23 CAS Latencies Supported, Fourth Byte + 0x78, ///< 24 Minimum CAS Latency Time (tAAmin) + 0x00, ///< 25 Read and Write Latency Set Options + 0x90, ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin) + 0xA8, ///< 27 Minimum Row Precharge Delay Time for all banks (tRPab) + 0x90, ///< 28 Minimum Row Precharge Delay Time per bank (tRPpb) + 0x10, ///< 29 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Least Significant Byte + 0x04, ///< 30 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Most Significant Byte + 0xE0, ///< 31 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Least Significant Byte + 0x01, ///< 32 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Most Significant Byte + 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bit Mapping + 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bit Mapping + 0, 0, ///< 78 - 79 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119 + 0x00, ///< 120 Fine Offset for Minimum Row Precharge Delay Time per bank (tRPpb) + 0x00, ///< 121 Fine Offset for Minimum Row Precharge Delay Time for all banks (tRPab) + 0x00, ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) + 0x00, ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin) + 0x7F, ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax) + 0x00, ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) + 0x00, ///< 126 CRC A + 0x00, ///< 127 CRC B + 0, 0, ///< 128 - 129 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319 + 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte + 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte + 0x00, ///< 322 Module Manufacturing Location + 0x00, ///< 323 Module Manufacturing Date Year + 0x00, ///< 324 Module Manufacturing Date Week + 0x55, ///< 325 Module Serial Number A + 0x00, ///< 326 Module Serial Number B + 0x00, ///< 327 Module Serial Number C + 0x00, ///< 328 Module Serial Number D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20) + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number + 0x00, ///< 349 Module Revision Code + 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte + 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte + 0x00, ///< 352 DRAM Stepping + 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509 + 0, 0 ///< 510 - 511 +}; +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp3SpdSize = sizeof (mSkylakeRvp3Spd); +#endif // _KABYLAKE_RVP3_SPD_TABLE_H_ diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.c new file mode 100644 index 00000000..2e079a03 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.c @@ -0,0 +1,39 @@ +/** @file + Kaby Lake RVP 3 Board Initialization Post-Memory library + +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +KabylakeRvp3BoardInitBeforeSiliconInit ( + VOID + ); + +EFI_STATUS +EFIAPI +BoardInitBeforeSiliconInit ( + VOID + ) +{ + KabylakeRvp3BoardInitBeforeSiliconInit (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterSiliconInit ( + VOID + ) +{ + return EFI_SUCCESS; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.inf new file mode 100644 index 00000000..bdf481b9 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.inf @@ -0,0 +1,54 @@ +## @file +# Component information file for KabylakeRvp3InitLib in PEI post memory phase. +# +# Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiBoardPostMemInitLib + FILE_GUID = 7fcc3900-d38d-419f-826b-72481e8b5509 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = BoardInitLib + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + GpioExpanderLib + PcdLib + SiliconInitLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + KabylakeSiliconPkg/SiPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Sources] + PeiKabylakeRvp3InitPostMemLib.c + KabylakeRvp3GpioTable.c + KabylakeRvp3HdaVerbTables.c + PeiBoardInitPostMemLib.c + +[FixedPcd] + +[Pcd] + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel + + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize + + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable + + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.c new file mode 100644 index 00000000..f5c695ec --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.c @@ -0,0 +1,108 @@ +/** @file + Kaby Lake RVP 3 Board Initialization Pre-Memory library + +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +KabylakeRvp3BoardDetect ( + VOID + ); + +EFI_BOOT_MODE +EFIAPI +KabylakeRvp3BoardBootModeDetect ( + VOID + ); + +EFI_STATUS +EFIAPI +KabylakeRvp3BoardDebugInit ( + VOID + ); + +EFI_STATUS +EFIAPI +KabylakeRvp3BoardInitBeforeMemoryInit ( + VOID + ); + +EFI_STATUS +EFIAPI +BoardDetect ( + VOID + ) +{ + KabylakeRvp3BoardDetect (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardDebugInit ( + VOID + ) +{ + KabylakeRvp3BoardDebugInit (); + return EFI_SUCCESS; +} + +EFI_BOOT_MODE +EFIAPI +BoardBootModeDetect ( + VOID + ) +{ + return KabylakeRvp3BoardBootModeDetect (); +} + +EFI_STATUS +EFIAPI +BoardInitBeforeMemoryInit ( + VOID + ) +{ + if ((LibPcdGetSku () == BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSku () == BoardIdSkylakeRvp3)) { + KabylakeRvp3BoardInitBeforeMemoryInit (); + } + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterMemoryInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitBeforeTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf new file mode 100644 index 00000000..850fc514 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf @@ -0,0 +1,135 @@ +## @file +# Component information file for PEI KabylakeRvp3 Board Init Pre-Mem Library +# +# Copyright (c) 2017 - 2021 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiBoardInitPreMemLib + FILE_GUID = ec3675bc-1470-417d-826e-37378140213d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = BoardInitLib + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PcdLib + SiliconInitLib + EcLib + PchResetLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + KabylakeSiliconPkg/SiPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Sources] + PeiKabylakeRvp3Detect.c + PeiKabylakeRvp3InitPreMemLib.c + KabylakeRvp3HsioPtssTables.c + KabylakeRvp3SpdTable.c + PeiBoardInitPreMemLib.c + +[Pcd] + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort + + # PCH-LP HSIO PTSS Table + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + + # PCH-H HSIO PTSS Table + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + + # SA Misc Config + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize + + # PEG Reset By GPIO + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive + + + # SPD Address Table + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 + + # CA Vref Configuration + + # Root Port Clock Info + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort0ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort4ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort5ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort7ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort8ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort9ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortLanClkInfo + + # USB 2.0 Port AFE + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe + + # USB 2.0 Port Over Current Pin + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 + + # USB 3.0 Port Over Current Pin + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 + + # Misc + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent + + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiKabylakeRvp3Detect.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiKabylakeRvp3Detect.c new file mode 100644 index 00000000..429f4316 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiKabylakeRvp3Detect.c @@ -0,0 +1,124 @@ +/** @file + +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PeiKabylakeRvp3InitLib.h" + +#include +#include +#include +#include + +#define BOARD_ID_MASK_8BIT 0xff + +/** + Get board fab ID. + + @param[out] DataBuffer + + @retval EFI_SUCCESS Command success + @retval EFI_DEVICE_ERROR Command error +**/ +EFI_STATUS +GetBoardFabId ( + OUT UINT8 *DataBuffer + ) +{ + UINT8 DataSize; + + // + // For 'EC_C_FAB_ID' command NumberOfSendData = 0, NumberOfReceiveData =2. + // + DataSize = 2; + return (LpcEcInterface (EC_C_FAB_ID, &DataSize, DataBuffer)); +} + +/** + Get RVP3 board ID. + There are 2 different RVP3 boards having different ID. + This function will return board ID to caller. + + @param[out] DataBuffer + + @retval EFI_SUCCESS Command success + @retval EFI_DEVICE_ERROR Command error +**/ +EFI_STATUS +GetRvp3BoardId ( + UINT8 *BoardId + ) +{ + EFI_STATUS Status; + UINT16 EcBoardInfo; + UINT8 DataBuffer[2]; + + Status = GetBoardFabId (DataBuffer); + if (Status == EFI_SUCCESS) { + EcBoardInfo = DataBuffer[0]; + EcBoardInfo = (EcBoardInfo << 8) | DataBuffer[1]; + // + // Get the following data: + // [7:0] - BOARD_IDx + // [8] - GEN_ID + // [11:9] - REV_FAB_IDx + // [12] - TP_SPD_PRSNT + // [15:13] - BOM_IDx + // + *BoardId = (UINT8) (EcBoardInfo & BOARD_ID_MASK_8BIT); + DEBUG ((DEBUG_INFO, "BoardId = %X\n", *BoardId)); + } + return Status; +} + +EFI_STATUS +EFIAPI +KabylakeRvp3BoardDetect ( + VOID + ) +{ + UINT8 BoardId; + + if (LibPcdGetSku () != 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "KabylakeRvp3DetectionCallback\n")); + if (GetRvp3BoardId (&BoardId) == EFI_SUCCESS) { + if (BoardId == BoardIdKabyLakeYLpddr3Rvp3) { + LibPcdSetSku (BoardIdKabyLakeYLpddr3Rvp3); + ASSERT (LibPcdGetSku() == BoardIdKabyLakeYLpddr3Rvp3); + } else if (BoardId == BoardIdSkylakeRvp3) { + LibPcdSetSku (BoardIdSkylakeRvp3); + ASSERT (LibPcdGetSku() == BoardIdSkylakeRvp3); + } + DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku())); + } + return EFI_SUCCESS; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiKabylakeRvp3InitLib.h b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiKabylakeRvp3InitLib.h new file mode 100644 index 00000000..5b2ccf6b --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiKabylakeRvp3InitLib.h @@ -0,0 +1,44 @@ +/** @file + +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PEI_KABYLAKE_RVP3_BOARD_INIT_LIB_H_ +#define _PEI_KABYLAKE_RVP3_BOARD_INIT_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +extern const UINT8 mDqByteMapSklRvp3[2][6][2]; +extern const UINT8 mDqsMapCpu2DramSklRvp3[2][8]; +extern const UINT8 mSkylakeRvp3Spd110[]; +extern const UINT16 mSkylakeRvp3Spd110Size; +extern const UINT8 mSkylakeRvp3Spd[]; +extern const UINT16 mSkylakeRvp3SpdSize; +extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_KabylakeRvp3[]; +extern UINT16 PchLpHsioPtss_Bx_KabylakeRvp3_Size; +extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_KabylakeRvp3[]; +extern UINT16 PchLpHsioPtss_Cx_KabylakeRvp3_Size; + +extern HDAUDIO_VERB_TABLE HdaVerbTableAlc286Rvp3; +extern GPIO_INIT_CONFIG mGpioTableLpddr3Rvp3UcmcDevice[]; +extern UINT16 mGpioTableLpddr3Rvp3UcmcDeviceSize; + +extern IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[]; +extern UINT16 mGpioTableIoExpanderSize; +extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3Touchpanel; +extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[]; +extern UINT16 mGpioTableLpDdr3Rvp3Size; + +#endif // _PEI_KABYLAKE_RVP3_BOARD_INIT_LIB_H_ diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiKabylakeRvp3InitPostMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiKabylakeRvp3InitPostMemLib.c new file mode 100644 index 00000000..5d398ab6 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiKabylakeRvp3InitPostMemLib.c @@ -0,0 +1,208 @@ +/** @file + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PeiKabylakeRvp3InitLib.h" + +/** + SkylaeA0Rvp3 board configuration init function for PEI post memory phase. + + PEI_BOARD_CONFIG_PCD_INIT + + @param Content pointer to the buffer contain init information for board init. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER The parameter is NULL. +**/ +EFI_STATUS +EFIAPI +KabylakeRvp3Init ( + VOID + ) +{ + PcdSet32S (PcdHdaVerbTable, (UINTN) &HdaVerbTableAlc286Rvp3); + + // + // Assign the GPIO table with pin configs to be used for UCMC + // + PcdSet32S (PcdBoardUcmcGpioTable, (UINTN)mGpioTableLpddr3Rvp3UcmcDevice); + PcdSet16S (PcdBoardUcmcGpioTableSize, mGpioTableLpddr3Rvp3UcmcDeviceSize); + + return EFI_SUCCESS; +} + +#define EXPANDERS 2 // defines expander's quantity + +/** + Configures GPIO + + @param[in] GpioTable Point to Platform Gpio table + @param[in] GpioTableCount Number of Gpio table entries + +**/ +VOID +ConfigureGpio ( + IN GPIO_INIT_CONFIG *GpioDefinition, + IN UINT16 GpioTableCount + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n")); + + Status = GpioConfigurePads (GpioTableCount, GpioDefinition); + + DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n")); +} + +VOID +SetBit ( + IN OUT UINT32 *Value, + IN UINT32 BitNumber, + IN BOOLEAN NewBitValue + ) +{ + if (NewBitValue) { + *Value |= 1 << BitNumber; + } else { + *Value &= ~(1 << BitNumber); + } +} + +/** + Configures IO Expander GPIO device + + @param[in] IOExpGpioDefinition Point to IO Expander Gpio table + @param[in] IOExpGpioTableCount Number of Gpio table entries + +**/ +void +ConfigureIoExpanderGpio ( + IN IO_EXPANDER_GPIO_CONFIG *IoExpGpioDefinition, + IN UINT16 IoExpGpioTableCount + ) +{ + UINT8 Index; + UINT32 Direction[EXPANDERS] = {0x00FFFFFF, 0x00FFFFFF}; + UINT32 Level[EXPANDERS] = {0}; + UINT32 Polarity[EXPANDERS] = {0}; + + // IoExpander {TCA6424A} + DEBUG ((DEBUG_INFO, "IO Expander Configuration Start\n")); + for (Index = 0; Index < IoExpGpioTableCount; Index++) { //Program IO Expander as per the table defined in PeiPlatformHooklib.c + SetBit(&Direction[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGpioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].GpioDirection); + SetBit(&Level[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGpioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].GpioLevel); + SetBit(&Polarity[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGpioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].GpioInversion); + } + for (Index = 0; Index < EXPANDERS; Index++) { + GpioExpBulkConfig(Index, Direction[Index], Polarity[Index], Level[Index]); + } + DEBUG ((DEBUG_INFO, "IO Expander Configuration End\n")); + return; +} + +/** + Configure GPIO behind IoExpander. + + @param[in] PeiServices General purpose services available to every PEIM. + @param[in] NotifyDescriptor + @param[in] Interface + + @retval EFI_SUCCESS Operation success. +**/ +VOID +ExpanderGpioInit ( + VOID + ) +{ + ConfigureIoExpanderGpio(mGpioTableIoExpander, mGpioTableIoExpanderSize); +} + +/** + Configure single GPIO pad for touchpanel interrupt + +**/ +VOID +TouchpanelGpioInit ( + VOID + ) +{ + GPIO_INIT_CONFIG* TouchpanelPad; + GPIO_PAD_OWN PadOwnVal; + + PadOwnVal = 0; + TouchpanelPad = &mGpioTableLpDdr3Rvp3Touchpanel; + + GpioGetPadOwnership (TouchpanelPad->GpioPad, &PadOwnVal); + if (PadOwnVal == GpioPadOwnHost) { + GpioConfigurePads (1, TouchpanelPad); + } +} + + +/** + Configure GPIO + +**/ +VOID +GpioInit ( + VOID + ) +{ + ConfigureGpio (mGpioTableLpDdr3Rvp3, mGpioTableLpDdr3Rvp3Size); + + TouchpanelGpioInit(); + + return; +} + + +/** + Configure GPIO and SIO + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +EFIAPI +KabylakeRvp3BoardInitBeforeSiliconInit ( + VOID + ) +{ + KabylakeRvp3Init (); + + GpioInit (); + ExpanderGpioInit (); + + /// + /// Do Late PCH init + /// + LateSiliconInit (); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c new file mode 100644 index 00000000..d34b0be3 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c @@ -0,0 +1,339 @@ +/** @file + +Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PeiKabylakeRvp3InitLib.h" + +#include +#include + +// +// Reference RCOMP resistors on motherboard - for SKL RVP1 +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp1[SA_MRC_MAX_RCOMP] = { 200, 81, 162 }; +// +// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for SKL RVP1 +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp1[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23, 40 }; + +/** + SkylaeA0Rvp3 board configuration init function for PEI pre-memory phase. + + PEI_BOARD_CONFIG_PCD_INIT + + @param Content pointer to the buffer contain init information for board init. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER The parameter is NULL. +**/ +EFI_STATUS +EFIAPI +KabylakeRvp3InitPreMem ( + VOID + ) +{ + PcdSet32S (PcdPcie0WakeGpioNo, 0); + PcdSet8S (PcdPcie0HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie0HoldRstGpioNo, 8); + PcdSetBoolS (PcdPcie0HoldRstActive, TRUE); + PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie0PwrEnableGpioNo, 16); + PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE); + + // + // HSIO PTSS Table + // + PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3); + PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3_Size); + PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3); + PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3_Size); + + // + // DRAM related definition + // + PcdSet8S (PcdSaMiscUserBd, 5); + + PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapSklRvp3); + PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapSklRvp3)); + PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramSklRvp3); + PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramSklRvp3)); + PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorSklRvp1); + PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetSklRvp1); + // + // Example policy for DIMM slots implementation boards: + // 1. Assign Smbus address of DIMMs and SpdData will be updated later + // by reading from DIMM SPD. + // 2. No need to apply hardcoded SpdData buffers here for such board. + // Example: + // PcdMrcSpdAddressTable0 = 0xA0 + // PcdMrcSpdAddressTable1 = 0xA2 + // PcdMrcSpdAddressTable2 = 0xA4 + // PcdMrcSpdAddressTable3 = 0xA6 + // PcdMrcSpdData = 0 + // PcdMrcSpdDataSize = 0 + // + // Kabylake RVP3 has 8GB Memory down implementation withouit SPD, + // So assign all SpdAddress to 0 and apply static SpdData buffers: + // PcdMrcSpdAddressTable0 = 0 + // PcdMrcSpdAddressTable1 = 0 + // PcdMrcSpdAddressTable2 = 0 + // PcdMrcSpdAddressTable3 = 0 + // PcdMrcSpdData = static data buffer + // PcdMrcSpdDataSize = sizeof (static data buffer) + // + PcdSet8S (PcdMrcSpdAddressTable0, 0); + PcdSet8S (PcdMrcSpdAddressTable1, 0); + PcdSet8S (PcdMrcSpdAddressTable2, 0); + PcdSet8S (PcdMrcSpdAddressTable3, 0); + PcdSet32S (PcdMrcSpdData, (UINTN) mSkylakeRvp3Spd110); + PcdSet16S (PcdMrcSpdDataSize, mSkylakeRvp3Spd110Size); + + PcdSetBoolS (PcdIoExpanderPresent, TRUE); + + return EFI_SUCCESS; +} + +/** + SkylaeA0Rvp3 board configuration init function for PEI pre-memory phase. + + PEI_BOARD_CONFIG_PCD_INIT + + @param Content pointer to the buffer contain init information for board init. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER The parameter is NULL. +**/ +EFI_STATUS +EFIAPI +SkylakeRvp3InitPreMem ( + VOID + ) +{ + PcdSet32S (PcdPcie0WakeGpioNo, 0); + PcdSet8S (PcdPcie0HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie0HoldRstGpioNo, 8); + PcdSetBoolS (PcdPcie0HoldRstActive, TRUE); + PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie0PwrEnableGpioNo, 16); + PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE); + + // + // HSIO PTSS Table + // + PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3); + PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3_Size); + PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3); + PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3_Size); + + // + // DRAM related definition + // + PcdSet8S (PcdSaMiscUserBd, 5); + + PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapSklRvp3); + PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapSklRvp3)); + PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramSklRvp3); + PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramSklRvp3)); + PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorSklRvp1); + PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetSklRvp1); + // + // Example policy for DIMM slots implementation boards: + // 1. Assign Smbus address of DIMMs and SpdData will be updated later + // by reading from DIMM SPD. + // 2. No need to apply hardcoded SpdData buffers here for such board. + // Example: + // PcdMrcSpdAddressTable0 = 0xA0 + // PcdMrcSpdAddressTable1 = 0xA2 + // PcdMrcSpdAddressTable2 = 0xA4 + // PcdMrcSpdAddressTable3 = 0xA6 + // PcdMrcSpdData = 0 + // PcdMrcSpdDataSize = 0 + // + // Skylake RVP3 has 4GB Memory down implementation withouit SPD, + // So assign all SpdAddress to 0 and apply static SpdData buffers: + // PcdMrcSpdAddressTable0 = 0 + // PcdMrcSpdAddressTable1 = 0 + // PcdMrcSpdAddressTable2 = 0 + // PcdMrcSpdAddressTable3 = 0 + // PcdMrcSpdData = static data buffer + // PcdMrcSpdDataSize = sizeof (static data buffer) + // + PcdSet8S (PcdMrcSpdAddressTable0, 0); + PcdSet8S (PcdMrcSpdAddressTable1, 0); + PcdSet8S (PcdMrcSpdAddressTable2, 0); + PcdSet8S (PcdMrcSpdAddressTable3, 0); + PcdSet32S (PcdMrcSpdData, (UINTN) mSkylakeRvp3Spd); + PcdSet16S (PcdMrcSpdDataSize, mSkylakeRvp3SpdSize); + + PcdSetBoolS (PcdIoExpanderPresent, TRUE); + + return EFI_SUCCESS; +} + +#define SIO_RUNTIME_REG_BASE_ADDRESS 0x0680 + +/** + Configures GPIO. + + @param[in] GpioTable Point to Platform Gpio table + @param[in] GpioTableCount Number of Gpio table entries + +**/ +VOID +ConfigureGpio ( + IN GPIO_INIT_CONFIG *GpioDefinition, + IN UINT16 GpioTableCount + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n")); + + Status = GpioConfigurePads (GpioTableCount, GpioDefinition); + + DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n")); +} + +/** + Configure GPIO Before Memory is not ready. + +**/ +VOID +GpioInitPreMem ( + VOID + ) +{ + // ConfigureGpio (); +} + +/** + Configure Super IO. + +**/ +VOID +SioInit ( + VOID + ) +{ + // + // Program and Enable Default Super IO Configuration Port Addresses and range + // + PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x10); + + // + // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF; + // + PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F), 0x10); + + return; +} + +/** + Configues the IC2 Controller on which GPIO Expander Communicates. + This Function is to enable the I2CGPIOExapanderLib to programm the Gpios + Complete intilization will be done in later Stage + +**/ +VOID +EFIAPI +I2CGpioExpanderInitPreMem( + VOID + ) +{ + ConfigureSerialIoController (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden); + SerialIoI2cGpioInit (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden, PchSerialIoIs33V); +} + +/** + Configure GPIO and SIO before memory ready. + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +EFIAPI +KabylakeRvp3BoardInitBeforeMemoryInit ( + VOID + ) +{ + EFI_STATUS Status; + + if (LibPcdGetSku () == BoardIdKabyLakeYLpddr3Rvp3) { + KabylakeRvp3InitPreMem (); + } else if (LibPcdGetSku () == BoardIdSkylakeRvp3) { + SkylakeRvp3InitPreMem (); + } + + // + // Configures the I2CGpioExpander + // + if (PcdGetBool (PcdIoExpanderPresent)) { + I2CGpioExpanderInitPreMem(); + } + + GpioInitPreMem (); + SioInit (); + + /// + /// Do basic PCH init + /// + SiliconInit (); + + // + // Install PCH RESET PPI and EFI RESET2 PeiService + // + Status = PchInitializeReset (); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +KabylakeRvp3BoardDebugInit ( + VOID + ) +{ + /// + /// Do Early PCH init + /// + EarlySiliconInit (); + return EFI_SUCCESS; +} + +EFI_BOOT_MODE +EFIAPI +KabylakeRvp3BoardBootModeDetect ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c new file mode 100644 index 00000000..70e93e94 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c @@ -0,0 +1,40 @@ +/** @file + Kaby Lake RVP 3 Multi-Board Initialization Post-Memory library + +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +KabylakeRvp3BoardInitBeforeSiliconInit ( + VOID + ); + +BOARD_POST_MEM_INIT_FUNC mKabylakeRvp3BoardInitFunc = { + KabylakeRvp3BoardInitBeforeSiliconInit, + NULL, // BoardInitAfterSiliconInit +}; + +EFI_STATUS +EFIAPI +PeiKabylakeRvp3MultiBoardInitLibConstructor ( + VOID + ) +{ + if ((LibPcdGetSku () == BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSku () == BoardIdSkylakeRvp3)) { + return RegisterBoardPostMemInit (&mKabylakeRvp3BoardInitFunc); + } + return EFI_SUCCESS; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf new file mode 100644 index 00000000..f955dd4e --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf @@ -0,0 +1,56 @@ +## @file +# Component information file for KabylakeRvp3InitLib in PEI post memory phase. +# +# Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiKabylakeRvp3MultiBoardInitLib + FILE_GUID = C7D39F17-E5BA-41D9-8DFE-FF9017499280 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = NULL + CONSTRUCTOR = PeiKabylakeRvp3MultiBoardInitLibConstructor + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + GpioExpanderLib + PcdLib + SiliconInitLib + MultiBoardInitSupportLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + KabylakeSiliconPkg/SiPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Sources] + PeiKabylakeRvp3InitPostMemLib.c + KabylakeRvp3GpioTable.c + KabylakeRvp3HdaVerbTables.c + PeiMultiBoardInitPostMemLib.c + +[FixedPcd] + +[Pcd] + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel + + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize + + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable + + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c new file mode 100644 index 00000000..69ea8b2c --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c @@ -0,0 +1,82 @@ +/** @file + Kaby Lake RVP 3 Multi-Board Initialization Pre-Memory library + +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +KabylakeRvp3BoardDetect ( + VOID + ); + +EFI_STATUS +EFIAPI +KabylakeRvp3MultiBoardDetect ( + VOID + ); + +EFI_BOOT_MODE +EFIAPI +KabylakeRvp3BoardBootModeDetect ( + VOID + ); + +EFI_STATUS +EFIAPI +KabylakeRvp3BoardDebugInit ( + VOID + ); + +EFI_STATUS +EFIAPI +KabylakeRvp3BoardInitBeforeMemoryInit ( + VOID + ); + +BOARD_DETECT_FUNC mKabylakeRvp3BoardDetectFunc = { + KabylakeRvp3MultiBoardDetect +}; + +BOARD_PRE_MEM_INIT_FUNC mKabylakeRvp3BoardPreMemInitFunc = { + KabylakeRvp3BoardDebugInit, + KabylakeRvp3BoardBootModeDetect, + KabylakeRvp3BoardInitBeforeMemoryInit, + NULL, // BoardInitAfterMemoryInit + NULL, // BoardInitBeforeTempRamExit + NULL, // BoardInitAfterTempRamExit +}; + +EFI_STATUS +EFIAPI +KabylakeRvp3MultiBoardDetect ( + VOID + ) +{ + KabylakeRvp3BoardDetect (); + if ((LibPcdGetSku () == BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSku () == BoardIdSkylakeRvp3)) { + RegisterBoardPreMemInit (&mKabylakeRvp3BoardPreMemInitFunc); + } + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +PeiKabylakeRvp3MultiBoardInitPreMemLibConstructor ( + VOID + ) +{ + return RegisterBoardDetect (&mKabylakeRvp3BoardDetectFunc); +} \ No newline at end of file diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf new file mode 100644 index 00000000..23fe6b6f --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf @@ -0,0 +1,137 @@ +## @file +# Component information file for PEI KabylakeRvp3 Board Init Pre-Mem Library +# +# Copyright (c) 2017 - 2021 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiKabylakeRvp3MultiBoardInitPreMemLib + FILE_GUID = EA05BD43-136F-45EE-BBBA-27D75817574F + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = NULL + CONSTRUCTOR = PeiKabylakeRvp3MultiBoardInitPreMemLibConstructor + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PcdLib + SiliconInitLib + MultiBoardInitSupportLib + EcLib + PchResetLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + KabylakeSiliconPkg/SiPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Sources] + PeiKabylakeRvp3InitPreMemLib.c + KabylakeRvp3HsioPtssTables.c + KabylakeRvp3SpdTable.c + PeiMultiBoardInitPreMemLib.c + PeiKabylakeRvp3Detect.c + +[Pcd] + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort + + # PCH-LP HSIO PTSS Table + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + + # PCH-H HSIO PTSS Table + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + + # SA Misc Config + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize + + # PEG Reset By GPIO + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive + + + # SPD Address Table + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 + + # CA Vref Configuration + + # Root Port Clock Info + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort0ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort4ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort5ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort7ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort8ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort9ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortLanClkInfo + + # USB 2.0 Port AFE + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe + + # USB 2.0 Port Over Current Pin + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 + + # USB 3.0 Port Over Current Pin + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 + + # Misc + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent + + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc new file mode 100644 index 00000000..f64555e3 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc @@ -0,0 +1,521 @@ +## @file +# The main build description file for the KabylakeRvp3 board. +# +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +[Defines] + DEFINE PLATFORM_PACKAGE = MinPlatformPkg + DEFINE PLATFORM_SI_PACKAGE = KabylakeSiliconPkg + DEFINE PLATFORM_SI_BIN_PACKAGE = KabylakeSiliconBinPkg + DEFINE PLATFORM_BOARD_PACKAGE = KabylakeOpenBoardPkg + DEFINE BOARD = KabylakeRvp3 + DEFINE PROJECT = $(PLATFORM_BOARD_PACKAGE)/$(BOARD) + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + DEFINE TOP_MEMORY_ADDRESS = 0x0 + + # + # Default value for OpenBoardPkg.fdf use + # + DEFINE BIOS_SIZE_OPTION = SIZE_70 + + PLATFORM_NAME = $(PLATFORM_PACKAGE) + PLATFORM_GUID = 8470676C-18E8-467F-B126-28DB1941AA5A + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010005 + OUTPUT_DIRECTORY = Build/$(PROJECT) + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = ALL + FLASH_DEFINITION = $(PROJECT)/OpenBoardPkg.fdf + + FIX_LOAD_TOP_MEMORY_ADDRESS = 0x0 + + # + # Include PCD configuration for this board. + # + !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc + + !include OpenBoardPkgPcd.dsc + !include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc + +[Defines] +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 + # + # For backward compatibility API mode will use KabylakeFspBinPkg. + # KabylakeFspBinPkg only supports API mode. + # + DEFINE PLATFORM_FSP_BIN_PACKAGE = KabylakeFspBinPkg +!else + # + # AmberLakeFspBinPkg supports both API and Dispatch modes + # + DEFINE PLATFORM_FSP_BIN_PACKAGE = AmberLakeFspBinPkg +!endif + +[PcdsDynamicExDefault.common.DEFAULT] +!if gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == TRUE +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 0 + # + # Include FSP DynamicEx PCD settings in Dispatch mode + # + !include $(PLATFORM_FSP_BIN_PACKAGE)/FspPcds.dsc + + # + # Override some FSP consumed PCD default value to match platform requirement. + # + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress |gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength +!endif +!endif + +################################################################################ +# +# SKU Identification section - list of all SKU IDs supported by this board. +# +################################################################################ +[SkuIds] + 0x00|DEFAULT # 0|DEFAULT is reserved and always required. + 0x04|KabylakeRvp3 + 0x60|KabyLakeYLpddr3Rvp3 + +################################################################################ +# +# Includes section - other DSC file contents included for this board build. +# +################################################################################ + +####################################### +# Library Includes +####################################### +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc + +####################################### +# Component Includes +####################################### + +# @todo: Change below line to [Components.$(PEI_ARCH)] after https://bugzilla.tianocore.org/show_bug.cgi?id=2308 +# is completed +[Components.IA32] +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc + +# @todo: Change below line to [Components.$(DXE_ARCH)] after https://bugzilla.tianocore.org/show_bug.cgi?id=2308 +# is completed +[Components.X64] +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc + +####################################### +# Build Option Includes +####################################### +!include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc +!include OpenBoardPkgBuildOption.dsc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this board. +# +################################################################################ + +[LibraryClasses.common] + ####################################### + # Edk2 Packages + ####################################### + FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf + FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib/PeiFspWrapperApiTestLib.inf + + ####################################### + # Silicon Initialization Package + ####################################### + ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf + SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf + +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 + # + # FSP API mode + # + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf +!else + # + # FSP Dispatch mode and non-FSP build (EDK2 build) + # + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf +!endif + + ##################################### + # Platform Package + ##################################### + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf + FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf + PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.inf + PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf + PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf + PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf + ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.inf + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf + + ####################################### + # Board Package + ####################################### + EcLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseEcLib/BaseEcLib.inf + GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.inf + I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAccessLib.inf + PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf + + # Thunderbolt +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE + DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.inf + TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf +!endif + + ####################################### + # Board-specific + ####################################### + PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookLib.inf + +[LibraryClasses.IA32.SEC] + ####################################### + # Platform Package + ####################################### + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SecTestPointCheckLib.inf + SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf + SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf + +[LibraryClasses.common.PEIM] + ####################################### + # Silicon Package + ####################################### + ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf + + ####################################### + # Platform Package + ####################################### + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf + MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointLib.inf +!if $(TARGET) == DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf +!endif + SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf + + ####################################### + # Board Package + ####################################### +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 + # + # FSP API mode + # + SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf +!else + # + # FSP Dispatch mode and non-FSP build (EDK2 build) + # + SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf +!endif + + # Thunderbolt +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE + PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.inf + PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf +!endif + +[LibraryClasses.common.DXE_DRIVER] + ####################################### + # Silicon Initialization Package + ####################################### + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/DxeSiliconPolicyInitLib/DxeSiliconPolicyInitLib.inf + + ####################################### + # Platform Package + ####################################### + BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrapperPlatformLib/DxeFspWrapperPlatformLib.inf + MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf + MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointLib.inf + +!if $(TARGET) == DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.inf +!endif + ####################################### + # Board Package + ####################################### + BoardBdsHookLib|BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf + BoardBootManagerLib|BoardModulePkg/Library/BoardBootManagerLib/BoardBootManagerLib.inf + + ####################################### + # Board-specific + ####################################### + SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf + +[LibraryClasses.X64.DXE_RUNTIME_DRIVER] + ####################################### + # Silicon Initialization Package + ####################################### + ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf + +[LibraryClasses.X64.DXE_SMM_DRIVER] + ####################################### + # Silicon Initialization Package + ####################################### + SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf + + ####################################### + # Platform Package + ####################################### + BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf + MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointLib.inf +!if $(TARGET) == DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf +!endif + +####################################### +# PEI Components +####################################### +# @todo: Change below line to [Components.$(PEI_ARCH)] after https://bugzilla.tianocore.org/show_bug.cgi?id=2308 +# is completed +[Components.IA32] + ####################################### + # Edk2 Packages + ####################################### + UefiCpuPkg/SecCore/SecCore.inf { + + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + } + +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 + # + # In FSP API mode the policy has to be installed before FSP Wrapper updating UPD. + # Add policy as dependency for FSP Wrapper + # + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf { + + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLibDependency/PeiPreMemSiliconPolicyInitLibDependency.inf + } + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf { + + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLibDependency/PeiPostMemSiliconPolicyInitLibDependency.inf + } +!else + # + # In FSP Dispatch mode the policy will be installed after FSP-M dispatched (only PrePolicy silicon-init executed). + # Do not add policy dependency and let FspmWrapper report FSP-M FV to dispatcher. + # + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf { + + SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf + } + # + # In FSP Dispatch mode the policy will be installed after FSP-S dispatched (only PrePolicy silicon-init executed). + # Do not add policy dependency and let FspsWrapper report FSP-S FV to dispatcher. + # + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf { + + SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf + } +!endif + + ####################################### + # Silicon Initialization Package + ####################################### + IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf + IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf + + ####################################### + # Platform Package + ####################################### + $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { + + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport == FALSE + BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.inf + !else + NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf + !endif + } + + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf { + + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport == FALSE + BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLib.inf + !else + NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf + !endif + } + +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf { + + # + # Hook a library constructor to update some policy fields when policy is installed. + # + NULL|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf + } + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf +!else + # + # FSP Dispatch mode will consume DefaultPolicyInit PPI produced by FSP to install a default policy PPI. + # Similar as UPD in FSP API mode, DefaultPolicyInit PPI in Dispatch mode can generate different policy structure + # for different FSP revisions, but they must maintain backward compatibility. + # + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf { + + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.inf + } + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf { + + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf + } +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf +!endif + + ####################################### + # Board Package + ####################################### + # Thunderbolt +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf +!endif + $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf + +####################################### +# DXE Components +####################################### +# @todo: Change below line to [Components.$(DXE_ARCH)] after https://bugzilla.tianocore.org/show_bug.cgi?id=2308 +# is completed +[Components.X64] + ####################################### + # Edk2 Packages + ####################################### + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf + MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf{ + + NULL|BoardModulePkg/Library/BdsPs2KbcLib/BdsPs2KbcLib.inf + } + UefiCpuPkg/CpuDxe/CpuDxe.inf + +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 + # + # FSP API mode + # + IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf +!endif + + ShellPkg/Application/Shell/Shell.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + } + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046 + + !if $(TARGET) == DEBUG + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !endif + } +!endif + + ####################################### + # Silicon Initialization Package + ####################################### + IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf + $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf + + ####################################### + # Platform Package + ####################################### + $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf + $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf + $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf + $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + + $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf + + $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { + + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport == FALSE + BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf + !else + NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf + !endif + } + + $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf { + + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport == FALSE + BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf + !else + NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf + !endif + } + +!endif + + ####################################### + # Board Package + ####################################### + # Thunderbolt +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf + $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf { + + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport == FALSE + BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf + !else + NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf + !endif + } +!endif + BoardModulePkg/LegacySioDxe/LegacySioDxe.inf + BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.fdf new file mode 100644 index 00000000..6cdf4e2f --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.fdf @@ -0,0 +1,715 @@ +## @file +# FDF file of Platform. +# +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ +[FD.KabylakeRvp3] +# +# FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks, cannot be +# assigned with PCD values. Instead, it uses the definitions for its variety, which +# are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS. +# +BaseAddress = $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress #The base address of the FLASH Device. +Size = $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize #The size in bytes of the FLASH Device +ErasePolarity = 1 +BlockSize = $(FLASH_BLOCK_SIZE) +NumBlocks = $(FLASH_NUM_BLOCKS) + +DEFINE SIPKG_DXE_SMM_BIN = INF +DEFINE SIPKG_PEI_BIN = INF + +# Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macro expression is not supported. +# So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase to get the real CodeCache base address. +SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase = $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset) +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x60 +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# Fv Size can be adjusted +# +################################################################################ +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +#NV_VARIABLE_STORE +DATA = { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x40000 + 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, + #Signature "_FVH" #Attributes + 0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00, + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision + # + # Be careful on CheckSum field. + # + 0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02, + #Blockmap[0]: 4 Blocks 0x10000 Bytes / Block + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + #Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER +!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE + # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, +!else + # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, +!endif + #Size: 0x1E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x1DFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xDF, 0x01, 0x00, + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA = { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +#NV_FTW_SPARE + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize +FV = FvAdvanced + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize +FV = FvSecurity + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize +FV = FvOsBoot + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize +FV = FvUefiBoot + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize +FV = FvPostMemory + +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize +#Microcode +FV = FvMicrocode + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize +# FSP_S Section +FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize +# FSP_M Section +FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize +# FSP_T Section +FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize +FV = FvAdvancedPreMemory + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize +FV = FvPreMemory + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ +[FV.FvMicrocode] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = FALSE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = FALSE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf + +[FV.FvPreMemory] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D + +INF UefiCpuPkg/SecCore/SecCore.inf +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1) +# +# PeiMain is needed only for FSP API mode or EDK2 build, +# in FSP dispatch mode the one inside FSP Binary is launched +# unless requested otherwise (PcdFspDispatchModeUseFspPeiMain == FALSE). +# +INF MdeModulePkg/Core/Pei/PeiMain.inf +!endif +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf + +INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf +INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf +INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf + +[FV.FvPostMemoryUncompact] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7 + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf + +# Init Board Config PCD +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf +INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf + +!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE +FILE FREEFORM = 4ad46122-ffeb-4a52-bfb0-518cfca02db0 { + SECTION RAW = $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin + SECTION UI = "Vbt" +} +FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D { + SECTION RAW = MdeModulePkg/Logo/Logo.bmp +} +!endif # PcdPeiDisplayEnable + +[FV.FvPostMemory] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 9DFE49DB-8EF0-4D9C-B273-0036144DE917 + +FILE FV_IMAGE = 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvPostMemoryUncompact + } +} + +[FV.FvUefiBootUncompact] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5 + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf + +INF UefiCpuPkg/CpuDxe/CpuDxe.inf +INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + +INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf +INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf +INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf +INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf +INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf +INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf +INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf + +INF ShellPkg/Application/Shell/Shell.inf + +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 + # + # Below module is used by FSP API mode + # + INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf +!endif + +INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf + +[FV.FvUefiBoot] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 0496D33D-EA79-495C-B65D-ABF607184E3B + +FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvUefiBootUncompact + } + } + +[FV.FvOsBootUncompact] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = A0F04529-B715-44C6-BCA4-2DEBDD01EEEC + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf + +INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf +INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf + +INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf +INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf + +INF RuleOverride = DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf + +INF $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf + +!endif + +[FV.FvLateSilicon] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxe.inf +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf + +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf + +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf + +INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf +INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf + +!endif + +[FV.FvOsBoot] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 13BF8810-75FD-4B1A-91E6-E16C4201F80A + +FILE FV_IMAGE = B9020753-84A8-4BB6-947C-CE7D41F5CE39 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvOsBootUncompact + } + } + +FILE FV_IMAGE = D4632741-510C-44E3-BE21-C3D6D7881485 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvLateSilicon + } + } + +[FV.FvSecurityPreMemory] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 #FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf + +INF IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf + +INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf + +[FV.FvSecurityPostMemory] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 #FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 4199E560-54AE-45E5-91A4-F7BC3804E14A + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf +!endif + +[FV.FvSecurityLate] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = F753FE9A-EEFD-485B-840B-E032D538102C + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf + +INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + +INF $(PLATFORM_SI_PACKAGE)/Hsti/Dxe/HstiSiliconDxe.inf + +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + +INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf +!endif + +!endif + +[FV.FvSecurity] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF + +FILE FV_IMAGE = 757CC075-1428-423D-A73C-22639706C119 { + SECTION FV_IMAGE = FvSecurityPreMemory + } + +FILE FV_IMAGE = 80BB8482-44D5-4BEC-82B5-8D87A933830B { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvSecurityPostMemory + } + } + +FILE FV_IMAGE = C83522D9-80A1-4D95-8C25-3F1370497406 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvSecurityLate + } + } + +# +# Pre-memory Advanced Features +# +[FV.FvAdvancedPreMemory] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 6053D78A-457E-4490-A237-31D0FBE2F305 + +!include AdvancedFeaturePkg/Include/PreMemory.fdf + +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE +INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf +!endif + +# +# Post-Memory Advanced Features +# +[FV.FvAdvancedUncompact] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = BE3DF86F-E464-44A3-83F7-0D27E6B88C27 + +!include AdvancedFeaturePkg/Include/PostMemory.fdf + +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE +INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf +INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf +INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf +!endif + +# +# Compressed FV with Post-Memory Advanced Features +# +[FV.FvAdvanced] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = B23E7388-9953-45C7-9201-0473DDE5487A + +FILE FV_IMAGE = 5248467B-B87B-4E74-AC02-398AF4BCB712 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvAdvancedUncompact + } + } + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + +!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgBuildOption.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgBuildOption.dsc new file mode 100644 index 00000000..8e885cc6 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgBuildOption.dsc @@ -0,0 +1,151 @@ +## @file +# platform build option configuration file. +# +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[BuildOptions] +# Define Build Options both for EDK and EDKII drivers. + + + DEFINE DSC_S3_BUILD_OPTIONS = + + DEFINE DSC_CSM_BUILD_OPTIONS = + +!if gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE + DEFINE DSC_ACPI_BUILD_OPTIONS = -DACPI_SUPPORT=1 +!else + DEFINE DSC_ACPI_BUILD_OPTIONS = +!endif + + DEFINE BIOS_GUARD_BUILD_OPTIONS = + + DEFINE OVERCLOCKING_BUILD_OPTION = + + DEFINE FSP_BINARY_BUILD_OPTIONS = + + DEFINE FSP_WRAPPER_BUILD_OPTIONS = -DFSP_WRAPPER_FLAG + + DEFINE SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS = + + DEFINE RESTRICTED_OPTION = + + + DEFINE SV_BUILD_OPTIONS = + + DEFINE TEST_MENU_BUILD_OPTION = + +!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable == FALSE + DEFINE OPTIMIZE_DISABLE_OPTIONS = -Od -GL- +!else + DEFINE OPTIMIZE_DISABLE_OPTIONS = +!endif + + DEFINE UP_SERVER_SUPPORT_BUILD_OPTIONS = + + + DEFINE TPM_BUILD_OPTION = + + DEFINE TPM2_BUILD_OPTION = + + DEFINE DSC_TBT_BUILD_OPTIONS = + + DEFINE DSC_DCTT_BUILD_OPTIONS = + + DEFINE EMB_BUILD_OPTIONS = + + DEFINE DSC_MEMORY_DOWN_BUILD_OPTIONS = -DMEM_DOWN_FLAG=1 + + DEFINE DSC_KBCEMUL_BUILD_OPTIONS = + + DEFINE BOOT_GUARD_BUILD_OPTIONS = + + DEFINE SECURE_BOOT_BUILD_OPTIONS = + + DEFINE USBTYPEC_BUILD_OPTION = + + DEFINE CAPSULE_BUILD_OPTIONS = + + DEFINE PERFORMANCE_BUILD_OPTION = + + DEFINE DEBUGUSEUSB_BUILD_OPTION = + + DEFINE DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION = -DDISABLE_NEW_DEPRECATED_INTERFACES=1 + + DEFINE SINITBIN_BUILD_OPTION = + + DEFINE MINTREE_FLAG_BUILD_OPTION = -DMINTREE_FLAG=1 + +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OVERCLOCKING_BUILD_OPTION) $(PERFORMANCE_BUILD_OPTION) $(EMB_BUILD_OPTIONS) $(BIOS_GUARD_BUILD_OPTIONS) $(DSC_TBT_BUILD_OPTIONS) +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(BOOT_GUARD_BUILD_OPTIONS) $(DSC_MEMORY_DOWN_BUILD_OPTIONS) $(DEBUGUSEUSB_BUILD_OPTION) $(DSC_S3_BUILD_OPTIONS) +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(FSP_BINARY_BUILD_OPTIONS) $(FSP_WRAPPER_BUILD_OPTIONS) $(SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS) +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(DSC_KBCEMUL_BUILD_OPTIONS) $(CAPSULE_BUILD_OPTIONS) $(SECURE_BOOT_BUILD_OPTIONS) $(DSC_CSM_BUILD_OPTIONS) $(DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION) +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(TPM2_BUILD_OPTION) $(TPM_BUILD_OPTION) $(DSC_DCTT_BUILD_OPTIONS) +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(DSC_ACPI_BUILD_OPTIONS) $(UP_SERVER_SUPPORT_BUILD_OPTIONS) $(USBTYPEC_BUILD_OPTION) $(SINITBIN_BUILD_OPTION) $(MINTREE_FLAG_BUILD_OPTION) + +[BuildOptions.Common.EDKII] + +# +# For IA32 Global Build Flag +# + *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI + *_*_IA32_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_APP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_ASLPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_NASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + +# +# For IA32 Specific Build Flag +# +GCC: *_*_IA32_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) +GCC: *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI -Wno-unused -Wl,--allow-multiple-definition +MSFT: *_*_IA32_ASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI +MSFT: *_*_IA32_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_APP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_ASLPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) + +# +# For X64 Global Build Flag +# + *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 + *_*_X64_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_APP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_ASLPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_NASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + + +# +# For X64 Specific Build Flag +# +GCC: *_*_X64_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) +GCC: *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -Wno-unused -Wl,--allow-multiple-definition +MSFT: *_*_X64_ASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 +MSFT: *_*_X64_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) +MSFT: *_*_X64_APP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) +MSFT: *_*_X64_ASLPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_X64_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + + +# Force PE/COFF sections to be aligned at 4KB boundaries to support page level protection +[BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE] + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096 + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 + +# Force PE/COFF sections to be aligned at 4KB boundaries to support MemoryAttribute table +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096 + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 + +# Force PE/COFF sections to be aligned at 4KB boundaries to support NX protection +[BuildOptions.common.EDKII.DXE_DRIVER, BuildOptions.common.EDKII.DXE_CORE, BuildOptions.common.EDKII.UEFI_DRIVER, BuildOptions.common.EDKII.UEFI_APPLICATION] + #MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096 + #GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc new file mode 100644 index 00000000..725596cb --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc @@ -0,0 +1,464 @@ +## @file +# PCD configuration build description file for the KabylakeRvp3 board. +# +# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Pcd Section - list of all PCD Entries used by this board. +# +################################################################################ + +[PcdsFixedAtBuild.common] + ###################################### + # Key Boot Stage and FSP configuration + ###################################### + # + # Please select the Boot Stage here. + # Stage 1 - enable debug (system deadloop after debug init) + # Stage 2 - mem init (system deadloop after mem init) + # Stage 3 - boot to shell only + # Stage 4 - boot to OS + # Stage 5 - boot to OS with security boot enabled + # Stage 6 - boot with advanced features enabled + # + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 + + # + # 0: FSP Wrapper is running in Dispatch mode. + # 1: FSP Wrapper is running in API mode. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0 + + # + # FALSE: The board is not a FSP wrapper (FSP binary not used) + # TRUE: The board is a FSP wrapper (FSP binary is used) + # + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE + + # + # FALSE: The PEI Main included in FvPreMemory is used to dispatch all PEIMs + # (both inside FSP and outside FSP). + # Pros: + # * PEI Main is re-built from source and is always the latest version + # * Platform code can link any desired LibraryClass to PEI Main + # (Ex: Custom DebugLib instance, SerialPortLib, etc.) + # Cons: + # * The PEI Main being used to execute FSP PEIMs is not the PEI Main + # that the FSP PEIMs were tested with, adding risk of breakage. + # * Two copies of PEI Main will exist in the final binary, + # #1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is never + # executed, wasting space. + # + # TRUE: The PEI Main included in FSP is used to dispatch all PEIMs + # (both inside FSP and outside FSP). PEI Main will not be included in + # FvPreMemory. This is the default and is the recommended choice. + # + gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE + + # + # FSP Base address PCD will be updated in FDF basing on flash map. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0 + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0 + + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 + gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 + gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 + gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000 + +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 + # + # FSP API mode does not share stack with the boot loader, + # so FSP needs more temporary memory for FSP heap + stack size. + # + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000 + # + # FSP API mode does not need to enlarge the boot loader stack size + # since the stacks are separate. + # + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 +!else + # + # In FSP Dispatch mode boot loader stack size must be large + # enough for executing both boot loader and FSP. + # + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x40000 +!endif + +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1) + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength +!else + # + # FSP Dispatch mode requires more platform memory as boot loader and FSP sharing the same + # platform memory. + # + gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x5500000 +!endif + +[PcdsFeatureFlag.common] + ###################################### + # Edk2 Configuration + ###################################### + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + + ###################################### + # Silicon Configuration + ###################################### + # Build switches + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE + + # CPU + gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE + + # SA + gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSkycamEnable|TRUE + gSiPkgTokenSpaceGuid.PcdGmmEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE + gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE + + # ME + gSiPkgTokenSpaceGuid.PcdAmtEnable|TRUE + gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE + gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE + + # Others + gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE + gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE + gSiPkgTokenSpaceGuid.PcdBootGuardEnable|TRUE + gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE + gSiPkgTokenSpaceGuid.PcdEvLoaderEnable|FALSE + gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE + gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE + gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE + gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE + gSiPkgTokenSpaceGuid.PcdSerialGpioEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE + gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE + gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSsaFlagEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE + + ###################################### + # Platform Configuration + ###################################### + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable|FALSE + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4 + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5 + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE +!endif + +!if $(TARGET) == DEBUG + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE +!else + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE +!endif + + ###################################### + # Board Configuration + ###################################### + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport|TRUE + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable|FALSE + +[PcdsFixedAtBuild.common] + ###################################### + # Edk2 Configuration + ###################################### +!if $(TARGET) == RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 +!endif + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 +!endif + + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01 + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS) + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400 +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000 + gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE +!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1 +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE +!if $(TARGET) == DEBUG + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE +!if $(TARGET) == RELEASE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE +!endif + + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x40 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08 + + # Specifies timeout value in microseconds for the BSP to detect all APs for the first time. + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000 +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1) + # + # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild + # (They will be DynamicEx in FSP Dispatch mode) + # + ## Specifies max supported number of Logical Processors. + # @Prompt Configure max supported number of Logical Processors + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|12 + + ## Specifies the size of the microcode Region. + # @Prompt Microcode Region size. + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0 + + ## Specifies the AP wait loop state during POST phase. + # The value is defined as below. + # 1: Place AP in the Hlt-Loop state. + # 2: Place AP in the Mwait-Loop state. + # 3: Place AP in the Run-Loop state. + # @Prompt The AP wait loop state. + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 +!endif + + ###################################### + # Silicon Configuration + ###################################### + + # Refer to HstiFeatureBit.h for bit definitions + gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 + gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 + + ###################################### + # Platform Configuration + ###################################### + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + + # + # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags + # + # BIT0: If set, expresses that for all synchronous SMM entries,SMM will validate that input and output buffers lie entirely within the expected fixed memory regions. + # BIT1: If set, expresses that for all synchronous SMM entries, SMM will validate that input and output pointers embedded within the fixed communication buffer only refer to address ranges \ + # that lie entirely within the expected fixed memory regions. + # BIT2: Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms. + # BIT3-31: Reserved + # + gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 + +!if $(TARGET) == RELEASE + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402 +!else + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B +!endif + + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b +!if $(TARGET) == RELEASE + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70 +!else + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0 +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 1 + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 2 + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 3 + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 4 + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 5 + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 6 + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} +!endif + + + ###################################### + # Board Configuration + ###################################### + gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable|1 + gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x00, 0x00, 0x1F, 0x00} + +[PcdsFixedAtBuild.IA32] + ###################################### + # Edk2 Configuration + ###################################### + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 + + ###################################### + # Platform Configuration + ###################################### + gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000 + +[PcdsFixedAtBuild.X64] + ###################################### + # Edk2 Configuration + ###################################### + + # Default platform supported RFC 4646 languages: (American) English + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US" + +[PcdsPatchableInModule.common] + ###################################### + # Edk2 Configuration + ###################################### + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208 + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 + + ###################################### + # Silicon Configuration + ###################################### +!if $(TARGET) == DEBUG + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1 +!endif + +[PcdsDynamicDefault] + ###################################### + # Edk2 Configuration + ###################################### + gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 + + # + # Set video to native resolution as Windows 8 WHCK requirement. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0 + + gEfiSecurityPkgTokenSpaceGuid.PcdTcg2HashAlgorithmBitmap|0 + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2HashMask|0x0000001F + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1 + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28, 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17} + + # + # FSP Base address PCD will be updated in FDF basing on flash map. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0 + # Platform will pre-allocate UPD buffer and pass it to FspWrapper + # Those dummy address will be patched before FspWrapper executing + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0xFFFFFFFF + + ###################################### + # Board Configuration + ###################################### + + # Thunderbolt Configuration + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcpiGpeSignature|0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting|0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm|0x0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x02010011 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtControllerEn|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtControllerType|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioAccessType|0x2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd|56 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemRsvd|100 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd|100 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieRpNumber|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSecurityMode|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport|0x0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWin10Support|0x0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdExpander|0x0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPchPcieRootPortHpe|0x00000001 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReqDelay|0x0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtOffDelay|5000 + +[PcdsDynamicHii.X64.DEFAULT] + ###################################### + # Edk2 Configuration + ###################################### + gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"Timeout" +!else + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout" +!endif diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c new file mode 100644 index 00000000..7744af6b --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c @@ -0,0 +1,175 @@ +/** @file + This file initialises and Installs GopPolicy Protocol. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "DxeGopPolicyInit.h" +#include + +GLOBAL_REMOVE_IF_UNREFERENCED GOP_POLICY_PROTOCOL mGOPPolicy; +GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mVbtSize = 0; +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mVbtAddress = 0; + +// +// Function implementations +// + +/** + + @param[out] CurrentLidStatus + + @retval EFI_SUCCESS + @retval EFI_UNSUPPORTED +**/ +EFI_STATUS +EFIAPI +GetPlatformLidStatus ( + OUT LID_STATUS *CurrentLidStatus + ) +{ + return EFI_UNSUPPORTED; +} +/** + + @param[out] CurrentDockStatus + + @retval EFI_SUCCESS + @retval EFI_UNSUPPORTED +**/ +EFI_STATUS +EFIAPI +GetPlatformDockStatus ( + OUT DOCK_STATUS CurrentDockStatus + ) +{ + return EFI_UNSUPPORTED; +} + + +/** + + @param[out] VbtAddress + @param[out] VbtSize + + @retval EFI_SUCCESS + @retval EFI_NOT_FOUND +**/ +EFI_STATUS +EFIAPI +GetVbtData ( + OUT EFI_PHYSICAL_ADDRESS *VbtAddress, + OUT UINT32 *VbtSize + ) +{ + EFI_STATUS Status; + UINTN FvProtocolCount; + EFI_HANDLE *FvHandles; + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv; + UINTN Index; + UINT32 AuthenticationStatus; + UINT8 *Buffer; + UINTN VbtBufferSize; + + + Status = EFI_NOT_FOUND; + if ( mVbtAddress == 0) { + Fv = NULL; + + Buffer = 0; + FvHandles = NULL; + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolume2ProtocolGuid, + NULL, + &FvProtocolCount, + &FvHandles + ); + if (!EFI_ERROR (Status)) { + for (Index = 0; Index < FvProtocolCount; Index++) { + Status = gBS->HandleProtocol ( + FvHandles[Index], + &gEfiFirmwareVolume2ProtocolGuid, + (VOID **) &Fv + ); + VbtBufferSize = 0; + Status = Fv->ReadSection ( + Fv, + PcdGetPtr (PcdGraphicsVbtGuid), + EFI_SECTION_RAW, + 0, + (VOID **) &Buffer, + &VbtBufferSize, + &AuthenticationStatus + ); + if (!EFI_ERROR (Status)) { + *VbtAddress = (EFI_PHYSICAL_ADDRESS)Buffer; + *VbtSize = (UINT32)VbtBufferSize; + mVbtAddress = *VbtAddress; + mVbtSize = *VbtSize; + Status = EFI_SUCCESS; + break; + } + } + } else { + Status = EFI_NOT_FOUND; + } + + if (FvHandles != NULL) { + FreePool (FvHandles); + FvHandles = NULL; + } + } else { + *VbtAddress = mVbtAddress; + *VbtSize = mVbtSize; + Status = EFI_SUCCESS; + } + + return Status; +} + + + +/** +Initialize GOP DXE Policy + +@param[in] ImageHandle Image handle of this driver. + +@retval EFI_SUCCESS Initialization complete. +@retval EFI_UNSUPPORTED The chipset is unsupported by this driver. +@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. +@retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ + +EFI_STATUS +EFIAPI +GopPolicyInitDxe ( + IN EFI_HANDLE ImageHandle + ) +{ + EFI_STATUS Status; + + // + // Initialize the EFI Driver Library + // + SetMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL), 0); + + mGOPPolicy.Revision = GOP_POLICY_PROTOCOL_REVISION_03; + mGOPPolicy.GetPlatformLidStatus = GetPlatformLidStatus; + mGOPPolicy.GetVbtData = GetVbtData; + mGOPPolicy.GetPlatformDockStatus = GetPlatformDockStatus; + + // + // Install protocol to allow access to this Policy. + // + Status = gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gGopPolicyProtocolGuid, + &mGOPPolicy, + NULL + ); + + return Status; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h new file mode 100644 index 00000000..17f9b545 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h @@ -0,0 +1,39 @@ +/** @file +Header file for the GopPolicyInitDxe Driver. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _GOP_POLICY_INIT_DXE_H_ +#define _GOP_POLICY_INIT_DXE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/** +Initialize GOP DXE Policy + +@param[in] ImageHandle Image handle of this driver. + +@retval EFI_SUCCESS Initialization complete. +@retval EFI_UNSUPPORTED The chipset is unsupported by this driver. +@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. +@retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +GopPolicyInitDxe( + IN EFI_HANDLE ImageHandle + ); + +#endif diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h new file mode 100644 index 00000000..b49e13da --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h @@ -0,0 +1,64 @@ +/** @file + Header file for the SaPolicyInitDxe Driver. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _SA_POLICY_INIT_DXE_H_ +#define _SA_POLICY_INIT_DXE_H_ + +#include +#include +#include +#include +#include +#include + +#include + + +/** + SA DXE Policy Driver Entry Point \n + - Introduction \n + System Agent DXE drivers behavior can be controlled by platform policy without modifying reference code directly. + Platform policy Protocol is initialized with default settings in this funciton. + This policy Protocol has to be initialized prior to System Agent initialization DXE drivers execution. + + - @pre + - Runtime variable service should be ready if policy initialization required. + + - @result + SA_POLICY_PROTOCOL will be installed successfully and ready for System Agent reference code use. + + - Porting Recommendations \n + Policy should be initialized basing on platform design or user selection (like BIOS Setup Menu) + + @param[in] ImageHandle - Image handle of this driver. + + @retval EFI_SUCCESS Initialization complete. + @exception EFI_UNSUPPORTED The chipset is unsupported by this driver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +SaPolicyInitDxe ( + IN EFI_HANDLE ImageHandle + ); + +/** + Get data for platform policy from setup options. + + @param[in] SaPolicy The pointer to get SA Policy protocol instance + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +UpdateDxeSaPolicy ( + IN OUT SA_POLICY_PROTOCOL *SaPolicy + ); + +#endif diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c new file mode 100644 index 00000000..fcd248fd --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c @@ -0,0 +1,66 @@ +/** @file + This file is the library for SA DXE Policy initialization. + +Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "DxeSaPolicyInit.h" +#include + +#define SA_VTD_RMRR_USB_LENGTH 0x20000 + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mAddress; +GLOBAL_REMOVE_IF_UNREFERENCED UINTN mSize; + +/** + Update RMRR Base and Limit Address for USB. + +**/ +VOID +UpdateRmrrUsbAddress ( + IN OUT SA_POLICY_PROTOCOL *SaPolicy + ) +{ + EFI_STATUS Status; + MISC_DXE_CONFIG *MiscDxeConfig; + + Status = GetConfigBlock ((VOID *)SaPolicy, &gMiscDxeConfigGuid, (VOID *)&MiscDxeConfig); + ASSERT_EFI_ERROR (Status); + + if (1) { + mSize = EFI_SIZE_TO_PAGES(SA_VTD_RMRR_USB_LENGTH); + mAddress = SIZE_4GB; + + Status = (gBS->AllocatePages) ( + AllocateMaxAddress, + EfiReservedMemoryType, + mSize, + &mAddress + ); + ASSERT_EFI_ERROR (Status); + + MiscDxeConfig->RmrrUsbBaseAddress[0] = mAddress; + MiscDxeConfig->RmrrUsbBaseAddress[1] = mAddress + SA_VTD_RMRR_USB_LENGTH - 1; + } +} + +/** + Get data for platform policy from setup options. + + @param[in] SaPolicy The pointer to get SA Policy protocol instance + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +UpdateDxeSaPolicy ( + IN OUT SA_POLICY_PROTOCOL *SaPolicy + ) +{ + UpdateRmrrUsbAddress (SaPolicy); + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c new file mode 100644 index 00000000..d4dbb414 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c @@ -0,0 +1,53 @@ +/** @file + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +#include "DxeSaPolicyInit.h" +#include "DxeGopPolicyInit.h" + +/** + Performs silicon late policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a Protocol, etc. + + The input Policy must be returned by SiliconPolicyDoneLate(). + + In FSP or non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdateLate ( + IN VOID *Policy + ) +{ + SA_POLICY_PROTOCOL *SaPolicy; + EFI_STATUS Status; + + SaPolicy = Policy; + UpdateDxeSaPolicy (SaPolicy); + + if (PcdGetBool(PcdIntelGopEnable)) { + // + // GOP Dxe Policy Initialization + // + Status = GopPolicyInitDxe(gImageHandle); + DEBUG((DEBUG_INFO, "GOP Dxe Policy Initialization done\n")); + ASSERT_EFI_ERROR(Status); + } + + return Policy; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf new file mode 100644 index 00000000..2abf1aef --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf @@ -0,0 +1,51 @@ +## @file +# Component information file for Silicon Update Library +# +# Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = DxeSiliconUpdateLib + FILE_GUID = C523609D-E354-416B-B24F-33468D4BD21D + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconUpdateLib + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + ConfigBlockLib + +[Packages] + MdePkg/MdePkg.dec + KabylakeSiliconPkg/SiPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Sources] + DxeSiliconPolicyUpdateLib.c + DxeGopPolicyInit.c + DxeSaPolicyUpdate.c + +[Pcd] + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid + +[Protocols] + gEfiFirmwareVolume2ProtocolGuid ## CONSUMES + gSaPolicyProtocolGuid ## CONSUMES + gDxeSiPolicyProtocolGuid ## PRODUCES + gGopPolicyProtocolGuid ## PRODUCES + +[Guids] + gMiscDxeConfigGuid + +[Depex] + gEfiVariableArchProtocolGuid + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c new file mode 100644 index 00000000..2dce9be6 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c @@ -0,0 +1,601 @@ +/** @file + Provides silicon policy update library functions. + +Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Get the next microcode patch pointer. + + @param[in, out] MicrocodeData - Input is a pointer to the last microcode patch address found, + and output points to the next patch address found. + + @retval EFI_SUCCESS - Patch found. + @retval EFI_NOT_FOUND - Patch not found. +**/ +EFI_STATUS +EFIAPI +RetrieveMicrocode ( + IN OUT CPU_MICROCODE_HEADER **MicrocodeData + ) +{ + UINTN MicrocodeStart; + UINTN MicrocodeEnd; + UINTN TotalSize; + + if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) == 0) || (FixedPcdGet32 (PcdFlashMicrocodeFvSize) == 0)) { + return EFI_NOT_FOUND; + } + + /// + /// Microcode binary in SEC + /// + MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + + ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase))->HeaderLength + + sizeof (EFI_FFS_FILE_HEADER); + + MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvSize); + + if (*MicrocodeData == NULL) { + *MicrocodeData = (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart; + } else { + if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart) { + DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart \n")); + return EFI_NOT_FOUND; + } + + TotalSize = (UINTN) ((*MicrocodeData)->TotalSize); + if (TotalSize == 0) { + TotalSize = 2048; + } + + *MicrocodeData = (CPU_MICROCODE_HEADER *) ((UINTN)*MicrocodeData + TotalSize); + if (*MicrocodeData >= (CPU_MICROCODE_HEADER *) (UINTN) (MicrocodeEnd) || (*MicrocodeData)->TotalSize == (UINT32) -1) { + DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >= MicrocodeEnd \n")); + return EFI_NOT_FOUND; + } + } + return EFI_SUCCESS; +} + +/** + Get the microcode patch pointer. + + @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NULL if not found. +**/ +EFI_PHYSICAL_ADDRESS +PlatformCpuLocateMicrocodePatch ( + VOID + ) +{ + EFI_STATUS Status; + CPU_MICROCODE_HEADER *MicrocodeData; + EFI_CPUID_REGISTER Cpuid; + UINT32 UcodeRevision; + UINTN MicrocodeBufferSize; + VOID *MicrocodeBuffer = NULL; + + AsmCpuid ( + CPUID_VERSION_INFO, + &Cpuid.RegEax, + &Cpuid.RegEbx, + &Cpuid.RegEcx, + &Cpuid.RegEdx + ); + + UcodeRevision = GetCpuUcodeRevision (); + MicrocodeData = NULL; + while (TRUE) { + /// + /// Find the next patch address + /// + Status = RetrieveMicrocode (&MicrocodeData); + DEBUG ((DEBUG_INFO, "MicrocodeData = %x\n", MicrocodeData)); + + if (Status != EFI_SUCCESS) { + break; + } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, &UcodeRevision)) { + break; + } + } + + if (EFI_ERROR (Status)) { + return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; + } + + /// + /// Check that microcode patch size is <= 128K max size, + /// then copy the patch from FV to temp buffer for faster access. + /// + MicrocodeBufferSize = (UINTN) MicrocodeData->TotalSize; + + if (MicrocodeBufferSize <= MAX_MICROCODE_PATCH_SIZE) { + MicrocodeBuffer = AllocatePages (EFI_SIZE_TO_PAGES (MicrocodeBufferSize)); + if (MicrocodeBuffer != NULL) { + DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n")); + CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize); + + return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer; + } else { + DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for Microcode Patch.\n")); + } + } else { + DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max allowed size of 128K.\n")); + } + return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; +} + +/** + Update HSIO policy per board. + + @param[in] Policy - Policy PPI pointer (caller should ensure it is valid pointer) + +**/ +VOID +InstallPlatformHsioPtssTable ( + IN VOID *Policy + ) +{ + HSIO_PTSS_TABLES *UnknowPtssTables; + HSIO_PTSS_TABLES *SpecificPtssTables; + HSIO_PTSS_TABLES *PtssTables; + UINT8 PtssTableIndex; + UINT32 UnknowTableSize; + UINT32 SpecificTableSize; + UINT32 TableSize; + UINT32 Entry; + UINT8 LaneNum; + UINT8 Index; + UINT8 MaxSataPorts; + UINT8 MaxPciePorts; + UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PciePort; + UINTN RpBase; + UINTN RpDevice; + UINTN RpFunction; + UINT32 StrapFuseCfg; + UINT8 PcieControllerCfg; + PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig; + PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig; + EFI_STATUS Status; + + Status = GetConfigBlock (Policy, &gHsioPciePreMemConfigGuid, (VOID *) &HsioPciePreMemConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock (Policy, &gHsioSataPreMemConfigGuid, (VOID *) &HsioSataPreMemConfig); + ASSERT_EFI_ERROR (Status); + + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + + if (GetPchGeneration () == SklPch) { + switch (PchStepping ()) { + case PchLpB0: + case PchLpB1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable1); + UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable1Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable1); + SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable1Size); + break; + case PchLpC0: + case PchLpC1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable2Size); + break; + case PchHB0: + case PchHC0: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable1); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable1Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable1); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable1Size); + break; + case PchHD0: + case PchHD1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size); + break; + default: + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); + } + } else { + switch (PchStepping ()) { + case KblPchHA0: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size); + break; + default: + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); + } + } + + PtssTableIndex = 0; + MaxSataPorts = GetPchMaxSataPortNum (); + MaxPciePorts = GetPchMaxPciePortNum (); + ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal)); + // + //Populate PCIe topology based on lane configuration + // + for (PciePort = 0; PciePort < MaxPciePorts; PciePort += 4) { + Status = GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction); + ASSERT_EFI_ERROR (Status); + + RpBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction); + StrapFuseCfg = MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG); + PcieControllerCfg = (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC); + DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value = %d\n", PciePort, PcieControllerCfg)); + } + for (Index = 0; Index < MaxPciePorts; Index++) { + DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology = %d\n", Index, PcieTopologyReal[Index])); + } + // + //Case 1: BoardId is known, Topology is known/unknown + //Case 1a: SATA + // + PtssTables = SpecificPtssTables; + TableSize = SpecificTableSize; + for (Index = 0; Index < MaxSataPorts; Index++) { + if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA) + ) + { + PtssTableIndex++; + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) { + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; + } else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8)) { + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) { + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); + } + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) { + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); + } + } else { + ASSERT (FALSE); + } + } + } + } + } + // + //Case 1b: PCIe + // + for (Index = 0; Index < MaxPciePorts; Index++) { + if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) && + (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) { + PtssTableIndex++; + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) { + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable = TRUE; + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); + + } else { + ASSERT (FALSE); + } + } + } + } + } + // + //Case 2: BoardId is unknown, Topology is known/unknown + // + if (PtssTableIndex == 0) { + DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be applied\n")); + + PtssTables = UnknowPtssTables; + TableSize = UnknowTableSize; + + for (Index = 0; Index < MaxSataPorts; Index++) { + if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA) + ) + { + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) { + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; + + } else if (PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8) { + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) { + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); + + } + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) { + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable = TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); + } + } else { + ASSERT (FALSE); + } + } + } + } + } + for (Index = 0; Index < MaxPciePorts; Index++) { + if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) && + (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) { + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) { + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable = TRUE; + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); + } else { + ASSERT (FALSE); + } + } + } + } + } + } +} + +/** + Update PreMem phase silicon policy per board. + + @param[in] Policy - Policy PPI pointer. + + @retval Policy - Policy PPI pointer. + +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePreMem ( + IN VOID *Policy + ) +{ + EFI_STATUS Status; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc; + VOID *Buffer; + UINTN VariableSize; + VOID *MemorySavedData; + UINT8 SpdAddressTable[4]; + + DEBUG((DEBUG_INFO, "\nUpdating Policy in Pre-Mem\n")); + + if (Policy != NULL) { + SpdAddressTable[0] = PcdGet8 (PcdMrcSpdAddressTable0); + SpdAddressTable[1] = PcdGet8 (PcdMrcSpdAddressTable1); + SpdAddressTable[2] = PcdGet8 (PcdMrcSpdAddressTable2); + SpdAddressTable[3] = PcdGet8 (PcdMrcSpdAddressTable3); + + MiscPeiPreMemConfig = NULL; + Status = GetConfigBlock (Policy, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + + if (MiscPeiPreMemConfig != NULL) { + // + // Pass board specific SpdAddressTable to policy + // + CopyMem ((VOID *) MiscPeiPreMemConfig->SpdAddressTable, (VOID *) SpdAddressTable, (sizeof (UINT8) * 4)); + + // + // Set size of SMRAM + // + MiscPeiPreMemConfig->TsegSize = PcdGet32 (PcdTsegSize); + + // + // Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths. + // Note: AmberLake FSP does not implement the FSPM_ARCH_CONFIG_PPI added in FSP 2.1, hence + // the platform specific S3DataPtr must be used instead. + // + VariableSize = 0; + MemorySavedData = NULL; + Status = PeiGetVariable ( + L"MemoryConfig", + &gFspNonVolatileStorageHobGuid, + &MemorySavedData, + &VariableSize + ); + DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHobGuid - %r\n", Status)); + DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize)); + if (!EFI_ERROR (Status)) { + MiscPeiPreMemConfig->S3DataPtr = MemorySavedData; + } + + // + // In FSP Dispatch Mode these BAR values are initialized by SiliconPolicyInitPreMem() in + // KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c; this function calls + // PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI->PeiPreMemPolicyInit() to initialize all Config Blocks + // with default policy values (including these BAR values.) PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI + // is implemented in the FSP. Make sure the value that FSP is using matches the value we are using. + // + ASSERT (PcdGet64 (PcdMchBaseAddress) <= 0xFFFFFFFF); + ASSERT (MiscPeiPreMemConfig->MchBar == (UINT32) PcdGet64 (PcdMchBaseAddress)); + ASSERT (MiscPeiPreMemConfig->SmbusBar == PcdGet16 (PcdSmbusBaseAddress)); + } + MemConfigNoCrc = NULL; + Status = GetConfigBlock (Policy, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc); + ASSERT_EFI_ERROR (Status); + + if (MemConfigNoCrc != NULL) { + MemConfigNoCrc->PlatformMemorySize = PcdGet32 (PcdPeiMinMemorySize); + + // + // Only if SpdAddressTables are all zero we need to pass hard-coded SPD data buffer. + // Otherwise FSP will retrieve SPD from DIMM basing on SpdAddressTables policy. + // + if (*((UINT32 *) (UINTN) SpdAddressTable) == 0) { + DEBUG((DEBUG_INFO, "Override MemorySpdPtr...\n")); + CopyMem((VOID *) MemConfigNoCrc->SpdData->SpdData[0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize)); + CopyMem((VOID *) MemConfigNoCrc->SpdData->SpdData[1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize)); + } + + DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n")); + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap); + if (Buffer) { + CopyMem ((VOID *) MemConfigNoCrc->DqByteMap->DqByteMap[0], Buffer, 12); + CopyMem ((VOID *) MemConfigNoCrc->DqByteMap->DqByteMap[1], (UINT8*) Buffer + 12, 12); + } + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram); + if (Buffer) { + CopyMem ((VOID *) MemConfigNoCrc->DqsMap->DqsMapCpu2Dram[0], Buffer, 8); + CopyMem ((VOID *) MemConfigNoCrc->DqsMap->DqsMapCpu2Dram[1], (UINT8*) Buffer + 8, 8); + } + + DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp Target Settings...\n")); + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor); + if (Buffer) { + CopyMem ((VOID *) &(MemConfigNoCrc->RcompData->RcompResistor[0]), Buffer, 6); + } + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget); + if (Buffer) { + CopyMem ((VOID *) &(MemConfigNoCrc->RcompData->RcompTarget[0]), Buffer, 10); + } + } + // + // Update PCD policy + // + InstallPlatformHsioPtssTable (Policy); + } + + return Policy; +} + +/** + Update PostMem phase silicon policy per board. + + @param[in] Policy - Policy PPI pointer. + + @retval Policy - Policy PPI pointer. + +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePostMem ( + IN VOID *Policy + ) +{ + EFI_STATUS Status; + VOID *Buffer; + VOID *MemBuffer; + UINT32 Size; + GRAPHICS_PEI_CONFIG *GtConfig; + CPU_CONFIG *CpuConfig; + + DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n")); + + GtConfig = NULL; + Status = GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (VOID *)&GtConfig); + ASSERT_EFI_ERROR (Status); + + if (GtConfig != NULL) { + // + // Always enable PEI graphics initialization. + // + GtConfig->PeiGraphicsPeimInit = 1; + Size = 0; + Buffer = NULL; + PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size); + if (Buffer == NULL) { + DEBUG((DEBUG_WARN, "Could not locate VBT\n")); + } else { + MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); + if ((MemBuffer != NULL) && (Buffer != NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + GtConfig->GraphicsConfigPtr = MemBuffer; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n")); + GtConfig->GraphicsConfigPtr = 0; + } + } + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", GtConfig->GraphicsConfigPtr)); + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size)); + Size = 0; + Buffer = NULL; + PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, &Size); + if (Buffer == NULL) { + DEBUG((DEBUG_WARN, "Could not locate Logo\n")); + } else { + MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); + if ((MemBuffer != NULL) && (Buffer != NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + GtConfig->LogoPtr = MemBuffer; + GtConfig->LogoSize = Size; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n")); + GtConfig->LogoPtr = 0; + GtConfig->LogoSize = 0; + } + } + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", GtConfig->LogoPtr)); + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", GtConfig->LogoSize)); + } + + CpuConfig = NULL; + Status = GetConfigBlock ((VOID *) Policy, &gCpuConfigGuid, (VOID *)&CpuConfig); + ASSERT_EFI_ERROR (Status); + + if (CpuConfig != NULL) { + CpuConfig->MicrocodePatchAddress = PlatformCpuLocateMicrocodePatch (); + } + return Policy; +} + +/** + Update late phase silicon policy per board. + + @param[in] Policy - Policy PPI pointer. + + @retval Policy - Policy PPI pointer. + +**/ +VOID * +EFIAPI +SiliconPolicyUpdateLate ( + IN VOID *Policy + ) +{ + return Policy; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf new file mode 100644 index 00000000..5c2da68b --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -0,0 +1,92 @@ +### @file +# Component information file for silicon policy update library +# +# Copyright (c) 2019 - 2021 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiSiliconPolicyUpdateLib + FILE_GUID = 14F5D83D-76A5-4241-BEC5-987E70E233D5 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconPolicyUpdateLib + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + ConfigBlockLib + BaseMemoryLib + MemoryAllocationLib + PeiLib + CpuPlatformLib + PchPcieRpLib + PchInfoLib + MmPciLib + IoLib + PchHsioLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + UefiCpuPkg/UefiCpuPkg.dec + KabylakeSiliconPkg/SiPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Sources] + PeiSiliconPolicyUpdateLib.c + +[Guids] + gMemoryConfigNoCrcGuid + gTianoLogoGuid ## CONSUMES + gGraphicsPeiConfigGuid ## CONSUMES + gCpuConfigGuid ## CONSUMES + gHsioPciePreMemConfigGuid ## CONSUMES + gHsioSataPreMemConfigGuid ## CONSUMES + gSaMiscPeiPreMemConfigGuid ## CONSUMES + gFspNonVolatileStorageHobGuid ## CONSUMES + +[Pcd] + gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize + gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase + gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize + gSiPkgTokenSpaceGuid.PcdMchBaseAddress + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress + gSiPkgTokenSpaceGuid.PcdTsegSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize + + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size + + # SPD Address Table + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_board.py b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_board.py new file mode 100644 index 00000000..41668120 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_board.py @@ -0,0 +1,68 @@ +# @ build_board.py +# This is a sample code provides Optional dynamic imports +# of build functions to the BuildBios.py script +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +""" +This module serves as a sample implementation of the build extension +scripts +""" + + +def pre_build_ex(config, functions): + """Additional Pre BIOS build function + + :param config: The environment variables to be used in the build process + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: nothing + """ + print("pre_build_ex") + return None + + +def build_ex(config, functions): + """Additional BIOS build function + + :param config: The environment variables to be used in the build process + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("build_ex") + return None + + +def post_build_ex(config, functions): + """Additional Post BIOS build function + + :param config: The environment variables to be used in the post + build process + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("post_build_ex") + return None + + +def clean_ex(config, functions): + """Additional clean function + + :param config: The environment variables to be used in the build process + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("clean_ex") + return None diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.cfg b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.cfg new file mode 100644 index 00000000..f6ae4b34 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.cfg @@ -0,0 +1,36 @@ +# @ build_config.cfg +# This is the KabylakeRvp3 board specific build settings +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# + + +[CONFIG] +WORKSPACE_PLATFORM_BIN = +EDK_SETUP_OPTION = +openssl_path = +PLATFORM_BOARD_PACKAGE = KabylakeOpenBoardPkg +PROJECT = KabylakeOpenBoardPkg/KabylakeRvp3 +BOARD = KabylakeRvp3 +FLASH_MAP_FDF = KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/FlashMapInclude.fdf +PROJECT_DSC = KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +BOARD_PKG_PCD_DSC = KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc +ADDITIONAL_SCRIPTS = KabylakeOpenBoardPkg/KabylakeRvp3/build_board.py +PrepRELEASE = DEBUG +SILENT_MODE = FALSE +EXT_CONFIG_CLEAR = +CapsuleBuild = FALSE +EXT_BUILD_FLAGS = +CAPSULE_BUILD = 0 +TARGET = DEBUG +TARGET_SHORT = D +PERFORMANCE_BUILD = FALSE +FSP_WRAPPER_BUILD = TRUE +FSP_BIN_PKG = AmberLakeFspBinPkg +FSP_BIN_PKG_FOR_API_MODE = KabylakeFspBinPkg +FSP_PKG_NAME = AmberLakeFspPkg +FSP_BINARY_BUILD = FALSE +FSP_TEST_RELEASE = FALSE +SECURE_BOOT_ENABLE = FALSE +BIOS_INFO_GUID = C83BCE0E-6F16-4D3C-8D9F-4D6F5A032929