Some bridges were missing the operations and were not marked
as hidden. Fix it for consistency.
Also the intenal GPP bridges are PCIe bridges and should use PCIe
bridge scann method. Otherwise, the devices may end up with mismatched
MaxPayload capability. For openSIL, which does not program PCIe
capabilities yet on the bridges and devices behind them, let coreboot
do it.
For external GPP bridges assign hotplug ops if hotplug enabled and port
is capable of hotplugging.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
If holes are not continuous, we may end up loosing some RAM, e.g.
if Remap1Tb entry is present in the list of holes.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Add missing memory hole definitions to have human readable information
what given hole represents.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
We do not cover enough of memory with page tables to reach higher
memory than 1TB. When there is more memory than 1TB in the system,
RMP is unreachable, resulting in page faults.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Increase MAX_ACPI_TABLE_SIZE_KB to fit all ACPI tables when a higher
core count CPU is used. The SSDT gets linearly bigger with higher core
count and the default fixed allocation for ACPI tables is not enough.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
On server platforms the maximum number of logical processors
is greater than default 64 defined in the DSC file. Use MAX_CPUs
Kconfig value to pass the epxected maximum processor count and
use the 100ms increments for each processor for the AP init timeout
as coreboot does for its own MP init.
TEST=Boot Gigbyte MZ33-AR1 with 128 core processor
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The bootblock may be placed in the CBFS as in the old days. The
Makefile.mk that prepares parameters for amdfwtool must simply
pass the right parameters about BIOS_BIN to be uncompressed and
where to look for the bootblock in flash. On AMD platforms it can
be the last block of COREBOOT region of C_ENV_BOOTBLOCK_SIZE.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
It is not required to build multilevel directories to make the platform
boot. If multilevel is disabled, the blob footprint is reduced due
to inclusion of a single copy of given blob, at the cost of PSP
recovery, which we do not support anyways.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Include new PMU firmware file in the PSP BIOS directories that
are available on Turin SOC.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Avoid adding APOB NV or BIOS NV is size is not specified. Otherwise,
the PSP BIOS directory may end up with BIOS NV of base 0 and size 0.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Add settings to specify the polarity of PCIe signals. Some board designs
invert RX or TX lines on the connectors.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This reverts commit 5e801cbb7b.
The repository osfv-scripts is public again, no need to use secrets.
Upstream-Status: Inappropriate [reverts non-upstream commit]
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Select options to utilize common AMD block for TSC. The coreboot
timestamp table needs the tick frequency to be provided by TSC.
Currently AMD PI CPU uses LAPIC as the timer, which does not provide
the TSC tick frequency. It is also required to properly measure
firmware performance in EDK2.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Using iPXE master revision may lead to unreproducible builds.
Make sure the iPXE is buitl from a fixed revision pointed by
IPXE_STABLE option.
Upstream-Status: Inappropriate [Dasharo downstream]
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The GH runners have UID 1001, while user coreboot in SDK has id 1000.
This creates a mismatch of IDs and causes permission problems when
mounting coreboot git repository under /home/coreboot/coreboot in the
container, because the /home/coreboot is a HOME directory of different
user.
To fix the problem, move the mountpoint to a "neutral" place, where
permissions should not be a an issue. The /build directory is chosen
so that it does not collide with any HOME directory or system directory.
Upstream-Status: Inappropriate [Dasharo CI]
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
For multijob builds to produce reproducible results, the SBOM rules
have to ensure that the respective git directory of component exists.
Otherwise sometimes the SBOM may contain component git version,
sometimes not during fresh builds. After a rebuild, when the git
directories were present, then the git versions appeared in SBOM,
causing the build to be different and not reproducible, despite
the source was not changed, only make was issued the second time.
Add proper rules to clone repositories or checkout necessary
submodules.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Likely due to AMD PSP initializing the memory or the active SME, the
memory contents are not retain after reset, so the Capsule Update after
reset will not work if Capsule is stored in RAM before reset.
Use Capsule on Disk only.
Upstream-Status: Inappropriate [custom config]
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Add option to indicate that Capsules do not survive resets. Platforms
that do not retain memory contents after reset would lose capsule that
has a CAPSULE_FLAGS_PERSIST_ACROSS_RESET flag set. The only way to
support such platforms is to use Capsule on Disk solely without the flag
set and with Capsule after reset disabled in the payload.
TEST=Perform Capsule on Disk Update on Gigabyte MZ33-AR1
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Set the EFI System Table fields with the PCDs containing firmware
information, such as vendor, release date, version and revision.
Do it so the information is the same in coreboot, EDK2 and SMBIOS.
Upstream-Status: Inappropriate [Dasharo downstream]
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Michał Żygowski