cpu/amd/pi: Use AMD common block for TSC

Select options to utilize common AMD block for TSC. The coreboot
timestamp table needs the tick frequency to be provided by TSC.
Currently AMD PI CPU uses LAPIC as the timer, which does not provide
the TSC tick frequency. It is also required to properly measure
firmware performance in EDK2.

Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>

src/cpu/amd/pi/Kconfig

@@ -6,15 +6,14 @@ config CPU_AMD_PI
 	default n
 	select ARCH_X86
 	select DRIVERS_AMD_PI
-	select TSC_SYNC_LFENCE
-	select UDELAY_LAPIC
-	select LAPIC_MONOTONIC_TIMER
 	select SPI_FLASH if HAVE_ACPI_RESUME
 	select SMM_TSEG
 	select PARALLEL_MP_AP_WORK
 	select SOC_AMD_COMMON_BLOCK_SMM
 	select SOC_AMD_COMMON_BLOCK_SMI
 	select SOC_AMD_COMMON_BLOCK_ACPI
+	select SOC_AMD_COMMON_BLOCK_TSC
+	select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H
 	select SSE2
 
 if CPU_AMD_PI

src/cpu/amd/pi/Makefile.mk

@@ -6,3 +6,5 @@ romstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c
 postcar-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c
 ramstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c
 ramstage-y += ../../../soc/amd/common/block/cpu/smm/smm_relocate.c
+
+CPPFLAGS_common += -I$(src)/cpu/amd/pi/include

src/cpu/amd/pi/include/soc/msr.h

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_PI_MSR_H
+#define AMD_PI_MSR_H
+
+/* MSRC001_00[6B:64] P-state [7:0] bit definitions */
+union pstate_msr {
+	struct {
+		uint64_t cpu_fid_0_5	:  6; /* [ 0.. 5] */
+		uint64_t cpu_dfs_id	:  3; /* [ 6.. 8] */
+		uint64_t cpu_vid_0_7	:  8; /* [ 9..16] */
+		uint64_t		:  5; /* [17..21] */
+		uint64_t nb_pstate	:  1; /* [22..22] */
+		uint64_t		:  9; /* [23..31] */
+		uint64_t idd_value	:  8; /* [32..39] */
+		uint64_t idd_div	:  2; /* [40..41] */
+		uint64_t		: 21; /* [42..62] */
+		uint64_t pstate_en	:  1; /* [63..63] */
+	};
+	uint64_t raw;
+};
+
+#endif /* AMD_PI_MSR_H */