Commit Graph

1280618 Commits

Author SHA1 Message Date
Łukasz Sobala
f07e92459e Fix amdgpu failure to compile (#387)
* fix amdgpu failure to compile

* fix indentation

* fix indentation

---------

Co-authored-by: Jianfeng Liu <liujianfeng1994@gmail.com>
2025-09-17 08:59:42 +08:00
Muhammed Efe Cetin
2590770a3d arm64: dts: rockchip: add support for BananaPi M5 Pro 2025-09-15 13:59:50 +03:00
Jianfeng Liu
41c42281a4 arch: arm: dts: add armsom forge1 support 2025-09-12 23:53:09 +08:00
Jianfeng Liu
18a5e3b094 arm64: dts: rockchip: add support for Radxa CM4 IO Board 2025-09-11 15:20:40 +08:00
SuperKali
b038d04435 dts: nanopi-r76s: fix CPUFreq issue and split DTS for upcoming M5 support (#396) 2025-09-09 08:44:29 +02:00
SuperKali
e616b735ce dts: arm64: nanopi r76s fixing bluetooth issue causing reset of entire module (#395) 2025-09-07 22:38:15 +02:00
SuperKali
af2a5e7041 arm64: dts: rockchip: add support for NanoPi R76S (#394)
Introduce initial device tree support for the FriendlyELEC NanoPi R76S
board, based on the Rockchip RK3576 SoC.
2025-09-07 18:50:19 +02:00
jack@armsom.org
9bf5251735 arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts: leds fix 2025-09-02 09:24:56 +02:00
Mecid
a7bb236096 Add Board: Radxa Rock-4D (#391)
* Add Board: Radxa Rock-4D

* Add Rock-4D SPI variant

* Fix Rock4D Makefile typo

* RK3576: Rock-4D delete bootargs in devicetree
2025-09-01 19:12:42 +02:00
Igor
c5fe17efa3 Update Armbian logo in README 2025-08-28 05:58:19 +02:00
Boris Brezillon
c35fb8e694 drm/panthor: Fix the panthor_gpu_coherency_init() error path
The panthor_gpu_coherency_init() call has been moved around, but the
error path hasn't been adjusted accordingly. Make sure we undo what
has been done before this call in case of failure.

Fixes: 7d5a3b22f5b5 ("drm/panthor: Call panthor_gpu_coherency_init() after PM resume()")
Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
Closes: https://lore.kernel.org/dri-devel/4da470aa-4f84-460e-aff8-dabc8cc4da15@stanley.mountain/T/#t
Reviewed-by: Steven Price <steven.price@arm.com>
Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
Link: https://lore.kernel.org/r/20250414130120.581274-1-boris.brezillon@collabora.com
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-08-28 05:46:56 +02:00
Boris Brezillon
2225ea242c drm/panthor: Don't update MMU_INT_MASK in panthor_mmu_irq_handler()
Interrupts are automatically unmasked in
panthor_mmu_irq_threaded_handler() when the handler returns. Unmasking
prematurely might generate spurious interrupts if the IRQ line is
shared.

Changes in v2:
- New patch

Changes in v3:
- Add R-bs

Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Link: https://lore.kernel.org/r/20250404080933.2912674-6-boris.brezillon@collabora.com
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-08-28 05:46:56 +02:00
Boris Brezillon
00bcc23a03 drm/panthor: Let IRQ handlers clear the interrupts themselves
MMU handler needs to be in control of the job interrupt clears because
clearing the interrupt also unblocks the writer/reader that triggered
the fault, and we don't want it to be unblocked until we've had a chance
to process the IRQ.

Since clearing the clearing is just one line, let's make it explicit
instead of doing it in the generic code path.

Note that this commit changes the existing behavior in that the MMU
COMPLETED irqs are no longer cleared, which is fine because they are
masked, so we're not risking an interrupt flood.

Changes in v3:
- Mention the fact we no longer clear MMU COMPLETED irqs
- Add Liviu's R-b

Changes in v2:
- Move the MMU_INT_CLEAR around

Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Link: https://lore.kernel.org/r/20250404080933.2912674-5-boris.brezillon@collabora.com
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-08-28 05:46:56 +02:00
Boris Brezillon
f765259e94 drm/panthor: Update panthor_mmu::irq::mask when needed
When we clear the faulty bits in the AS mask, we also need to update
the panthor_mmu::irq::mask field otherwise our IRQ handler won't get
called again until the GPU is reset.

Changes in v2:
- Add Liviu's R-b

Changes in v3:
- Add Steve's R-b

Fixes: 647810ec2476 ("drm/panthor: Add the MMU/VM logical block")
Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Link: https://lore.kernel.org/r/20250404080933.2912674-4-boris.brezillon@collabora.com
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-08-28 05:46:56 +02:00
Boris Brezillon
4b30325e8b drm/panthor: Call panthor_gpu_coherency_init() after PM resume()
When the device is coherent, panthor_gpu_coherency_init() will read
GPU_COHERENCY_FEATURES to make sure the GPU supports the ACE-Lite
coherency protocol, which will fail if the clocks/power-domains are
not enabled when the read is done. Move the
panthor_gpu_coherency_init() call after the device has been resumed
to prevent that.

Changes in v2:
- Add Liviu's R-b

Changes in v3:
- Add Steve's R-b

Fixes: dd7db8d911a1 ("drm/panthor: Explicitly set the coherency mode")
Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Link: https://lore.kernel.org/r/20250404080933.2912674-3-boris.brezillon@collabora.com
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-08-28 05:46:56 +02:00
Boris Brezillon
76b0019a6b drm/panthor: Fix GPU_COHERENCY_ACE[_LITE] definitions
GPU_COHERENCY_ACE and GPU_COHERENCY_ACE_LITE definitions have been
swapped.

Changes in v2:
- New patch

Changes in v3:
- Add Steve's R-b

Reported-by: Liviu Dudau <liviu.dudau@arm.com>
Fixes: 546b366600ef ("drm/panthor: Add GPU register definitions")
Reviewed-by: Steven Price <steven.price@arm.com>
Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
Link: https://lore.kernel.org/r/20250404080933.2912674-2-boris.brezillon@collabora.com
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-08-28 05:46:56 +02:00
Dmitry Osipenko
34b67fc3e9 drm/gem: Change locked/unlocked postfix of drm_gem_v/unmap() function names
Make drm/gem API function names consistent by having locked function
use the _locked postfix in the name, while the unlocked variants don't
use the _unlocked postfix. Rename drm_gem_v/unmap() function names to
make them consistent with the rest of the API functions.

Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Thomas Zimmermann <tzimmermann@suse.d>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250322212608.40511-2-dmitry.osipenko@collabora.com
2025-08-28 05:46:56 +02:00
SuperKali
f343dbf754 ARM: dts: nanopc-t6: fix RT5616 headphone jack DAPM pin mismatch (#388)
The simple-audio-card hp-pin-name was referencing "Headphone Jack"
but the actual widget is defined as "Headphones", causing ALSA
to report "ASoC: DAPM unknown pin Headphone Jack" error.
2025-08-26 17:21:04 +02:00
Rafay Ahmed
d94588328f Enable lte_em05 to be built as a module (#384) 2025-08-15 20:05:01 +02:00
Rafay Ahmed
670f4c34f9 Add LTE EM05 driver 2025-08-13 11:55:09 +08:00
Mecid
0e6860fe85 Sync Rock5B, 5B-Plus, 5T DT's with Radxa (#381)
* Sync Rock5B, 5B-Plus, 5T DT's

From Radxa's Kernel fork: https://github.com/radxa/kernel/blob/linux-6.1-stan-rkr5.1/arch/arm64/boot/dts/rockchip/

* Keep Armbian's soc_thermal for fan speed on Rock5B
2025-08-12 19:22:03 +02:00
Alban Browaeys
fcd6317671 Fix PCI SATA link training instability on rock-5-itx
Based on upstream initial dts definition.

Signed-off-by: Alban Browaeys <alban.browaeys@gmail.com>
2025-08-11 18:15:18 +02:00
Niklas Cassel
46bbde3971 UPSTREAM: phy: rockchip-snps-pcie3: add support for rockchip,rx-common-refclk-mode
>From the RK3588 Technical Reference Manual, Part1,
section 6.19 PCIe3PHY_GRF Register Description:
"rxX_cmn_refclk_mode"
RX common reference clock mode for lane X. This mode should be enabled
only when the far-end and near-end devices are running with a common
reference clock.

The hardware reset value for this field is 0x1 (enabled).
Note that this register field is only available on RK3588, not on RK3568.

The link training either fails or is highly unstable (link state will jump
continuously between L0 and recovery) when this mode is enabled while
using an endpoint running in Separate Reference Clock with No SSC (SRNS)
mode or Separate Reference Clock with SSC (SRIS) mode.
(Which is usually the case when using a real SoC as endpoint, e.g. the
RK3588 PCIe controller can run in both Root Complex and Endpoint mode.)

Add support for the device tree property rockchip,rx-common-refclk-mode,
such that the PCIe PHY can be used in configurations where the Root
Complex and Endpoint are not using a common reference clock.

Signed-off-by: Niklas Cassel <cassel@kernel.org>
Link: https://lore.kernel.org/r/20240412125818.17052-3-cassel@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Alban Browaeys <alban.browaeys@gmail.com>
2025-08-11 18:15:18 +02:00
Jonas Karlman
c8af2ee277 RFC: drm/panthor: Do not set clk rate when device is suspended
On Rockchip RK3588 trying to change the SCMI_CLK_GPU rate when the GPU
device is PM runtime suspended may cause a kernel panic:

  $ echo 1000000000 > /sys/class/devfreq/fb000000.gpu/min_freq

  SError Interrupt on CPU4, code 0x00000000be000411 -- SError
  CPU: 4 UID: 0 PID: 241 Comm: sh Not tainted 6.15.0-rc3 #1 VOLUNTARY
  Hardware name: Radxa ROCK 5B (DT)
  pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
  pc : smc_send_message+0x140/0x148
  lr : smc_send_message+0xd8/0x148
  sp : ffff8000827138c0
  x29: ffff8000827138c0 x28: ffff000008764000 x27: 0000000000000000
  x26: 0000000000000000 x25: 00000000ffffffff x24: ffff800082713b28
  x23: ffff00000696b010 x22: ffff000003db4da0 x21: ffff000003fdae80
  x20: ffff0000053f22c0 x19: ffff000003db4d80 x18: 0000000000000000
  x17: 0000000000000000 x16: 0000000000000000 x15: 00000000245df550
  x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000
  x11: 0000000000000040 x10: ffff000003fde138 x9 : ffff000003fde130
  x8 : ffff000005e5c948 x7 : 0000000000000000 x6 : 0000000000000000
  x5 : 0000000000000000 x4 : 0000000000000000 x3 : 0000000000000000
  x2 : 0000000000000000 x1 : 0000000000000000 x0 : 0000000000000000
  Kernel panic - not syncing: Asynchronous SError Interrupt
  CPU: 4 UID: 0 PID: 241 Comm: sh Not tainted 6.15.0-rc3 #1 VOLUNTARY
  Hardware name: Radxa ROCK 5B (DT)
  Call trace:
   show_stack+0x28/0x78 (C)
   dump_stack_lvl+0x58/0x74
   dump_stack+0x14/0x1c
   panic+0x14c/0x328
   add_taint+0x0/0xc0
   arm64_serror_panic+0x60/0x6c
   do_serror+0x24/0x60
   el1h_64_error_handler+0x2c/0x40
   el1h_64_error+0x6c/0x70
   smc_send_message+0x140/0x148 (P)
   do_xfer+0xb0/0x1f8
   scmi_clock_rate_set+0xc0/0x220
   scmi_clk_set_rate+0x24/0x38
   clk_change_rate+0x164/0x288
   clk_core_set_rate_nolock+0x1dc/0x314
   clk_set_rate+0x34/0x144
   _opp_config_clk_single+0x2c/0x90
   _set_opp+0x104/0x564
   dev_pm_opp_set_rate+0x110/0x260
   panthor_devfreq_target+0x38/0x60 [panthor]
   devfreq_set_target+0x84/0x180
   devfreq_update_target+0xb4/0xcc
   update_devfreq+0x10/0x18
   set_freq_store+0x6c/0xb4
   dev_attr_store+0x14/0x24
   sysfs_kf_write+0x54/0x60
   kernfs_fop_write_iter+0x118/0x1e0
   vfs_write+0x224/0x390
   ksys_write+0x68/0x100
   __arm64_sys_write+0x18/0x20
   invoke_syscall+0x44/0x100
   el0_svc_common.constprop.0+0x3c/0xe0
   do_el0_svc+0x18/0x20
   el0_svc+0x2c/0xc0
   el0t_64_sync_handler+0x104/0x130
   el0t_64_sync+0x170/0x174
  SMP: stopping secondary CPUs
  Kernel Offset: disabled
  CPU features: 0x0e00,000000e0,01202650,8201700b
  Memory Limit: 3838 MB
  ---[ end Kernel panic - not syncing: Asynchronous SError Interrupt ]---

This typically happen when CLK_GPU is disabled or when PD_GPU is down.

Add a config_clks ops that will not set core clk rate when the device is
PM runtime suspended.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2025-08-11 18:14:50 +02:00
Jonas Karlman
bd3e32bbfb RFC: arm64: dts: rockchip: rk3588: Use scmi gpu clk as main GPU clock
CLK_GPU is the main clock for the GPU on RK3588, it's typical source
pll can be one of gpll, cpll, aupll, npll or spll. For higher clock
rates it is also possible to use the gpu pvtpll as pll source.

The logic to switch between a normal pll and the pvtpll depending on
rate is handled in TF-A firmware, and exposed to Linux as a scmi clock.
TF-A will typically change to use normal pll for rates up to 200 MHz and
use pvtpll for 300 MHz or more.

Change to use the SCMI_CLK_GPU as the main GPU clock and add the normal
CLK_GPU as a bus clk to model this in a similar way as on RK356x.

Prior to this change the GPU clk rate was max 850 MHz:

  $ glmark2-es2-gbm -b terrain
  [...]
    GL_VENDOR:      Mesa
    GL_RENDERER:    Mali-G610 (Panfrost)
    GL_VERSION:     OpenGL ES 3.1 Mesa 25.0.4
    Surface Config: buf=32 r=8 g=8 b=8 a=8 depth=24 stencil=0 samples=0
    Surface Size:   800x600 fullscreen
  [...]
  [terrain] <default>: FPS: 139 FrameTime: 7.231 ms

After this the GPU clk rate can use the 1 GHz rate with PVTPLL:

  [terrain] <default>: FPS: 152 FrameTime: 6.579 ms

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2025-08-11 18:14:50 +02:00