Merge commit 'abd61db9d69e17126436259705e58fd6cc74a8f5'

* commit 'abd61db9d69e17126436259705e58fd6cc74a8f5': edac: rockchip: add edac driver arm64: dts: rockchip: rk3562: Add arm_pmu label media: rockchip: vicap: fixes rv1126/rk3568 bt1120/bt656 buffer timestamp ARM: configs: rockchip: Update rv1106-tb-nofastae.config media: rockchip: isp: support unite mode for isp32 PCI: rockchip: dw: Save and restore PCIE_CLIENT_INTR_MASK_LEGACY in PM ARM: dts: rockchip: rv1106-thunder-boot: set rkvenc clock to 410000000 rpmsg: rockchip_test: add new device id for mcu arm64: dts: rockchip: rk3562-amp: change rpmsg shared memory address arm64: dts: rockchip: rk3562-amp: set mailbox txpoll to 1 ms ARM: dts: rockchip: add rv1106g-evb2-v12-nofastae-spi-nor ARM: dts: rockchip: add rv1106g-evb2-v12-nofastae-emmc ARM: dts: rockchip: Add rv1106 nofastae dtsi ARM: configs: rockchip: Add rv1106-tb-nofastae.config ASoC: codecs: Add tda7803 amplifier driver support clk: rockchip: rk3568: Add protect clocks drm/bridge: dw-hdmi-qp: Don't read edid again if edid is exist Change-Id: I2db1ef5fd1c89b634bf2500e25f479568cf1c60e
2026-01-06 11:08:10 -08:00 · 2023-09-11 10:39:48 +08:00
parent 7bbab4044b abd61db9d6
commit dead21504e
47 changed files with 3511 additions and 1706 deletions
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1148,6 +1148,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rv1106g-evb2-v10.dtb \
 	rv1106g-evb2-v10-dual-camera.dtb \
 	rv1106g-evb2-v11-emmc.dtb \
+	rv1106g-evb2-v12-nofastae-emmc.dtb \
+	rv1106g-evb2-v12-nofastae-spi-nor.dtb \
 	rv1106g-evb2-v12-wakeup.dtb \
 	rv1106g-smart-door-lock-rmsl-v10.dtb \
 	rv1106g-smart-door-lock-rmsl-v12.dtb \
--- a/arch/arm/boot/dts/rv1106-tb-nofastae-emmc.dtsi
+++ b/arch/arm/boot/dts/rv1106-tb-nofastae-emmc.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+#include "rv1106-tb-nofastae.dtsi"
+
+/ {
+	reserved-memory {
+		mmc_ecsd: mmc@3f000 {
+			reg = <0x3f000 0x00001000>;
+		};
+
+		mmc_idmac: mmc@100000 {
+			reg = <0x00100000 0x00100000>;
+		};
+	};
+
+	thunder_boot_mmc: thunder-boot-mmc {
+		compatible = "rockchip,thunder-boot-mmc";
+		reg = <0xffa90000 0x4000>;
+		memory-region-src = <&ramdisk_c>;
+		memory-region-dst = <&ramdisk_r>;
+		memory-region-idmac = <&mmc_idmac>;
+	};
+};
+
+&emmc {
+	memory-region-ecsd = <&mmc_ecsd>;
+	post-power-on-delay-ms = <0>;
+};
--- a/arch/arm/boot/dts/rv1106-tb-nofastae-spi-nor.dtsi
+++ b/arch/arm/boot/dts/rv1106-tb-nofastae-spi-nor.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+#include "rv1106-tb-nofastae.dtsi"
+
+/ {
+	thunder_boot_spi_nor: thunder-boot-spi-nor {
+		compatible = "rockchip,thunder-boot-sfc";
+		reg = <0xffac0000 0x4000>;
+		memory-region-src = <&ramdisk_c>;
+		memory-region-dst = <&ramdisk_r>;
+	};
+};
+
+&emmc {
+	status = "disabled";
+};
--- a/arch/arm/boot/dts/rv1106-tb-nofastae.dtsi
+++ b/arch/arm/boot/dts/rv1106-tb-nofastae.dtsi
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+/ {
+	memory: memory {
+		device_type = "memory";
+		reg = <0x00000000 0x08000000>;
+	};
+
+	ramdisk: ramdisk {
+		compatible = "rockchip,ramdisk";
+		memory-region = <&ramdisk_r>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		ramdisk_r: ramdisk_r {
+			reg = <0x800000 (10 * 0x00100000)>;
+		};
+
+		ramdisk_c: ramdisk_c {
+			reg = <0x1200000 (5 * 0x00100000)>;
+		};
+	};
+};
+
+&hw_decompress {
+	status = "okay";
+	memory-region = <&ramdisk_c>;
+};
--- a/arch/arm/boot/dts/rv1106-thunder-boot.dtsi
+++ b/arch/arm/boot/dts/rv1106-thunder-boot.dtsi
@@ -98,3 +98,8 @@
 &rkisp_vir0 {
 	memory-region-thunderboot = <&rkisp_thunderboot>;
 };
+
+&rkvenc {
+	assigned-clocks = <&cru CLK_CORE_VEPU>;
+	assigned-clock-rates = <410000000>;
+};
--- a/arch/arm/boot/dts/rv1106g-evb2-v12-nofastae-emmc.dts
+++ b/arch/arm/boot/dts/rv1106g-evb2-v12-nofastae-emmc.dts
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "rv1106.dtsi"
+#include "rv1106-evb-v10.dtsi"
+#include "rv1106-evb-cam.dtsi"
+#include "rv1106-tb-nofastae-emmc.dtsi"
+
+/ {
+	model = "Rockchip RV1106G EVB2 V12 Board";
+	compatible = "rockchip,rv1106g-evb2-v12", "rockchip,rv1106";
+
+	chosen {
+		bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip";
+	};
+
+	vcc_1v8: vcc-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	vcc_3v3: vcc-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vcc3v3_sd: vcc3v3-sd {
+		compatible = "regulator-fixed";
+		gpio = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
+		regulator-name = "vcc3v3_sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc_pwren>;
+	};
+
+	wireless_wlan: wireless-wlan {
+		compatible = "wlan-platdata";
+		WIFI,host_wake_irq = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+};
+
+&fiq_debugger {
+	rockchip,baudrate = <1500000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2m1_xfer>;
+};
+
+&pinctrl {
+	sdmmc {
+		/omit-if-no-ref/
+		sdmmc_pwren: sdmmc-pwren {
+			rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pwm10 {
+	status = "okay";
+};
+
+&pwm11 {
+	status = "okay";
+};
+
+&ramdisk_r {
+	reg = <0x800000 (20 * 0x00100000)>;
+};
+
+&ramdisk_c {
+	reg = <0x1C00000 (10 * 0x00100000)>;
+};
+
+&sdio {
+	max-frequency = <50000000>;
+	bus-width = <1>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	non-removable;
+	rockchip,default-sample-phase = <90>;
+	no-sd;
+	no-mmc;
+	supports-sdio;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus4>;
+	status = "okay";
+};
+
+&sdmmc {
+	max-frequency = <200000000>;
+	no-sdio;
+	no-mmc;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "normal", "idle";
+	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
+	pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det>;
+	vmmc-supply = <&vcc3v3_sd>;
+	status = "okay";
+};
+
+&sfc {
+	assigned-clocks = <&cru SCLK_SFC>;
+	assigned-clock-rates = <125000000>;
+	status = "disabled";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <125000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+&usbdrd_dwc3 {
+	dr_mode = "peripheral";
+};
--- a/arch/arm/boot/dts/rv1106g-evb2-v12-nofastae-spi-nor.dts
+++ b/arch/arm/boot/dts/rv1106g-evb2-v12-nofastae-spi-nor.dts
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "rv1106.dtsi"
+#include "rv1106-evb-v10.dtsi"
+#include "rv1106-evb-cam.dtsi"
+#include "rv1106-tb-nofastae-spi-nor.dtsi"
+
+/ {
+	model = "Rockchip RV1106G EVB2 V12 Board";
+	compatible = "rockchip,rv1106g-evb2-v12", "rockchip,rv1106";
+
+	chosen {
+		bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip";
+	};
+
+	vcc_1v8: vcc-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	vcc_3v3: vcc-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vcc3v3_sd: vcc3v3-sd {
+		compatible = "regulator-fixed";
+		gpio = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
+		regulator-name = "vcc3v3_sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc_pwren>;
+	};
+
+	wireless_wlan: wireless-wlan {
+		compatible = "wlan-platdata";
+		WIFI,host_wake_irq = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+};
+
+&fiq_debugger {
+	rockchip,baudrate = <1500000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2m1_xfer>;
+};
+
+&pinctrl {
+	sdmmc {
+		/omit-if-no-ref/
+		sdmmc_pwren: sdmmc-pwren {
+			rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pwm10 {
+	status = "okay";
+};
+
+&pwm11 {
+	status = "okay";
+};
+
+&ramdisk_r {
+	reg = <0x800000 (10 * 0x00100000)>;
+};
+
+&ramdisk_c {
+	reg = <0x1200000 (5 * 0x00100000)>;
+};
+
+&sdio {
+	max-frequency = <50000000>;
+	bus-width = <1>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	non-removable;
+	rockchip,default-sample-phase = <90>;
+	no-sd;
+	no-mmc;
+	supports-sdio;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus4>;
+	status = "okay";
+};
+
+&sdmmc {
+	max-frequency = <200000000>;
+	no-sdio;
+	no-mmc;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "normal", "idle";
+	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
+	pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det>;
+	vmmc-supply = <&vcc3v3_sd>;
+	status = "okay";
+};
+
+&sfc {
+	assigned-clocks = <&cru SCLK_SFC>;
+	assigned-clock-rates = <125000000>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <125000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+&usbdrd_dwc3 {
+	dr_mode = "peripheral";
+};
--- a/arch/arm/configs/rv1106-tb-nofastae.config
+++ b/arch/arm/configs/rv1106-tb-nofastae.config
@@ -0,0 +1,421 @@
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CRC16=m
+CONFIG_CRYPTO=y
+CONFIG_DAX=y
+CONFIG_EROFS_FS=y
+# CONFIG_ETHERNET is not set
+CONFIG_EXT4_FS=m
+CONFIG_FILE_LOCKING=y
+CONFIG_JFFS2_FS=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_XZ is not set
+CONFIG_LIBCRC32C=y
+CONFIG_MAILBOX=y
+# CONFIG_MDIO_DEVICE is not set
+CONFIG_MMC=y
+CONFIG_MSDOS_FS=m
+CONFIG_MSDOS_PARTITION=y
+CONFIG_MTD_BLOCK=m
+CONFIG_NLS_CODEPAGE_936=m
+# CONFIG_PHYLIB is not set
+CONFIG_PHY_ROCKCHIP_CSI2_DPHY=y
+CONFIG_PRINTK_TIME_FROM_ARM_ARCH_TIMER=y
+CONFIG_ROCKCHIP_DVBM=y
+CONFIG_ROCKCHIP_HW_DECOMPRESS=y
+CONFIG_ROCKCHIP_MULTI_RGA=y
+CONFIG_ROCKCHIP_RAMDISK=y
+CONFIG_ROCKCHIP_RGA_PROC_FS=y
+CONFIG_ROCKCHIP_THUNDER_BOOT=y
+CONFIG_ROCKCHIP_VENDOR_STORAGE=m
+# CONFIG_SLUB_SYSFS is not set
+CONFIG_SND_SIMPLE_CARD=m
+CONFIG_SND_SIMPLE_CARD_UTILS=m
+CONFIG_SND_SOC_ROCKCHIP=m
+CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
+CONFIG_SND_SOC_RV1106=m
+CONFIG_SPI=y
+CONFIG_VFAT_FS=m
+CONFIG_VIDEO_ROCKCHIP_CIF=y
+CONFIG_VIDEO_ROCKCHIP_ISP=y
+CONFIG_VIDEO_SC230AI=y
+CONFIG_VIDEO_SC301IOT=y
+CONFIG_VIDEO_SC3338=y
+# CONFIG_AD2S1200 is not set
+# CONFIG_AD2S1210 is not set
+# CONFIG_AD2S90 is not set
+# CONFIG_AD5360 is not set
+# CONFIG_AD5421 is not set
+# CONFIG_AD5449 is not set
+# CONFIG_AD5504 is not set
+# CONFIG_AD5592R is not set
+# CONFIG_AD5624R_SPI is not set
+# CONFIG_AD5686_SPI is not set
+# CONFIG_AD5755 is not set
+# CONFIG_AD5758 is not set
+# CONFIG_AD5761 is not set
+# CONFIG_AD5764 is not set
+# CONFIG_AD5770R is not set
+# CONFIG_AD5791 is not set
+# CONFIG_AD7124 is not set
+# CONFIG_AD7192 is not set
+# CONFIG_AD7266 is not set
+# CONFIG_AD7280 is not set
+# CONFIG_AD7292 is not set
+# CONFIG_AD7298 is not set
+# CONFIG_AD7303 is not set
+# CONFIG_AD7476 is not set
+# CONFIG_AD7606_IFACE_SPI is not set
+# CONFIG_AD7766 is not set
+# CONFIG_AD7768_1 is not set
+# CONFIG_AD7780 is not set
+# CONFIG_AD7791 is not set
+# CONFIG_AD7793 is not set
+# CONFIG_AD7816 is not set
+# CONFIG_AD7887 is not set
+# CONFIG_AD7923 is not set
+# CONFIG_AD7949 is not set
+# CONFIG_AD8366 is not set
+# CONFIG_AD8801 is not set
+# CONFIG_AD9523 is not set
+# CONFIG_AD9832 is not set
+# CONFIG_AD9834 is not set
+# CONFIG_ADF4350 is not set
+# CONFIG_ADF4371 is not set
+# CONFIG_ADIS16080 is not set
+# CONFIG_ADIS16130 is not set
+# CONFIG_ADIS16136 is not set
+# CONFIG_ADIS16201 is not set
+# CONFIG_ADIS16203 is not set
+# CONFIG_ADIS16209 is not set
+# CONFIG_ADIS16240 is not set
+# CONFIG_ADIS16260 is not set
+# CONFIG_ADIS16400 is not set
+# CONFIG_ADIS16460 is not set
+# CONFIG_ADIS16475 is not set
+# CONFIG_ADIS16480 is not set
+# CONFIG_ADXL345_SPI is not set
+# CONFIG_ADXL372_SPI is not set
+# CONFIG_ADXRS290 is not set
+# CONFIG_ADXRS450 is not set
+# CONFIG_AFE4403 is not set
+# CONFIG_ALTERA_MBOX is not set
+# CONFIG_ARM_CRYPTO is not set
+# CONFIG_ARM_MHU is not set
+# CONFIG_ARM_SCMI_PROTOCOL is not set
+# CONFIG_ARM_SCPI_PROTOCOL is not set
+# CONFIG_AS3935 is not set
+# CONFIG_BMA220 is not set
+# CONFIG_BMC150_MAGN_SPI is not set
+# CONFIG_BMI160_SPI is not set
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_CRYPTO_842 is not set
+# CONFIG_CRYPTO_ADIANTUM is not set
+# CONFIG_CRYPTO_AEGIS128 is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_AES_TI is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_BLAKE2B is not set
+# CONFIG_CRYPTO_BLAKE2S is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_CFB is not set
+# CONFIG_CRYPTO_CHACHA20 is not set
+# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
+# CONFIG_CRYPTO_CMAC is not set
+# CONFIG_CRYPTO_CRC32 is not set
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_CRCT10DIF is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_CURVE25519 is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_DH is not set
+# CONFIG_CRYPTO_DRBG_MENU is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_ECDH is not set
+# CONFIG_CRYPTO_ECHAINIV is not set
+# CONFIG_CRYPTO_ECRDSA is not set
+# CONFIG_CRYPTO_ESSIV is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_GHASH is not set
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_CRYPTO_JITTERENTROPY is not set
+# CONFIG_CRYPTO_KEYWRAP is not set
+# CONFIG_CRYPTO_LIB_CHACHA is not set
+# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_LZ4 is not set
+# CONFIG_CRYPTO_LZ4HC is not set
+# CONFIG_CRYPTO_LZO is not set
+# CONFIG_CRYPTO_MANAGER is not set
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_OFB is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_POLY1305 is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_RSA is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEQIV is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA3 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_SM2 is not set
+# CONFIG_CRYPTO_SM3 is not set
+# CONFIG_CRYPTO_SM4 is not set
+# CONFIG_CRYPTO_STREEBOG is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_USER is not set
+# CONFIG_CRYPTO_USER_API_AEAD is not set
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_RNG is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+# CONFIG_CRYPTO_VMAC is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_XXHASH is not set
+# CONFIG_CRYPTO_ZSTD is not set
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EROFS_FS_DEBUG is not set
+# CONFIG_EROFS_FS_XATTR is not set
+# CONFIG_EROFS_FS_ZIP is not set
+# CONFIG_EXT4_DEBUG is not set
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+CONFIG_EXT4_USE_FOR_EXT2=y
+# CONFIG_EZX_PCAP is not set
+CONFIG_FAT_DEFAULT_CODEPAGE=936
+CONFIG_FAT_DEFAULT_IOCHARSET="cp936"
+CONFIG_FAT_DEFAULT_UTF8=y
+CONFIG_FAT_FS=m
+CONFIG_FS_DAX=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=m
+# CONFIG_FXOS8700_SPI is not set
+# CONFIG_GPIO_74X164 is not set
+# CONFIG_GPIO_MAX3191X is not set
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_PISOSR is not set
+# CONFIG_GPIO_XRA1403 is not set
+# CONFIG_HI8435 is not set
+# CONFIG_IIO_SSP_SENSORHUB is not set
+# CONFIG_INITCALL_ASYNC is not set
+# CONFIG_INITRAMFS_FORCE is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INITRD_ASYNC=y
+# CONFIG_INV_ICM42600_SPI is not set
+# CONFIG_INV_MPU6050_SPI is not set
+CONFIG_JBD2=m
+# CONFIG_JBD2_DEBUG is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_LZO is not set
+# CONFIG_JFFS2_RTIME is not set
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_SUMMARY is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_LATTICE_ECP3_CONFIG is not set
+CONFIG_LIB_MEMNEQ=y
+# CONFIG_LTC1660 is not set
+# CONFIG_LTC2496 is not set
+# CONFIG_LTC2632 is not set
+# CONFIG_LTC2983 is not set
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_MANDATORY_FILE_LOCKING=y
+# CONFIG_MAX1027 is not set
+# CONFIG_MAX11100 is not set
+# CONFIG_MAX1118 is not set
+# CONFIG_MAX1241 is not set
+# CONFIG_MAX31856 is not set
+# CONFIG_MAX5481 is not set
+# CONFIG_MAX5487 is not set
+# CONFIG_MAXIM_THERMOCOUPLE is not set
+# CONFIG_MCP320X is not set
+# CONFIG_MCP3911 is not set
+# CONFIG_MCP41010 is not set
+# CONFIG_MCP4131 is not set
+# CONFIG_MCP4922 is not set
+# CONFIG_MFD_ARIZONA_SPI is not set
+# CONFIG_MFD_CPCAP is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_INTEL_M10_BMC is not set
+# CONFIG_MFD_MC13XXX_SPI is not set
+# CONFIG_MFD_RK806_SPI is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MICREL_KS8995MA is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_MMA7455_SPI is not set
+# CONFIG_MMC_ARMMMCI is not set
+CONFIG_MMC_BLOCK=m
+CONFIG_MMC_BLOCK_MINORS=32
+# CONFIG_MMC_CQHCI is not set
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_DW=m
+# CONFIG_MMC_DW_BLUEFIELD is not set
+# CONFIG_MMC_DW_EXYNOS is not set
+# CONFIG_MMC_DW_HI3798CV200 is not set
+# CONFIG_MMC_DW_K3 is not set
+CONFIG_MMC_DW_PLTFM=m
+CONFIG_MMC_DW_ROCKCHIP=m
+# CONFIG_MMC_HSQ is not set
+# CONFIG_MMC_MTK is not set
+CONFIG_MMC_QUEUE_DEPTH=1
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_SPI is not set
+# CONFIG_MMC_TEST is not set
+# CONFIG_MMC_USDHI6ROL0 is not set
+# CONFIG_MOXTET is not set
+# CONFIG_MPL115_SPI is not set
+CONFIG_MTD_BLKDEVS=m
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_MCHP23K256 is not set
+# CONFIG_MTD_SPI_NAND is not set
+CONFIG_MTD_SPI_NOR=m
+CONFIG_MTD_SPI_NOR_MISC=y
+# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_PI433 is not set
+# CONFIG_PL320_MBOX is not set
+# CONFIG_PLATFORM_MHU is not set
+# CONFIG_PWRSEQ_EMMC is not set
+# CONFIG_PWRSEQ_SIMPLE is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_LZ4 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_ZSTD is not set
+CONFIG_REGMAP_SPI=y
+# CONFIG_REGULATOR_TPS6524X is not set
+# CONFIG_ROCKCHIP_MBOX is not set
+# CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE is not set
+CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE=m
+CONFIG_ROCKCHIP_RGA_DEBUGGER=y
+CONFIG_ROCKCHIP_THUNDER_BOOT_MMC=y
+# CONFIG_ROCKCHIP_THUNDER_BOOT_SERVICE is not set
+CONFIG_ROCKCHIP_THUNDER_BOOT_SFC=y
+# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
+# CONFIG_RTC_DRV_DS1302 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1343 is not set
+# CONFIG_RTC_DRV_DS1347 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_MAX6916 is not set
+# CONFIG_RTC_DRV_MCP795 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_RX4581 is not set
+# CONFIG_RTC_DRV_RX6110 is not set
+# CONFIG_SCA3000 is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_SENSORS_HMC5843_SPI is not set
+# CONFIG_SENSORS_RM3100_SPI is not set
+# CONFIG_SERIAL_IFX6X60 is not set
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX310X is not set
+# CONFIG_SND_SOC_ADAU1761_SPI is not set
+# CONFIG_SND_SOC_AK4104 is not set
+# CONFIG_SND_SOC_CS4271_SPI is not set
+# CONFIG_SND_SOC_ES8328_SPI is not set
+# CONFIG_SND_SOC_PCM179X_SPI is not set
+# CONFIG_SND_SOC_PCM186X_SPI is not set
+# CONFIG_SND_SOC_PCM3060_SPI is not set
+# CONFIG_SND_SOC_PCM3168A_SPI is not set
+# CONFIG_SND_SOC_PCM512x_SPI is not set
+# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set
+# CONFIG_SND_SOC_SSM2602_SPI is not set
+# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
+# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
+# CONFIG_SND_SOC_WM8770 is not set
+# CONFIG_SND_SOC_WM8804_SPI is not set
+# CONFIG_SND_SOC_ZL38060 is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_AMD is not set
+# CONFIG_SPI_AXI_SPI_ENGINE is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_CADENCE is not set
+# CONFIG_SPI_CADENCE_QUADSPI is not set
+# CONFIG_SPI_DEBUG is not set
+# CONFIG_SPI_DESIGNWARE is not set
+# CONFIG_SPI_FSL_SPI is not set
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_LOOPBACK_TEST is not set
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SPI_MUX is not set
+# CONFIG_SPI_MXIC is not set
+# CONFIG_SPI_NXP_FLEXSPI is not set
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_PL022 is not set
+# CONFIG_SPI_ROCKCHIP is not set
+CONFIG_SPI_ROCKCHIP_SFC=y
+# CONFIG_SPI_SC18IS602 is not set
+# CONFIG_SPI_SIFIVE is not set
+# CONFIG_SPI_SLAVE is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_SPI_XCOMM is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_ZYNQMP_GQSPI is not set
+# CONFIG_TI_ADC0832 is not set
+# CONFIG_TI_ADC084S021 is not set
+# CONFIG_TI_ADC108S102 is not set
+# CONFIG_TI_ADC12138 is not set
+# CONFIG_TI_ADC128S052 is not set
+# CONFIG_TI_ADC161S626 is not set
+# CONFIG_TI_ADS124S08 is not set
+# CONFIG_TI_ADS7950 is not set
+# CONFIG_TI_ADS8344 is not set
+# CONFIG_TI_ADS8688 is not set
+# CONFIG_TI_DAC082S085 is not set
+# CONFIG_TI_DAC7311 is not set
+# CONFIG_TI_DAC7612 is not set
+# CONFIG_TI_TLC4541 is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_VIDEO_GS1662 is not set
+# CONFIG_VIDEO_ROCKCHIP_PREISP is not set
+# CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP is not set
+# CONFIG_VIDEO_S5C73M3 is not set
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
--- a/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi
@@ -17,13 +17,13 @@
 		status = "okay";
 	};

-	rpmsg: rpmsg@a0000000 {
+	rpmsg: rpmsg@7c00000 {
 		compatible = "rockchip,rk3562-rpmsg";
 		mbox-names = "rpmsg-rx", "rpmsg-tx";
 		mboxes = <&mailbox 0 &mailbox 3>;
 		rockchip,vdev-nums = <1>;
 		rockchip,link-id = <0x04>;
-		reg = <0x0 0xa0000000 0x0 0x20000>;
+		reg = <0x0 0x7c00000 0x0 0x20000>;
 		memory-region = <&rpmsg_dma_reserved>;

 		status = "okay";
@@ -40,19 +40,20 @@
 			no-map;
 		};

-		rpmsg_reserved: rpmsg@a0000000 {
-			reg = <0x0 0xa0000000 0x0 0x400000>;
+		rpmsg_reserved: rpmsg@7c00000 {
+			reg = <0x0 0x07c00000 0x0 0x400000>;
 			no-map;
 		};

-		rpmsg_dma_reserved: rpmsg-dma@a0400000 {
+		rpmsg_dma_reserved: rpmsg-dma@8000000 {
 			compatible = "shared-dma-pool";
-			reg = <0x0 0xa0400000 0x0 0x100000>;
+			reg = <0x0 0x08000000 0x0 0x100000>;
 			no-map;
 		};
 	};
 };

 &mailbox {
+	rockchip,txpoll-period-ms = <1>;
 	status = "okay";
 };
--- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
@@ -352,7 +352,7 @@
 		};
 	};

-	arm-pmu {
+	arm_pmu: arm-pmu {
 		compatible = "arm,cortex-a53-pmu";
 		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -1624,6 +1624,16 @@ static void rk3568_dump_cru(void)
 	}
 }

+static int protect_clocks[] = {
+	ACLK_VO,
+	HCLK_VO,
+	ACLK_VOP,
+	HCLK_VOP,
+	DCLK_VOP0,
+	DCLK_VOP1,
+	DCLK_VOP2,
+};
+
 static void __init rk3568_pmu_clk_init(struct device_node *np)
 {
 	struct rockchip_clk_provider *ctx;
@@ -1701,6 +1711,8 @@ static void __init rk3568_clk_init(struct device_node *np)

 	if (!rk_dump_cru)
 		rk_dump_cru = rk3568_dump_cru;
+
+	rockchip_clk_protect(ctx, protect_clocks, ARRAY_SIZE(protect_clocks));
 }

 CLK_OF_DECLARE(rk3568_cru, "rockchip,rk3568-cru", rk3568_clk_init);
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -541,4 +541,11 @@ config EDAC_DMC520
 	  Support for error detection and correction on the
 	  SoCs with ARM DMC-520 DRAM controller.

+config EDAC_ROCKCHIP
+	tristate "Rockchip DDR ECC"
+	depends on ARCH_ROCKCHIP && HAVE_ARM_SMCCC
+	help
+	  Support for error detection and correction on the
+	  rockchip family of SOCs.
+
 endif # EDAC
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -84,3 +84,4 @@ obj-$(CONFIG_EDAC_QCOM)			+= qcom_edac.o
 obj-$(CONFIG_EDAC_ASPEED)		+= aspeed_edac.o
 obj-$(CONFIG_EDAC_BLUEFIELD)		+= bluefield_edac.o
 obj-$(CONFIG_EDAC_DMC520)		+= dmc520_edac.o
+obj-$(CONFIG_EDAC_ROCKCHIP)		+= rockchip_edac.o
--- a/drivers/edac/rockchip_edac.c
+++ b/drivers/edac/rockchip_edac.c
@@ -0,0 +1,358 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+#include <linux/edac.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/rockchip/rockchip_sip.h>
+#include <soc/rockchip/rockchip_sip.h>
+
+#include "edac_module.h"
+
+#define MAX_CS					(4)
+
+#define MAX_CH					(1)
+
+#define	RK_EDAC_MOD				"1"
+
+/* ECCCADDR0 */
+#define ECC_CORR_RANK_SHIFT			(24)
+#define ECC_CORR_RANK_MASK			(0x3)
+#define ECC_CORR_ROW_MASK			(0x3ffff)
+/* ECCCADDR1 */
+#define ECC_CORR_CID_SHIFT			(28)
+#define ECC_CORR_CID_MASK			(0x3)
+#define ECC_CORR_BG_SHIFT			(24)
+#define ECC_CORR_BG_MASK			(0x3)
+#define ECC_CORR_BANK_SHIFT			(16)
+#define ECC_CORR_BANK_MASK			(0x7)
+#define ECC_CORR_COL_MASK			(0xfff)
+/* ECCUADDR0 */
+#define ECC_UNCORR_RANK_SHIFT			(24)
+#define ECC_UNCORR_RANK_MASK			(0x3)
+#define ECC_UNCORR_ROW_MASK			(0x3ffff)
+/* ECCUADDR1 */
+#define ECC_UNCORR_CID_SHIFT			(28)
+#define ECC_UNCORR_CID_MASK			(0x3)
+#define ECC_UNCORR_BG_SHIFT			(24)
+#define ECC_UNCORR_BG_MASK			(0x3)
+#define ECC_UNCORR_BANK_SHIFT			(16)
+#define ECC_UNCORR_BANK_MASK			(0x7)
+#define ECC_UNCORR_COL_MASK			(0xfff)
+
+/**
+ * struct ddr_ecc_error_info - DDR ECC error log information
+ * @err_cnt:	error count
+ * @rank:	Rank number
+ * @row:	Row number
+ * @chip_id:	Chip id number
+ * @bank_group:	Bank Group number
+ * @bank:	Bank number
+ * @col:	Column number
+ * @bitpos:	Bit position
+ */
+struct ddr_ecc_error_info {
+	u32 err_cnt;
+	u32 rank;
+	u32 row;
+	u32 chip_id;
+	u32 bank_group;
+	u32 bank;
+	u32 col;
+	u32 bitpos;
+};
+
+/**
+ * struct ddr_ecc_status - DDR ECC status information to report
+ * @ceinfo:	Correctable error log information
+ * @ueinfo:	Uncorrectable error log information
+ */
+struct ddr_ecc_status {
+	struct ddr_ecc_error_info ceinfo;
+	struct ddr_ecc_error_info ueinfo;
+};
+
+/**
+ * struct rk_edac_priv - RK DDR memory controller private instance data
+ * @name:	EDAC name
+ * @stat:	DDR ECC status information
+ * @ce_cnt:	Correctable Error count
+ * @ue_cnt:	Uncorrectable Error count
+ * @irq_ce:	Corrected interrupt number
+ * @irq_ue:	Uncorrected interrupt number
+ */
+struct rk_edac_priv {
+	char *name;
+	struct ddr_ecc_status stat;
+	u32 ce_cnt;
+	u32 ue_cnt;
+	int irq_ce;
+	int irq_ue;
+};
+
+static struct ddr_ecc_status *ddr_edac_info;
+
+static inline void opstate_init_int(void)
+{
+	switch (edac_op_state) {
+	case EDAC_OPSTATE_POLL:
+	case EDAC_OPSTATE_INT:
+		break;
+	default:
+		edac_op_state = EDAC_OPSTATE_INT;
+		break;
+	}
+}
+
+static void rockchip_edac_handle_ce_error(struct mem_ctl_info *mci,
+					  struct ddr_ecc_status *p)
+{
+	struct ddr_ecc_error_info *pinf;
+
+	if (p->ceinfo.err_cnt) {
+		pinf = &p->ceinfo;
+		edac_mc_printk(mci, KERN_ERR,
+			       "DDR ECC CE error: CS%d, Row 0x%x, Bg 0x%x, Bk 0x%x, Col 0x%x bit 0x%x\n",
+			       pinf->rank, pinf->row, pinf->bank_group,
+			       pinf->bank, pinf->col,
+			       pinf->bitpos);
+		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
+				     p->ceinfo.err_cnt, 0, 0, 0, 0, 0, -1,
+				     mci->ctl_name, "");
+	}
+}
+
+static void rockchip_edac_handle_ue_error(struct mem_ctl_info *mci,
+					  struct ddr_ecc_status *p)
+{
+	struct ddr_ecc_error_info *pinf;
+
+	if (p->ueinfo.err_cnt) {
+		pinf = &p->ueinfo;
+		edac_mc_printk(mci, KERN_ERR,
+			       "DDR ECC UE error: CS%d, Row 0x%x, Bg 0x%x, Bk 0x%x, Col 0x%x\n",
+			       pinf->rank, pinf->row,
+			       pinf->bank_group, pinf->bank, pinf->col);
+		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
+				     p->ueinfo.err_cnt, 0, 0, 0, 0, 0, -1,
+				     mci->ctl_name, "");
+	}
+}
+
+static int rockchip_edac_get_error_info(struct mem_ctl_info *mci)
+{
+	struct arm_smccc_res res;
+
+	res = sip_smc_dram(SHARE_PAGE_TYPE_DDRECC, 0,
+			   ROCKCHIP_SIP_CONFIG_DRAM_ECC);
+	if ((res.a0) || (res.a1)) {
+		edac_mc_printk(mci, KERN_ERR, "ROCKCHIP_SIP_CONFIG_DRAM_ECC not support: 0x%lx\n",
+			       res.a0);
+		return -ENXIO;
+	}
+
+	return 0;
+}
+
+static void rockchip_edac_check(struct mem_ctl_info *mci)
+{
+	struct rk_edac_priv *priv = mci->pvt_info;
+	int ret;
+
+	ret = rockchip_edac_get_error_info(mci);
+	if (ret)
+		return;
+
+	priv->ce_cnt += ddr_edac_info->ceinfo.err_cnt;
+	priv->ue_cnt += ddr_edac_info->ceinfo.err_cnt;
+	rockchip_edac_handle_ce_error(mci, ddr_edac_info);
+	rockchip_edac_handle_ue_error(mci, ddr_edac_info);
+}
+
+static irqreturn_t rockchip_edac_mc_ce_isr(int irq, void *dev_id)
+{
+	struct mem_ctl_info *mci = dev_id;
+	struct rk_edac_priv *priv = mci->pvt_info;
+	int ret;
+
+	ret = rockchip_edac_get_error_info(mci);
+	if (ret)
+		return IRQ_NONE;
+
+	priv->ce_cnt += ddr_edac_info->ceinfo.err_cnt;
+
+	rockchip_edac_handle_ce_error(mci, ddr_edac_info);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t rockchip_edac_mc_ue_isr(int irq, void *dev_id)
+{
+	struct mem_ctl_info *mci = dev_id;
+	struct rk_edac_priv *priv = mci->pvt_info;
+	int ret;
+
+	ret = rockchip_edac_get_error_info(mci);
+	if (ret)
+		return IRQ_NONE;
+
+	priv->ue_cnt += ddr_edac_info->ueinfo.err_cnt;
+
+	rockchip_edac_handle_ue_error(mci, ddr_edac_info);
+
+	return IRQ_HANDLED;
+}
+
+static int rockchip_edac_mc_init(struct mem_ctl_info *mci,
+			   struct platform_device *pdev)
+{
+	struct rk_edac_priv *priv = mci->pvt_info;
+	struct arm_smccc_res res;
+	int ret;
+
+	mci->pdev = &pdev->dev;
+	dev_set_drvdata(mci->pdev, mci);
+	mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR4;
+	mci->edac_ctl_cap = EDAC_FLAG_SECDED;
+	mci->scrub_cap = SCRUB_NONE;
+	mci->scrub_mode = SCRUB_NONE;
+
+	mci->edac_cap = EDAC_FLAG_SECDED;
+	mci->ctl_name = priv->name;
+	mci->dev_name = priv->name;
+	mci->mod_name = RK_EDAC_MOD;
+
+	if (edac_op_state == EDAC_OPSTATE_POLL)
+		mci->edac_check = rockchip_edac_check;
+	mci->ctl_page_to_phys = NULL;
+
+	res = sip_smc_request_share_mem(1, SHARE_PAGE_TYPE_DDRECC);
+	if (res.a0 != 0) {
+		dev_err(&pdev->dev, "no ATF memory for init, ret 0x%lx\n", res.a0);
+		return -ENOMEM;
+	}
+	ddr_edac_info = (struct ddr_ecc_status *)res.a1;
+	memset(ddr_edac_info, 0, sizeof(struct ddr_ecc_status));
+
+	ret = rockchip_edac_get_error_info(mci);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int rockchip_edac_probe(struct platform_device *pdev)
+{
+	struct mem_ctl_info *mci;
+	struct edac_mc_layer layers[2];
+	struct rk_edac_priv *priv;
+	int ret;
+
+	opstate_init_int();
+	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
+	layers[0].size = MAX_CS;
+	layers[0].is_virt_csrow = true;
+	layers[1].type = EDAC_MC_LAYER_CHANNEL;
+	layers[1].size = MAX_CH;
+	layers[1].is_virt_csrow = false;
+
+	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
+			    sizeof(struct rk_edac_priv));
+	if (!mci) {
+		edac_printk(KERN_ERR, EDAC_MC,
+			    "Failed memory allocation for mc instance\n");
+		return -ENOMEM;
+	}
+
+	priv = mci->pvt_info;
+	priv->name = "rk_edac_ecc";
+	ret = rockchip_edac_mc_init(mci, pdev);
+	if (ret) {
+		edac_printk(KERN_ERR, EDAC_MC,
+			    "Failed to initialize instance\n");
+		goto free_edac_mc;
+	}
+
+	ret = edac_mc_add_mc(mci);
+	if (ret) {
+		edac_printk(KERN_ERR, EDAC_MC,
+			    "Failed edac_mc_add_mc()\n");
+		goto free_edac_mc;
+	}
+
+	if (edac_op_state == EDAC_OPSTATE_INT) {
+		/* register interrupts */
+		priv->irq_ce = platform_get_irq_byname(pdev, "ce");
+		ret = devm_request_irq(&pdev->dev, priv->irq_ce,
+				       rockchip_edac_mc_ce_isr,
+				       0,
+				       "[EDAC] MC err", mci);
+		if (ret < 0) {
+			edac_printk(KERN_ERR, EDAC_MC,
+				    "%s: Unable to request ce irq %d for RK EDAC\n",
+				    __func__, priv->irq_ce);
+			goto del_mc;
+		}
+
+		edac_printk(KERN_INFO, EDAC_MC,
+			    "acquired ce irq %d for MC\n",
+			    priv->irq_ce);
+
+		priv->irq_ue = platform_get_irq_byname(pdev, "ue");
+		ret = devm_request_irq(&pdev->dev, priv->irq_ue,
+				       rockchip_edac_mc_ue_isr,
+				       0,
+				       "[EDAC] MC err", mci);
+		if (ret < 0) {
+			edac_printk(KERN_ERR, EDAC_MC,
+				    "%s: Unable to request ue irq %d for RK EDAC\n",
+				    __func__, priv->irq_ue);
+			goto del_mc;
+		}
+
+		edac_printk(KERN_INFO, EDAC_MC,
+			    "acquired ue irq %d for MC\n",
+			    priv->irq_ue);
+	}
+
+	return 0;
+
+del_mc:
+	edac_mc_del_mc(&pdev->dev);
+free_edac_mc:
+	edac_mc_free(mci);
+
+	return -ENODEV;
+}
+
+static int rockchip_edac_remove(struct platform_device *pdev)
+{
+	struct mem_ctl_info *mci = dev_get_drvdata(&pdev->dev);
+
+	edac_mc_del_mc(&pdev->dev);
+	edac_mc_free(mci);
+
+	return 0;
+}
+
+static const struct of_device_id rk_ddr_mc_err_of_match[] = {
+	{ .compatible = "rockchip,rk3568-edac", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, rk_ddr_mc_err_of_match);
+
+static struct platform_driver rockchip_edac_driver = {
+	.probe = rockchip_edac_probe,
+	.remove = rockchip_edac_remove,
+	.driver = {
+		.name = "rk_edac",
+		.of_match_table = rk_ddr_mc_err_of_match,
+	},
+};
+module_platform_driver(rockchip_edac_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("He Zhihuan <huan.he@rock-chips.com>\n");
+MODULE_DESCRIPTION("ROCKCHIP EDAC kernel module");
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
@@ -2262,6 +2262,7 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
 	struct drm_display_mode *mode;
 	struct drm_display_info *info = &connector->display_info;
 	void *data = hdmi->plat_data->phy_data;
+	struct drm_property_blob *edid_blob_ptr = connector->edid_blob_ptr;
 	int i, ret = 0;

 	if (hdmi->plat_data->right && hdmi->plat_data->right->next_bridge) {
@@ -2283,7 +2284,17 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
 		return 0;

 	memset(metedata, 0, sizeof(*metedata));
-	edid = drm_get_edid(connector, hdmi->ddc);
+
+	if (edid_blob_ptr && edid_blob_ptr->length) {
+		edid = kmalloc(edid_blob_ptr->length, GFP_KERNEL);
+		if (!edid)
+			return -ENOMEM;
+		memcpy(edid, edid_blob_ptr->data, edid_blob_ptr->length);
+	} else {
+		edid = drm_get_edid(connector, hdmi->ddc);
+		hdmi->hdcp_caps = dw_hdmi_qp_hdcp_capable(hdmi);
+	}
+
 	if (edid) {
 		dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
 			edid->width_cm, edid->height_cm);
@@ -2311,8 +2322,10 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
 			else if (hdmi->plat_data->right)
 				secondary = hdmi->plat_data->right;

-			if (!secondary)
+			if (!secondary) {
+				kfree(edid);
 				return -ENOMEM;
+			}
 			secondary_data = secondary->plat_data->phy_data;

 			list_for_each_entry(mode, &connector->probed_modes, head)
@@ -4051,6 +4064,7 @@ void dw_hdmi_qp_suspend(struct device *dev, struct dw_hdmi_qp *hdmi)
 		disable_irq(hdmi->earc_irq);

 	pinctrl_pm_select_sleep_state(dev);
+	drm_connector_update_edid_property(&hdmi->connector, NULL);
 }
 EXPORT_SYMBOL_GPL(dw_hdmi_qp_suspend);

--- a/drivers/media/platform/rockchip/cif/capture.c
+++ b/drivers/media/platform/rockchip/cif/capture.c
@@ -8513,7 +8513,11 @@ static void rkcif_buf_done_prepare(struct rkcif_stream *stream,

 	if (active_buf) {
 		vb_done = &active_buf->vb;
-		vb_done->vb2_buf.timestamp = stream->readout.fs_timestamp;
+		if (cif_dev->chip_id < CHIP_RK3588_CIF &&
+		    cif_dev->active_sensor->mbus.type == V4L2_MBUS_BT656)
+			vb_done->vb2_buf.timestamp = stream->readout.fe_timestamp;
+		else
+			vb_done->vb2_buf.timestamp = stream->readout.fs_timestamp;
 		vb_done->sequence = stream->frame_idx - 1;
 		active_buf->fe_timestamp = ktime_get_ns();
 		if (stream->is_line_wake_up) {
@@ -8834,6 +8838,10 @@ static void rkcif_update_stream(struct rkcif_device *cif_dev,
 		if (ret && cif_dev->chip_id < CHIP_RK3588_CIF)
 			return;
 	}
+	if (cif_dev->chip_id < CHIP_RK3588_CIF &&
+	    cif_dev->active_sensor->mbus.type == V4L2_MBUS_BT656 &&
+	    stream->id != 0)
+		stream->frame_idx++;
 	if (!stream->is_line_wake_up && stream->dma_en & RKCIF_DMAEN_BY_VICAP)
 		rkcif_buf_done_prepare(stream, active_buf, mipi_id, 0);

--- a/drivers/media/platform/rockchip/isp/capture.c
+++ b/drivers/media/platform/rockchip/isp/capture.c
@@ -626,7 +626,7 @@ static void restrict_rsz_resolution(struct rkisp_stream *stream,

 		max_rsz->width = ALIGN(DIV_ROUND_UP(input_win->width, div), 4);
 		max_rsz->height = DIV_ROUND_UP(input_win->height, div);
-	} else if (dev->hw_dev->is_unite) {
+	} else if (dev->hw_dev->unite) {
 		/* scale down only for unite mode */
 		max_rsz->width = min_t(int, input_win->width, cfg->max_rsz_width);
 		max_rsz->height = min_t(int, input_win->height, cfg->max_rsz_height);
@@ -1140,7 +1140,8 @@ static int rkisp_set_wrap_line(struct rkisp_stream *stream, struct rkisp_wrap_in

 	if (dev->isp_ver != ISP_V32 ||
 	    dev->hw_dev->dev_link_num > 1 ||
-	    !stream->ops->set_wrap) {
+	    !stream->ops->set_wrap ||
+	    dev->hw_dev->unite) {
 		v4l2_err(&dev->v4l2_dev,
 			 "wrap only support for single sensor and mainpath\n");
 		return -EINVAL;
@@ -1465,7 +1466,7 @@ static struct v4l2_rect *rkisp_update_crop(struct rkisp_stream *stream,
 					    const struct v4l2_rect *in)
 {
 	struct rkisp_device *dev = stream->ispdev;
-	bool is_unite = dev->hw_dev->is_unite;
+	bool is_unite = !!dev->hw_dev->unite;
 	u32 align = is_unite ? 4 : 2;

 	/* Not crop for MP bayer raw data and dmatx path */
@@ -1735,17 +1736,21 @@ int rkisp_register_stream_vdevs(struct rkisp_device *dev)
 		st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V21;
 		ret = rkisp_register_stream_v21(dev);
 	} else if (dev->isp_ver == ISP_V30) {
-		st_cfg->max_rsz_width = dev->hw_dev->is_unite ?
+		st_cfg->max_rsz_width = dev->hw_dev->unite ?
 					CIF_ISP_INPUT_W_MAX_V30_UNITE : CIF_ISP_INPUT_W_MAX_V30;
-		st_cfg->max_rsz_height = dev->hw_dev->is_unite ?
+		st_cfg->max_rsz_height = dev->hw_dev->unite ?
 					 CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30;
 		ret = rkisp_register_stream_v30(dev);
 	} else if (dev->isp_ver == ISP_V32) {
-		st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32;
-		st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V32;
+		st_cfg->max_rsz_width = dev->hw_dev->unite ?
+					CIF_ISP_INPUT_W_MAX_V32_UNITE : CIF_ISP_INPUT_W_MAX_V32;
+		st_cfg->max_rsz_height = dev->hw_dev->unite ?
+					CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32;
 		st_cfg = &rkisp_sp_stream_config;
-		st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32;
-		st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V32;
+		st_cfg->max_rsz_width = dev->hw_dev->unite ?
+					CIF_ISP_INPUT_W_MAX_V32_UNITE : CIF_ISP_INPUT_W_MAX_V32;
+		st_cfg->max_rsz_height = dev->hw_dev->unite ?
+					 CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32;
 		ret = rkisp_register_stream_v32(dev);
 	} else if (dev->isp_ver == ISP_V32_L) {
 		st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32_L;
--- a/drivers/media/platform/rockchip/isp/capture_v30.c
+++ b/drivers/media/platform/rockchip/isp/capture_v30.c
@@ -332,7 +332,7 @@ static int rkisp_stream_config_dcrop(struct rkisp_stream *stream, bool async)
 	if (dcrop->width == input_win->width &&
 	    dcrop->height == input_win->height &&
 	    dcrop->left == 0 && dcrop->top == 0 &&
-	    !dev->hw_dev->is_unite) {
+	    !dev->hw_dev->unite) {
 		rkisp_disable_dcrop(stream, async);
 		v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
 			 "stream %d crop disabled\n", stream->id);
@@ -472,7 +472,7 @@ static int mp_config_mi(struct rkisp_stream *stream)
 {
 	struct rkisp_device *dev = stream->ispdev;
 	struct v4l2_pix_format_mplane *out_fmt = &stream->out_fmt;
-	bool is_unite = dev->hw_dev->is_unite;
+	bool is_unite = !!dev->hw_dev->unite;
 	u32 val, mask;

       /*
@@ -480,26 +480,26 @@ static int mp_config_mi(struct rkisp_stream *stream)
 	* memory plane formats, so calculate the size explicitly.
 	*/
 	val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height;
-	rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false, is_unite);
+	rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false);

 	val = out_fmt->plane_fmt[1].sizeimage;
-	rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false, is_unite);
+	rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false);

 	val = out_fmt->plane_fmt[2].sizeimage;
-	rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false, is_unite);
+	rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false);

 	val = is_unite ? out_fmt->width / 2 : out_fmt->width;
-	rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_PIC_WIDTH, val, false, is_unite);
+	rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_PIC_WIDTH, val, false);

 	val = out_fmt->height;
-	rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_PIC_HEIGHT, val, false, is_unite);
+	rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_PIC_HEIGHT, val, false);

 	val = out_fmt->plane_fmt[0].bytesperline;
-	rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false, is_unite);
+	rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false);

 	val = stream->out_isp_fmt.uv_swap ? ISP3X_MI_XTD_FORMAT_MP_UV_SWAP : 0;
 	mask = ISP3X_MI_XTD_FORMAT_MP_UV_SWAP;
-	rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false, is_unite);
+	rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false);

 	mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_MP_YUV_MODE;
 	val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask;
@@ -511,13 +511,13 @@ static int mp_config_mi(struct rkisp_stream *stream)
 		val |= ISP3X_SEPERATE_YUV_CFG;
 	else
 		val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_MP_YUV_MODE;
-	rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false, is_unite);
+	rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false);

 	val = calc_burst_len(stream) | CIF_MI_CTRL_INIT_BASE_EN |
 		CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_MP_AUTOUPDATE_ENABLE |
 		stream->out_isp_fmt.write_format;
 	mask = GENMASK(19, 16) | MI_CTRL_MP_FMT_MASK;
-	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false, is_unite);
+	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false);

 	mi_frame_end_int_enable(stream);
 	/* set up first buffer */
@@ -558,7 +558,7 @@ static int sp_config_mi(struct rkisp_stream *stream)
 	struct v4l2_pix_format_mplane *out_fmt = &stream->out_fmt;
 	struct ispsd_out_fmt *input_isp_fmt =
 			rkisp_get_ispsd_out_fmt(&dev->isp_sdev);
-	bool is_unite = dev->hw_dev->is_unite;
+	bool is_unite = !!dev->hw_dev->unite;
 	u32 sp_in_fmt, val, mask;

 	if (mbus_code_sp_in_fmt(input_isp_fmt->mbus_code,
@@ -572,26 +572,26 @@ static int sp_config_mi(struct rkisp_stream *stream)
 	* memory plane formats, so calculate the size explicitly.
 	*/
 	val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height;
-	rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false, is_unite);
+	rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false);

 	val = out_fmt->plane_fmt[1].sizeimage;
-	rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false, is_unite);
+	rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false);

 	val = out_fmt->plane_fmt[2].sizeimage;
-	rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false, is_unite);
+	rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false);

 	val = is_unite ? out_fmt->width / 2 : out_fmt->width;
-	rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_PIC_WIDTH, val, false, is_unite);
+	rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_PIC_WIDTH, val, false);

 	val = out_fmt->height;
-	rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_PIC_HEIGHT, val, false, is_unite);
+	rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_PIC_HEIGHT, val, false);

 	val = stream->u.sp.y_stride;
-	rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_LLENGTH, val, false, is_unite);
+	rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_LLENGTH, val, false);

 	val = stream->out_isp_fmt.uv_swap ? ISP3X_MI_XTD_FORMAT_SP_UV_SWAP : 0;
 	mask = ISP3X_MI_XTD_FORMAT_SP_UV_SWAP;
-	rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false, is_unite);
+	rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false);

 	mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_SP_YUV_MODE;
 	val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask;
@@ -603,14 +603,14 @@ static int sp_config_mi(struct rkisp_stream *stream)
 		val |= ISP3X_SEPERATE_YUV_CFG;
 	else
 		val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_SP_YUV_MODE;
-	rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false, is_unite);
+	rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false);

 	val = calc_burst_len(stream) | CIF_MI_CTRL_INIT_BASE_EN |
 		CIF_MI_CTRL_INIT_OFFSET_EN | stream->out_isp_fmt.write_format |
 		sp_in_fmt | stream->out_isp_fmt.output_format |
 		CIF_MI_SP_AUTOUPDATE_ENABLE;
 	mask = GENMASK(19, 16) | MI_CTRL_SP_FMT_MASK;
-	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false, is_unite);
+	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false);

 	mi_frame_end_int_enable(stream);
 	/* set up first buffer */
@@ -625,12 +625,12 @@ static int fbc_config_mi(struct rkisp_stream *stream)
 	u32 h = ALIGN(stream->out_fmt.height, 16);
 	u32 w = ALIGN(stream->out_fmt.width, 16);
 	u32 offs = ALIGN(w * h / 16, RK_MPP_ALIGN);
-	bool is_unite = stream->ispdev->hw_dev->is_unite;
+	bool is_unite = !!stream->ispdev->hw_dev->unite;

 	rkisp_write(stream->ispdev, ISP3X_MPFBC_HEAD_OFFSET, offs, false);
-	rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_VIR_WIDTH, w, false, is_unite);
-	rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_PAYL_WIDTH, w, false, is_unite);
-	rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_VIR_HEIGHT, h, false, is_unite);
+	rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_VIR_WIDTH, w, false);
+	rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_PAYL_WIDTH, w, false);
+	rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_VIR_HEIGHT, h, false);
 	if (is_unite) {
 		u32 left_w = (stream->out_fmt.width / 2) & ~0xf;

@@ -638,8 +638,7 @@ static int fbc_config_mi(struct rkisp_stream *stream)
 		rkisp_next_write(stream->ispdev, ISP3X_MPFBC_HEAD_OFFSET, offs, false);
 	}
 	rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, 0,
-			     CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN,
-			     false, is_unite);
+			     CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN, false);
 	mi_frame_end_int_enable(stream);
 	/* set up first buffer */
 	mi_frame_end(stream, FRAME_INIT);
@@ -650,7 +649,7 @@ static int bp_config_mi(struct rkisp_stream *stream)
 {
 	struct v4l2_pix_format_mplane *out_fmt = &stream->out_fmt;
 	struct rkisp_device *dev = stream->ispdev;
-	bool is_unite = dev->hw_dev->is_unite;
+	bool is_unite = dev->hw_dev->unite;
 	u32 val, mask;

       /*
@@ -658,19 +657,19 @@ static int bp_config_mi(struct rkisp_stream *stream)
 	* memory plane formats, so calculate the size explicitly.
 	*/
 	val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height;
-	rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false, is_unite);
+	rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false);

 	val = out_fmt->plane_fmt[1].sizeimage;
-	rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false, is_unite);
+	rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false);

 	val = is_unite ? out_fmt->width / 2 : out_fmt->width;
-	rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_PIC_WIDTH, val, false, is_unite);
+	rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_PIC_WIDTH, val, false);

 	val = out_fmt->height;
-	rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_PIC_HEIGHT, val, false, is_unite);
+	rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_PIC_HEIGHT, val, false);

 	val = out_fmt->plane_fmt[0].bytesperline;
-	rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false, is_unite);
+	rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false);

 	mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_BP_YUV_MODE;
 	val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask;
@@ -680,9 +679,9 @@ static int bp_config_mi(struct rkisp_stream *stream)
 		val |= ISP3X_SEPERATE_YUV_CFG;
 	else
 		val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_BP_YUV_MODE;
-	rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false, is_unite);
+	rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false);
 	val = CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN;
-	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false, is_unite);
+	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false);
 	mi_frame_end_int_enable(stream);
 	/* set up first buffer */
 	mi_frame_end(stream, FRAME_INIT);
@@ -697,8 +696,7 @@ static void mp_enable_mi(struct rkisp_stream *stream)

 	if (isp_fmt->fmt_type == FMT_BAYER)
 		val = CIF_MI_CTRL_RAW_ENABLE;
-	rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val,
-			     false, stream->ispdev->hw_dev->is_unite);
+	rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false);
 }

 static void sp_enable_mi(struct rkisp_stream *stream)
@@ -711,21 +709,18 @@ static void sp_enable_mi(struct rkisp_stream *stream)
 	if (fmt->fmt_type == FMT_RGB &&
 	    dev->isp_sdev.quantization == V4L2_QUANTIZATION_FULL_RANGE)
 		val |= mask;
-	rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL,
-			     mask, val, false,
-			     stream->ispdev->hw_dev->is_unite);
+	rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false);
 }

 static void fbc_enable_mi(struct rkisp_stream *stream)
 {
 	u32 val, mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_MPFBC_YUV_MASK |
 			ISP3X_MPFBC_SPARSE_MODE;
-	bool is_unite = stream->ispdev->hw_dev->is_unite;

 	/* config no effect immediately, read back is shadow, get config value from cache */
 	val = rkisp_read_reg_cache(stream->ispdev, ISP3X_MPFBC_CTRL) & ~mask;
 	val |= stream->out_isp_fmt.write_format | ISP3X_HEAD_OFFSET_EN | ISP3X_MPFBC_EN;
-	rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_CTRL, val, false, is_unite);
+	rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_CTRL, val, false);
 }

 static void bp_enable_mi(struct rkisp_stream *stream)
@@ -733,36 +728,31 @@ static void bp_enable_mi(struct rkisp_stream *stream)
 	u32 val = stream->out_isp_fmt.write_format |
 		ISP3X_BP_ENABLE | ISP3X_BP_AUTO_UPD;

-	rkisp_unite_write(stream->ispdev, ISP3X_MI_BP_WR_CTRL, val, false,
-			  stream->ispdev->hw_dev->is_unite);
+	rkisp_unite_write(stream->ispdev, ISP3X_MI_BP_WR_CTRL, val, false);
 }

 static void mp_disable_mi(struct rkisp_stream *stream)
 {
 	u32 mask = CIF_MI_CTRL_MP_ENABLE | CIF_MI_CTRL_RAW_ENABLE;

-	rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, false,
-			       stream->ispdev->hw_dev->is_unite);
+	rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, false);
 }

 static void sp_disable_mi(struct rkisp_stream *stream)
 {
-	rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, CIF_MI_CTRL_SP_ENABLE,
-			       false, stream->ispdev->hw_dev->is_unite);
+	rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, CIF_MI_CTRL_SP_ENABLE, false);
 }

 static void fbc_disable_mi(struct rkisp_stream *stream)
 {
 	u32 mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_MPFBC_EN;

-	rkisp_unite_clear_bits(stream->ispdev, ISP3X_MPFBC_CTRL, mask,
-			       false, stream->ispdev->hw_dev->is_unite);
+	rkisp_unite_clear_bits(stream->ispdev, ISP3X_MPFBC_CTRL, mask, false);
 }

 static void bp_disable_mi(struct rkisp_stream *stream)
 {
-	rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_BP_WR_CTRL, ISP3X_BP_ENABLE,
-			       false, stream->ispdev->hw_dev->is_unite);
+	rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_BP_WR_CTRL, ISP3X_BP_ENABLE, false);
 }

 static void update_mi(struct rkisp_stream *stream)
@@ -786,7 +776,7 @@ static void update_mi(struct rkisp_stream *stream)
 			rkisp_write(dev, reg, val, false);
 		}

-		if (dev->hw_dev->is_unite) {
+		if (dev->hw_dev->unite) {
 			u32 mult = stream->id != RKISP_STREAM_FBC ? 1 :
 				   (stream->out_isp_fmt.write_format ? 32 : 24);
 			u32 div = stream->out_isp_fmt.fourcc == V4L2_PIX_FMT_UYVY ? 1 : 2;
@@ -818,22 +808,22 @@ static void update_mi(struct rkisp_stream *stream)
 		stream->dbg.frameloss++;
 		val = dummy_buf->dma_addr;
 		reg = stream->config->mi.y_base_ad_init;
-		rkisp_unite_write(dev, reg, val, false, dev->hw_dev->is_unite);
+		rkisp_unite_write(dev, reg, val, false);
 		reg = stream->config->mi.cb_base_ad_init;
-		rkisp_unite_write(dev, reg, val, false, dev->hw_dev->is_unite);
+		rkisp_unite_write(dev, reg, val, false);
 		reg = stream->config->mi.cr_base_ad_init;
 		if (stream->id != RKISP_STREAM_FBC && stream->id != RKISP_STREAM_BP)
-			rkisp_unite_write(dev, reg, val, false, dev->hw_dev->is_unite);
+			rkisp_unite_write(dev, reg, val, false);
 	}

 	if (stream->id != RKISP_STREAM_FBC) {
 		reg = stream->config->mi.y_offs_cnt_init;
-		rkisp_unite_write(dev, reg, 0, false, dev->hw_dev->is_unite);
+		rkisp_unite_write(dev, reg, 0, false);
 		reg = stream->config->mi.cb_offs_cnt_init;
-		rkisp_unite_write(dev, reg, 0, false, dev->hw_dev->is_unite);
+		rkisp_unite_write(dev, reg, 0, false);
 		reg = stream->config->mi.cr_offs_cnt_init;
 		if (stream->id != RKISP_STREAM_BP)
-			rkisp_unite_write(dev, reg, 0, false, dev->hw_dev->is_unite);
+			rkisp_unite_write(dev, reg, 0, false);
 	}

 	v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
@@ -842,7 +832,7 @@ static void update_mi(struct rkisp_stream *stream)
 		 rkisp_read(dev, stream->config->mi.y_base_ad_init, false),
 		 rkisp_read(dev, stream->config->mi.cb_base_ad_init, false),
 		 rkisp_read(dev, stream->config->mi.y_base_ad_shd, true));
-	if (dev->hw_dev->is_unite)
+	if (dev->hw_dev->unite)
 		v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
 			 "%s stream:%d Y:0x%x CB:0x%x | Y_SHD:0x%x, right\n",
 			 __func__, stream->id,
@@ -897,11 +887,10 @@ static void stream_self_update(struct rkisp_stream *stream)
 {
 	struct rkisp_device *dev = stream->ispdev;
 	u32 val, mask = ISP3X_MPSELF_UPD | ISP3X_SPSELF_UPD | ISP3X_BPSELF_UPD;
-	bool is_unite = dev->hw_dev->is_unite;

 	if (stream->id == RKISP_STREAM_FBC) {
 		val = ISP3X_MPFBC_FORCE_UPD;
-		rkisp_unite_set_bits(dev, ISP3X_MPFBC_CTRL, 0, val, false, is_unite);
+		rkisp_unite_set_bits(dev, ISP3X_MPFBC_CTRL, 0, val, false);
 		return;
 	}

@@ -919,7 +908,7 @@ static void stream_self_update(struct rkisp_stream *stream)
 		return;
 	}

-	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL2, mask, val, false, is_unite);
+	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL2, mask, val, false);
 }

 static int mi_frame_start(struct rkisp_stream *stream, u32 mis)
@@ -1690,7 +1679,7 @@ void rkisp_mi_v30_isr(u32 mis_val, struct rkisp_device *dev)
 	struct rkisp_stream *stream;
 	unsigned int i;

-	if (dev->hw_dev->is_unite) {
+	if (dev->hw_dev->unite) {
 		u32 val = rkisp_read(dev, ISP3X_MI_RIS, true);

 		if (val) {
--- a/drivers/media/platform/rockchip/isp/capture_v32.c
+++ b/drivers/media/platform/rockchip/isp/capture_v32.c
@@ -554,7 +554,8 @@ static int rkisp_stream_config_dcrop(struct rkisp_stream *stream, bool async)

 	if (dcrop->width == input_win->width &&
 	    dcrop->height == input_win->height &&
-	    dcrop->left == 0 && dcrop->top == 0) {
+	    dcrop->left == 0 && dcrop->top == 0 &&
+	    !dev->hw_dev->unite) {
 		rkisp_disable_dcrop(stream, async);
 		v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
 			 "stream %d crop disabled\n", stream->id);
@@ -704,29 +705,29 @@ static int mp_config_mi(struct rkisp_stream *stream)
 	/* in bytes for isp32 */
 	if (dev->isp_ver == ISP_V32 &&
 	    stream->out_isp_fmt.write_format != MI_CTRL_MP_WRITE_YUVINT)
-		rkisp_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false);
+		rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false);
 	val /= DIV_ROUND_UP(fmt->bpp[0], 8);
 	/* in pixels for isp32 lite */
 	if (dev->isp_ver == ISP_V32_L)
-		rkisp_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false);
+		rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false);
 	val *= height;
-	rkisp_write(dev, stream->config->mi.y_pic_size, val, false);
+	rkisp_unite_write(dev, stream->config->mi.y_pic_size, val, false);
 	val = out_fmt->plane_fmt[0].bytesperline * height;
-	rkisp_write(dev, stream->config->mi.y_size_init, val, false);
+	rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false);

 	val = out_fmt->plane_fmt[1].sizeimage;
 	if (dev->cap_dev.wrap_line)
 		val = out_fmt->plane_fmt[0].bytesperline * height / 2;
-	rkisp_write(dev, stream->config->mi.cb_size_init, val, false);
+	rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false);

 	val = out_fmt->plane_fmt[2].sizeimage;
 	if (dev->cap_dev.wrap_line)
 		val = out_fmt->plane_fmt[0].bytesperline * height / 2;
-	rkisp_write(dev, stream->config->mi.cr_size_init, val, false);
+	rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false);

 	val = stream->out_isp_fmt.uv_swap ? ISP3X_MI_XTD_FORMAT_MP_UV_SWAP : 0;
 	mask = ISP3X_MI_XTD_FORMAT_MP_UV_SWAP;
-	rkisp_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false);
+	rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false);

 	mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_MP_YUV_MODE;
 	val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask;
@@ -738,24 +739,24 @@ static int mp_config_mi(struct rkisp_stream *stream)
 		val |= ISP3X_SEPERATE_YUV_CFG;
 	else
 		val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_MP_YUV_MODE;
-	rkisp_write(dev, ISP3X_MPFBC_CTRL, val, false);
+	rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false);

 	val = stream->out_isp_fmt.output_format;
-	rkisp_write(dev, ISP32_MI_MP_WR_CTRL, val, false);
+	rkisp_unite_write(dev, ISP32_MI_MP_WR_CTRL, val, false);

 	val = calc_burst_len(stream) | CIF_MI_CTRL_INIT_BASE_EN |
 		CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_MP_AUTOUPDATE_ENABLE |
 		stream->out_isp_fmt.write_format;
 	mask = GENMASK(19, 16) | MI_CTRL_MP_FMT_MASK;
-	rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false);
+	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false);

 	mi_frame_end_int_enable(stream);
 	/* set up first buffer */
 	mi_frame_end(stream, FRAME_INIT);

-	rkisp_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
-	rkisp_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
-	rkisp_write(dev, stream->config->mi.cr_offs_cnt_init, 0, false);
+	rkisp_unite_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
+	rkisp_unite_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
+	rkisp_unite_write(dev, stream->config->mi.cr_offs_cnt_init, 0, false);
 	return 0;
 }

@@ -805,21 +806,21 @@ static int sp_config_mi(struct rkisp_stream *stream)
 	* memory plane formats, so calculate the size explicitly.
 	*/
 	val = stream->u.sp.y_stride;
-	rkisp_write(dev, ISP3X_MI_SP_WR_Y_LLENGTH, val, false);
+	rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_LLENGTH, val, false);
 	val *= out_fmt->height;
-	rkisp_write(dev, stream->config->mi.y_pic_size, val, false);
+	rkisp_unite_write(dev, stream->config->mi.y_pic_size, val, false);
 	val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height;
-	rkisp_write(dev, stream->config->mi.y_size_init, val, false);
+	rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false);

 	val = out_fmt->plane_fmt[1].sizeimage;
-	rkisp_write(dev, stream->config->mi.cb_size_init, val, false);
+	rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false);

 	val = out_fmt->plane_fmt[2].sizeimage;
-	rkisp_write(dev, stream->config->mi.cr_size_init, val, false);
+	rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false);

 	val = stream->out_isp_fmt.uv_swap ? ISP3X_MI_XTD_FORMAT_SP_UV_SWAP : 0;
 	mask = ISP3X_MI_XTD_FORMAT_SP_UV_SWAP;
-	rkisp_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false);
+	rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false);

 	mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_SP_YUV_MODE;
 	val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask;
@@ -831,22 +832,22 @@ static int sp_config_mi(struct rkisp_stream *stream)
 		val |= ISP3X_SEPERATE_YUV_CFG;
 	else
 		val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_SP_YUV_MODE;
-	rkisp_write(dev, ISP3X_MPFBC_CTRL, val, false);
+	rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false);

 	val = calc_burst_len(stream) | CIF_MI_CTRL_INIT_BASE_EN |
 		CIF_MI_CTRL_INIT_OFFSET_EN | stream->out_isp_fmt.write_format |
 		sp_in_fmt | stream->out_isp_fmt.output_format |
 		CIF_MI_SP_AUTOUPDATE_ENABLE;
 	mask = GENMASK(19, 16) | MI_CTRL_SP_FMT_MASK;
-	rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false);
+	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false);

 	mi_frame_end_int_enable(stream);
 	/* set up first buffer */
 	mi_frame_end(stream, FRAME_INIT);

-	rkisp_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
-	rkisp_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
-	rkisp_write(dev, stream->config->mi.cr_offs_cnt_init, 0, false);
+	rkisp_unite_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
+	rkisp_unite_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
+	rkisp_unite_write(dev, stream->config->mi.cr_offs_cnt_init, 0, false);
 	return 0;
 }

@@ -864,18 +865,18 @@ static int bp_config_mi(struct rkisp_stream *stream)
 	val = out_fmt->plane_fmt[0].bytesperline;
 	/* in bytes */
 	if (stream->out_isp_fmt.write_format != ISP3X_BP_FORMAT_INT)
-		rkisp_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false);
+		rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false);
 	val /= DIV_ROUND_UP(fmt->bpp[0], 8);
 	/* in pixels */
 	if (stream->out_isp_fmt.write_format == ISP3X_BP_FORMAT_INT)
-		rkisp_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false);
+		rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false);
 	val *= out_fmt->height;
-	rkisp_write(dev, stream->config->mi.y_pic_size, val, false);
+	rkisp_unite_write(dev, stream->config->mi.y_pic_size, val, false);
 	val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height;
-	rkisp_write(dev, stream->config->mi.y_size_init, val, false);
+	rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false);

 	val = out_fmt->plane_fmt[1].sizeimage;
-	rkisp_write(dev, stream->config->mi.cb_size_init, val, false);
+	rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false);

 	mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_BP_YUV_MODE;
 	val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask;
@@ -885,15 +886,15 @@ static int bp_config_mi(struct rkisp_stream *stream)
 		val |= ISP3X_SEPERATE_YUV_CFG;
 	else
 		val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_BP_YUV_MODE;
-	rkisp_write(dev, ISP3X_MPFBC_CTRL, val, false);
+	rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false);
 	val = CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN;
-	rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false);
+	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false);
 	mi_frame_end_int_enable(stream);
 	/* set up first buffer */
 	mi_frame_end(stream, FRAME_INIT);

-	rkisp_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
-	rkisp_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
+	rkisp_unite_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
+	rkisp_unite_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
 	return 0;
 }

@@ -906,27 +907,27 @@ static int ds_config_mi(struct rkisp_stream *stream)

 	val = out_fmt->plane_fmt[0].bytesperline;
 	if (stream->out_isp_fmt.write_format != ISP3X_BP_FORMAT_INT)
-		rkisp_write(dev, stream->config->mi.length, val, false);
+		rkisp_unite_write(dev, stream->config->mi.length, val, false);
 	val /= DIV_ROUND_UP(fmt->bpp[0], 8);
 	if (stream->out_isp_fmt.write_format == ISP3X_BP_FORMAT_INT)
-		rkisp_write(dev, stream->config->mi.length, val, false);
+		rkisp_unite_write(dev, stream->config->mi.length, val, false);
 	val *= out_fmt->height;
-	rkisp_write(dev, stream->config->mi.y_pic_size, val, false);
+	rkisp_unite_write(dev, stream->config->mi.y_pic_size, val, false);
 	val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height;
-	rkisp_write(dev, stream->config->mi.y_size_init, val, false);
+	rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false);

 	val = out_fmt->plane_fmt[1].sizeimage;
-	rkisp_write(dev, stream->config->mi.cb_size_init, val, false);
+	rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false);

 	val = CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN;
-	rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false);
+	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false);

 	mi_frame_end_int_enable(stream);

 	mi_frame_end(stream, FRAME_INIT);

-	rkisp_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
-	rkisp_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
+	rkisp_unite_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
+	rkisp_unite_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
 	return 0;
 }

@@ -940,7 +941,7 @@ static void mp_enable_mi(struct rkisp_stream *stream)

 	if (isp_fmt->fmt_type == FMT_BAYER)
 		val = CIF_MI_CTRL_RAW_ENABLE;
-	rkisp_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false);
+	rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false);

 	/* enable bpds path output */
 	if (t->streaming && !t->is_pause)
@@ -957,7 +958,7 @@ static void sp_enable_mi(struct rkisp_stream *stream)
 	if (fmt->fmt_type == FMT_RGB &&
 	    dev->isp_sdev.quantization == V4L2_QUANTIZATION_FULL_RANGE)
 		val |= mask;
-	rkisp_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false);
+	rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false);
 }

 static void bp_enable_mi(struct rkisp_stream *stream)
@@ -969,7 +970,7 @@ static void bp_enable_mi(struct rkisp_stream *stream)
 		  stream->out_isp_fmt.output_format |
 		  ISP3X_BP_ENABLE | ISP3X_BP_AUTO_UPD;

-	rkisp_write(stream->ispdev, ISP3X_MI_BP_WR_CTRL, val, false);
+	rkisp_unite_write(stream->ispdev, ISP3X_MI_BP_WR_CTRL, val, false);

 	/* enable bpds path output */
 	if (t->streaming && !t->is_pause)
@@ -982,7 +983,7 @@ static void ds_enable_mi(struct rkisp_stream *stream)
 		  stream->out_isp_fmt.output_format |
 		  ISP32_DS_ENABLE | ISP32_DS_AUTO_UPD;

-	rkisp_write(stream->ispdev, stream->config->mi.ctrl, val, false);
+	rkisp_unite_write(stream->ispdev, stream->config->mi.ctrl, val, false);
 }

 static void mp_disable_mi(struct rkisp_stream *stream)
@@ -991,8 +992,7 @@ static void mp_disable_mi(struct rkisp_stream *stream)
 	struct rkisp_stream *t = &dev->cap_dev.stream[stream->conn_id];
 	u32 mask = CIF_MI_CTRL_MP_ENABLE | CIF_MI_CTRL_RAW_ENABLE;

-	rkisp_set_bits(dev, 0x1814, 0, BIT(0), false);
-	rkisp_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, false);
+	rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, false);

 	/* disable mpds path output */
 	if (!stream->is_pause && t->streaming)
@@ -1001,7 +1001,7 @@ static void mp_disable_mi(struct rkisp_stream *stream)

 static void sp_disable_mi(struct rkisp_stream *stream)
 {
-	rkisp_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, CIF_MI_CTRL_SP_ENABLE, false);
+	rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, CIF_MI_CTRL_SP_ENABLE, false);
 }

 static void bp_disable_mi(struct rkisp_stream *stream)
@@ -1009,7 +1009,7 @@ static void bp_disable_mi(struct rkisp_stream *stream)
 	struct rkisp_device *dev = stream->ispdev;
 	struct rkisp_stream *t = &dev->cap_dev.stream[stream->conn_id];

-	rkisp_clear_bits(stream->ispdev, ISP3X_MI_BP_WR_CTRL, ISP3X_BP_ENABLE, false);
+	rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_BP_WR_CTRL, ISP3X_BP_ENABLE, false);

 	/* disable bpds path output */
 	if (!stream->is_pause && t->streaming)
@@ -1018,7 +1018,7 @@ static void bp_disable_mi(struct rkisp_stream *stream)

 static void ds_disable_mi(struct rkisp_stream *stream)
 {
-	rkisp_clear_bits(stream->ispdev, stream->config->mi.ctrl, ISP32_DS_ENABLE, false);
+	rkisp_unite_clear_bits(stream->ispdev, stream->config->mi.ctrl, ISP32_DS_ENABLE, false);
 }

 static void update_mi(struct rkisp_stream *stream)
@@ -1048,6 +1048,25 @@ static void update_mi(struct rkisp_stream *stream)
 			rkisp_write(dev, reg, val, false);
 		}

+		if (dev->hw_dev->unite) {
+			reg = stream->config->mi.y_base_ad_init;
+			val = stream->next_buf->buff_addr[RKISP_PLANE_Y];
+			val += ((stream->out_fmt.width / 2) & ~0xf);
+			rkisp_next_write(dev, reg, val, false);
+
+			reg = stream->config->mi.cb_base_ad_init;
+			val = stream->next_buf->buff_addr[RKISP_PLANE_CB];
+			val += ((stream->out_fmt.width / 2) & ~0xf);
+			rkisp_next_write(dev, reg, val, false);
+
+			if (is_cr_cfg) {
+				reg = stream->config->mi.cr_base_ad_init;
+				val = stream->next_buf->buff_addr[RKISP_PLANE_CR];
+				val += ((stream->out_fmt.width / 2) & ~0xf);
+				rkisp_next_write(dev, reg, val, false);
+			}
+		}
+
 		if (stream->is_pause) {
 			/* single sensor mode with pingpong buffer:
 			 * if mi on, addr will auto update at frame end
@@ -1141,9 +1160,9 @@ static int set_mirror_flip(struct rkisp_stream *stream)

 	stream->is_mf_upd = false;
 	if (dev->cap_dev.is_mirror)
-		rkisp_set_bits(dev, ISP3X_ISP_CTRL0, 0, ISP32_MIR_ENABLE, false);
+		rkisp_unite_set_bits(dev, ISP3X_ISP_CTRL0, 0, ISP32_MIR_ENABLE, false);
 	else
-		rkisp_clear_bits(dev, ISP3X_ISP_CTRL0, ISP32_MIR_ENABLE, false);
+		rkisp_unite_clear_bits(dev, ISP3X_ISP_CTRL0, ISP32_MIR_ENABLE, false);

 	switch (stream->id) {
 	case RKISP_STREAM_SP:
@@ -1169,9 +1188,9 @@ static int set_mirror_flip(struct rkisp_stream *stream)

 	tmp = rkisp_read_reg_cache(dev, ISP32_MI_WR_VFLIP_CTRL);
 	if (stream->is_flip)
-		rkisp_write(dev, ISP32_MI_WR_VFLIP_CTRL, tmp | val, false);
+		rkisp_unite_write(dev, ISP32_MI_WR_VFLIP_CTRL, tmp | val, false);
 	else
-		rkisp_write(dev, ISP32_MI_WR_VFLIP_CTRL, tmp & ~val, false);
+		rkisp_unite_write(dev, ISP32_MI_WR_VFLIP_CTRL, tmp & ~val, false);
 	return 0;
 }

@@ -2268,6 +2287,12 @@ void rkisp_mi_v32_isr(u32 mis_val, struct rkisp_device *dev)
 	v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
 		 "mi isr:0x%x\n", mis_val);

+	if (dev->hw_dev->unite == ISP_UNITE_ONE &&
+	    dev->unite_index == ISP_UNITE_LEFT) {
+		rkisp_write(dev, ISP3X_MI_ICR, mis_val, true);
+		goto end;
+	}
+
 	for (i = 0; i < RKISP_MAX_STREAM; ++i) {
 		stream = &dev->cap_dev.stream[i];

@@ -2310,7 +2335,7 @@ void rkisp_mi_v32_isr(u32 mis_val, struct rkisp_device *dev)
 			mi_frame_end(stream, FRAME_IRQ);
 		}
 	}
-
+end:
 	if (mis_val & ISP3X_MI_MP_FRAME) {
 		stream = &dev->cap_dev.stream[RKISP_STREAM_MP];
 		if (!stream->streaming)
--- a/drivers/media/platform/rockchip/isp/common.c
+++ b/drivers/media/platform/rockchip/isp/common.c
@@ -6,6 +6,7 @@
 #include <linux/of_platform.h>
 #include <linux/slab.h>
 #include "dev.h"
+#include "hw.h"
 #include "isp_ispp.h"
 #include "regs.h"

@@ -36,6 +37,8 @@ void rkisp_next_write(struct rkisp_device *dev, u32 reg, u32 val, bool is_direct
 	*flag = SW_REG_CACHE;
 	if (dev->hw_dev->is_single || is_direct) {
 		*flag = SW_REG_CACHE_SYNC;
+		if (dev->hw_dev->unite == ISP_UNITE_ONE)
+			return;
 		writel(val, dev->hw_dev->base_next_addr + reg);
 	}
 }
@@ -166,13 +169,16 @@ void rkisp_update_regs(struct rkisp_device *dev, u32 start, u32 end)
 				continue;
 		}

+		if (hw->unite == ISP_UNITE_ONE && dev->unite_index == ISP_UNITE_RIGHT)
+			val = dev->sw_base_addr + i + RKISP_ISP_SW_MAX_SIZE;
+
 		if (*flag == SW_REG_CACHE) {
 			if ((i == ISP3X_MAIN_RESIZE_CTRL ||
 			     i == ISP32_BP_RESIZE_CTRL ||
 			     i == ISP3X_SELF_RESIZE_CTRL) && *val == 0)
 				*val = CIF_RSZ_CTRL_CFG_UPD;
 			writel(*val, base + i);
-			if (hw->is_unite) {
+			if (hw->unite == ISP_UNITE_TWO) {
 				val = dev->sw_base_addr + i + RKISP_ISP_SW_MAX_SIZE;
 				if ((i == ISP3X_MAIN_RESIZE_CTRL ||
 				     i == ISP32_BP_RESIZE_CTRL ||
--- a/Show More
+++ b/Show More