From 7168fdec082c595deaea20a4b73352a693b275fd Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Fri, 12 May 2023 15:58:23 +0800 Subject: [PATCH 01/17] drm/bridge: dw-hdmi-qp: Don't read edid again if edid is exist Reading edid only after plug in or resume. Signed-off-by: Algea Cao Change-Id: I0b69a26d9caeebf81f360bc8674aeacf964fd807 --- drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c index 5f0958fbd8cd..906f0f628c2a 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -2261,6 +2261,7 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector) struct drm_display_mode *mode; struct drm_display_info *info = &connector->display_info; void *data = hdmi->plat_data->phy_data; + struct drm_property_blob *edid_blob_ptr = connector->edid_blob_ptr; int i, ret = 0; if (hdmi->plat_data->right && hdmi->plat_data->right->next_bridge) { @@ -2282,7 +2283,17 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector) return 0; memset(metedata, 0, sizeof(*metedata)); - edid = drm_get_edid(connector, hdmi->ddc); + + if (edid_blob_ptr && edid_blob_ptr->length) { + edid = kmalloc(edid_blob_ptr->length, GFP_KERNEL); + if (!edid) + return -ENOMEM; + memcpy(edid, edid_blob_ptr->data, edid_blob_ptr->length); + } else { + edid = drm_get_edid(connector, hdmi->ddc); + hdmi->hdcp_caps = dw_hdmi_qp_hdcp_capable(hdmi); + } + if (edid) { dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", edid->width_cm, edid->height_cm); @@ -2310,8 +2321,10 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector) else if (hdmi->plat_data->right) secondary = hdmi->plat_data->right; - if (!secondary) + if (!secondary) { + kfree(edid); return -ENOMEM; + } secondary_data = secondary->plat_data->phy_data; list_for_each_entry(mode, &connector->probed_modes, head) @@ -4049,6 +4062,7 @@ void dw_hdmi_qp_suspend(struct device *dev, struct dw_hdmi_qp *hdmi) disable_irq(hdmi->earc_irq); pinctrl_pm_select_sleep_state(dev); + drm_connector_update_edid_property(&hdmi->connector, NULL); } EXPORT_SYMBOL_GPL(dw_hdmi_qp_suspend); From f731199376342134c3ed7c1f7cb11abbbe793f89 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Fri, 1 Sep 2023 11:15:04 +0800 Subject: [PATCH 02/17] clk: rockchip: rk3568: Add protect clocks Change-Id: I21571988341288f98444719694c2cc195cb2f313 Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3568.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 5c10de93dc53..79365eb18af3 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -1618,6 +1618,16 @@ static void rk3568_dump_cru(void) } } +static int protect_clocks[] = { + ACLK_VO, + HCLK_VO, + ACLK_VOP, + HCLK_VOP, + DCLK_VOP0, + DCLK_VOP1, + DCLK_VOP2, +}; + static void __init rk3568_pmu_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; @@ -1695,6 +1705,8 @@ static void __init rk3568_clk_init(struct device_node *np) if (!rk_dump_cru) rk_dump_cru = rk3568_dump_cru; + + rockchip_clk_protect(ctx, protect_clocks, ARRAY_SIZE(protect_clocks)); } CLK_OF_DECLARE(rk3568_cru, "rockchip,rk3568-cru", rk3568_clk_init); From d0ad961087a3c1da693765a5b2173134d416c4ba Mon Sep 17 00:00:00 2001 From: Jun Zeng Date: Fri, 1 Sep 2023 12:00:55 +0800 Subject: [PATCH 03/17] ASoC: codecs: Add tda7803 amplifier driver support Add driver to support TDA7803 amplifier devices. Change-Id: Iceb83a801d7a9f4a7faa7b7617be63f93c57be76 Signed-off-by: Jun Zeng --- sound/soc/codecs/Kconfig | 6 ++ sound/soc/codecs/Makefile | 2 + sound/soc/codecs/tda7803.c | 171 +++++++++++++++++++++++++++++++++++++ sound/soc/codecs/tda7803.h | 138 ++++++++++++++++++++++++++++++ 4 files changed, 317 insertions(+) create mode 100644 sound/soc/codecs/tda7803.c create mode 100644 sound/soc/codecs/tda7803.h diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 8121978a31a8..cb3b581dbfb5 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -216,6 +216,7 @@ config SND_SOC_ALL_CODECS imply SND_SOC_TAS5720 imply SND_SOC_TAS6424 imply SND_SOC_TDA7419 + imply SND_SOC_TDA7803 imply SND_SOC_TFA9879 imply SND_SOC_TLV320ADCX140 imply SND_SOC_TLV320AIC23_I2C @@ -1442,6 +1443,11 @@ config SND_SOC_TDA7419 depends on I2C select REGMAP_I2C +config SND_SOC_TDA7803 + tristate "ST TDA7803 audio processor" + depends on I2C + select REGMAP_I2C + config SND_SOC_TFA9879 tristate "NXP Semiconductors TFA9879 amplifier" depends on I2C diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 20ee39074e71..fd3e6861e75c 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -232,6 +232,7 @@ snd-soc-tas571x-objs := tas571x.o snd-soc-tas5720-objs := tas5720.o snd-soc-tas6424-objs := tas6424.o snd-soc-tda7419-objs := tda7419.o +snd-soc-tda7803-objs := tda7803.o snd-soc-tas2770-objs := tas2770.o snd-soc-tfa9879-objs := tfa9879.o snd-soc-tlv320aic23-objs := tlv320aic23.o @@ -560,6 +561,7 @@ obj-$(CONFIG_SND_SOC_TAS571X) += snd-soc-tas571x.o obj-$(CONFIG_SND_SOC_TAS5720) += snd-soc-tas5720.o obj-$(CONFIG_SND_SOC_TAS6424) += snd-soc-tas6424.o obj-$(CONFIG_SND_SOC_TDA7419) += snd-soc-tda7419.o +obj-$(CONFIG_SND_SOC_TDA7803) += snd-soc-tda7803.o obj-$(CONFIG_SND_SOC_TAS2770) += snd-soc-tas2770.o obj-$(CONFIG_SND_SOC_TFA9879) += snd-soc-tfa9879.o obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o diff --git a/sound/soc/codecs/tda7803.c b/sound/soc/codecs/tda7803.c new file mode 100644 index 000000000000..b75459180f0b --- /dev/null +++ b/sound/soc/codecs/tda7803.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "tda7803.h" + +#define TDA7803_SAMPLE_RATE \ + (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \ + SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) + +struct tda7803_priv { + struct regmap *regmap; + u32 input_format; +}; + +static int tda7803_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct tda7803_priv *tda7803 = snd_soc_component_get_drvdata(component); + struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); + struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0); + int val = 0; + + snd_soc_component_write(component, TDA7803_REG2, DIGITAL_MUTE_OFF | + CH2_4_UMUTE | CH1_3_UMUTE | + MUTE_TIME_SETTING_1_45MS); + snd_soc_component_write(component, TDA7803_REG7, AMPLIEFIR_SWITCH_ON); + + switch (tda7803->input_format) { + case 0: + val = INPUT_FORMAT_TDM_8CH_MODEL1; + break; + case 1: + val = INPUT_FORMAT_TDM_8CH_MODEL2; + break; + default: + return -EINVAL; + } + + snd_soc_dai_set_fmt(codec_dai, val); + + return 0; +} + +static int tda7803_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + int val = 0; + + switch (params_rate(params)) { + case 44100: + val = SAMPLE_FREQUENCY_RANGE_44100HZ; + break; + case 48000: + val = SAMPLE_FREQUENCY_RANGE_48000HZ; + break; + case 96000: + val = SAMPLE_FREQUENCY_RANGE_96000HZ; + break; + case 192000: + val = SAMPLE_FREQUENCY_RANGE_192000HZ; + break; + default: + return -EINVAL; + } + + snd_soc_component_write(component, TDA7803_REG3, val); + + return 0; +} + +static int tda7803_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct snd_soc_component *component = dai->component; + + snd_soc_component_write(component, TDA7803_REG3, fmt); + + return 0; +} + +static const struct snd_soc_dai_ops tda7803_ops = { + .startup = tda7803_startup, + .hw_params = tda7803_hw_params, + .set_fmt = tda7803_set_fmt, +}; + +static struct snd_soc_dai_driver tda7803_dai = { + .name = "tda7803-hifi", + .playback = { + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 8, + .rates = TDA7803_SAMPLE_RATE, + .formats = SNDRV_PCM_FMTBIT_S32_LE | + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = &tda7803_ops, +}; + +static const struct snd_soc_component_driver soc_codec_dev_tda7803 = { + .name = "tda7803", +}; + +static const struct regmap_config tda7803_i2c_regmap = { + .reg_bits = 8, + .val_bits = 8, + .max_register = TDA7803_REGMAX, + .cache_type = REGCACHE_RBTREE, +}; + +static int tda7803_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct tda7803_priv *tda7803; + int val; + + tda7803 = devm_kzalloc(&i2c->dev, sizeof(*tda7803), GFP_KERNEL); + if (!tda7803) + return -ENOMEM; + + i2c_set_clientdata(i2c, tda7803); + + tda7803->regmap = devm_regmap_init_i2c(i2c, &tda7803_i2c_regmap); + if (IS_ERR(tda7803->regmap)) + return PTR_ERR(tda7803->regmap); + + if (!device_property_read_u32(&i2c->dev, "st,tda7803-format", &val)) + tda7803->input_format = val; + + return devm_snd_soc_register_component(&i2c->dev, + &soc_codec_dev_tda7803, + &tda7803_dai, 1); +} + +static const struct i2c_device_id tda7803_i2c_id[] = { + { "tda7803", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, tda7803_i2c_id); + +static const struct of_device_id tda7803_of_match[] = { + { .compatible = "st,tda7803" }, + { }, +}; + +static struct i2c_driver tda7803_i2c_driver = { + .driver = { + .name = "tda7803", + .of_match_table = of_match_ptr(tda7803_of_match), + }, + .probe = tda7803_i2c_probe, + .id_table = tda7803_i2c_id, +}; +module_i2c_driver(tda7803_i2c_driver); + +MODULE_AUTHOR("Jun Zeng "); +MODULE_DESCRIPTION("TDA7803 audio processor driver"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/tda7803.h b/sound/soc/codecs/tda7803.h new file mode 100644 index 000000000000..54a7b610722f --- /dev/null +++ b/sound/soc/codecs/tda7803.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#ifndef __TDA7803_H__ +#define __TDA7803_H__ + +/* tda7803 registers space*/ +#define TDA7803_REG0 (0x00) +#define CH1_AMP_SBI_MODE (0x00 << 0) +#define CH1_AMP_ABI_MODE (0x01 << 0) +#define CH2_AMP_SBI_MODE (0x00 << 1) +#define CH2_AMP_ABI_MODE (0x01 << 1) +#define CH3_AMP_SBI_MODE (0x00 << 2) +#define CH3_AMP_ABI_MODE (0x01 << 2) +#define CH4_AMP_SBI_MODE (0x00 << 3) +#define CH4_AMP_ABI_MODE (0x01 << 3) +#define CH1_TRI_MODE_OFF (0x00 << 4) +#define CH1_TRI_MODE_ON (0x01 << 4) +#define CH2_TRI_MODE_OFF (0x00 << 5) +#define CH2_TRI_MODE_ON (0x01 << 5) +#define CH3_TRI_MODE_OFF (0x00 << 6) +#define CH3_TRI_MODE_ON (0x01 << 6) +#define CH4_TRI_MODE_OFF (0x00 << 7) +#define CH4_TRI_MODE_ON (0x01 << 7) + +#define TDA7803_REG1 (0x01) +#define CH2_4_GAIN_GV1 (0x00 << 0) +#define CH2_4_GAIN_GV2 (0x01 << 0) +#define CH2_4_GAIN_GV3 (0x02 << 0) +#define CH2_4_GAIN_GV4 (0x03 << 0) +#define CH1_3_GAIN_GV1 (0x00 << 2) +#define CH1_3_GAIN_GV2 (0x01 << 2) +#define CH1_3_GAIN_GV3 (0x02 << 2) +#define CH1_3_GAIN_GV4 (0x03 << 2) +#define GAIN_SELECT_NO (0x00 << 4) +#define GAIN_SELECT_6DB (0x01 << 4) +#define GAIN_SELECT_12DB (0x02 << 4) +#define GAIN_SELECT_NOT_USED (0x03 << 4) +#define IMPEDANCE_OPTIMIZER_REAR_2OHM (0x00 << 6) +#define IMPEDANCE_OPTIMIZER_REAR_4OHM (0x01 << 6) +#define IMPEDANCE_OPTIMIZER_FRONT_2OHM (0x00 << 7) +#define IMPEDANCE_OPTIMIZER_FRONT_4OHM (0x01 << 7) + +#define TDA7803_REG2 (0x02) +#define LOW_BATTERY_MUTE_THRESHOLD_1 (0x00 << 0) +#define LOW_BATTERY_MUTE_THRESHOLD_2 (0x01 << 0) +#define DIGITAL_MUTE_ON (0x00 << 2) +#define DIGITAL_MUTE_OFF (0x01 << 2) +#define CH2_4_MUTE (0x00 << 3) +#define CH2_4_UMUTE (0x01 << 3) +#define CH1_3_MUTE (0x00 << 4) +#define CH1_3_UMUTE (0x01 << 4) +#define MUTE_TIME_SETTING_1_45MS (0x00 << 5) +#define MUTE_TIME_SETTING_5_8MS (0x01 << 5) +#define MUTE_TIME_SETTING_11_6MS (0x02 << 5) +#define MUTE_TIME_SETTING_23_2MS (0x03 << 5) +#define MUTE_TIME_SETTING_46_4MS (0x04 << 5) +#define MUTE_TIME_SETTING_92_8MS (0x05 << 5) +#define MUTE_TIME_SETTING_185_5MS (0x06 << 5) +#define MUTE_TIME_SETTING_371_1MS (0x07 << 5) + +#define TDA7803_REG3 (0x03) +#define HIGH_PASS_FILTER_DISABLE (0x00 << 0) +#define HIGH_PASS_FILTER_ENABLE (0x01 << 0) +#define INPUT_OFFSET_DETECTION_DIS (0x00 << 1) +#define INPUT_OFFSET_DETECTION_EN (0x01 << 1) +#define NOISE_GATING_FUNCTION_EN (0x00 << 2) +#define NOISE_GATING_FUNCTION_DIS (0x01 << 2) +#define INPUT_FORMAT_I2S_STD (0x00 << 3) +#define INPUT_FORMAT_TDM_4CH (0x01 << 3) +#define INPUT_FORMAT_TDM_8CH_MODEL1 (0x02 << 3) +#define INPUT_FORMAT_TDM_8CH_MODEL2 (0x03 << 3) +#define INPUT_FORMAT_TDM_16CH_MODEL1 (0x04 << 3) +#define INPUT_FORMAT_TDM_16CH_MODEL2 (0x05 << 3) +#define INPUT_FORMAT_TDM_16CH_MODEL3 (0x06 << 3) +#define INPUT_FORMAT_TDM_16CH_MODEL4 (0x07 << 3) +#define SAMPLE_FREQUENCY_RANGE_44100HZ (0x00 << 6) +#define SAMPLE_FREQUENCY_RANGE_48000HZ (0x01 << 6) +#define SAMPLE_FREQUENCY_RANGE_96000HZ (0x02 << 6) +#define SAMPLE_FREQUENCY_RANGE_192000HZ (0x03 << 6) + +#define TDA7803_REG4 (0x04) +#define DIAGNOSTIC_MODE_DISABLE (0x00 << 0) +#define DIAGNOSTIC_MODE_ENABLE (0x01 << 0) +#define CH2_4_SPEAKER_MODE (0x00 << 1) +#define CH2_4_LINE_DRIVER_MODE (0x01 << 1) +#define CH1_3_SPEAKER_MODE (0x00 << 2) +#define CH1_3_LINE_DRIVER_MODE (0x01 << 2) +#define DIAGNOSTIC_DISABLE (0X00 << 3) +#define DIAGNOSTIC_ENABLE (0X01 << 3) +#define DIAGNOSTIC_CURRENT_THRESHOLD_HIGH (0X00 << 4) +#define DIAGNOSTIC_CURRENT_THRESHOLD_LOW (0X01 << 4) +#define OFFSET_INFORMATION_YES (0X00 << 5) +#define OFFSET_INFORMATION_NO (0X01 << 5) +#define SHORT_FAULT_INFORMATION_YES (0X00 << 6) +#define SHORT_FAULT_INFORMATION_NO (0X01 << 6) + +#define TDA7803_REG5 (0x05) +#define CAPABILITY_ENHANCER_DISABLE (0x00 << 1) +#define CAPABILITY_ENHANCER_ENABLE (0x0F << 1) +#define THERMAL_THRESHOLD_DEFAULT (0x00 << 6) +#define THERMAL_THRESHOLD_TW_NEGATIVE_10 (0x01 << 6) +#define THERMAL_THRESHOLD_TW_NEGATIVE_20 (0x02 << 6) + +#define TDA7803_REG6 (0x06) +#define PARALLEL_MODE_CONFIG_MODE_1 (0x00 << 2) +#define PARALLEL_MODE_CONFIG_MODE_2 (0x01 << 2) +#define PARALLEL_MODE_CONFIG_MODE_3 (0x02 << 2) +#define PARALLEL_MODE_CONFIG_MODE_4 (0x03 << 2) +#define DIAGNOSITC_PULSE_STRETCH_MODE_1 (0x00 << 5) +#define DIAGNOSITC_PULSE_STRETCH_MODE_2 (0x01 << 5) +#define DIAGNOSITC_PULSE_STRETCH_MODE_3 (0x02 << 5) +#define DIAGNOSITC_PULSE_STRETCH_MODE_4 (0x03 << 5) +#define DIAGNOSITC_PULSE_STRETCH_MODE_5 (0x04 << 5) +#define DIAGNOSITC_PULSE_STRETCH_DEFAULT (0x05 << 5) + +#define TDA7803_REG7 (0x07) +#define AMPLIEFIR_SWITCH_OFF (0x00 << 0) +#define AMPLIEFIR_SWITCH_ON (0x01 << 0) +#define CLIPP_LEVEL_1_REAR_CHANNELS2_4 (0x00 << 1) +#define CLIPP_LEVEL_2_REAR_CHANNELS2_4 (0x01 << 1) +#define CLIPP_LEVEL_3_REAR_CHANNELS2_4 (0x02 << 1) +#define NOT_CLIPP_FOR_REAR_CHANNELS2_4 (0x03 << 1) +#define CLIPP_LEVEL_1_REAR_CHANNELS1_3 (0x00 << 3) +#define CLIPP_LEVEL_2_REAR_CHANNELS1_3 (0x01 << 3) +#define CLIPP_LEVEL_3_REAR_CHANNELS1_3 (0x02 << 3) +#define NOT_CLIPP_FOR_REAR_CHANNELS1_3 (0x03 << 3) +#define TEMPERATURE_WARNING_TW1 (0x00 << 5) +#define TEMPERATURE_WARNING_TW2 (0x01 << 5) +#define TEMPERATURE_WARNING_TW3 (0x02 << 5) +#define TEMPERATURE_WARNING_TW4 (0x03 << 5) +#define NOT_TEMPERATURE_WARNING (0x04 << 5) + +#define TDA7803_REGMAX (0x08) +#endif /* __TDA7803_H__ */ From 0fc248ba82b1a3107c41fc071b5220e1971c53d4 Mon Sep 17 00:00:00 2001 From: Weiwen Chen Date: Mon, 28 Aug 2023 17:24:04 +0800 Subject: [PATCH 04/17] ARM: configs: rockchip: Add rv1106-tb-nofastae.config Updated by: make ARCH=arm rv1106_defconfig rv1106-tb.config rv1106-battery-ipc.config cp .config rv1106.config make ARCH=arm rv1106_defconfig rv1106-tb.config rv1106-battery-ipc.config rv1106-tb-nofastae.config make ARCH=arm menuconfig ./scripts/diffconfig -m rv1106.config .config > arch/arm/configs/rv1106-tb-nofastae.config Signed-off-by: Weiwen Chen Change-Id: I12373396d5e06dae95da691a7a0889d23b3f263e --- arch/arm/configs/rv1106-tb-nofastae.config | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 arch/arm/configs/rv1106-tb-nofastae.config diff --git a/arch/arm/configs/rv1106-tb-nofastae.config b/arch/arm/configs/rv1106-tb-nofastae.config new file mode 100644 index 000000000000..c0142d4101f3 --- /dev/null +++ b/arch/arm/configs/rv1106-tb-nofastae.config @@ -0,0 +1,3 @@ +# CONFIG_ROCKCHIP_MBOX is not set +# CONFIG_ROCKCHIP_THUNDER_BOOT_SERVICE is not set +# CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP is not set From 188bdeb4619d2af6fe14a7eb481ae3f11377d5e6 Mon Sep 17 00:00:00 2001 From: Weiwen Chen Date: Sat, 26 Aug 2023 14:44:47 +0800 Subject: [PATCH 05/17] ARM: dts: rockchip: Add rv1106 nofastae dtsi Signed-off-by: Weiwen Chen Change-Id: Id240c4238410a18dff6c14c129063ffbd10b7e37 --- .../arm/boot/dts/rv1106-tb-nofastae-emmc.dtsi | 31 ++++++++++++++++ .../boot/dts/rv1106-tb-nofastae-spi-nor.dtsi | 19 ++++++++++ arch/arm/boot/dts/rv1106-tb-nofastae.dtsi | 35 +++++++++++++++++++ 3 files changed, 85 insertions(+) create mode 100644 arch/arm/boot/dts/rv1106-tb-nofastae-emmc.dtsi create mode 100644 arch/arm/boot/dts/rv1106-tb-nofastae-spi-nor.dtsi create mode 100644 arch/arm/boot/dts/rv1106-tb-nofastae.dtsi diff --git a/arch/arm/boot/dts/rv1106-tb-nofastae-emmc.dtsi b/arch/arm/boot/dts/rv1106-tb-nofastae-emmc.dtsi new file mode 100644 index 000000000000..1095b35564d4 --- /dev/null +++ b/arch/arm/boot/dts/rv1106-tb-nofastae-emmc.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#include "rv1106-tb-nofastae.dtsi" + +/ { + reserved-memory { + mmc_ecsd: mmc@3f000 { + reg = <0x3f000 0x00001000>; + }; + + mmc_idmac: mmc@100000 { + reg = <0x00100000 0x00100000>; + }; + }; + + thunder_boot_mmc: thunder-boot-mmc { + compatible = "rockchip,thunder-boot-mmc"; + reg = <0xffa90000 0x4000>; + memory-region-src = <&ramdisk_c>; + memory-region-dst = <&ramdisk_r>; + memory-region-idmac = <&mmc_idmac>; + }; +}; + +&emmc { + memory-region-ecsd = <&mmc_ecsd>; + post-power-on-delay-ms = <0>; +}; diff --git a/arch/arm/boot/dts/rv1106-tb-nofastae-spi-nor.dtsi b/arch/arm/boot/dts/rv1106-tb-nofastae-spi-nor.dtsi new file mode 100644 index 000000000000..e0770091de6f --- /dev/null +++ b/arch/arm/boot/dts/rv1106-tb-nofastae-spi-nor.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#include "rv1106-tb-nofastae.dtsi" + +/ { + thunder_boot_spi_nor: thunder-boot-spi-nor { + compatible = "rockchip,thunder-boot-sfc"; + reg = <0xffac0000 0x4000>; + memory-region-src = <&ramdisk_c>; + memory-region-dst = <&ramdisk_r>; + }; +}; + +&emmc { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/rv1106-tb-nofastae.dtsi b/arch/arm/boot/dts/rv1106-tb-nofastae.dtsi new file mode 100644 index 000000000000..de10bc2d951b --- /dev/null +++ b/arch/arm/boot/dts/rv1106-tb-nofastae.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +/ { + memory: memory { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + ramdisk: ramdisk { + compatible = "rockchip,ramdisk"; + memory-region = <&ramdisk_r>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramdisk_r: ramdisk_r { + reg = <0x800000 (10 * 0x00100000)>; + }; + + ramdisk_c: ramdisk_c { + reg = <0x1200000 (5 * 0x00100000)>; + }; + }; +}; + +&hw_decompress { + status = "okay"; + memory-region = <&ramdisk_c>; +}; From 061e9815fd76bc8b55176c1e1291641dea989efb Mon Sep 17 00:00:00 2001 From: Weiwen Chen Date: Mon, 28 Aug 2023 17:22:23 +0800 Subject: [PATCH 06/17] ARM: dts: rockchip: add rv1106g-evb2-v12-nofastae-emmc Signed-off-by: Weiwen Chen Change-Id: Iff6518bd618b1a747f38500291cc666bbeb080e0 --- arch/arm/boot/dts/Makefile | 1 + .../dts/rv1106g-evb2-v12-nofastae-emmc.dts | 134 ++++++++++++++++++ 2 files changed, 135 insertions(+) create mode 100644 arch/arm/boot/dts/rv1106g-evb2-v12-nofastae-emmc.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 68b8029d57a6..0c6e6e6433ef 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1002,6 +1002,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rv1106g-evb2-v10.dtb \ rv1106g-evb2-v10-dual-camera.dtb \ rv1106g-evb2-v11-emmc.dtb \ + rv1106g-evb2-v12-nofastae-emmc.dtb \ rv1106g-evb2-v12-wakeup.dtb \ rv1106g-smart-door-lock-rmsl-v10.dtb \ rv1106g-smart-door-lock-rmsl-v12.dtb \ diff --git a/arch/arm/boot/dts/rv1106g-evb2-v12-nofastae-emmc.dts b/arch/arm/boot/dts/rv1106g-evb2-v12-nofastae-emmc.dts new file mode 100644 index 000000000000..a49f45d5436d --- /dev/null +++ b/arch/arm/boot/dts/rv1106g-evb2-v12-nofastae-emmc.dts @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rv1106.dtsi" +#include "rv1106-evb-v10.dtsi" +#include "rv1106-evb-cam.dtsi" +#include "rv1106-tb-nofastae-emmc.dtsi" + +/ { + model = "Rockchip RV1106G EVB2 V12 Board"; + compatible = "rockchip,rv1106g-evb2-v12", "rockchip,rv1106"; + + chosen { + bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip"; + }; + + vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc3v3_sd: vcc3v3-sd { + compatible = "regulator-fixed"; + gpio = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + WIFI,host_wake_irq = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&fiq_debugger { + rockchip,baudrate = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; +}; + +&pinctrl { + sdmmc { + /omit-if-no-ref/ + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm10 { + status = "okay"; +}; + +&pwm11 { + status = "okay"; +}; + +&ramdisk_r { + reg = <0x800000 (20 * 0x00100000)>; +}; + +&ramdisk_c { + reg = <0x1C00000 (10 * 0x00100000)>; +}; + +&sdio { + max-frequency = <50000000>; + bus-width = <1>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + rockchip,default-sample-phase = <90>; + no-sd; + no-mmc; + supports-sdio; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus4>; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "normal", "idle"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>; + pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det>; + vmmc-supply = <&vcc3v3_sd>; + status = "okay"; +}; + +&sfc { + assigned-clocks = <&cru SCLK_SFC>; + assigned-clock-rates = <125000000>; + status = "disabled"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <125000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&usbdrd_dwc3 { + dr_mode = "peripheral"; +}; From 270c1dfde4111ba347868d1092ebd60aaf658951 Mon Sep 17 00:00:00 2001 From: Weiwen Chen Date: Mon, 28 Aug 2023 17:23:05 +0800 Subject: [PATCH 07/17] ARM: dts: rockchip: add rv1106g-evb2-v12-nofastae-spi-nor Signed-off-by: Weiwen Chen Change-Id: I28c8e65ac1b3c997140f9aed6efe2d3857f78c3b --- arch/arm/boot/dts/Makefile | 1 + .../dts/rv1106g-evb2-v12-nofastae-spi-nor.dts | 134 ++++++++++++++++++ 2 files changed, 135 insertions(+) create mode 100644 arch/arm/boot/dts/rv1106g-evb2-v12-nofastae-spi-nor.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0c6e6e6433ef..463d6172ac85 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1003,6 +1003,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rv1106g-evb2-v10-dual-camera.dtb \ rv1106g-evb2-v11-emmc.dtb \ rv1106g-evb2-v12-nofastae-emmc.dtb \ + rv1106g-evb2-v12-nofastae-spi-nor.dtb \ rv1106g-evb2-v12-wakeup.dtb \ rv1106g-smart-door-lock-rmsl-v10.dtb \ rv1106g-smart-door-lock-rmsl-v12.dtb \ diff --git a/arch/arm/boot/dts/rv1106g-evb2-v12-nofastae-spi-nor.dts b/arch/arm/boot/dts/rv1106g-evb2-v12-nofastae-spi-nor.dts new file mode 100644 index 000000000000..dcc4da3e5aa5 --- /dev/null +++ b/arch/arm/boot/dts/rv1106g-evb2-v12-nofastae-spi-nor.dts @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rv1106.dtsi" +#include "rv1106-evb-v10.dtsi" +#include "rv1106-evb-cam.dtsi" +#include "rv1106-tb-nofastae-spi-nor.dtsi" + +/ { + model = "Rockchip RV1106G EVB2 V12 Board"; + compatible = "rockchip,rv1106g-evb2-v12", "rockchip,rv1106"; + + chosen { + bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip"; + }; + + vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc3v3_sd: vcc3v3-sd { + compatible = "regulator-fixed"; + gpio = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + WIFI,host_wake_irq = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&fiq_debugger { + rockchip,baudrate = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; +}; + +&pinctrl { + sdmmc { + /omit-if-no-ref/ + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm10 { + status = "okay"; +}; + +&pwm11 { + status = "okay"; +}; + +&ramdisk_r { + reg = <0x800000 (10 * 0x00100000)>; +}; + +&ramdisk_c { + reg = <0x1200000 (5 * 0x00100000)>; +}; + +&sdio { + max-frequency = <50000000>; + bus-width = <1>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + rockchip,default-sample-phase = <90>; + no-sd; + no-mmc; + supports-sdio; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus4>; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "normal", "idle"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>; + pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det>; + vmmc-supply = <&vcc3v3_sd>; + status = "okay"; +}; + +&sfc { + assigned-clocks = <&cru SCLK_SFC>; + assigned-clock-rates = <125000000>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <125000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&usbdrd_dwc3 { + dr_mode = "peripheral"; +}; From ce082f50d63c46ab1f7a412b229cd8038e42bfe9 Mon Sep 17 00:00:00 2001 From: Jiahang Zheng Date: Wed, 6 Sep 2023 15:21:23 +0800 Subject: [PATCH 08/17] arm64: dts: rockchip: rk3562-amp: set mailbox txpoll to 1 ms Change-Id: I5809679e016072e19334a3336f4c8b572672892a Signed-off-by: Jiahang Zheng --- arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi index 0968d9616850..ea4f81ed5e2c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi @@ -54,5 +54,6 @@ }; &mailbox { + rockchip,txpoll-period-ms = <1>; status = "okay"; }; From 92bb1f717ade409048b27581fd00f5901aecb1be Mon Sep 17 00:00:00 2001 From: Jiahang Zheng Date: Wed, 6 Sep 2023 15:23:50 +0800 Subject: [PATCH 09/17] arm64: dts: rockchip: rk3562-amp: change rpmsg shared memory address Change-Id: Id50d36134fd0ded06a594dd6cf163e1f1bf97e4a Signed-off-by: Jiahang Zheng --- arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi index ea4f81ed5e2c..d0979a1b28a8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi @@ -17,13 +17,13 @@ status = "okay"; }; - rpmsg: rpmsg@a0000000 { + rpmsg: rpmsg@7c00000 { compatible = "rockchip,rk3562-rpmsg"; mbox-names = "rpmsg-rx", "rpmsg-tx"; mboxes = <&mailbox 0 &mailbox 3>; rockchip,vdev-nums = <1>; rockchip,link-id = <0x04>; - reg = <0x0 0xa0000000 0x0 0x20000>; + reg = <0x0 0x7c00000 0x0 0x20000>; memory-region = <&rpmsg_dma_reserved>; status = "okay"; @@ -40,14 +40,14 @@ no-map; }; - rpmsg_reserved: rpmsg@a0000000 { - reg = <0x0 0xa0000000 0x0 0x400000>; + rpmsg_reserved: rpmsg@7c00000 { + reg = <0x0 0x07c00000 0x0 0x400000>; no-map; }; - rpmsg_dma_reserved: rpmsg-dma@a0400000 { + rpmsg_dma_reserved: rpmsg-dma@8000000 { compatible = "shared-dma-pool"; - reg = <0x0 0xa0400000 0x0 0x100000>; + reg = <0x0 0x08000000 0x0 0x100000>; no-map; }; }; From 85d050d65d8a0b96d392930fe14ee8773a5ff3cc Mon Sep 17 00:00:00 2001 From: Jiahang Zheng Date: Wed, 6 Sep 2023 15:36:05 +0800 Subject: [PATCH 10/17] rpmsg: rockchip_test: add new device id for mcu Change-Id: I3c05237bac273ee6475678dd1cb7c9a3af0a268e Signed-off-by: Jiahang Zheng --- drivers/rpmsg/rockchip_rpmsg_test.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/rpmsg/rockchip_rpmsg_test.c b/drivers/rpmsg/rockchip_rpmsg_test.c index 08e882112e53..7f607bd296e0 100644 --- a/drivers/rpmsg/rockchip_rpmsg_test.c +++ b/drivers/rpmsg/rockchip_rpmsg_test.c @@ -92,6 +92,7 @@ static void rockchip_rpmsg_test_remove(struct rpmsg_device *rp) static struct rpmsg_device_id rockchip_rpmsg_test_id_table[] = { { .name = "rpmsg-ap3-ch0" }, + { .name = "rpmsg-mcu0-test" }, { /* sentinel */ }, }; From b91450d8c776c6174e34a5f6a6959d860705aee2 Mon Sep 17 00:00:00 2001 From: Weiwen Chen Date: Mon, 4 Sep 2023 19:21:57 +0800 Subject: [PATCH 11/17] ARM: dts: rockchip: rv1106-thunder-boot: set rkvenc clock to 410000000 Signed-off-by: Weiwen Chen Change-Id: I912f05b66d546197e748da1274f25461979eea61 --- arch/arm/boot/dts/rv1106-thunder-boot.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/rv1106-thunder-boot.dtsi b/arch/arm/boot/dts/rv1106-thunder-boot.dtsi index ea2557ce39c2..5f357a63f47b 100644 --- a/arch/arm/boot/dts/rv1106-thunder-boot.dtsi +++ b/arch/arm/boot/dts/rv1106-thunder-boot.dtsi @@ -98,3 +98,8 @@ &rkisp_vir0 { memory-region-thunderboot = <&rkisp_thunderboot>; }; + +&rkvenc { + assigned-clocks = <&cru CLK_CORE_VEPU>; + assigned-clock-rates = <410000000>; +}; From ce7600d754114adfad3f8dec0e8739c39a6d0525 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Tue, 5 Sep 2023 16:56:14 +0800 Subject: [PATCH 12/17] PCI: rockchip: dw: Save and restore PCIE_CLIENT_INTR_MASK_LEGACY in PM Signed-off-by: Shawn Lin Change-Id: I35ca5baeb233827ba9b494fb0fddaa807e464fb2 --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index e0f26f4b0189..ca12580bd5b5 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -193,6 +193,7 @@ struct rk_pcie { struct workqueue_struct *hot_rst_wq; struct work_struct hot_rst_work; u32 comp_prst[2]; + u32 intx; }; struct rk_pcie_of_data { @@ -2359,6 +2360,8 @@ no_l2: phy_power_off(rk_pcie->phy); phy_exit(rk_pcie->phy); + rk_pcie->intx = rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_INTR_MASK_LEGACY); + clk_bulk_disable_unprepare(rk_pcie->clk_cnt, rk_pcie->clks); rk_pcie->in_suspend = true; @@ -2423,6 +2426,9 @@ static int __maybe_unused rockchip_dw_pcie_resume(struct device *dev) if (std_rc) dw_pcie_setup_rc(&rk_pcie->pci->pp); + rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_MASK_LEGACY, + rk_pcie->intx | 0xffff0000); + ret = rk_pcie_establish_link(rk_pcie->pci); if (ret) { dev_err(dev, "failed to establish pcie link\n"); From 35d463f90019d3e709b4bbcaddc1a032ae310902 Mon Sep 17 00:00:00 2001 From: Cai YiWei Date: Thu, 20 Apr 2023 11:04:05 +0800 Subject: [PATCH 13/17] media: rockchip: isp: support unite mode for isp32 Change-Id: Iae10911ee0f199210c7913d3e99dd85ec4642f81 Signed-off-by: Cai YiWei --- drivers/media/platform/rockchip/isp/capture.c | 23 +- .../media/platform/rockchip/isp/capture_v30.c | 117 +- .../media/platform/rockchip/isp/capture_v32.c | 137 +- drivers/media/platform/rockchip/isp/common.c | 8 +- drivers/media/platform/rockchip/isp/common.h | 26 - drivers/media/platform/rockchip/isp/csi.c | 16 +- drivers/media/platform/rockchip/isp/dev.c | 13 +- drivers/media/platform/rockchip/isp/dev.h | 48 + drivers/media/platform/rockchip/isp/dmarx.c | 20 +- drivers/media/platform/rockchip/isp/hw.c | 72 +- drivers/media/platform/rockchip/isp/hw.h | 2 +- .../media/platform/rockchip/isp/isp_params.c | 28 +- .../platform/rockchip/isp/isp_params_v32.c | 2331 +++++++++-------- .../platform/rockchip/isp/isp_params_v32.h | 158 +- .../platform/rockchip/isp/isp_params_v3x.c | 54 +- .../platform/rockchip/isp/isp_stats_v32.c | 195 +- .../platform/rockchip/isp/isp_stats_v3x.c | 18 +- drivers/media/platform/rockchip/isp/procfs.c | 4 +- drivers/media/platform/rockchip/isp/regs.c | 62 +- drivers/media/platform/rockchip/isp/regs.h | 14 +- .../media/platform/rockchip/isp/regs_v2x.h | 2 +- .../media/platform/rockchip/isp/regs_v3x.h | 9 + drivers/media/platform/rockchip/isp/rkisp.c | 331 +-- drivers/media/platform/rockchip/isp/rkisp.h | 2 + 24 files changed, 1994 insertions(+), 1696 deletions(-) diff --git a/drivers/media/platform/rockchip/isp/capture.c b/drivers/media/platform/rockchip/isp/capture.c index 60b81ada21be..a43e6e4f9963 100644 --- a/drivers/media/platform/rockchip/isp/capture.c +++ b/drivers/media/platform/rockchip/isp/capture.c @@ -626,7 +626,7 @@ static void restrict_rsz_resolution(struct rkisp_stream *stream, max_rsz->width = ALIGN(DIV_ROUND_UP(input_win->width, div), 4); max_rsz->height = DIV_ROUND_UP(input_win->height, div); - } else if (dev->hw_dev->is_unite) { + } else if (dev->hw_dev->unite) { /* scale down only for unite mode */ max_rsz->width = min_t(int, input_win->width, cfg->max_rsz_width); max_rsz->height = min_t(int, input_win->height, cfg->max_rsz_height); @@ -1140,7 +1140,8 @@ static int rkisp_set_wrap_line(struct rkisp_stream *stream, struct rkisp_wrap_in if (dev->isp_ver != ISP_V32 || dev->hw_dev->dev_link_num > 1 || - !stream->ops->set_wrap) { + !stream->ops->set_wrap || + dev->hw_dev->unite) { v4l2_err(&dev->v4l2_dev, "wrap only support for single sensor and mainpath\n"); return -EINVAL; @@ -1465,7 +1466,7 @@ static struct v4l2_rect *rkisp_update_crop(struct rkisp_stream *stream, const struct v4l2_rect *in) { struct rkisp_device *dev = stream->ispdev; - bool is_unite = dev->hw_dev->is_unite; + bool is_unite = !!dev->hw_dev->unite; u32 align = is_unite ? 4 : 2; /* Not crop for MP bayer raw data and dmatx path */ @@ -1735,17 +1736,21 @@ int rkisp_register_stream_vdevs(struct rkisp_device *dev) st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V21; ret = rkisp_register_stream_v21(dev); } else if (dev->isp_ver == ISP_V30) { - st_cfg->max_rsz_width = dev->hw_dev->is_unite ? + st_cfg->max_rsz_width = dev->hw_dev->unite ? CIF_ISP_INPUT_W_MAX_V30_UNITE : CIF_ISP_INPUT_W_MAX_V30; - st_cfg->max_rsz_height = dev->hw_dev->is_unite ? + st_cfg->max_rsz_height = dev->hw_dev->unite ? CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30; ret = rkisp_register_stream_v30(dev); } else if (dev->isp_ver == ISP_V32) { - st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32; - st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V32; + st_cfg->max_rsz_width = dev->hw_dev->unite ? + CIF_ISP_INPUT_W_MAX_V32_UNITE : CIF_ISP_INPUT_W_MAX_V32; + st_cfg->max_rsz_height = dev->hw_dev->unite ? + CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32; st_cfg = &rkisp_sp_stream_config; - st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32; - st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V32; + st_cfg->max_rsz_width = dev->hw_dev->unite ? + CIF_ISP_INPUT_W_MAX_V32_UNITE : CIF_ISP_INPUT_W_MAX_V32; + st_cfg->max_rsz_height = dev->hw_dev->unite ? + CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32; ret = rkisp_register_stream_v32(dev); } else if (dev->isp_ver == ISP_V32_L) { st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32_L; diff --git a/drivers/media/platform/rockchip/isp/capture_v30.c b/drivers/media/platform/rockchip/isp/capture_v30.c index 62a8ae82d343..5f6616cdb031 100644 --- a/drivers/media/platform/rockchip/isp/capture_v30.c +++ b/drivers/media/platform/rockchip/isp/capture_v30.c @@ -332,7 +332,7 @@ static int rkisp_stream_config_dcrop(struct rkisp_stream *stream, bool async) if (dcrop->width == input_win->width && dcrop->height == input_win->height && dcrop->left == 0 && dcrop->top == 0 && - !dev->hw_dev->is_unite) { + !dev->hw_dev->unite) { rkisp_disable_dcrop(stream, async); v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev, "stream %d crop disabled\n", stream->id); @@ -472,7 +472,7 @@ static int mp_config_mi(struct rkisp_stream *stream) { struct rkisp_device *dev = stream->ispdev; struct v4l2_pix_format_mplane *out_fmt = &stream->out_fmt; - bool is_unite = dev->hw_dev->is_unite; + bool is_unite = !!dev->hw_dev->unite; u32 val, mask; /* @@ -480,26 +480,26 @@ static int mp_config_mi(struct rkisp_stream *stream) * memory plane formats, so calculate the size explicitly. */ val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height; - rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false, is_unite); + rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false); val = out_fmt->plane_fmt[1].sizeimage; - rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false, is_unite); + rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false); val = out_fmt->plane_fmt[2].sizeimage; - rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false, is_unite); + rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false); val = is_unite ? out_fmt->width / 2 : out_fmt->width; - rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_PIC_WIDTH, val, false, is_unite); + rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_PIC_WIDTH, val, false); val = out_fmt->height; - rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_PIC_HEIGHT, val, false, is_unite); + rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_PIC_HEIGHT, val, false); val = out_fmt->plane_fmt[0].bytesperline; - rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false, is_unite); + rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false); val = stream->out_isp_fmt.uv_swap ? ISP3X_MI_XTD_FORMAT_MP_UV_SWAP : 0; mask = ISP3X_MI_XTD_FORMAT_MP_UV_SWAP; - rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false, is_unite); + rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false); mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_MP_YUV_MODE; val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask; @@ -511,13 +511,13 @@ static int mp_config_mi(struct rkisp_stream *stream) val |= ISP3X_SEPERATE_YUV_CFG; else val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_MP_YUV_MODE; - rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false, is_unite); + rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false); val = calc_burst_len(stream) | CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_MP_AUTOUPDATE_ENABLE | stream->out_isp_fmt.write_format; mask = GENMASK(19, 16) | MI_CTRL_MP_FMT_MASK; - rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false, is_unite); + rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false); mi_frame_end_int_enable(stream); /* set up first buffer */ @@ -558,7 +558,7 @@ static int sp_config_mi(struct rkisp_stream *stream) struct v4l2_pix_format_mplane *out_fmt = &stream->out_fmt; struct ispsd_out_fmt *input_isp_fmt = rkisp_get_ispsd_out_fmt(&dev->isp_sdev); - bool is_unite = dev->hw_dev->is_unite; + bool is_unite = !!dev->hw_dev->unite; u32 sp_in_fmt, val, mask; if (mbus_code_sp_in_fmt(input_isp_fmt->mbus_code, @@ -572,26 +572,26 @@ static int sp_config_mi(struct rkisp_stream *stream) * memory plane formats, so calculate the size explicitly. */ val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height; - rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false, is_unite); + rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false); val = out_fmt->plane_fmt[1].sizeimage; - rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false, is_unite); + rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false); val = out_fmt->plane_fmt[2].sizeimage; - rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false, is_unite); + rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false); val = is_unite ? out_fmt->width / 2 : out_fmt->width; - rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_PIC_WIDTH, val, false, is_unite); + rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_PIC_WIDTH, val, false); val = out_fmt->height; - rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_PIC_HEIGHT, val, false, is_unite); + rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_PIC_HEIGHT, val, false); val = stream->u.sp.y_stride; - rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_LLENGTH, val, false, is_unite); + rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_LLENGTH, val, false); val = stream->out_isp_fmt.uv_swap ? ISP3X_MI_XTD_FORMAT_SP_UV_SWAP : 0; mask = ISP3X_MI_XTD_FORMAT_SP_UV_SWAP; - rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false, is_unite); + rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false); mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_SP_YUV_MODE; val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask; @@ -603,14 +603,14 @@ static int sp_config_mi(struct rkisp_stream *stream) val |= ISP3X_SEPERATE_YUV_CFG; else val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_SP_YUV_MODE; - rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false, is_unite); + rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false); val = calc_burst_len(stream) | CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN | stream->out_isp_fmt.write_format | sp_in_fmt | stream->out_isp_fmt.output_format | CIF_MI_SP_AUTOUPDATE_ENABLE; mask = GENMASK(19, 16) | MI_CTRL_SP_FMT_MASK; - rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false, is_unite); + rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false); mi_frame_end_int_enable(stream); /* set up first buffer */ @@ -625,12 +625,12 @@ static int fbc_config_mi(struct rkisp_stream *stream) u32 h = ALIGN(stream->out_fmt.height, 16); u32 w = ALIGN(stream->out_fmt.width, 16); u32 offs = ALIGN(w * h / 16, RK_MPP_ALIGN); - bool is_unite = stream->ispdev->hw_dev->is_unite; + bool is_unite = !!stream->ispdev->hw_dev->unite; rkisp_write(stream->ispdev, ISP3X_MPFBC_HEAD_OFFSET, offs, false); - rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_VIR_WIDTH, w, false, is_unite); - rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_PAYL_WIDTH, w, false, is_unite); - rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_VIR_HEIGHT, h, false, is_unite); + rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_VIR_WIDTH, w, false); + rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_PAYL_WIDTH, w, false); + rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_VIR_HEIGHT, h, false); if (is_unite) { u32 left_w = (stream->out_fmt.width / 2) & ~0xf; @@ -638,8 +638,7 @@ static int fbc_config_mi(struct rkisp_stream *stream) rkisp_next_write(stream->ispdev, ISP3X_MPFBC_HEAD_OFFSET, offs, false); } rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, 0, - CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN, - false, is_unite); + CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN, false); mi_frame_end_int_enable(stream); /* set up first buffer */ mi_frame_end(stream, FRAME_INIT); @@ -650,7 +649,7 @@ static int bp_config_mi(struct rkisp_stream *stream) { struct v4l2_pix_format_mplane *out_fmt = &stream->out_fmt; struct rkisp_device *dev = stream->ispdev; - bool is_unite = dev->hw_dev->is_unite; + bool is_unite = dev->hw_dev->unite; u32 val, mask; /* @@ -658,19 +657,19 @@ static int bp_config_mi(struct rkisp_stream *stream) * memory plane formats, so calculate the size explicitly. */ val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height; - rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false, is_unite); + rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false); val = out_fmt->plane_fmt[1].sizeimage; - rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false, is_unite); + rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false); val = is_unite ? out_fmt->width / 2 : out_fmt->width; - rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_PIC_WIDTH, val, false, is_unite); + rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_PIC_WIDTH, val, false); val = out_fmt->height; - rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_PIC_HEIGHT, val, false, is_unite); + rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_PIC_HEIGHT, val, false); val = out_fmt->plane_fmt[0].bytesperline; - rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false, is_unite); + rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false); mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_BP_YUV_MODE; val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask; @@ -680,9 +679,9 @@ static int bp_config_mi(struct rkisp_stream *stream) val |= ISP3X_SEPERATE_YUV_CFG; else val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_BP_YUV_MODE; - rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false, is_unite); + rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false); val = CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN; - rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false, is_unite); + rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false); mi_frame_end_int_enable(stream); /* set up first buffer */ mi_frame_end(stream, FRAME_INIT); @@ -697,8 +696,7 @@ static void mp_enable_mi(struct rkisp_stream *stream) if (isp_fmt->fmt_type == FMT_BAYER) val = CIF_MI_CTRL_RAW_ENABLE; - rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, - false, stream->ispdev->hw_dev->is_unite); + rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false); } static void sp_enable_mi(struct rkisp_stream *stream) @@ -711,21 +709,18 @@ static void sp_enable_mi(struct rkisp_stream *stream) if (fmt->fmt_type == FMT_RGB && dev->isp_sdev.quantization == V4L2_QUANTIZATION_FULL_RANGE) val |= mask; - rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, - mask, val, false, - stream->ispdev->hw_dev->is_unite); + rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false); } static void fbc_enable_mi(struct rkisp_stream *stream) { u32 val, mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_MPFBC_YUV_MASK | ISP3X_MPFBC_SPARSE_MODE; - bool is_unite = stream->ispdev->hw_dev->is_unite; /* config no effect immediately, read back is shadow, get config value from cache */ val = rkisp_read_reg_cache(stream->ispdev, ISP3X_MPFBC_CTRL) & ~mask; val |= stream->out_isp_fmt.write_format | ISP3X_HEAD_OFFSET_EN | ISP3X_MPFBC_EN; - rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_CTRL, val, false, is_unite); + rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_CTRL, val, false); } static void bp_enable_mi(struct rkisp_stream *stream) @@ -733,36 +728,31 @@ static void bp_enable_mi(struct rkisp_stream *stream) u32 val = stream->out_isp_fmt.write_format | ISP3X_BP_ENABLE | ISP3X_BP_AUTO_UPD; - rkisp_unite_write(stream->ispdev, ISP3X_MI_BP_WR_CTRL, val, false, - stream->ispdev->hw_dev->is_unite); + rkisp_unite_write(stream->ispdev, ISP3X_MI_BP_WR_CTRL, val, false); } static void mp_disable_mi(struct rkisp_stream *stream) { u32 mask = CIF_MI_CTRL_MP_ENABLE | CIF_MI_CTRL_RAW_ENABLE; - rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, false, - stream->ispdev->hw_dev->is_unite); + rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, false); } static void sp_disable_mi(struct rkisp_stream *stream) { - rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, CIF_MI_CTRL_SP_ENABLE, - false, stream->ispdev->hw_dev->is_unite); + rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, CIF_MI_CTRL_SP_ENABLE, false); } static void fbc_disable_mi(struct rkisp_stream *stream) { u32 mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_MPFBC_EN; - rkisp_unite_clear_bits(stream->ispdev, ISP3X_MPFBC_CTRL, mask, - false, stream->ispdev->hw_dev->is_unite); + rkisp_unite_clear_bits(stream->ispdev, ISP3X_MPFBC_CTRL, mask, false); } static void bp_disable_mi(struct rkisp_stream *stream) { - rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_BP_WR_CTRL, ISP3X_BP_ENABLE, - false, stream->ispdev->hw_dev->is_unite); + rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_BP_WR_CTRL, ISP3X_BP_ENABLE, false); } static void update_mi(struct rkisp_stream *stream) @@ -786,7 +776,7 @@ static void update_mi(struct rkisp_stream *stream) rkisp_write(dev, reg, val, false); } - if (dev->hw_dev->is_unite) { + if (dev->hw_dev->unite) { u32 mult = stream->id != RKISP_STREAM_FBC ? 1 : (stream->out_isp_fmt.write_format ? 32 : 24); u32 div = stream->out_isp_fmt.fourcc == V4L2_PIX_FMT_UYVY ? 1 : 2; @@ -818,22 +808,22 @@ static void update_mi(struct rkisp_stream *stream) stream->dbg.frameloss++; val = dummy_buf->dma_addr; reg = stream->config->mi.y_base_ad_init; - rkisp_unite_write(dev, reg, val, false, dev->hw_dev->is_unite); + rkisp_unite_write(dev, reg, val, false); reg = stream->config->mi.cb_base_ad_init; - rkisp_unite_write(dev, reg, val, false, dev->hw_dev->is_unite); + rkisp_unite_write(dev, reg, val, false); reg = stream->config->mi.cr_base_ad_init; if (stream->id != RKISP_STREAM_FBC && stream->id != RKISP_STREAM_BP) - rkisp_unite_write(dev, reg, val, false, dev->hw_dev->is_unite); + rkisp_unite_write(dev, reg, val, false); } if (stream->id != RKISP_STREAM_FBC) { reg = stream->config->mi.y_offs_cnt_init; - rkisp_unite_write(dev, reg, 0, false, dev->hw_dev->is_unite); + rkisp_unite_write(dev, reg, 0, false); reg = stream->config->mi.cb_offs_cnt_init; - rkisp_unite_write(dev, reg, 0, false, dev->hw_dev->is_unite); + rkisp_unite_write(dev, reg, 0, false); reg = stream->config->mi.cr_offs_cnt_init; if (stream->id != RKISP_STREAM_BP) - rkisp_unite_write(dev, reg, 0, false, dev->hw_dev->is_unite); + rkisp_unite_write(dev, reg, 0, false); } v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev, @@ -842,7 +832,7 @@ static void update_mi(struct rkisp_stream *stream) rkisp_read(dev, stream->config->mi.y_base_ad_init, false), rkisp_read(dev, stream->config->mi.cb_base_ad_init, false), rkisp_read(dev, stream->config->mi.y_base_ad_shd, true)); - if (dev->hw_dev->is_unite) + if (dev->hw_dev->unite) v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev, "%s stream:%d Y:0x%x CB:0x%x | Y_SHD:0x%x, right\n", __func__, stream->id, @@ -897,11 +887,10 @@ static void stream_self_update(struct rkisp_stream *stream) { struct rkisp_device *dev = stream->ispdev; u32 val, mask = ISP3X_MPSELF_UPD | ISP3X_SPSELF_UPD | ISP3X_BPSELF_UPD; - bool is_unite = dev->hw_dev->is_unite; if (stream->id == RKISP_STREAM_FBC) { val = ISP3X_MPFBC_FORCE_UPD; - rkisp_unite_set_bits(dev, ISP3X_MPFBC_CTRL, 0, val, false, is_unite); + rkisp_unite_set_bits(dev, ISP3X_MPFBC_CTRL, 0, val, false); return; } @@ -919,7 +908,7 @@ static void stream_self_update(struct rkisp_stream *stream) return; } - rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL2, mask, val, false, is_unite); + rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL2, mask, val, false); } static int mi_frame_start(struct rkisp_stream *stream, u32 mis) @@ -1690,7 +1679,7 @@ void rkisp_mi_v30_isr(u32 mis_val, struct rkisp_device *dev) struct rkisp_stream *stream; unsigned int i; - if (dev->hw_dev->is_unite) { + if (dev->hw_dev->unite) { u32 val = rkisp_read(dev, ISP3X_MI_RIS, true); if (val) { diff --git a/drivers/media/platform/rockchip/isp/capture_v32.c b/drivers/media/platform/rockchip/isp/capture_v32.c index 1d3891ff3744..c71a701ebccb 100644 --- a/drivers/media/platform/rockchip/isp/capture_v32.c +++ b/drivers/media/platform/rockchip/isp/capture_v32.c @@ -554,7 +554,8 @@ static int rkisp_stream_config_dcrop(struct rkisp_stream *stream, bool async) if (dcrop->width == input_win->width && dcrop->height == input_win->height && - dcrop->left == 0 && dcrop->top == 0) { + dcrop->left == 0 && dcrop->top == 0 && + !dev->hw_dev->unite) { rkisp_disable_dcrop(stream, async); v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev, "stream %d crop disabled\n", stream->id); @@ -704,29 +705,29 @@ static int mp_config_mi(struct rkisp_stream *stream) /* in bytes for isp32 */ if (dev->isp_ver == ISP_V32 && stream->out_isp_fmt.write_format != MI_CTRL_MP_WRITE_YUVINT) - rkisp_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false); + rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false); val /= DIV_ROUND_UP(fmt->bpp[0], 8); /* in pixels for isp32 lite */ if (dev->isp_ver == ISP_V32_L) - rkisp_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false); + rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false); val *= height; - rkisp_write(dev, stream->config->mi.y_pic_size, val, false); + rkisp_unite_write(dev, stream->config->mi.y_pic_size, val, false); val = out_fmt->plane_fmt[0].bytesperline * height; - rkisp_write(dev, stream->config->mi.y_size_init, val, false); + rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false); val = out_fmt->plane_fmt[1].sizeimage; if (dev->cap_dev.wrap_line) val = out_fmt->plane_fmt[0].bytesperline * height / 2; - rkisp_write(dev, stream->config->mi.cb_size_init, val, false); + rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false); val = out_fmt->plane_fmt[2].sizeimage; if (dev->cap_dev.wrap_line) val = out_fmt->plane_fmt[0].bytesperline * height / 2; - rkisp_write(dev, stream->config->mi.cr_size_init, val, false); + rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false); val = stream->out_isp_fmt.uv_swap ? ISP3X_MI_XTD_FORMAT_MP_UV_SWAP : 0; mask = ISP3X_MI_XTD_FORMAT_MP_UV_SWAP; - rkisp_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false); + rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false); mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_MP_YUV_MODE; val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask; @@ -738,24 +739,24 @@ static int mp_config_mi(struct rkisp_stream *stream) val |= ISP3X_SEPERATE_YUV_CFG; else val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_MP_YUV_MODE; - rkisp_write(dev, ISP3X_MPFBC_CTRL, val, false); + rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false); val = stream->out_isp_fmt.output_format; - rkisp_write(dev, ISP32_MI_MP_WR_CTRL, val, false); + rkisp_unite_write(dev, ISP32_MI_MP_WR_CTRL, val, false); val = calc_burst_len(stream) | CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_MP_AUTOUPDATE_ENABLE | stream->out_isp_fmt.write_format; mask = GENMASK(19, 16) | MI_CTRL_MP_FMT_MASK; - rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false); + rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false); mi_frame_end_int_enable(stream); /* set up first buffer */ mi_frame_end(stream, FRAME_INIT); - rkisp_write(dev, stream->config->mi.y_offs_cnt_init, 0, false); - rkisp_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false); - rkisp_write(dev, stream->config->mi.cr_offs_cnt_init, 0, false); + rkisp_unite_write(dev, stream->config->mi.y_offs_cnt_init, 0, false); + rkisp_unite_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false); + rkisp_unite_write(dev, stream->config->mi.cr_offs_cnt_init, 0, false); return 0; } @@ -805,21 +806,21 @@ static int sp_config_mi(struct rkisp_stream *stream) * memory plane formats, so calculate the size explicitly. */ val = stream->u.sp.y_stride; - rkisp_write(dev, ISP3X_MI_SP_WR_Y_LLENGTH, val, false); + rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_LLENGTH, val, false); val *= out_fmt->height; - rkisp_write(dev, stream->config->mi.y_pic_size, val, false); + rkisp_unite_write(dev, stream->config->mi.y_pic_size, val, false); val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height; - rkisp_write(dev, stream->config->mi.y_size_init, val, false); + rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false); val = out_fmt->plane_fmt[1].sizeimage; - rkisp_write(dev, stream->config->mi.cb_size_init, val, false); + rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false); val = out_fmt->plane_fmt[2].sizeimage; - rkisp_write(dev, stream->config->mi.cr_size_init, val, false); + rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false); val = stream->out_isp_fmt.uv_swap ? ISP3X_MI_XTD_FORMAT_SP_UV_SWAP : 0; mask = ISP3X_MI_XTD_FORMAT_SP_UV_SWAP; - rkisp_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false); + rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false); mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_SP_YUV_MODE; val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask; @@ -831,22 +832,22 @@ static int sp_config_mi(struct rkisp_stream *stream) val |= ISP3X_SEPERATE_YUV_CFG; else val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_SP_YUV_MODE; - rkisp_write(dev, ISP3X_MPFBC_CTRL, val, false); + rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false); val = calc_burst_len(stream) | CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN | stream->out_isp_fmt.write_format | sp_in_fmt | stream->out_isp_fmt.output_format | CIF_MI_SP_AUTOUPDATE_ENABLE; mask = GENMASK(19, 16) | MI_CTRL_SP_FMT_MASK; - rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false); + rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false); mi_frame_end_int_enable(stream); /* set up first buffer */ mi_frame_end(stream, FRAME_INIT); - rkisp_write(dev, stream->config->mi.y_offs_cnt_init, 0, false); - rkisp_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false); - rkisp_write(dev, stream->config->mi.cr_offs_cnt_init, 0, false); + rkisp_unite_write(dev, stream->config->mi.y_offs_cnt_init, 0, false); + rkisp_unite_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false); + rkisp_unite_write(dev, stream->config->mi.cr_offs_cnt_init, 0, false); return 0; } @@ -864,18 +865,18 @@ static int bp_config_mi(struct rkisp_stream *stream) val = out_fmt->plane_fmt[0].bytesperline; /* in bytes */ if (stream->out_isp_fmt.write_format != ISP3X_BP_FORMAT_INT) - rkisp_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false); + rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false); val /= DIV_ROUND_UP(fmt->bpp[0], 8); /* in pixels */ if (stream->out_isp_fmt.write_format == ISP3X_BP_FORMAT_INT) - rkisp_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false); + rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false); val *= out_fmt->height; - rkisp_write(dev, stream->config->mi.y_pic_size, val, false); + rkisp_unite_write(dev, stream->config->mi.y_pic_size, val, false); val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height; - rkisp_write(dev, stream->config->mi.y_size_init, val, false); + rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false); val = out_fmt->plane_fmt[1].sizeimage; - rkisp_write(dev, stream->config->mi.cb_size_init, val, false); + rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false); mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_BP_YUV_MODE; val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask; @@ -885,15 +886,15 @@ static int bp_config_mi(struct rkisp_stream *stream) val |= ISP3X_SEPERATE_YUV_CFG; else val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_BP_YUV_MODE; - rkisp_write(dev, ISP3X_MPFBC_CTRL, val, false); + rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false); val = CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN; - rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false); + rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false); mi_frame_end_int_enable(stream); /* set up first buffer */ mi_frame_end(stream, FRAME_INIT); - rkisp_write(dev, stream->config->mi.y_offs_cnt_init, 0, false); - rkisp_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false); + rkisp_unite_write(dev, stream->config->mi.y_offs_cnt_init, 0, false); + rkisp_unite_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false); return 0; } @@ -906,27 +907,27 @@ static int ds_config_mi(struct rkisp_stream *stream) val = out_fmt->plane_fmt[0].bytesperline; if (stream->out_isp_fmt.write_format != ISP3X_BP_FORMAT_INT) - rkisp_write(dev, stream->config->mi.length, val, false); + rkisp_unite_write(dev, stream->config->mi.length, val, false); val /= DIV_ROUND_UP(fmt->bpp[0], 8); if (stream->out_isp_fmt.write_format == ISP3X_BP_FORMAT_INT) - rkisp_write(dev, stream->config->mi.length, val, false); + rkisp_unite_write(dev, stream->config->mi.length, val, false); val *= out_fmt->height; - rkisp_write(dev, stream->config->mi.y_pic_size, val, false); + rkisp_unite_write(dev, stream->config->mi.y_pic_size, val, false); val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height; - rkisp_write(dev, stream->config->mi.y_size_init, val, false); + rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false); val = out_fmt->plane_fmt[1].sizeimage; - rkisp_write(dev, stream->config->mi.cb_size_init, val, false); + rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false); val = CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN; - rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false); + rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false); mi_frame_end_int_enable(stream); mi_frame_end(stream, FRAME_INIT); - rkisp_write(dev, stream->config->mi.y_offs_cnt_init, 0, false); - rkisp_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false); + rkisp_unite_write(dev, stream->config->mi.y_offs_cnt_init, 0, false); + rkisp_unite_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false); return 0; } @@ -940,7 +941,7 @@ static void mp_enable_mi(struct rkisp_stream *stream) if (isp_fmt->fmt_type == FMT_BAYER) val = CIF_MI_CTRL_RAW_ENABLE; - rkisp_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false); + rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false); /* enable bpds path output */ if (t->streaming && !t->is_pause) @@ -957,7 +958,7 @@ static void sp_enable_mi(struct rkisp_stream *stream) if (fmt->fmt_type == FMT_RGB && dev->isp_sdev.quantization == V4L2_QUANTIZATION_FULL_RANGE) val |= mask; - rkisp_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false); + rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false); } static void bp_enable_mi(struct rkisp_stream *stream) @@ -969,7 +970,7 @@ static void bp_enable_mi(struct rkisp_stream *stream) stream->out_isp_fmt.output_format | ISP3X_BP_ENABLE | ISP3X_BP_AUTO_UPD; - rkisp_write(stream->ispdev, ISP3X_MI_BP_WR_CTRL, val, false); + rkisp_unite_write(stream->ispdev, ISP3X_MI_BP_WR_CTRL, val, false); /* enable bpds path output */ if (t->streaming && !t->is_pause) @@ -982,7 +983,7 @@ static void ds_enable_mi(struct rkisp_stream *stream) stream->out_isp_fmt.output_format | ISP32_DS_ENABLE | ISP32_DS_AUTO_UPD; - rkisp_write(stream->ispdev, stream->config->mi.ctrl, val, false); + rkisp_unite_write(stream->ispdev, stream->config->mi.ctrl, val, false); } static void mp_disable_mi(struct rkisp_stream *stream) @@ -991,8 +992,7 @@ static void mp_disable_mi(struct rkisp_stream *stream) struct rkisp_stream *t = &dev->cap_dev.stream[stream->conn_id]; u32 mask = CIF_MI_CTRL_MP_ENABLE | CIF_MI_CTRL_RAW_ENABLE; - rkisp_set_bits(dev, 0x1814, 0, BIT(0), false); - rkisp_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, false); + rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, false); /* disable mpds path output */ if (!stream->is_pause && t->streaming) @@ -1001,7 +1001,7 @@ static void mp_disable_mi(struct rkisp_stream *stream) static void sp_disable_mi(struct rkisp_stream *stream) { - rkisp_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, CIF_MI_CTRL_SP_ENABLE, false); + rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, CIF_MI_CTRL_SP_ENABLE, false); } static void bp_disable_mi(struct rkisp_stream *stream) @@ -1009,7 +1009,7 @@ static void bp_disable_mi(struct rkisp_stream *stream) struct rkisp_device *dev = stream->ispdev; struct rkisp_stream *t = &dev->cap_dev.stream[stream->conn_id]; - rkisp_clear_bits(stream->ispdev, ISP3X_MI_BP_WR_CTRL, ISP3X_BP_ENABLE, false); + rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_BP_WR_CTRL, ISP3X_BP_ENABLE, false); /* disable bpds path output */ if (!stream->is_pause && t->streaming) @@ -1018,7 +1018,7 @@ static void bp_disable_mi(struct rkisp_stream *stream) static void ds_disable_mi(struct rkisp_stream *stream) { - rkisp_clear_bits(stream->ispdev, stream->config->mi.ctrl, ISP32_DS_ENABLE, false); + rkisp_unite_clear_bits(stream->ispdev, stream->config->mi.ctrl, ISP32_DS_ENABLE, false); } static void update_mi(struct rkisp_stream *stream) @@ -1048,6 +1048,25 @@ static void update_mi(struct rkisp_stream *stream) rkisp_write(dev, reg, val, false); } + if (dev->hw_dev->unite) { + reg = stream->config->mi.y_base_ad_init; + val = stream->next_buf->buff_addr[RKISP_PLANE_Y]; + val += ((stream->out_fmt.width / 2) & ~0xf); + rkisp_next_write(dev, reg, val, false); + + reg = stream->config->mi.cb_base_ad_init; + val = stream->next_buf->buff_addr[RKISP_PLANE_CB]; + val += ((stream->out_fmt.width / 2) & ~0xf); + rkisp_next_write(dev, reg, val, false); + + if (is_cr_cfg) { + reg = stream->config->mi.cr_base_ad_init; + val = stream->next_buf->buff_addr[RKISP_PLANE_CR]; + val += ((stream->out_fmt.width / 2) & ~0xf); + rkisp_next_write(dev, reg, val, false); + } + } + if (stream->is_pause) { /* single sensor mode with pingpong buffer: * if mi on, addr will auto update at frame end @@ -1141,9 +1160,9 @@ static int set_mirror_flip(struct rkisp_stream *stream) stream->is_mf_upd = false; if (dev->cap_dev.is_mirror) - rkisp_set_bits(dev, ISP3X_ISP_CTRL0, 0, ISP32_MIR_ENABLE, false); + rkisp_unite_set_bits(dev, ISP3X_ISP_CTRL0, 0, ISP32_MIR_ENABLE, false); else - rkisp_clear_bits(dev, ISP3X_ISP_CTRL0, ISP32_MIR_ENABLE, false); + rkisp_unite_clear_bits(dev, ISP3X_ISP_CTRL0, ISP32_MIR_ENABLE, false); switch (stream->id) { case RKISP_STREAM_SP: @@ -1169,9 +1188,9 @@ static int set_mirror_flip(struct rkisp_stream *stream) tmp = rkisp_read_reg_cache(dev, ISP32_MI_WR_VFLIP_CTRL); if (stream->is_flip) - rkisp_write(dev, ISP32_MI_WR_VFLIP_CTRL, tmp | val, false); + rkisp_unite_write(dev, ISP32_MI_WR_VFLIP_CTRL, tmp | val, false); else - rkisp_write(dev, ISP32_MI_WR_VFLIP_CTRL, tmp & ~val, false); + rkisp_unite_write(dev, ISP32_MI_WR_VFLIP_CTRL, tmp & ~val, false); return 0; } @@ -2268,6 +2287,12 @@ void rkisp_mi_v32_isr(u32 mis_val, struct rkisp_device *dev) v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev, "mi isr:0x%x\n", mis_val); + if (dev->hw_dev->unite == ISP_UNITE_ONE && + dev->unite_index == ISP_UNITE_LEFT) { + rkisp_write(dev, ISP3X_MI_ICR, mis_val, true); + goto end; + } + for (i = 0; i < RKISP_MAX_STREAM; ++i) { stream = &dev->cap_dev.stream[i]; @@ -2310,7 +2335,7 @@ void rkisp_mi_v32_isr(u32 mis_val, struct rkisp_device *dev) mi_frame_end(stream, FRAME_IRQ); } } - +end: if (mis_val & ISP3X_MI_MP_FRAME) { stream = &dev->cap_dev.stream[RKISP_STREAM_MP]; if (!stream->streaming) diff --git a/drivers/media/platform/rockchip/isp/common.c b/drivers/media/platform/rockchip/isp/common.c index 875d6da59ed0..e7421abcd93a 100644 --- a/drivers/media/platform/rockchip/isp/common.c +++ b/drivers/media/platform/rockchip/isp/common.c @@ -6,6 +6,7 @@ #include #include #include "dev.h" +#include "hw.h" #include "isp_ispp.h" #include "regs.h" @@ -36,6 +37,8 @@ void rkisp_next_write(struct rkisp_device *dev, u32 reg, u32 val, bool is_direct *flag = SW_REG_CACHE; if (dev->hw_dev->is_single || is_direct) { *flag = SW_REG_CACHE_SYNC; + if (dev->hw_dev->unite == ISP_UNITE_ONE) + return; writel(val, dev->hw_dev->base_next_addr + reg); } } @@ -166,13 +169,16 @@ void rkisp_update_regs(struct rkisp_device *dev, u32 start, u32 end) continue; } + if (hw->unite == ISP_UNITE_ONE && dev->unite_index == ISP_UNITE_RIGHT) + val = dev->sw_base_addr + i + RKISP_ISP_SW_MAX_SIZE; + if (*flag == SW_REG_CACHE) { if ((i == ISP3X_MAIN_RESIZE_CTRL || i == ISP32_BP_RESIZE_CTRL || i == ISP3X_SELF_RESIZE_CTRL) && *val == 0) *val = CIF_RSZ_CTRL_CFG_UPD; writel(*val, base + i); - if (hw->is_unite) { + if (hw->unite == ISP_UNITE_TWO) { val = dev->sw_base_addr + i + RKISP_ISP_SW_MAX_SIZE; if ((i == ISP3X_MAIN_RESIZE_CTRL || i == ISP32_BP_RESIZE_CTRL || diff --git a/drivers/media/platform/rockchip/isp/common.h b/drivers/media/platform/rockchip/isp/common.h index 609d95074c04..66c7ad8d4620 100644 --- a/drivers/media/platform/rockchip/isp/common.h +++ b/drivers/media/platform/rockchip/isp/common.h @@ -184,32 +184,6 @@ u32 rkisp_next_read_reg_cache(struct rkisp_device *dev, u32 reg); void rkisp_next_set_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val); void rkisp_next_clear_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask); -static inline void -rkisp_unite_write(struct rkisp_device *dev, u32 reg, u32 val, bool is_direct, bool is_unite) -{ - rkisp_write(dev, reg, val, is_direct); - if (is_unite) - rkisp_next_write(dev, reg, val, is_direct); -} - -static inline void -rkisp_unite_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, - u32 val, bool is_direct, bool is_unite) -{ - rkisp_set_bits(dev, reg, mask, val, is_direct); - if (is_unite) - rkisp_next_set_bits(dev, reg, mask, val, is_direct); -} - -static inline void -rkisp_unite_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask, - bool is_direct, bool is_unite) -{ - rkisp_clear_bits(dev, reg, mask, is_direct); - if (is_unite) - rkisp_next_clear_bits(dev, reg, mask, is_direct); -} - void rkisp_update_regs(struct rkisp_device *dev, u32 start, u32 end); int rkisp_alloc_buffer(struct rkisp_device *dev, struct rkisp_dummy_buffer *buf); diff --git a/drivers/media/platform/rockchip/isp/csi.c b/drivers/media/platform/rockchip/isp/csi.c index cb64f02110a0..a747d6737010 100644 --- a/drivers/media/platform/rockchip/isp/csi.c +++ b/drivers/media/platform/rockchip/isp/csi.c @@ -626,8 +626,7 @@ int rkisp_csi_config_patch(struct rkisp_device *dev) if (!dev->hw_dev->is_mi_update) rkisp_unite_write(dev, CSI2RX_CTRL0, - SW_IBUF_OP_MODE(dev->hdr.op_mode), - true, dev->hw_dev->is_unite); + SW_IBUF_OP_MODE(dev->hdr.op_mode), true); /* hdr merge */ switch (dev->hdr.op_mode) { @@ -651,25 +650,22 @@ int rkisp_csi_config_patch(struct rkisp_device *dev) return -EINVAL; } } - rkisp_unite_write(dev, ISP_HDRMGE_BASE, val, false, dev->hw_dev->is_unite); + rkisp_unite_write(dev, ISP_HDRMGE_BASE, val, false); val = RAW_RD_SIZE_ERR; if (!IS_HDR_RDBK(dev->hdr.op_mode)) val |= ISP21_MIPI_DROP_FRM; - rkisp_unite_set_bits(dev, CSI2RX_MASK_STAT, 0, val, true, dev->hw_dev->is_unite); + rkisp_unite_set_bits(dev, CSI2RX_MASK_STAT, 0, val, true); } if (IS_HDR_RDBK(dev->hdr.op_mode)) - rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, SW_MPIP_DROP_FRM_DIS, - true, dev->hw_dev->is_unite); + rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, SW_MPIP_DROP_FRM_DIS, true); if (dev->isp_ver >= ISP_V30) - rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, ISP3X_SW_ACK_FRM_PRO_DIS, - true, dev->hw_dev->is_unite); + rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, ISP3X_SW_ACK_FRM_PRO_DIS, true); /* line counter from isp out, default from mp out */ if (dev->isp_ver == ISP_V32_L) - rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, ISP32L_ISP2ENC_CNT_MUX, - true, dev->hw_dev->is_unite); + rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, ISP32L_ISP2ENC_CNT_MUX, true); dev->rdbk_cnt = -1; dev->rdbk_cnt_x1 = -1; dev->rdbk_cnt_x2 = -1; diff --git a/drivers/media/platform/rockchip/isp/dev.c b/drivers/media/platform/rockchip/isp/dev.c index f272630149cd..7da2c73b01fa 100644 --- a/drivers/media/platform/rockchip/isp/dev.c +++ b/drivers/media/platform/rockchip/isp/dev.c @@ -239,6 +239,8 @@ static int __isp_pipeline_s_isp_clk(struct rkisp_pipeline *p) data_rate >>= 3; end: do_div(data_rate, 1000 * 1000); + if (hw_dev->unite == ISP_UNITE_ONE) + data_rate *= 4; /* increase 25% margin */ data_rate += data_rate >> 2; @@ -252,7 +254,7 @@ end: /* set isp clock rate */ rkisp_set_clk_rate(hw_dev->clks[0], hw_dev->clk_rate_tbl[i].clk_rate * 1000000UL); - if (hw_dev->is_unite) + if (hw_dev->unite == ISP_UNITE_TWO) rkisp_set_clk_rate(hw_dev->clks[5], hw_dev->clk_rate_tbl[i].clk_rate * 1000000UL); /* aclk equal to core clk */ if (dev->isp_ver == ISP_V32) @@ -842,7 +844,7 @@ static int rkisp_plat_probe(struct platform_device *pdev) if (ret) return ret; - if (isp_dev->hw_dev->is_unite) + if (isp_dev->hw_dev->unite) mult = 2; isp_dev->sw_base_addr = devm_kzalloc(dev, RKISP_ISP_SW_MAX_SIZE * mult, GFP_KERNEL); if (!isp_dev->sw_base_addr) @@ -854,7 +856,7 @@ static int rkisp_plat_probe(struct platform_device *pdev) snprintf(isp_dev->media_dev.model, sizeof(isp_dev->media_dev.model), "%s%d", DRIVER_NAME, isp_dev->dev_id); - if (!isp_dev->hw_dev->is_unite) + if (!isp_dev->hw_dev->unite) strscpy(isp_dev->name, dev_name(dev), sizeof(isp_dev->name)); else snprintf(isp_dev->name, sizeof(isp_dev->name), @@ -980,6 +982,11 @@ static int __maybe_unused rkisp_runtime_resume(struct device *dev) if (isp_dev->hw_dev->is_assigned_clk) rkisp_clk_dbg = true; + + if (isp_dev->hw_dev->unite == ISP_UNITE_ONE && + !(isp_dev->isp_inp & INP_RAWRD2)) + rkisp_rdbk_auto = true; + isp_dev->cap_dev.wait_line = rkisp_wait_line; isp_dev->cap_dev.wrap_line = rkisp_wrap_line; isp_dev->is_rdbk_auto = rkisp_rdbk_auto; diff --git a/drivers/media/platform/rockchip/isp/dev.h b/drivers/media/platform/rockchip/isp/dev.h index 0b73b4f3ba20..4510f9ea04aa 100644 --- a/drivers/media/platform/rockchip/isp/dev.h +++ b/drivers/media/platform/rockchip/isp/dev.h @@ -103,6 +103,25 @@ enum rkisp_rdbk_filt { RDBK_F_MAX }; +/* unite mode for isp to process high resolution + * ISP_UNITE_TWO: image splits left and right to two isp hardware + * ISP_UNITE_ONE: image splits left and right to single isp hardware + */ +enum { + ISP_UNITE_NONE = 0, + ISP_UNITE_TWO = 1, + ISP_UNITE_ONE = 2, +}; + +/* left and right index + * ISP_UNITE_LEFT: left of image to isp process + * ISP_UNITE_RIGHT: right of image to isp process + */ +enum { + ISP_UNITE_LEFT = 0, + ISP_UNITE_RIGHT = 1, +}; + /* * struct rkisp_pipeline - An ISP hardware pipeline * @@ -249,11 +268,40 @@ struct rkisp_device { bool is_pre_on; bool is_first_double; bool is_probe_end; + bool is_frame_double; struct rkisp_vicap_input vicap_in; u8 multi_mode; u8 multi_index; u8 rawaf_irq_cnt; + u8 unite_index; }; + +static inline void +rkisp_unite_write(struct rkisp_device *dev, u32 reg, u32 val, bool is_direct) +{ + rkisp_write(dev, reg, val, is_direct); + if (dev->hw_dev->unite) + rkisp_next_write(dev, reg, val, is_direct); +} + +static inline void +rkisp_unite_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, + u32 val, bool is_direct) +{ + rkisp_set_bits(dev, reg, mask, val, is_direct); + if (dev->hw_dev->unite) + rkisp_next_set_bits(dev, reg, mask, val, is_direct); +} + +static inline void +rkisp_unite_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask, + bool is_direct) +{ + rkisp_clear_bits(dev, reg, mask, is_direct); + if (dev->hw_dev->unite) + rkisp_next_clear_bits(dev, reg, mask, is_direct); +} + #endif diff --git a/drivers/media/platform/rockchip/isp/dmarx.c b/drivers/media/platform/rockchip/isp/dmarx.c index b7af0af8dc3f..529c0999a779 100644 --- a/drivers/media/platform/rockchip/isp/dmarx.c +++ b/drivers/media/platform/rockchip/isp/dmarx.c @@ -318,7 +318,6 @@ static struct streams_ops rkisp_dmarx_streams_ops = { static int rawrd_config_mi(struct rkisp_stream *stream) { struct rkisp_device *dev = stream->ispdev; - bool is_unite = dev->hw_dev->is_unite; u32 val; val = rkisp_read(dev, CSI2RX_DATA_IDS_1, true); @@ -348,8 +347,8 @@ static int rawrd_config_mi(struct rkisp_stream *stream) val |= CIF_CSI2_DT_RAW12; } rkisp_unite_write(dev, CSI2RX_RAW_RD_CTRL, - stream->memory << 2, false, is_unite); - rkisp_unite_write(dev, CSI2RX_DATA_IDS_1, val, false, is_unite); + stream->memory << 2, false); + rkisp_unite_write(dev, CSI2RX_DATA_IDS_1, val, false); rkisp_rawrd_set_pic_size(dev, stream->out_fmt.width, stream->out_fmt.height); mi_raw_length(stream); @@ -376,7 +375,7 @@ static void update_rawrd(struct rkisp_stream *stream) } val += stream->curr_buf->buff_addr[RKISP_PLANE_Y]; rkisp_write(dev, stream->config->mi.y_base_ad_init, val, false); - if (dev->hw_dev->is_unite) { + if (dev->hw_dev->unite) { u32 offs = stream->out_fmt.width / 2 - RKMOUDLE_UNITE_EXTEND_PIXEL; if (stream->memory) @@ -464,13 +463,10 @@ static int dmarx_frame_end(struct rkisp_stream *stream) } dev->hdr.op_mode = dev->rd_mode; rkisp_unite_write(dev, CSI2RX_CTRL0, - SW_IBUF_OP_MODE(dev->hdr.op_mode), - true, dev->hw_dev->is_unite); + SW_IBUF_OP_MODE(dev->hdr.op_mode), true); rkisp_unite_set_bits(dev, CSI2RX_MASK_STAT, - 0, ISP21_MIPI_DROP_FRM, - true, dev->hw_dev->is_unite); - rkisp_unite_clear_bits(dev, CIF_ISP_IMSC, CIF_ISP_FRAME_IN, - true, dev->hw_dev->is_unite); + 0, ISP21_MIPI_DROP_FRM, true); + rkisp_unite_clear_bits(dev, CIF_ISP_IMSC, CIF_ISP_FRAME_IN, true); dev_info(dev->dev, "switch online seq:%d mode:0x%x\n", rx_buf->sequence, dev->rd_mode); @@ -1135,7 +1131,7 @@ void rkisp_rawrd_set_pic_size(struct rkisp_device *dev, { struct rkisp_isp_subdev *sdev = &dev->isp_sdev; u8 mult = sdev->in_fmt.fmt_type == FMT_YUV ? 2 : 1; - bool is_unite = dev->hw_dev->is_unite; + bool is_unite = !!dev->hw_dev->unite; u32 w = !is_unite ? width : width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL; /* rx height should equal to isp height + offset for read back mode */ @@ -1149,7 +1145,7 @@ void rkisp_rawrd_set_pic_size(struct rkisp_device *dev, height += RKMODULE_EXTEND_LINE; w *= mult; - rkisp_unite_write(dev, CSI2RX_RAW_RD_PIC_SIZE, height << 16 | w, false, is_unite); + rkisp_unite_write(dev, CSI2RX_RAW_RD_PIC_SIZE, height << 16 | w, false); } void rkisp_dmarx_get_frame(struct rkisp_device *dev, u32 *id, diff --git a/drivers/media/platform/rockchip/isp/hw.c b/drivers/media/platform/rockchip/isp/hw.c index e892f7340e2b..d9d1627f6de5 100644 --- a/drivers/media/platform/rockchip/isp/hw.c +++ b/drivers/media/platform/rockchip/isp/hw.c @@ -132,7 +132,7 @@ static void default_sw_reg_flag(struct rkisp_device *dev) for (i = 0; i < size; i++) { flag = dev->sw_base_addr + reg[i] + RKISP_ISP_SW_REG_SIZE; *flag = SW_REG_CACHE; - if (dev->hw_dev->is_unite) { + if (dev->hw_dev->unite) { flag += RKISP_ISP_SW_MAX_SIZE / 4; *flag = SW_REG_CACHE; } @@ -144,7 +144,7 @@ static irqreturn_t mipi_irq_hdl(int irq, void *ctx) struct device *dev = ctx; struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev); struct rkisp_device *isp = hw_dev->isp[hw_dev->mipi_dev_id]; - void __iomem *base = !hw_dev->is_unite ? + void __iomem *base = hw_dev->unite != ISP_UNITE_TWO ? hw_dev->base_addr : hw_dev->base_next_addr; ktime_t t = 0; s64 us; @@ -201,7 +201,7 @@ static irqreturn_t mi_irq_hdl(int irq, void *ctx) struct device *dev = ctx; struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev); struct rkisp_device *isp = hw_dev->isp[hw_dev->cur_dev_id]; - void __iomem *base = !hw_dev->is_unite ? + void __iomem *base = hw_dev->unite != ISP_UNITE_TWO ? hw_dev->base_addr : hw_dev->base_next_addr; u32 mis_val, tx_isr = MI_RAW0_WR_FRAME | MI_RAW1_WR_FRAME | MI_RAW2_WR_FRAME | MI_RAW3_WR_FRAME; @@ -237,7 +237,7 @@ static irqreturn_t isp_irq_hdl(int irq, void *ctx) struct device *dev = ctx; struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev); struct rkisp_device *isp = hw_dev->isp[hw_dev->cur_dev_id]; - void __iomem *base = !hw_dev->is_unite ? + void __iomem *base = hw_dev->unite != ISP_UNITE_TWO ? hw_dev->base_addr : hw_dev->base_next_addr; unsigned int mis_val, mis_3a = 0; ktime_t t = 0; @@ -455,6 +455,9 @@ static const struct isp_clk_info rv1106_isp_clk_rate[] = { }, { .clk_rate = 350, .refer_data = 3072, + }, { + .clk_rate = 440, + .refer_data = 3840, } }; @@ -636,7 +639,7 @@ void rkisp_soft_reset(struct rkisp_hw_dev *dev, bool is_secure) /* record clk config and recover */ iccl0 = readl(base + CIF_ICCL); clk_ctrl0 = readl(base + CTRL_VI_ISP_CLK_CTRL); - if (dev->is_unite) { + if (dev->unite == ISP_UNITE_TWO) { iccl1 = readl(dev->base_next_addr + CIF_ICCL); clk_ctrl1 = readl(dev->base_next_addr + CTRL_VI_ISP_CLK_CTRL); } @@ -646,7 +649,7 @@ void rkisp_soft_reset(struct rkisp_hw_dev *dev, bool is_secure) * isp soft reset first to protect isp reset. */ writel(0xffff, base + CIF_IRCL); - if (dev->is_unite) + if (dev->unite == ISP_UNITE_TWO) writel(0xffff, dev->base_next_addr + CIF_IRCL); udelay(10); } @@ -669,7 +672,7 @@ void rkisp_soft_reset(struct rkisp_hw_dev *dev, bool is_secure) writel(val, base + CIF_IRCL); if (dev->isp_ver == ISP_V32) rv1106_sdmmc_put_lock(); - if (dev->is_unite) + if (dev->unite == ISP_UNITE_TWO) writel(0xffff, dev->base_next_addr + CIF_IRCL); udelay(10); @@ -681,7 +684,7 @@ void rkisp_soft_reset(struct rkisp_hw_dev *dev, bool is_secure) writel(iccl0, base + CIF_ICCL); writel(clk_ctrl0, base + CTRL_VI_ISP_CLK_CTRL); - if (dev->is_unite) { + if (dev->unite == ISP_UNITE_TWO) { writel(iccl1, dev->base_next_addr + CIF_ICCL); writel(clk_ctrl1, dev->base_next_addr + CTRL_VI_ISP_CLK_CTRL); } @@ -722,7 +725,7 @@ static void isp_config_clk(struct rkisp_hw_dev *dev, int on) writel(val, dev->base_addr + CIF_ICCL); if (dev->isp_ver == ISP_V32) rv1106_sdmmc_put_lock(); - if (dev->is_unite) + if (dev->unite == ISP_UNITE_TWO) writel(val, dev->base_next_addr + CIF_ICCL); if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) { @@ -752,7 +755,7 @@ static void isp_config_clk(struct rkisp_hw_dev *dev, int on) writel(val, dev->base_addr + CTRL_VI_ISP_CLK_CTRL); if (dev->isp_ver == ISP_V32) rv1106_sdmmc_put_lock(); - if (dev->is_unite) + if (dev->unite == ISP_UNITE_TWO) writel(val, dev->base_next_addr + CTRL_VI_ISP_CLK_CTRL); } } @@ -789,7 +792,7 @@ static int enable_sys_clk(struct rkisp_hw_dev *dev) if (!dev->is_assigned_clk) { rate = dev->clk_rate_tbl[0].clk_rate * 1000000UL; rkisp_set_clk_rate(dev->clks[0], rate); - if (dev->is_unite) + if (dev->unite == ISP_UNITE_TWO) rkisp_set_clk_rate(dev->clks[5], rate); } rkisp_soft_reset(dev, false); @@ -861,21 +864,11 @@ static int rkisp_hw_probe(struct platform_device *pdev) return -ENOMEM; match_data = match->data; - hw_dev->is_unite = match_data->unite; dev_set_drvdata(dev, hw_dev); hw_dev->dev = dev; hw_dev->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP); dev_info(dev, "is_thunderboot: %d\n", hw_dev->is_thunderboot); - memset(&hw_dev->max_in, 0, sizeof(hw_dev->max_in)); - if (!of_property_read_u32_array(node, "max-input", &hw_dev->max_in.w, 3)) { - hw_dev->max_in.is_fix = true; - if (hw_dev->is_unite) { - hw_dev->max_in.w /= 2; - hw_dev->max_in.w += RKMOUDLE_UNITE_EXTEND_PIXEL; - } - } - dev_info(dev, "max input:%dx%d@%dfps\n", - hw_dev->max_in.w, hw_dev->max_in.h, hw_dev->max_in.fps); + hw_dev->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf"); if (IS_ERR(hw_dev->grf)) dev_warn(dev, "Missing rockchip,grf property\n"); @@ -922,6 +915,27 @@ static int rkisp_hw_probe(struct platform_device *pdev) } } + hw_dev->isp_ver = match_data->isp_ver; + if (match_data->unite) { + hw_dev->unite = ISP_UNITE_TWO; + } else if (device_property_read_bool(dev, "rockchip,unite-en")) { + hw_dev->unite = ISP_UNITE_ONE; + hw_dev->base_next_addr = hw_dev->base_addr; + } else { + hw_dev->unite = ISP_UNITE_NONE; + } + + memset(&hw_dev->max_in, 0, sizeof(hw_dev->max_in)); + if (!of_property_read_u32_array(node, "max-input", &hw_dev->max_in.w, 3)) { + hw_dev->max_in.is_fix = true; + if (hw_dev->unite) { + hw_dev->max_in.w /= 2; + hw_dev->max_in.w += RKMOUDLE_UNITE_EXTEND_PIXEL; + } + } + dev_info(dev, "max input:%dx%d@%dfps\n", + hw_dev->max_in.w, hw_dev->max_in.h, hw_dev->max_in.fps); + rkisp_monitor = device_property_read_bool(dev, "rockchip,restart-monitor-en"); hw_dev->mipi_irq = -1; @@ -967,10 +981,8 @@ static int rkisp_hw_probe(struct platform_device *pdev) hw_dev->dev_link_num = 0; hw_dev->cur_dev_id = 0; hw_dev->mipi_dev_id = 0; - hw_dev->pre_dev_id = 0; + hw_dev->pre_dev_id = -1; hw_dev->is_multi_overflow = false; - hw_dev->isp_ver = match_data->isp_ver; - hw_dev->is_unite = match_data->unite; mutex_init(&hw_dev->dev_lock); spin_lock_init(&hw_dev->rdbk_lock); atomic_set(&hw_dev->refcnt, 0); @@ -1020,7 +1032,7 @@ static void rkisp_hw_shutdown(struct platform_device *pdev) hw_dev->is_shutdown = true; if (pm_runtime_active(&pdev->dev)) { writel(0xffff, hw_dev->base_addr + CIF_IRCL); - if (hw_dev->is_unite) + if (hw_dev->unite == ISP_UNITE_TWO) writel(0xffff, hw_dev->base_next_addr + CIF_IRCL); } dev_info(&pdev->dev, "%s\n", __func__); @@ -1060,7 +1072,7 @@ void rkisp_hw_enum_isp_size(struct rkisp_hw_dev *hw_dev) hw_dev->is_single = false; w = isp->isp_sdev.in_crop.width; h = isp->isp_sdev.in_crop.height; - if (hw_dev->is_unite) + if (hw_dev->unite) w = w / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL; hw_dev->isp_size[i].w = w; hw_dev->isp_size[i].h = h; @@ -1072,6 +1084,8 @@ void rkisp_hw_enum_isp_size(struct rkisp_hw_dev *hw_dev) hw_dev->max_in.h = h; } } + if (hw_dev->unite == ISP_UNITE_ONE) + hw_dev->is_single = false; for (i = 0; i < hw_dev->dev_num; i++) { isp = hw_dev->isp[i]; if (!isp || (isp && !isp->is_hw_link)) @@ -1085,7 +1099,7 @@ static int __maybe_unused rkisp_runtime_resume(struct device *dev) struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev); void __iomem *base = hw_dev->base_addr; struct rkisp_device *isp; - int mult = hw_dev->is_unite ? 2 : 1; + int mult = hw_dev->unite ? 2 : 1; int ret, i; void *buf; @@ -1101,7 +1115,7 @@ static int __maybe_unused rkisp_runtime_resume(struct device *dev) buf = isp->sw_base_addr; memset(buf, 0, RKISP_ISP_SW_MAX_SIZE * mult); memcpy_fromio(buf, base, RKISP_ISP_SW_REG_SIZE); - if (hw_dev->is_unite) { + if (hw_dev->unite) { buf += RKISP_ISP_SW_MAX_SIZE; base = hw_dev->base_next_addr; memcpy_fromio(buf, base, RKISP_ISP_SW_REG_SIZE); diff --git a/drivers/media/platform/rockchip/isp/hw.h b/drivers/media/platform/rockchip/isp/hw.h index ce57aef2fbc6..5c7129463101 100644 --- a/drivers/media/platform/rockchip/isp/hw.h +++ b/drivers/media/platform/rockchip/isp/hw.h @@ -89,6 +89,7 @@ struct rkisp_hw_dev { struct rkisp_monitor monitor; u64 iq_feature; int buf_init_cnt; + u32 unite; bool is_feature_on; bool is_dma_contig; bool is_dma_sg_ops; @@ -99,7 +100,6 @@ struct rkisp_hw_dev { bool is_thunderboot; bool is_buf_init; bool is_shutdown; - bool is_unite; bool is_multi_overflow; bool is_runing; bool is_frm_buf; diff --git a/drivers/media/platform/rockchip/isp/isp_params.c b/drivers/media/platform/rockchip/isp/isp_params.c index 65f8525e536b..3db85a23c220 100644 --- a/drivers/media/platform/rockchip/isp/isp_params.c +++ b/drivers/media/platform/rockchip/isp/isp_params.c @@ -146,11 +146,12 @@ static void rkisp_params_vb2_buf_queue(struct vb2_buffer *vb) struct rkisp_buffer *params_buf = to_rkisp_buffer(vbuf); struct vb2_queue *vq = vb->vb2_queue; struct rkisp_isp_params_vdev *params_vdev = vq->drv_priv; + struct rkisp_device *dev = params_vdev->dev; void *first_param; unsigned long flags; unsigned int cur_frame_id = -1; - cur_frame_id = atomic_read(¶ms_vdev->dev->isp_sdev.frm_sync_seq) - 1; + cur_frame_id = atomic_read(&dev->isp_sdev.frm_sync_seq) - 1; if (params_vdev->first_params) { first_param = vb2_plane_vaddr(vb, 0); params_vdev->ops->save_first_param(params_vdev, first_param); @@ -159,16 +160,22 @@ static void rkisp_params_vb2_buf_queue(struct vb2_buffer *vb) vb2_buffer_done(¶ms_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); params_vdev->first_params = false; wake_up(¶ms_vdev->dev->sync_onoff); - if (params_vdev->dev->is_first_double) { - dev_info(params_vdev->dev->dev, "first params for fast\n"); - params_vdev->dev->is_first_double = false; - rkisp_trigger_read_back(params_vdev->dev, false, false, false); + if (dev->is_first_double) { + dev_info(dev->dev, "first params for fast\n"); + dev->is_first_double = false; + dev->sw_rd_cnt = 0; + if (dev->hw_dev->unite == ISP_UNITE_ONE) { + dev->unite_index = ISP_UNITE_LEFT; + dev->sw_rd_cnt += dev->hw_dev->is_multi_overflow ? 3 : 1; + } + params_vdev->rdbk_times = dev->sw_rd_cnt + 1; + rkisp_trigger_read_back(dev, false, false, false); } - dev_info(params_vdev->dev->dev, "first params buf queue\n"); + dev_info(dev->dev, "first params buf queue\n"); return; } - if (params_vdev->dev->procfs.mode & + if (dev->procfs.mode & (RKISP_PROCFS_FIL_AIQ | RKISP_PROCFS_FIL_SW)) { vb2_buffer_done(¶ms_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); return; @@ -208,9 +215,7 @@ static void rkisp_params_vb2_stop_streaming(struct vb2_queue *vq) break; } - if (buf) - vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); - buf = NULL; + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); } if (params_vdev->cur_buf) { @@ -406,8 +411,7 @@ void rkisp_params_first_cfg(struct rkisp_isp_params_vdev *params_vdev, stream->out_isp_fmt.fmt_type == FMT_RGB) rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, quantization == V4L2_QUANTIZATION_FULL_RANGE ? - mask : 0, - false, dev->hw_dev->is_unite); + mask : 0, false); dev->isp_sdev.quantization = quantization; } } diff --git a/drivers/media/platform/rockchip/isp/isp_params_v32.c b/drivers/media/platform/rockchip/isp/isp_params_v32.c index d4c5e49d4973..4343412c111c 100644 --- a/drivers/media/platform/rockchip/isp/isp_params_v32.c +++ b/drivers/media/platform/rockchip/isp/isp_params_v32.c @@ -47,9 +47,12 @@ isp3_param_write_direct(struct rkisp_isp_params_vdev *params_vdev, static inline void isp3_param_write(struct rkisp_isp_params_vdev *params_vdev, - u32 value, u32 addr) + u32 value, u32 addr, u32 id) { - rkisp_write(params_vdev->dev, addr, value, false); + if (id == ISP3_LEFT) + rkisp_write(params_vdev->dev, addr, value, false); + else + rkisp_next_write(params_vdev->dev, addr, value, false); } static inline u32 @@ -59,45 +62,63 @@ isp3_param_read_direct(struct rkisp_isp_params_vdev *params_vdev, u32 addr) } static inline u32 -isp3_param_read(struct rkisp_isp_params_vdev *params_vdev, u32 addr) +isp3_param_read(struct rkisp_isp_params_vdev *params_vdev, u32 addr, u32 id) { - return rkisp_read(params_vdev->dev, addr, false); + u32 val; + + if (id == ISP3_LEFT) + val = rkisp_read(params_vdev->dev, addr, false); + else + val = rkisp_next_read(params_vdev->dev, addr, false); + return val; } static inline u32 -isp3_param_read_cache(struct rkisp_isp_params_vdev *params_vdev, u32 addr) +isp3_param_read_cache(struct rkisp_isp_params_vdev *params_vdev, u32 addr, u32 id) { - return rkisp_read_reg_cache(params_vdev->dev, addr); + u32 val; + + if (id == ISP3_LEFT) + val = rkisp_read_reg_cache(params_vdev->dev, addr); + else + val = rkisp_next_read_reg_cache(params_vdev->dev, addr); + return val; } static inline void isp3_param_set_bits(struct rkisp_isp_params_vdev *params_vdev, - u32 reg, u32 bit_mask) + u32 reg, u32 bit_mask, u32 id) { - rkisp_set_bits(params_vdev->dev, reg, 0, bit_mask, false); + if (id == ISP3_LEFT) + rkisp_set_bits(params_vdev->dev, reg, 0, bit_mask, false); + else + rkisp_next_set_bits(params_vdev->dev, reg, 0, bit_mask, false); } static inline void isp3_param_clear_bits(struct rkisp_isp_params_vdev *params_vdev, - u32 reg, u32 bit_mask) + u32 reg, u32 bit_mask, u32 id) { - rkisp_clear_bits(params_vdev->dev, reg, bit_mask, false); + if (id == ISP3_LEFT) + rkisp_clear_bits(params_vdev->dev, reg, bit_mask, false); + else + rkisp_next_clear_bits(params_vdev->dev, reg, bit_mask, false); } static void isp_dpcc_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_dpcc_cfg *arg) + const struct isp2x_dpcc_cfg *arg, u32 id) { u32 value; int i; - value = isp3_param_read(params_vdev, ISP3X_DPCC0_MODE); + value = isp3_param_read(params_vdev, ISP3X_DPCC0_MODE, id); value &= ISP_DPCC_EN; value |= !!arg->stage1_enable << 2 | !!arg->grayscale_mode << 1; - isp3_param_write(params_vdev, value, ISP3X_DPCC0_MODE); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_MODE); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_MODE, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_MODE, id); value = (arg->sw_rk_out_sel & 0x03) << 5 | !!arg->sw_dpcc_output_sel << 4 | @@ -105,15 +126,15 @@ isp_dpcc_config(struct rkisp_isp_params_vdev *params_vdev, !!arg->stage1_g_3x3 << 2 | !!arg->stage1_incl_rb_center << 1 | !!arg->stage1_incl_green_center; - isp3_param_write(params_vdev, value, ISP3X_DPCC0_OUTPUT_MODE); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_OUTPUT_MODE); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_OUTPUT_MODE, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_OUTPUT_MODE, id); value = !!arg->stage1_use_fix_set << 3 | !!arg->stage1_use_set_3 << 2 | !!arg->stage1_use_set_2 << 1 | !!arg->stage1_use_set_1; - isp3_param_write(params_vdev, value, ISP3X_DPCC0_SET_USE); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_SET_USE); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_SET_USE, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_SET_USE, id); value = !!arg->sw_rk_red_blue1_en << 13 | !!arg->rg_red_blue1_enable << 12 | @@ -127,8 +148,8 @@ isp_dpcc_config(struct rkisp_isp_params_vdev *params_vdev, !!arg->ro_green1_enable << 2 | !!arg->lc_green1_enable << 1 | !!arg->pg_green1_enable; - isp3_param_write(params_vdev, value, ISP3X_DPCC0_METHODS_SET_1); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_METHODS_SET_1); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_METHODS_SET_1, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_METHODS_SET_1, id); value = !!arg->sw_rk_red_blue2_en << 13 | !!arg->rg_red_blue2_enable << 12 | @@ -142,8 +163,8 @@ isp_dpcc_config(struct rkisp_isp_params_vdev *params_vdev, !!arg->ro_green2_enable << 2 | !!arg->lc_green2_enable << 1 | !!arg->pg_green2_enable; - isp3_param_write(params_vdev, value, ISP3X_DPCC0_METHODS_SET_2); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_METHODS_SET_2); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_METHODS_SET_2, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_METHODS_SET_2, id); value = !!arg->sw_rk_red_blue3_en << 13 | !!arg->rg_red_blue3_enable << 12 | @@ -157,74 +178,74 @@ isp_dpcc_config(struct rkisp_isp_params_vdev *params_vdev, !!arg->ro_green3_enable << 2 | !!arg->lc_green3_enable << 1 | !!arg->pg_green3_enable; - isp3_param_write(params_vdev, value, ISP3X_DPCC0_METHODS_SET_3); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_METHODS_SET_3); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_METHODS_SET_3, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_METHODS_SET_3, id); value = ISP_PACK_4BYTE(arg->line_thr_1_g, arg->line_thr_1_rb, arg->sw_mindis1_g, arg->sw_mindis1_rb); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_THRESH_1); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_THRESH_1); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_THRESH_1, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_THRESH_1, id); value = ISP_PACK_4BYTE(arg->line_mad_fac_1_g, arg->line_mad_fac_1_rb, arg->sw_dis_scale_max1, arg->sw_dis_scale_min1); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_MAD_FAC_1); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_MAD_FAC_1); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_MAD_FAC_1, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_MAD_FAC_1, id); value = ISP_PACK_4BYTE(arg->pg_fac_1_g, arg->pg_fac_1_rb, 0, 0); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_PG_FAC_1); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_PG_FAC_1); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_PG_FAC_1, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_PG_FAC_1, id); value = ISP_PACK_4BYTE(arg->rnd_thr_1_g, arg->rnd_thr_1_rb, 0, 0); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_THRESH_1); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_THRESH_1); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_THRESH_1, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_THRESH_1, id); value = ISP_PACK_4BYTE(arg->rg_fac_1_g, arg->rg_fac_1_rb, 0, 0); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_RG_FAC_1); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_RG_FAC_1); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_RG_FAC_1, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_RG_FAC_1, id); value = ISP_PACK_4BYTE(arg->line_thr_2_g, arg->line_thr_2_rb, arg->sw_mindis2_g, arg->sw_mindis2_rb); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_THRESH_2); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_THRESH_2); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_THRESH_2, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_THRESH_2, id); value = ISP_PACK_4BYTE(arg->line_mad_fac_2_g, arg->line_mad_fac_2_rb, arg->sw_dis_scale_max2, arg->sw_dis_scale_min2); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_MAD_FAC_2); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_MAD_FAC_2); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_MAD_FAC_2, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_MAD_FAC_2, id); value = ISP_PACK_4BYTE(arg->pg_fac_2_g, arg->pg_fac_2_rb, 0, 0); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_PG_FAC_2); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_PG_FAC_2); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_PG_FAC_2, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_PG_FAC_2, id); value = ISP_PACK_4BYTE(arg->rnd_thr_2_g, arg->rnd_thr_2_rb, 0, 0); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_THRESH_2); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_THRESH_2); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_THRESH_2, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_THRESH_2, id); value = ISP_PACK_4BYTE(arg->rg_fac_2_g, arg->rg_fac_2_rb, 0, 0); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_RG_FAC_2); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_RG_FAC_2); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_RG_FAC_2, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_RG_FAC_2, id); value = ISP_PACK_4BYTE(arg->line_thr_3_g, arg->line_thr_3_rb, arg->sw_mindis3_g, arg->sw_mindis3_rb); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_THRESH_3); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_THRESH_3); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_THRESH_3, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_THRESH_3, id); value = ISP_PACK_4BYTE(arg->line_mad_fac_3_g, arg->line_mad_fac_3_rb, arg->sw_dis_scale_max3, arg->sw_dis_scale_min3); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_MAD_FAC_3); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_MAD_FAC_3); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_MAD_FAC_3, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_MAD_FAC_3, id); value = ISP_PACK_4BYTE(arg->pg_fac_3_g, arg->pg_fac_3_rb, 0, 0); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_PG_FAC_3); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_PG_FAC_3); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_PG_FAC_3, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_PG_FAC_3, id); value = ISP_PACK_4BYTE(arg->rnd_thr_3_g, arg->rnd_thr_3_rb, 0, 0); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_THRESH_3); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_THRESH_3); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_THRESH_3, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_THRESH_3, id); value = ISP_PACK_4BYTE(arg->rg_fac_3_g, arg->rg_fac_3_rb, 0, 0); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_RG_FAC_3); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_RG_FAC_3); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_RG_FAC_3, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_RG_FAC_3, id); value = (arg->ro_lim_3_rb & 0x03) << 10 | (arg->ro_lim_3_g & 0x03) << 8 | @@ -232,8 +253,8 @@ isp_dpcc_config(struct rkisp_isp_params_vdev *params_vdev, (arg->ro_lim_2_g & 0x03) << 4 | (arg->ro_lim_1_rb & 0x03) << 2 | (arg->ro_lim_1_g & 0x03); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_RO_LIMITS); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_RO_LIMITS); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_RO_LIMITS, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_RO_LIMITS, id); value = (arg->rnd_offs_3_rb & 0x03) << 10 | (arg->rnd_offs_3_g & 0x03) << 8 | @@ -241,8 +262,8 @@ isp_dpcc_config(struct rkisp_isp_params_vdev *params_vdev, (arg->rnd_offs_2_g & 0x03) << 4 | (arg->rnd_offs_1_rb & 0x03) << 2 | (arg->rnd_offs_1_g & 0x03); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_OFFS); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_OFFS); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_OFFS, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_OFFS, id); value = !!arg->bpt_rb_3x3 << 11 | !!arg->bpt_g_3x3 << 10 | @@ -254,75 +275,75 @@ isp_dpcc_config(struct rkisp_isp_params_vdev *params_vdev, !!arg->bpt_use_set_1 << 4 | !!arg->bpt_cor_en << 1 | !!arg->bpt_det_en; - isp3_param_write(params_vdev, value, ISP3X_DPCC0_BPT_CTRL); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_BPT_CTRL); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_BPT_CTRL, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_BPT_CTRL, id); - isp3_param_write(params_vdev, arg->bp_number, ISP3X_DPCC0_BPT_NUMBER); - isp3_param_write(params_vdev, arg->bp_number, ISP3X_DPCC1_BPT_NUMBER); - isp3_param_write(params_vdev, arg->bp_table_addr, ISP3X_DPCC0_BPT_ADDR); - isp3_param_write(params_vdev, arg->bp_table_addr, ISP3X_DPCC1_BPT_ADDR); + isp3_param_write(params_vdev, arg->bp_number, ISP3X_DPCC0_BPT_NUMBER, id); + isp3_param_write(params_vdev, arg->bp_number, ISP3X_DPCC1_BPT_NUMBER, id); + isp3_param_write(params_vdev, arg->bp_table_addr, ISP3X_DPCC0_BPT_ADDR, id); + isp3_param_write(params_vdev, arg->bp_table_addr, ISP3X_DPCC1_BPT_ADDR, id); value = ISP_PACK_2SHORT(arg->bpt_h_addr, arg->bpt_v_addr); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_BPT_DATA); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_BPT_DATA); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_BPT_DATA, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_BPT_DATA, id); - isp3_param_write(params_vdev, arg->bp_cnt, ISP3X_DPCC0_BP_CNT); - isp3_param_write(params_vdev, arg->bp_cnt, ISP3X_DPCC1_BP_CNT); + isp3_param_write(params_vdev, arg->bp_cnt, ISP3X_DPCC0_BP_CNT, id); + isp3_param_write(params_vdev, arg->bp_cnt, ISP3X_DPCC1_BP_CNT, id); - isp3_param_write(params_vdev, arg->sw_pdaf_en, ISP3X_DPCC0_PDAF_EN); - isp3_param_write(params_vdev, arg->sw_pdaf_en, ISP3X_DPCC1_PDAF_EN); + isp3_param_write(params_vdev, arg->sw_pdaf_en, ISP3X_DPCC0_PDAF_EN, id); + isp3_param_write(params_vdev, arg->sw_pdaf_en, ISP3X_DPCC1_PDAF_EN, id); value = 0; for (i = 0; i < ISP32_DPCC_PDAF_POINT_NUM; i++) value |= !!arg->pdaf_point_en[i] << i; - isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_POINT_EN); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_POINT_EN); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_POINT_EN, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_POINT_EN, id); value = ISP_PACK_2SHORT(arg->pdaf_offsetx, arg->pdaf_offsety); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_OFFSET); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_OFFSET); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_OFFSET, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_OFFSET, id); value = ISP_PACK_2SHORT(arg->pdaf_wrapx, arg->pdaf_wrapy); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_WRAP); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_WRAP); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_WRAP, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_WRAP, id); value = ISP_PACK_2SHORT(arg->pdaf_wrapx_num, arg->pdaf_wrapy_num); - isp3_param_write(params_vdev, value, ISP_DPCC0_PDAF_SCOPE); - isp3_param_write(params_vdev, value, ISP_DPCC1_PDAF_SCOPE); + isp3_param_write(params_vdev, value, ISP_DPCC0_PDAF_SCOPE, id); + isp3_param_write(params_vdev, value, ISP_DPCC1_PDAF_SCOPE, id); for (i = 0; i < ISP32_DPCC_PDAF_POINT_NUM / 2; i++) { value = ISP_PACK_4BYTE(arg->point[2 * i].x, arg->point[2 * i].y, arg->point[2 * i + 1].x, arg->point[2 * i + 1].y); - isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_POINT_0 + 4 * i); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_POINT_0 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_POINT_0 + 4 * i, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_POINT_0 + 4 * i, id); } - isp3_param_write(params_vdev, arg->pdaf_forward_med, ISP3X_DPCC0_PDAF_FORWARD_MED); - isp3_param_write(params_vdev, arg->pdaf_forward_med, ISP3X_DPCC1_PDAF_FORWARD_MED); + isp3_param_write(params_vdev, arg->pdaf_forward_med, ISP3X_DPCC0_PDAF_FORWARD_MED, id); + isp3_param_write(params_vdev, arg->pdaf_forward_med, ISP3X_DPCC1_PDAF_FORWARD_MED, id); } static void -isp_dpcc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_dpcc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { u32 value; - value = isp3_param_read(params_vdev, ISP3X_DPCC0_MODE); + value = isp3_param_read(params_vdev, ISP3X_DPCC0_MODE, id); value &= ~ISP_DPCC_EN; if (en) value |= ISP_DPCC_EN; - isp3_param_write(params_vdev, value, ISP3X_DPCC0_MODE); - isp3_param_write(params_vdev, value, ISP3X_DPCC1_MODE); + isp3_param_write(params_vdev, value, ISP3X_DPCC0_MODE, id); + isp3_param_write(params_vdev, value, ISP3X_DPCC1_MODE, id); } static void isp_bls_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_bls_cfg *arg) + const struct isp32_bls_cfg *arg, u32 id) { const struct isp2x_bls_fixed_val *pval; u32 new_control, value; - new_control = isp3_param_read(params_vdev, ISP3X_BLS_CTRL); + new_control = isp3_param_read(params_vdev, ISP3X_BLS_CTRL, id); new_control &= (ISP_BLS_ENA | ISP32_BLS_BLS2_EN); pval = &arg->bls1_val; @@ -331,29 +352,29 @@ isp_bls_config(struct rkisp_isp_params_vdev *params_vdev, switch (params_vdev->raw_type) { case RAW_BGGR: - isp3_param_write(params_vdev, pval->r, ISP3X_BLS1_D_FIXED); - isp3_param_write(params_vdev, pval->gr, ISP3X_BLS1_C_FIXED); - isp3_param_write(params_vdev, pval->gb, ISP3X_BLS1_B_FIXED); - isp3_param_write(params_vdev, pval->b, ISP3X_BLS1_A_FIXED); + isp3_param_write(params_vdev, pval->r, ISP3X_BLS1_D_FIXED, id); + isp3_param_write(params_vdev, pval->gr, ISP3X_BLS1_C_FIXED, id); + isp3_param_write(params_vdev, pval->gb, ISP3X_BLS1_B_FIXED, id); + isp3_param_write(params_vdev, pval->b, ISP3X_BLS1_A_FIXED, id); break; case RAW_GBRG: - isp3_param_write(params_vdev, pval->r, ISP3X_BLS1_C_FIXED); - isp3_param_write(params_vdev, pval->gr, ISP3X_BLS1_D_FIXED); - isp3_param_write(params_vdev, pval->gb, ISP3X_BLS1_A_FIXED); - isp3_param_write(params_vdev, pval->b, ISP3X_BLS1_B_FIXED); + isp3_param_write(params_vdev, pval->r, ISP3X_BLS1_C_FIXED, id); + isp3_param_write(params_vdev, pval->gr, ISP3X_BLS1_D_FIXED, id); + isp3_param_write(params_vdev, pval->gb, ISP3X_BLS1_A_FIXED, id); + isp3_param_write(params_vdev, pval->b, ISP3X_BLS1_B_FIXED, id); break; case RAW_GRBG: - isp3_param_write(params_vdev, pval->r, ISP3X_BLS1_B_FIXED); - isp3_param_write(params_vdev, pval->gr, ISP3X_BLS1_A_FIXED); - isp3_param_write(params_vdev, pval->gb, ISP3X_BLS1_D_FIXED); - isp3_param_write(params_vdev, pval->b, ISP3X_BLS1_C_FIXED); + isp3_param_write(params_vdev, pval->r, ISP3X_BLS1_B_FIXED, id); + isp3_param_write(params_vdev, pval->gr, ISP3X_BLS1_A_FIXED, id); + isp3_param_write(params_vdev, pval->gb, ISP3X_BLS1_D_FIXED, id); + isp3_param_write(params_vdev, pval->b, ISP3X_BLS1_C_FIXED, id); break; case RAW_RGGB: default: - isp3_param_write(params_vdev, pval->r, ISP3X_BLS1_A_FIXED); - isp3_param_write(params_vdev, pval->gr, ISP3X_BLS1_B_FIXED); - isp3_param_write(params_vdev, pval->gb, ISP3X_BLS1_C_FIXED); - isp3_param_write(params_vdev, pval->b, ISP3X_BLS1_D_FIXED); + isp3_param_write(params_vdev, pval->r, ISP3X_BLS1_A_FIXED, id); + isp3_param_write(params_vdev, pval->gr, ISP3X_BLS1_B_FIXED, id); + isp3_param_write(params_vdev, pval->gb, ISP3X_BLS1_C_FIXED, id); + isp3_param_write(params_vdev, pval->b, ISP3X_BLS1_D_FIXED, id); break; } } @@ -363,107 +384,107 @@ isp_bls_config(struct rkisp_isp_params_vdev *params_vdev, if (!arg->enable_auto) { switch (params_vdev->raw_type) { case RAW_BGGR: - isp3_param_write(params_vdev, pval->r, ISP3X_BLS_D_FIXED); - isp3_param_write(params_vdev, pval->gr, ISP3X_BLS_C_FIXED); - isp3_param_write(params_vdev, pval->gb, ISP3X_BLS_B_FIXED); - isp3_param_write(params_vdev, pval->b, ISP3X_BLS_A_FIXED); + isp3_param_write(params_vdev, pval->r, ISP3X_BLS_D_FIXED, id); + isp3_param_write(params_vdev, pval->gr, ISP3X_BLS_C_FIXED, id); + isp3_param_write(params_vdev, pval->gb, ISP3X_BLS_B_FIXED, id); + isp3_param_write(params_vdev, pval->b, ISP3X_BLS_A_FIXED, id); break; case RAW_GBRG: - isp3_param_write(params_vdev, pval->r, ISP3X_BLS_C_FIXED); - isp3_param_write(params_vdev, pval->gr, ISP3X_BLS_D_FIXED); - isp3_param_write(params_vdev, pval->gb, ISP3X_BLS_A_FIXED); - isp3_param_write(params_vdev, pval->b, ISP3X_BLS_B_FIXED); + isp3_param_write(params_vdev, pval->r, ISP3X_BLS_C_FIXED, id); + isp3_param_write(params_vdev, pval->gr, ISP3X_BLS_D_FIXED, id); + isp3_param_write(params_vdev, pval->gb, ISP3X_BLS_A_FIXED, id); + isp3_param_write(params_vdev, pval->b, ISP3X_BLS_B_FIXED, id); break; case RAW_GRBG: - isp3_param_write(params_vdev, pval->r, ISP3X_BLS_B_FIXED); - isp3_param_write(params_vdev, pval->gr, ISP3X_BLS_A_FIXED); - isp3_param_write(params_vdev, pval->gb, ISP3X_BLS_D_FIXED); - isp3_param_write(params_vdev, pval->b, ISP3X_BLS_C_FIXED); + isp3_param_write(params_vdev, pval->r, ISP3X_BLS_B_FIXED, id); + isp3_param_write(params_vdev, pval->gr, ISP3X_BLS_A_FIXED, id); + isp3_param_write(params_vdev, pval->gb, ISP3X_BLS_D_FIXED, id); + isp3_param_write(params_vdev, pval->b, ISP3X_BLS_C_FIXED, id); break; case RAW_RGGB: default: - isp3_param_write(params_vdev, pval->r, ISP3X_BLS_A_FIXED); - isp3_param_write(params_vdev, pval->gr, ISP3X_BLS_B_FIXED); - isp3_param_write(params_vdev, pval->gb, ISP3X_BLS_C_FIXED); - isp3_param_write(params_vdev, pval->b, ISP3X_BLS_D_FIXED); + isp3_param_write(params_vdev, pval->r, ISP3X_BLS_A_FIXED, id); + isp3_param_write(params_vdev, pval->gr, ISP3X_BLS_B_FIXED, id); + isp3_param_write(params_vdev, pval->gb, ISP3X_BLS_C_FIXED, id); + isp3_param_write(params_vdev, pval->b, ISP3X_BLS_D_FIXED, id); break; } } else { if (arg->en_windows & BIT(1)) { - isp3_param_write(params_vdev, arg->bls_window2.h_offs, ISP3X_BLS_H2_START); + isp3_param_write(params_vdev, arg->bls_window2.h_offs, ISP3X_BLS_H2_START, id); value = arg->bls_window2.h_offs + arg->bls_window2.h_size; - isp3_param_write(params_vdev, value, ISP3X_BLS_H2_STOP); - isp3_param_write(params_vdev, arg->bls_window2.v_offs, ISP3X_BLS_V2_START); + isp3_param_write(params_vdev, value, ISP3X_BLS_H2_STOP, id); + isp3_param_write(params_vdev, arg->bls_window2.v_offs, ISP3X_BLS_V2_START, id); value = arg->bls_window2.v_offs + arg->bls_window2.v_size; - isp3_param_write(params_vdev, value, ISP3X_BLS_V2_STOP); + isp3_param_write(params_vdev, value, ISP3X_BLS_V2_STOP, id); new_control |= ISP_BLS_WINDOW_2; } if (arg->en_windows & BIT(0)) { - isp3_param_write(params_vdev, arg->bls_window1.h_offs, ISP3X_BLS_H1_START); + isp3_param_write(params_vdev, arg->bls_window1.h_offs, ISP3X_BLS_H1_START, id); value = arg->bls_window1.h_offs + arg->bls_window1.h_size; - isp3_param_write(params_vdev, value, ISP3X_BLS_H1_STOP); - isp3_param_write(params_vdev, arg->bls_window1.v_offs, ISP3X_BLS_V1_START); + isp3_param_write(params_vdev, value, ISP3X_BLS_H1_STOP, id); + isp3_param_write(params_vdev, arg->bls_window1.v_offs, ISP3X_BLS_V1_START, id); value = arg->bls_window1.v_offs + arg->bls_window1.v_size; - isp3_param_write(params_vdev, value, ISP3X_BLS_V1_STOP); + isp3_param_write(params_vdev, value, ISP3X_BLS_V1_STOP, id); new_control |= ISP_BLS_WINDOW_1; } - isp3_param_write(params_vdev, arg->bls_samples, ISP3X_BLS_SAMPLES); + isp3_param_write(params_vdev, arg->bls_samples, ISP3X_BLS_SAMPLES, id); new_control |= ISP_BLS_MODE_MEASURED; } - isp3_param_write(params_vdev, new_control, ISP3X_BLS_CTRL); + isp3_param_write(params_vdev, new_control, ISP3X_BLS_CTRL, id); - isp3_param_write(params_vdev, arg->isp_ob_offset, ISP32_BLS_ISP_OB_OFFSET); - isp3_param_write(params_vdev, arg->isp_ob_predgain, ISP32_BLS_ISP_OB_PREDGAIN); - isp3_param_write(params_vdev, arg->isp_ob_max, ISP32_BLS_ISP_OB_MAX); + isp3_param_write(params_vdev, arg->isp_ob_offset, ISP32_BLS_ISP_OB_OFFSET, id); + isp3_param_write(params_vdev, arg->isp_ob_predgain, ISP32_BLS_ISP_OB_PREDGAIN, id); + isp3_param_write(params_vdev, arg->isp_ob_max, ISP32_BLS_ISP_OB_MAX, id); } static void -isp_bls_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_bls_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { u32 new_control; - new_control = isp3_param_read(params_vdev, ISP3X_BLS_CTRL); + new_control = isp3_param_read(params_vdev, ISP3X_BLS_CTRL, id); if (en) new_control |= ISP_BLS_ENA; else new_control &= ~ISP_BLS_ENA; - isp3_param_write(params_vdev, new_control, ISP3X_BLS_CTRL); + isp3_param_write(params_vdev, new_control, ISP3X_BLS_CTRL, id); } static void isp_sdg_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_sdg_cfg *arg) + const struct isp2x_sdg_cfg *arg, u32 id) { int i; - isp3_param_write(params_vdev, arg->xa_pnts.gamma_dx0, ISP3X_ISP_GAMMA_DX_LO); - isp3_param_write(params_vdev, arg->xa_pnts.gamma_dx1, ISP3X_ISP_GAMMA_DX_HI); + isp3_param_write(params_vdev, arg->xa_pnts.gamma_dx0, ISP3X_ISP_GAMMA_DX_LO, id); + isp3_param_write(params_vdev, arg->xa_pnts.gamma_dx1, ISP3X_ISP_GAMMA_DX_HI, id); for (i = 0; i < ISP32_DEGAMMA_CURVE_SIZE; i++) { isp3_param_write(params_vdev, arg->curve_r.gamma_y[i], - ISP3X_ISP_GAMMA_R_Y_0 + i * 4); + ISP3X_ISP_GAMMA_R_Y_0 + i * 4, id); isp3_param_write(params_vdev, arg->curve_g.gamma_y[i], - ISP3X_ISP_GAMMA_G_Y_0 + i * 4); + ISP3X_ISP_GAMMA_G_Y_0 + i * 4, id); isp3_param_write(params_vdev, arg->curve_b.gamma_y[i], - ISP3X_ISP_GAMMA_B_Y_0 + i * 4); + ISP3X_ISP_GAMMA_B_Y_0 + i * 4, id); } } static void -isp_sdg_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_sdg_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { u32 val; - val = isp3_param_read_cache(params_vdev, ISP3X_ISP_CTRL0); + val = isp3_param_read_cache(params_vdev, ISP3X_ISP_CTRL0, id); if (en) isp3_param_write(params_vdev, val | CIF_ISP_CTRL_ISP_GAMMA_IN_ENA, - ISP3X_ISP_CTRL0); + ISP3X_ISP_CTRL0, id); else isp3_param_write(params_vdev, val & ~CIF_ISP_CTRL_ISP_GAMMA_IN_ENA, - ISP3X_ISP_CTRL0); + ISP3X_ISP_CTRL0, id); } static void __maybe_unused @@ -524,21 +545,21 @@ isp_lsc_matrix_cfg_ddr(struct rkisp_isp_params_vdev *params_vdev, } rkisp_prepare_buffer(params_vdev->dev, &priv_val->buf_lsclut[buf_idx]); data = priv_val->buf_lsclut[buf_idx].dma_addr; - isp3_param_write(params_vdev, data, ISP3X_MI_LUT_LSC_RD_BASE); - isp3_param_write(params_vdev, ISP32_LSC_LUT_TBL_SIZE, ISP3X_MI_LUT_LSC_RD_WSIZE); + isp3_param_write(params_vdev, data, ISP3X_MI_LUT_LSC_RD_BASE, 0); + isp3_param_write(params_vdev, ISP32_LSC_LUT_TBL_SIZE, ISP3X_MI_LUT_LSC_RD_WSIZE, 0); } static void isp_lsc_matrix_cfg_sram(struct rkisp_isp_params_vdev *params_vdev, const struct isp3x_lsc_cfg *pconfig, - bool is_check) + bool is_check, u32 id) { struct rkisp_device *dev = params_vdev->dev; u32 sram_addr, data, table; int i, j; if (is_check && - !(isp3_param_read(params_vdev, ISP3X_LSC_CTRL) & ISP_LSC_EN)) + !(isp3_param_read(params_vdev, ISP3X_LSC_CTRL, id) & ISP_LSC_EN)) return; table = isp3_param_read_direct(params_vdev, ISP3X_LSC_STATUS); @@ -601,21 +622,21 @@ isp_lsc_cfg_sram_task(unsigned long data) (struct rkisp_isp_params_vdev *)data; struct isp32_isp_params_cfg *params = params_vdev->isp32_params; - isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true); + isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true, 0); } static void isp_lsc_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp3x_lsc_cfg *arg) + const struct isp3x_lsc_cfg *arg, u32 id) { struct rkisp_isp_params_val_v32 *priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; - struct isp32_isp_params_cfg *params_rec = params_vdev->isp32_params; + struct isp32_isp_params_cfg *params_rec = params_vdev->isp32_params + id; struct rkisp_device *dev = params_vdev->dev; u32 data, lsc_ctrl; int i; - lsc_ctrl = isp3_param_read(params_vdev, ISP3X_LSC_CTRL); + lsc_ctrl = isp3_param_read(params_vdev, ISP3X_LSC_CTRL, id); if (dev->isp_ver == ISP_V32_L) { /* one lsc sram table * online mode lsc lut load from ddr quick for some sensor VB short @@ -625,7 +646,7 @@ isp_lsc_config(struct rkisp_isp_params_vdev *params_vdev, if (!IS_HDR_RDBK(dev->rd_mode)) isp_lsc_matrix_cfg_ddr(params_vdev, arg); else if (dev->hw_dev->is_single) - isp_lsc_matrix_cfg_sram(params_vdev, arg, false); + isp_lsc_matrix_cfg_sram(params_vdev, arg, false, id); else params_rec->others.lsc_cfg = *arg; } else { @@ -637,27 +658,27 @@ isp_lsc_config(struct rkisp_isp_params_vdev *params_vdev, for (i = 0; i < ISP32_LSC_SIZE_TBL_SIZE / 4; i++) { /* program x size tables */ data = CIF_ISP_LSC_SECT_SIZE(arg->x_size_tbl[i * 2], arg->x_size_tbl[i * 2 + 1]); - isp3_param_write(params_vdev, data, ISP3X_LSC_XSIZE_01 + i * 4); + isp3_param_write(params_vdev, data, ISP3X_LSC_XSIZE_01 + i * 4, id); data = CIF_ISP_LSC_SECT_SIZE(arg->x_size_tbl[i * 2 + 8], arg->x_size_tbl[i * 2 + 9]); - isp3_param_write(params_vdev, data, ISP3X_LSC_XSIZE_89 + i * 4); + isp3_param_write(params_vdev, data, ISP3X_LSC_XSIZE_89 + i * 4, id); /* program x grad tables */ data = CIF_ISP_LSC_SECT_SIZE(arg->x_grad_tbl[i * 2], arg->x_grad_tbl[i * 2 + 1]); - isp3_param_write(params_vdev, data, ISP3X_LSC_XGRAD_01 + i * 4); + isp3_param_write(params_vdev, data, ISP3X_LSC_XGRAD_01 + i * 4, id); data = CIF_ISP_LSC_SECT_SIZE(arg->x_grad_tbl[i * 2 + 8], arg->x_grad_tbl[i * 2 + 9]); - isp3_param_write(params_vdev, data, ISP3X_LSC_XGRAD_89 + i * 4); + isp3_param_write(params_vdev, data, ISP3X_LSC_XGRAD_89 + i * 4, id); /* program y size tables */ data = CIF_ISP_LSC_SECT_SIZE(arg->y_size_tbl[i * 2], arg->y_size_tbl[i * 2 + 1]); - isp3_param_write(params_vdev, data, ISP3X_LSC_YSIZE_01 + i * 4); + isp3_param_write(params_vdev, data, ISP3X_LSC_YSIZE_01 + i * 4, id); data = CIF_ISP_LSC_SECT_SIZE(arg->y_size_tbl[i * 2 + 8], arg->y_size_tbl[i * 2 + 9]); - isp3_param_write(params_vdev, data, ISP3X_LSC_YSIZE_89 + i * 4); + isp3_param_write(params_vdev, data, ISP3X_LSC_YSIZE_89 + i * 4, id); /* program y grad tables */ data = CIF_ISP_LSC_SECT_SIZE(arg->y_grad_tbl[i * 2], arg->y_grad_tbl[i * 2 + 1]); - isp3_param_write(params_vdev, data, ISP3X_LSC_YGRAD_01 + i * 4); + isp3_param_write(params_vdev, data, ISP3X_LSC_YGRAD_01 + i * 4, id); data = CIF_ISP_LSC_SECT_SIZE(arg->y_grad_tbl[i * 2 + 8], arg->y_grad_tbl[i * 2 + 9]); - isp3_param_write(params_vdev, data, ISP3X_LSC_YGRAD_89 + i * 4); + isp3_param_write(params_vdev, data, ISP3X_LSC_YGRAD_89 + i * 4, id); } if (arg->sector_16x16) @@ -666,15 +687,15 @@ isp_lsc_config(struct rkisp_isp_params_vdev *params_vdev, lsc_ctrl &= ~ISP3X_LSC_SECTOR_16X16; if (dev->isp_ver == ISP_V32_L && !IS_HDR_RDBK(dev->rd_mode)) lsc_ctrl |= ISP3X_LSC_LUT_EN; - isp3_param_write(params_vdev, lsc_ctrl, ISP3X_LSC_CTRL); + isp3_param_write(params_vdev, lsc_ctrl, ISP3X_LSC_CTRL, id); } static void -isp_lsc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_lsc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { struct rkisp_device *dev = params_vdev->dev; - struct isp32_isp_params_cfg *params_rec = params_vdev->isp32_params; - u32 val = isp3_param_read(params_vdev, ISP3X_LSC_CTRL); + struct isp32_isp_params_cfg *params_rec = params_vdev->isp32_params + id; + u32 val = isp3_param_read(params_vdev, ISP3X_LSC_CTRL, id); if (en == !!(val & ISP_LSC_EN)) return; @@ -683,99 +704,99 @@ isp_lsc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) val = ISP_LSC_EN | ISP32_SELF_FORCE_UPD; if (dev->isp_ver == ISP_V32_L && !IS_HDR_RDBK(dev->rd_mode)) val |= ISP3X_LSC_LUT_EN; - isp3_param_set_bits(params_vdev, ISP3X_LSC_CTRL, val); + isp3_param_set_bits(params_vdev, ISP3X_LSC_CTRL, val, id); if (dev->isp_ver == ISP_V32 && params_vdev->dev->hw_dev->is_single) isp_lsc_matrix_cfg_sram(params_vdev, - ¶ms_rec->others.lsc_cfg, false); + ¶ms_rec->others.lsc_cfg, false, id); } else { - isp3_param_clear_bits(params_vdev, ISP3X_LSC_CTRL, ISP_LSC_EN); - isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(8)); + isp3_param_clear_bits(params_vdev, ISP3X_LSC_CTRL, ISP_LSC_EN, id); + isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(8), id); } } static void isp_debayer_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_debayer_cfg *arg) + const struct isp32_debayer_cfg *arg, u32 id) { u32 value; - value = isp3_param_read(params_vdev, ISP3X_DEBAYER_CONTROL); + value = isp3_param_read(params_vdev, ISP3X_DEBAYER_CONTROL, id); value &= ISP_DEBAYER_EN; value |= !!arg->filter_g_en << 4; if (params_vdev->dev->isp_ver == ISP_V32) value |= !!arg->filter_c_en << 8; - isp3_param_write(params_vdev, value, ISP3X_DEBAYER_CONTROL); + isp3_param_write(params_vdev, value, ISP3X_DEBAYER_CONTROL, id); value = (arg->max_ratio & 0x3F) << 24 | arg->select_thed << 16 | (arg->thed1 & 0x0F) << 12 | (arg->thed0 & 0x0F) << 8 | (arg->dist_scale & 0x0F) << 4 | !!arg->clip_en; - isp3_param_write(params_vdev, value, ISP3X_DEBAYER_G_INTERP); + isp3_param_write(params_vdev, value, ISP3X_DEBAYER_G_INTERP, id); value = (arg->filter1_coe4 & 0x1F) << 24 | (arg->filter1_coe3 & 0x1F) << 16 | (arg->filter1_coe2 & 0x1F) << 8 | (arg->filter1_coe1 & 0x1F); - isp3_param_write(params_vdev, value, ISP3X_DEBAYER_G_INTERP_FILTER1); + isp3_param_write(params_vdev, value, ISP3X_DEBAYER_G_INTERP_FILTER1, id); value = (arg->filter2_coe4 & 0x1F) << 24 | (arg->filter2_coe3 & 0x1F) << 16 | (arg->filter2_coe2 & 0x1F) << 8 | (arg->filter2_coe1 & 0x1F); - isp3_param_write(params_vdev, value, ISP3X_DEBAYER_G_INTERP_FILTER2); + isp3_param_write(params_vdev, value, ISP3X_DEBAYER_G_INTERP_FILTER2, id); value = arg->hf_offset << 16 | (arg->gain_offset & 0xFFF); - isp3_param_write(params_vdev, value, ISP32_DEBAYER_G_INTERP_OFFSET); + isp3_param_write(params_vdev, value, ISP32_DEBAYER_G_INTERP_OFFSET, id); value = (arg->offset & 0x7FF); - isp3_param_write(params_vdev, value, ISP32_DEBAYER_G_FILTER_OFFSET); + isp3_param_write(params_vdev, value, ISP32_DEBAYER_G_FILTER_OFFSET, id); if (params_vdev->dev->isp_ver != ISP_V32) return; value = arg->guid_gaus_coe2 << 16 | arg->guid_gaus_coe1 << 8 | arg->guid_gaus_coe0; - isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_GUIDE_GAUS); + isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_GUIDE_GAUS, id); value = arg->ce_gaus_coe2 << 16 | arg->ce_gaus_coe1 << 8 | arg->ce_gaus_coe0; - isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_CE_GAUS); + isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_CE_GAUS, id); value = arg->alpha_gaus_coe2 << 16 | arg->alpha_gaus_coe1 << 8 | arg->alpha_gaus_coe0; - isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_ALPHA_GAUS); + isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_ALPHA_GAUS, id); value = (arg->loggd_offset & 0xfff) << 16 | (arg->loghf_offset & 0x1fff); - isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_LOG_OFFSET); + isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_LOG_OFFSET, id); value = (arg->alpha_scale & 0xfffff) << 12 | (arg->alpha_offset & 0xfff); - isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_ALPHA); + isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_ALPHA, id); value = (arg->edge_scale & 0xfffff) << 12 | (arg->edge_offset & 0xfff); - isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_EDGE); + isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_EDGE, id); value = (arg->wgtslope & 0xfff) << 16 | (arg->exp_shift & 0x3f) << 8 | arg->ce_sgm; - isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_IIR_0); + isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_IIR_0, id); value = (arg->wet_ghost & 0x3f) << 8 | (arg->wet_clip & 0x7f); - isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_IIR_1); + isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_IIR_1, id); value = (arg->bf_curwgt & 0x7f) << 24 | (arg->bf_clip & 0x7f) << 16 | arg->bf_sgm; - isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_BF); + isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_BF, id); } static void -isp_debayer_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_debayer_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { if (en) isp3_param_set_bits(params_vdev, - ISP3X_DEBAYER_CONTROL, ISP32_MODULE_EN); + ISP3X_DEBAYER_CONTROL, ISP32_MODULE_EN, id); else isp3_param_clear_bits(params_vdev, - ISP3X_DEBAYER_CONTROL, ISP32_MODULE_EN); + ISP3X_DEBAYER_CONTROL, ISP32_MODULE_EN, id); } static void isp_awbgain_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_awb_gain_cfg *arg) + const struct isp32_awb_gain_cfg *arg, u32 id) { struct rkisp_device *dev = params_vdev->dev; @@ -791,184 +812,184 @@ isp_awbgain_config(struct rkisp_isp_params_vdev *params_vdev, isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->gain0_green_b, arg->gain0_green_r), - ISP3X_ISP_AWB_GAIN0_G); + ISP3X_ISP_AWB_GAIN0_G, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->gain0_blue, arg->gain0_red), - ISP3X_ISP_AWB_GAIN0_RB); + ISP3X_ISP_AWB_GAIN0_RB, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->gain1_green_b, arg->gain1_green_r), - ISP3X_ISP_AWB_GAIN1_G); + ISP3X_ISP_AWB_GAIN1_G, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->gain1_blue, arg->gain1_red), - ISP3X_ISP_AWB_GAIN1_RB); + ISP3X_ISP_AWB_GAIN1_RB, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->gain2_green_b, arg->gain2_green_r), - ISP3X_ISP_AWB_GAIN2_G); + ISP3X_ISP_AWB_GAIN2_G, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->gain2_blue, arg->gain2_red), - ISP3X_ISP_AWB_GAIN2_RB); + ISP3X_ISP_AWB_GAIN2_RB, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->awb1_gain_gb, arg->awb1_gain_gr), - ISP32_ISP_AWB1_GAIN_G); + ISP32_ISP_AWB1_GAIN_G, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->awb1_gain_b, arg->awb1_gain_r), - ISP32_ISP_AWB1_GAIN_RB); + ISP32_ISP_AWB1_GAIN_RB, id); } static void -isp_awbgain_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_awbgain_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { u32 val; - val = isp3_param_read_cache(params_vdev, ISP3X_ISP_CTRL0); + val = isp3_param_read_cache(params_vdev, ISP3X_ISP_CTRL0, id); if (en) isp3_param_write(params_vdev, val | CIF_ISP_CTRL_ISP_AWB_ENA, - ISP3X_ISP_CTRL0); + ISP3X_ISP_CTRL0, id); else isp3_param_write(params_vdev, val & ~CIF_ISP_CTRL_ISP_AWB_ENA, - ISP3X_ISP_CTRL0); + ISP3X_ISP_CTRL0, id); } static void isp_ccm_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_ccm_cfg *arg) + const struct isp32_ccm_cfg *arg, u32 id) { u32 value; u32 i; - value = isp3_param_read(params_vdev, ISP3X_CCM_CTRL); + value = isp3_param_read(params_vdev, ISP3X_CCM_CTRL, id); value &= ISP_CCM_EN; value |= !!arg->asym_adj_en << 3 | !!arg->enh_adj_en << 2 | !!arg->highy_adjust_dis << 1; - isp3_param_write(params_vdev, value, ISP3X_CCM_CTRL); + isp3_param_write(params_vdev, value, ISP3X_CCM_CTRL, id); value = ISP_PACK_2SHORT(arg->coeff0_r, arg->coeff1_r); - isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_R); + isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_R, id); value = ISP_PACK_2SHORT(arg->coeff2_r, arg->offset_r); - isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_R); + isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_R, id); value = ISP_PACK_2SHORT(arg->coeff0_g, arg->coeff1_g); - isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_G); + isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_G, id); value = ISP_PACK_2SHORT(arg->coeff2_g, arg->offset_g); - isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_G); + isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_G, id); value = ISP_PACK_2SHORT(arg->coeff0_b, arg->coeff1_b); - isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_B); + isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_B, id); value = ISP_PACK_2SHORT(arg->coeff2_b, arg->offset_b); - isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_B); + isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_B, id); value = ISP_PACK_2SHORT(arg->coeff0_y, arg->coeff1_y); - isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_Y); + isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_Y, id); value = ISP_PACK_2SHORT(arg->coeff2_y, 0); - isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_Y); + isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_Y, id); for (i = 0; i < ISP32_CCM_CURVE_NUM / 2; i++) { value = ISP_PACK_2SHORT(arg->alp_y[2 * i], arg->alp_y[2 * i + 1]); - isp3_param_write(params_vdev, value, ISP3X_CCM_ALP_Y0 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_CCM_ALP_Y0 + 4 * i, id); } value = (arg->right_bit & 0xf) << 4 | (arg->bound_bit & 0xf); - isp3_param_write(params_vdev, value, ISP3X_CCM_BOUND_BIT); + isp3_param_write(params_vdev, value, ISP3X_CCM_BOUND_BIT, id); value = (arg->color_coef1_g2y & 0x7ff) << 16 | (arg->color_coef0_r2y & 0x7ff); - isp3_param_write(params_vdev, value, ISP32_CCM_ENHANCE0); + isp3_param_write(params_vdev, value, ISP32_CCM_ENHANCE0, id); value = (arg->color_enh_rat_max & 0x3fff) << 16 | (arg->color_coef2_b2y & 0x7ff); - isp3_param_write(params_vdev, value, ISP32_CCM_ENHANCE1); + isp3_param_write(params_vdev, value, ISP32_CCM_ENHANCE1, id); } static void -isp_ccm_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_ccm_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { if (en) - isp3_param_set_bits(params_vdev, ISP3X_CCM_CTRL, ISP_CCM_EN); + isp3_param_set_bits(params_vdev, ISP3X_CCM_CTRL, ISP_CCM_EN, id); else - isp3_param_clear_bits(params_vdev, ISP3X_CCM_CTRL, ISP_CCM_EN); + isp3_param_clear_bits(params_vdev, ISP3X_CCM_CTRL, ISP_CCM_EN, id); } static void isp_goc_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp3x_gammaout_cfg *arg) + const struct isp3x_gammaout_cfg *arg, u32 id) { int i; u32 value; - value = isp3_param_read(params_vdev, ISP3X_GAMMA_OUT_CTRL); + value = isp3_param_read(params_vdev, ISP3X_GAMMA_OUT_CTRL, id); value &= ISP3X_GAMMA_OUT_EN; value |= !!arg->equ_segm << 1 | !!arg->finalx4_dense_en << 2; - isp3_param_write(params_vdev, value, ISP3X_GAMMA_OUT_CTRL); + isp3_param_write(params_vdev, value, ISP3X_GAMMA_OUT_CTRL, id); - isp3_param_write(params_vdev, arg->offset, ISP3X_GAMMA_OUT_OFFSET); + isp3_param_write(params_vdev, arg->offset, ISP3X_GAMMA_OUT_OFFSET, id); for (i = 0; i < ISP32_GAMMA_OUT_MAX_SAMPLES / 2; i++) { value = ISP_PACK_2SHORT(arg->gamma_y[2 * i], arg->gamma_y[2 * i + 1]); - isp3_param_write(params_vdev, value, ISP3X_GAMMA_OUT_Y0 + i * 4); + isp3_param_write(params_vdev, value, ISP3X_GAMMA_OUT_Y0 + i * 4, id); } - isp3_param_write(params_vdev, arg->gamma_y[2 * i], ISP3X_GAMMA_OUT_Y0 + i * 4); + isp3_param_write(params_vdev, arg->gamma_y[2 * i], ISP3X_GAMMA_OUT_Y0 + i * 4, id); } static void -isp_goc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_goc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { if (en) - isp3_param_set_bits(params_vdev, ISP3X_GAMMA_OUT_CTRL, ISP3X_GAMMA_OUT_EN); + isp3_param_set_bits(params_vdev, ISP3X_GAMMA_OUT_CTRL, ISP3X_GAMMA_OUT_EN, id); else - isp3_param_clear_bits(params_vdev, ISP3X_GAMMA_OUT_CTRL, ISP3X_GAMMA_OUT_EN); + isp3_param_clear_bits(params_vdev, ISP3X_GAMMA_OUT_CTRL, ISP3X_GAMMA_OUT_EN, id); } static void isp_cproc_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_cproc_cfg *arg) + const struct isp2x_cproc_cfg *arg, u32 id) { u32 quantization = params_vdev->quantization; - isp3_param_write(params_vdev, arg->contrast, ISP3X_CPROC_CONTRAST); - isp3_param_write(params_vdev, arg->hue, ISP3X_CPROC_HUE); - isp3_param_write(params_vdev, arg->sat, ISP3X_CPROC_SATURATION); - isp3_param_write(params_vdev, arg->brightness, ISP3X_CPROC_BRIGHTNESS); + isp3_param_write(params_vdev, arg->contrast, ISP3X_CPROC_CONTRAST, id); + isp3_param_write(params_vdev, arg->hue, ISP3X_CPROC_HUE, id); + isp3_param_write(params_vdev, arg->sat, ISP3X_CPROC_SATURATION, id); + isp3_param_write(params_vdev, arg->brightness, ISP3X_CPROC_BRIGHTNESS, id); if (quantization != V4L2_QUANTIZATION_FULL_RANGE) { isp3_param_clear_bits(params_vdev, ISP3X_CPROC_CTRL, CIF_C_PROC_YOUT_FULL | CIF_C_PROC_YIN_FULL | - CIF_C_PROC_COUT_FULL); + CIF_C_PROC_COUT_FULL, id); } else { isp3_param_set_bits(params_vdev, ISP3X_CPROC_CTRL, CIF_C_PROC_YOUT_FULL | CIF_C_PROC_YIN_FULL | - CIF_C_PROC_COUT_FULL); + CIF_C_PROC_COUT_FULL, id); } } static void -isp_cproc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_cproc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { if (en) isp3_param_set_bits(params_vdev, ISP3X_CPROC_CTRL, - CIF_C_PROC_CTR_ENABLE); + CIF_C_PROC_CTR_ENABLE, id); else isp3_param_clear_bits(params_vdev, ISP3X_CPROC_CTRL, - CIF_C_PROC_CTR_ENABLE); + CIF_C_PROC_CTR_ENABLE, id); } static void isp_ie_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_ie_cfg *arg) + const struct isp2x_ie_cfg *arg, u32 id) { u32 eff_ctrl; - eff_ctrl = isp3_param_read(params_vdev, ISP3X_IMG_EFF_CTRL); + eff_ctrl = isp3_param_read(params_vdev, ISP3X_IMG_EFF_CTRL, id); eff_ctrl &= ~CIF_IMG_EFF_CTRL_MODE_MASK; if (params_vdev->quantization == V4L2_QUANTIZATION_FULL_RANGE) @@ -979,7 +1000,7 @@ isp_ie_config(struct rkisp_isp_params_vdev *params_vdev, eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SEPIA; break; case V4L2_COLORFX_SET_CBCR: - isp3_param_write(params_vdev, arg->eff_tint, ISP3X_IMG_EFF_TINT); + isp3_param_write(params_vdev, arg->eff_tint, ISP3X_IMG_EFF_TINT, id); eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SEPIA; break; /* @@ -989,25 +1010,25 @@ isp_ie_config(struct rkisp_isp_params_vdev *params_vdev, case V4L2_COLORFX_AQUA: eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_COLOR_SEL; isp3_param_write(params_vdev, arg->color_sel, - ISP3X_IMG_EFF_COLOR_SEL); + ISP3X_IMG_EFF_COLOR_SEL, id); break; case V4L2_COLORFX_EMBOSS: eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_EMBOSS; isp3_param_write(params_vdev, arg->eff_mat_1, - CIF_IMG_EFF_MAT_1); + CIF_IMG_EFF_MAT_1, id); isp3_param_write(params_vdev, arg->eff_mat_2, - CIF_IMG_EFF_MAT_2); + CIF_IMG_EFF_MAT_2, id); isp3_param_write(params_vdev, arg->eff_mat_3, - CIF_IMG_EFF_MAT_3); + CIF_IMG_EFF_MAT_3, id); break; case V4L2_COLORFX_SKETCH: eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SKETCH; isp3_param_write(params_vdev, arg->eff_mat_3, - CIF_IMG_EFF_MAT_3); + CIF_IMG_EFF_MAT_3, id); isp3_param_write(params_vdev, arg->eff_mat_4, - CIF_IMG_EFF_MAT_4); + CIF_IMG_EFF_MAT_4, id); isp3_param_write(params_vdev, arg->eff_mat_5, - CIF_IMG_EFF_MAT_5); + CIF_IMG_EFF_MAT_5, id); break; case V4L2_COLORFX_BW: eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_BLACKWHITE; @@ -1019,25 +1040,26 @@ isp_ie_config(struct rkisp_isp_params_vdev *params_vdev, break; } - isp3_param_write(params_vdev, eff_ctrl, ISP3X_IMG_EFF_CTRL); + isp3_param_write(params_vdev, eff_ctrl, ISP3X_IMG_EFF_CTRL, id); } static void -isp_ie_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_ie_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { if (en) { isp3_param_set_bits(params_vdev, ISP3X_IMG_EFF_CTRL, CIF_IMG_EFF_CTRL_CFG_UPD | - CIF_IMG_EFF_CTRL_ENABLE); + CIF_IMG_EFF_CTRL_ENABLE, id); } else { isp3_param_clear_bits(params_vdev, ISP3X_IMG_EFF_CTRL, - CIF_IMG_EFF_CTRL_ENABLE); + CIF_IMG_EFF_CTRL_ENABLE, id); } } static void isp_rawae_config_foraf(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_rawaf_meas_cfg *arg) + const struct isp32_rawaf_meas_cfg *arg, + struct isp2x_window *win, u32 id) { u32 block_hsize, block_vsize; u32 addr, value; @@ -1052,33 +1074,40 @@ isp_rawae_config_foraf(struct rkisp_isp_params_vdev *params_vdev, } else { addr = ISP3X_RAWAE_BIG1_BASE; } - value = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL); + value = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL, id); value &= ISP3X_RAWAE_BIG_EN; value |= ISP3X_RAWAE_BIG_WND0_NUM(wnd_num_idx); - isp3_param_write(params_vdev, value, addr + ISP3X_RAWAE_BIG_CTRL); + isp3_param_write(params_vdev, value, addr + ISP3X_RAWAE_BIG_CTRL, id); isp3_param_write(params_vdev, - ISP_PACK_2SHORT(arg->win[0].h_offs, arg->win[0].v_offs), - addr + ISP3X_RAWAE_BIG_OFFSET); + ISP_PACK_2SHORT(win->h_offs, win->v_offs), + addr + ISP3X_RAWAE_BIG_OFFSET, id); - block_hsize = arg->win[0].h_size / ae_wnd_num[wnd_num_idx]; - block_vsize = arg->win[0].v_size / ae_wnd_num[wnd_num_idx]; + block_hsize = win->h_size / ae_wnd_num[wnd_num_idx]; + block_vsize = win->v_size / ae_wnd_num[wnd_num_idx]; isp3_param_write(params_vdev, ISP_PACK_2SHORT(block_hsize, block_vsize), - addr + ISP3X_RAWAE_BIG_BLK_SIZE); + addr + ISP3X_RAWAE_BIG_BLK_SIZE, id); } static void isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_rawaf_meas_cfg *arg) + const struct isp32_rawaf_meas_cfg *arg, u32 id) { + struct rkisp_device *dev = params_vdev->dev; + struct v4l2_rect *out_crop = &dev->isp_sdev.out_crop; + u32 width = out_crop->width, height = out_crop->height; u32 i, var, ctrl; u16 h_size, v_size; u16 h_offs, v_offs; u8 gaus_en, viir_en, v1_fir_sel; size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->win), arg->num_afm_win); + struct isp2x_window win_ae; + + if (dev->hw_dev->unite) + width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL; for (i = 0; i < num_of_win; i++) { h_size = arg->win[i].h_size; @@ -1086,9 +1115,19 @@ isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev, h_offs = arg->win[i].h_offs < 2 ? 2 : arg->win[i].h_offs; v_offs = arg->win[i].v_offs < 1 ? 1 : arg->win[i].v_offs; + if (!v_size || v_size + v_offs - 2 > height) + v_size = height - v_offs - 2; + if (!h_size || h_size + h_offs - 2 > width) + h_size = width - h_offs - 2; + if (i == 0) { h_size = h_size / 15 * 15; v_size = v_size / 15 * 15; + + win_ae.h_size = h_size; + win_ae.v_size = v_size; + win_ae.h_offs = h_offs; + win_ae.v_offs = v_offs; } /* @@ -1097,7 +1136,7 @@ isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev, */ isp3_param_write(params_vdev, ISP_PACK_2SHORT(v_offs, h_offs), - ISP3X_RAWAF_OFFSET_WINA + i * 8); + ISP3X_RAWAF_OFFSET_WINA + i * 8, id); /* * value must be smaller than [width of picture -2] @@ -1105,7 +1144,7 @@ isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev, */ isp3_param_write(params_vdev, ISP_PACK_2SHORT(v_size, h_size), - ISP3X_RAWAF_SIZE_WINA + i * 8); + ISP3X_RAWAF_SIZE_WINA + i * 8, id); } var = 0; @@ -1114,60 +1153,60 @@ isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev, var |= ISP3X_RAWAF_INTLINE0_EN << i; var |= ISP3X_RAWAF_INELINE0(arg->line_num[i]) << 4 * i; } - isp3_param_write(params_vdev, var, ISP3X_RAWAF_INT_LINE); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_INT_LINE, id); if (params_vdev->dev->isp_ver == ISP_V32_L) { var = (arg->hldg_dilate_num & 0x7) << 16 | !!arg->bls_en << 12 | (arg->bls_offset & 0x1FF); - isp3_param_write(params_vdev, var, ISP32L_RAWAF_CTRL1); + isp3_param_write(params_vdev, var, ISP32L_RAWAF_CTRL1, id); } - var = isp3_param_read(params_vdev, ISP3X_RAWAF_THRES); + var = isp3_param_read(params_vdev, ISP3X_RAWAF_THRES, id); var &= ~0xFFFF; var |= arg->afm_thres; - isp3_param_write(params_vdev, var, ISP3X_RAWAF_THRES); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_THRES, id); var = (arg->lum_var_shift[1] & 0x7) << 20 | (arg->lum_var_shift[0] & 0x7) << 16 | (arg->afm_var_shift[1] & 0x7) << 4 | (arg->afm_var_shift[0] & 0x7); if (params_vdev->dev->isp_ver == ISP_V32_L) var |= (arg->tnrin_shift & 0xf) << 8; - isp3_param_write(params_vdev, var, ISP3X_RAWAF_VAR_SHIFT); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_VAR_SHIFT, id); for (i = 0; i < ISP32_RAWAF_GAMMA_NUM / 2; i++) { var = ISP_PACK_2SHORT(arg->gamma_y[2 * i], arg->gamma_y[2 * i + 1]); - isp3_param_write(params_vdev, var, ISP3X_RAWAF_GAMMA_Y0 + i * 4); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_GAMMA_Y0 + i * 4, id); } var = ISP_PACK_2SHORT(arg->gamma_y[16], 0); - isp3_param_write(params_vdev, var, ISP3X_RAWAF_GAMMA_Y8); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_GAMMA_Y8, id); var = (arg->v1iir_var_shift & 0x7) << 8 | (arg->h1iir_var_shift & 0x7); if (params_vdev->dev->isp_ver == ISP_V32) var |= (arg->v2iir_var_shift & 0x7) << 12 | (arg->h2iir_var_shift & 0x7) << 4; - isp3_param_write(params_vdev, var, ISP3X_RAWAF_HVIIR_VAR_SHIFT); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_HVIIR_VAR_SHIFT, id); var = ISP_PACK_2SHORT(arg->h_fv_thresh, arg->v_fv_thresh); - isp3_param_write(params_vdev, var, ISP3X_RAWAF_HIIR_THRESH); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_HIIR_THRESH, id); for (i = 0; i < ISP32_RAWAF_VFIR_COE_NUM; i++) { var = ISP_PACK_2SHORT(arg->v1fir_coe[i], arg->v2fir_coe[i]); - isp3_param_write(params_vdev, var, ISP32_RAWAF_V_FIR_COE0 + i * 4); + isp3_param_write(params_vdev, var, ISP32_RAWAF_V_FIR_COE0 + i * 4, id); } for (i = 0; i < ISP32_RAWAF_GAUS_COE_NUM / 4; i++) { var = ISP_PACK_4BYTE(arg->gaus_coe[i * 4], arg->gaus_coe[i * 4 + 1], arg->gaus_coe[i * 4 + 2], arg->gaus_coe[i * 4 + 3]); - isp3_param_write(params_vdev, var, ISP32_RAWAF_GAUS_COE03 + i * 4); + isp3_param_write(params_vdev, var, ISP32_RAWAF_GAUS_COE03 + i * 4, id); } var = ISP_PACK_4BYTE(arg->gaus_coe[ISP32_RAWAF_GAUS_COE_NUM - 1], 0, 0, 0); - isp3_param_write(params_vdev, var, ISP32_RAWAF_GAUS_COE8); + isp3_param_write(params_vdev, var, ISP32_RAWAF_GAUS_COE8, id); - isp3_param_write(params_vdev, arg->highlit_thresh, ISP3X_RAWAF_HIGHLIT_THRESH); + isp3_param_write(params_vdev, arg->highlit_thresh, ISP3X_RAWAF_HIGHLIT_THRESH, id); if (params_vdev->dev->isp_ver == ISP_V32_L) { var = ISP_PACK_2SHORT(arg->h_fv_limit, arg->h_fv_slope); - isp3_param_write(params_vdev, var, ISP32L_RAWAF_CORING_H); + isp3_param_write(params_vdev, var, ISP32L_RAWAF_CORING_H, id); var = ISP_PACK_2SHORT(arg->v_fv_limit, arg->v_fv_slope); - isp3_param_write(params_vdev, var, ISP32L_RAWAF_CORING_V); + isp3_param_write(params_vdev, var, ISP32L_RAWAF_CORING_V, id); } viir_en = arg->viir_en; @@ -1176,23 +1215,23 @@ isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev, if (viir_en == 0) v1_fir_sel = 0; - ctrl = isp3_param_read(params_vdev, ISP3X_RAWAF_CTRL); + ctrl = isp3_param_read(params_vdev, ISP3X_RAWAF_CTRL, id); ctrl &= ISP3X_RAWAF_EN; if (arg->hiir_en) { ctrl |= ISP3X_RAWAF_HIIR_EN; for (i = 0; i < ISP32_RAWAF_HIIR_COE_NUM / 2; i++) { var = ISP_PACK_2SHORT(arg->h1iir1_coe[i * 2], arg->h1iir1_coe[i * 2 + 1]); - isp3_param_write(params_vdev, var, ISP3X_RAWAF_H1_IIR1_COE01 + i * 4); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_H1_IIR1_COE01 + i * 4, id); var = ISP_PACK_2SHORT(arg->h1iir2_coe[i * 2], arg->h1iir2_coe[i * 2 + 1]); - isp3_param_write(params_vdev, var, ISP3X_RAWAF_H1_IIR2_COE01 + i * 4); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_H1_IIR2_COE01 + i * 4, id); if (params_vdev->dev->isp_ver == ISP_V32_L) continue; var = ISP_PACK_2SHORT(arg->h2iir1_coe[i * 2], arg->h2iir1_coe[i * 2 + 1]); - isp3_param_write(params_vdev, var, ISP3X_RAWAF_H2_IIR1_COE01 + i * 4); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_H2_IIR1_COE01 + i * 4, id); var = ISP_PACK_2SHORT(arg->h2iir2_coe[i * 2], arg->h2iir2_coe[i * 2 + 1]); - isp3_param_write(params_vdev, var, ISP3X_RAWAF_H2_IIR2_COE01 + i * 4); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_H2_IIR2_COE01 + i * 4, id); } } if (viir_en) { @@ -1202,7 +1241,7 @@ isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev, var = ISP_PACK_2SHORT(arg->v1iir_coe[i], arg->v2iir_coe[i]); else var = ISP_PACK_2SHORT(arg->v1iir_coe[i], 0); - isp3_param_write(params_vdev, var, ISP3X_RAWAF_V_IIR_COE0 + i * 4); + isp3_param_write(params_vdev, var, ISP3X_RAWAF_V_IIR_COE0 + i * 4, id); } } if (arg->ldg_en) { @@ -1212,12 +1251,12 @@ isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev, arg->curve_h[i].ldg_lumth | arg->curve_h[i].ldg_gain << 8 | arg->curve_h[i].ldg_gslp << 16, - ISP3X_RAWAF_H_CURVEL + i * 16); + ISP3X_RAWAF_H_CURVEL + i * 16, id); isp3_param_write(params_vdev, arg->curve_v[i].ldg_lumth | arg->curve_v[i].ldg_gain << 8 | arg->curve_v[i].ldg_gslp << 16, - ISP3X_RAWAF_V_CURVEL + i * 16); + ISP3X_RAWAF_V_CURVEL + i * 16, id); } } @@ -1239,9 +1278,9 @@ isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev, !!arg->v1_acc_mode << 26 | !!arg->v2_acc_mode << 27 | !!arg->ae_sel << 29; - isp3_param_write(params_vdev, ctrl, ISP3X_RAWAF_CTRL); + isp3_param_write(params_vdev, ctrl, ISP3X_RAWAF_CTRL, id); - ctrl = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH); + ctrl = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH, id); if (((ctrl & ISP3X_RAWAF_SEL(3)) != ISP3X_RAWAF_SEL(arg->rawaf_sel)) || (((!!(ctrl & ISP32L_BNR2AF_SEL)) != arg->bnr2af_sel) && (params_vdev->dev->isp_ver == ISP_V32_L))) { @@ -1254,16 +1293,16 @@ isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev, else ctrl &= ~ISP32L_BNR2AF_SEL; } - isp3_param_write(params_vdev, ctrl, ISP3X_VI_ISP_PATH); + isp3_param_write(params_vdev, ctrl, ISP3X_VI_ISP_PATH, id); } params_vdev->afaemode_en = arg->ae_mode; if (params_vdev->afaemode_en) - isp_rawae_config_foraf(params_vdev, arg); + isp_rawae_config_foraf(params_vdev, arg, &win_ae, id); } static void -isp_rawae_enable_foraf(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_rawae_enable_foraf(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { u32 exp_ctrl; u32 addr = ISP3X_RAWAE_BIG1_BASE; @@ -1271,20 +1310,20 @@ isp_rawae_enable_foraf(struct rkisp_isp_params_vdev *params_vdev, bool en) if (params_vdev->dev->isp_ver == ISP_V32_L) addr = ISP3X_RAWAE_LITE_BASE; - exp_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL); + exp_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL, id); exp_ctrl &= ~ISP32_REG_WR_MASK; if (en) exp_ctrl |= ISP32_MODULE_EN; else exp_ctrl &= ~ISP32_MODULE_EN; - isp3_param_write(params_vdev, exp_ctrl, addr + ISP3X_RAWAE_BIG_CTRL); + isp3_param_write(params_vdev, exp_ctrl, addr + ISP3X_RAWAE_BIG_CTRL, id); } static void -isp_rawaf_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_rawaf_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { - u32 afm_ctrl = isp3_param_read(params_vdev, ISP3X_RAWAF_CTRL); + u32 afm_ctrl = isp3_param_read(params_vdev, ISP3X_RAWAF_CTRL, id); afm_ctrl &= ~ISP32_REG_WR_MASK; if (en) @@ -1292,9 +1331,9 @@ isp_rawaf_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) else afm_ctrl &= ~ISP3X_RAWAF_EN; - isp3_param_write(params_vdev, afm_ctrl, ISP3X_RAWAF_CTRL); + isp3_param_write(params_vdev, afm_ctrl, ISP3X_RAWAF_CTRL, id); if (params_vdev->afaemode_en) { - isp_rawae_enable_foraf(params_vdev, en); + isp_rawae_enable_foraf(params_vdev, en, id); if (!en) params_vdev->afaemode_en = false; } @@ -1302,78 +1341,78 @@ isp_rawaf_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) static void isp_rawaelite_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_rawaelite_meas_cfg *arg) + const struct isp2x_rawaelite_meas_cfg *arg, u32 id) { struct rkisp_device *ispdev = params_vdev->dev; struct v4l2_rect *out_crop = &ispdev->isp_sdev.out_crop; - u32 width = out_crop->width; + u32 width = out_crop->width, height = out_crop->height; + u32 h_size, v_size, h_offs, v_offs; u32 block_hsize, block_vsize, value; u32 wnd_num_idx = 0; const u32 ae_wnd_num[] = {1, 5}; - value = isp3_param_read(params_vdev, ISP3X_RAWAE_LITE_CTRL); + value = isp3_param_read(params_vdev, ISP3X_RAWAE_LITE_CTRL, id); value &= ~(ISP3X_RAWAE_LITE_WNDNUM); if (arg->wnd_num) { value |= ISP3X_RAWAE_LITE_WNDNUM; wnd_num_idx = 1; } value &= ~ISP32_REG_WR_MASK; - isp3_param_write(params_vdev, value, ISP3X_RAWAE_LITE_CTRL); + isp3_param_write(params_vdev, value, ISP3X_RAWAE_LITE_CTRL, id); + h_offs = arg->win.h_offs & ~0x1; + v_offs = arg->win.v_offs & ~0x1; isp3_param_write(params_vdev, - ISP_PACK_2SHORT(arg->win.h_offs, arg->win.v_offs), - ISP3X_RAWAE_LITE_OFFSET); + ISP_PACK_2SHORT(h_offs, v_offs), + ISP3X_RAWAE_LITE_OFFSET, id); - block_hsize = arg->win.h_size / ae_wnd_num[wnd_num_idx]; - value = block_hsize * ae_wnd_num[wnd_num_idx] + arg->win.h_offs; - if (ispdev->hw_dev->is_unite) + if (ispdev->hw_dev->unite) width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL; - if (value + 1 > width) - block_hsize -= 1; - block_vsize = arg->win.v_size / ae_wnd_num[wnd_num_idx]; - value = block_vsize * ae_wnd_num[wnd_num_idx] + arg->win.v_offs; - if (value + 2 > out_crop->height) - block_vsize -= 1; - if (block_vsize % 2) - block_vsize -= 1; + h_size = arg->win.h_size; + v_size = arg->win.v_size; + if (!h_size || h_size + h_offs + 1 > width) + h_size = width - h_offs - 1; + if (!v_size || v_size + v_offs + 2 > height) + v_size = height - v_offs - 2; + block_hsize = (h_size / ae_wnd_num[wnd_num_idx]) & ~0x1; + block_vsize = (v_size / ae_wnd_num[wnd_num_idx]) & ~0x1; isp3_param_write(params_vdev, ISP_PACK_2SHORT(block_hsize, block_vsize), - ISP3X_RAWAE_LITE_BLK_SIZ); + ISP3X_RAWAE_LITE_BLK_SIZ, id); - value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH); + value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH, id); if ((value & ISP3X_RAWAE012_SEL(3)) != ISP3X_RAWAE012_SEL(arg->rawae_sel)) { value &= ~(ISP3X_RAWAE012_SEL(3)); value |= ISP3X_RAWAE012_SEL(arg->rawae_sel); - isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH); + isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH, id); } } static void -isp_rawaelite_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_rawaelite_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { u32 exp_ctrl; - exp_ctrl = isp3_param_read(params_vdev, ISP3X_RAWAE_LITE_CTRL); + exp_ctrl = isp3_param_read(params_vdev, ISP3X_RAWAE_LITE_CTRL, id); exp_ctrl &= ~ISP32_REG_WR_MASK; if (en) exp_ctrl |= ISP3X_RAWAE_LITE_EN; else exp_ctrl &= ~ISP3X_RAWAE_LITE_EN; - isp3_param_write(params_vdev, exp_ctrl, ISP3X_RAWAE_LITE_CTRL); + isp3_param_write(params_vdev, exp_ctrl, ISP3X_RAWAE_LITE_CTRL, id); } static void isp_rawaebig_config(struct rkisp_isp_params_vdev *params_vdev, const struct isp2x_rawaebig_meas_cfg *arg, - u32 blk_no) + u32 blk_no, u32 id) { struct rkisp_device *ispdev = params_vdev->dev; struct v4l2_rect *out_crop = &ispdev->isp_sdev.out_crop; - u32 width = out_crop->width; - u32 block_hsize, block_vsize; - u32 addr, i, value, h_size, v_size; - u32 wnd_num_idx = 0; + u32 width = out_crop->width, height = out_crop->height; + u32 addr, i, value, h_size, v_size, h_offs, v_offs; + u32 block_hsize, block_vsize, wnd_num_idx = 0; const u32 ae_wnd_num[] = { 1, 5, 15, 15 }; @@ -1392,7 +1431,7 @@ isp_rawaebig_config(struct rkisp_isp_params_vdev *params_vdev, } /* avoid to override the old enable value */ - value = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL); + value = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL, id); value &= ISP3X_RAWAE_BIG_EN; wnd_num_idx = arg->wnd_num; @@ -1408,59 +1447,65 @@ isp_rawaebig_config(struct rkisp_isp_params_vdev *params_vdev, if (arg->subwin_en[3]) value |= ISP3X_RAWAE_BIG_WND4_EN; } - isp3_param_write(params_vdev, value, addr + ISP3X_RAWAE_BIG_CTRL); + isp3_param_write(params_vdev, value, addr + ISP3X_RAWAE_BIG_CTRL, id); + h_offs = arg->win.h_offs & ~0x1; + v_offs = arg->win.v_offs & ~0x1; isp3_param_write(params_vdev, - ISP_PACK_2SHORT(arg->win.h_offs, arg->win.v_offs), - addr + ISP3X_RAWAE_BIG_OFFSET); + ISP_PACK_2SHORT(h_offs, v_offs), + addr + ISP3X_RAWAE_BIG_OFFSET, id); - block_hsize = arg->win.h_size / ae_wnd_num[wnd_num_idx]; - value = block_hsize * ae_wnd_num[wnd_num_idx] + arg->win.h_offs; - if (ispdev->hw_dev->is_unite) + if (ispdev->hw_dev->unite) width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL; - if (value + 1 > width) - block_hsize -= 1; - block_vsize = arg->win.v_size / ae_wnd_num[wnd_num_idx]; - value = block_vsize * ae_wnd_num[wnd_num_idx] + arg->win.v_offs; - if (value + 2 > out_crop->height) - block_vsize -= 1; - if (block_vsize % 2) - block_vsize -= 1; + h_size = arg->win.h_size; + v_size = arg->win.v_size; + if (!h_size || h_size + h_offs + 1 > width) + h_size = width - h_offs - 1; + if (!v_size || v_size + v_offs + 2 > height) + v_size = height - v_offs - 2; + block_hsize = (h_size / ae_wnd_num[wnd_num_idx]) & ~0x1; + block_vsize = (v_size / ae_wnd_num[wnd_num_idx]) & ~0x1; isp3_param_write(params_vdev, ISP_PACK_2SHORT(block_hsize, block_vsize), - addr + ISP3X_RAWAE_BIG_BLK_SIZE); + addr + ISP3X_RAWAE_BIG_BLK_SIZE, id); for (i = 0; i < ISP32_RAWAEBIG_SUBWIN_NUM; i++) { - isp3_param_write(params_vdev, - ISP_PACK_2SHORT(arg->subwin[i].h_offs, arg->subwin[i].v_offs), - addr + ISP3X_RAWAE_BIG_WND1_OFFSET + 8 * i); + h_offs = arg->subwin[i].h_offs & ~0x1; + v_offs = arg->subwin[i].v_offs & ~0x1; + isp3_param_write(params_vdev, ISP_PACK_2SHORT(h_offs, v_offs), + addr + ISP3X_RAWAE_BIG_WND1_OFFSET + 8 * i, id); - v_size = arg->subwin[i].v_size + arg->subwin[i].v_offs; - h_size = arg->subwin[i].h_size + arg->subwin[i].h_offs; - isp3_param_write(params_vdev, - ISP_PACK_2SHORT(h_size, v_size), - addr + ISP3X_RAWAE_BIG_WND1_SIZE + 8 * i); + v_size = arg->subwin[i].v_size; + h_size = arg->subwin[i].h_size; + if (!h_size || h_size + h_offs > width) + h_size = width - h_offs; + if (!v_size || v_size + v_offs > height) + v_size = height - v_offs; + h_size = (h_size + h_offs) & ~0x1; + v_size = (v_size + v_offs) & ~0x1; + isp3_param_write(params_vdev, ISP_PACK_2SHORT(h_size, v_size), + addr + ISP3X_RAWAE_BIG_WND1_SIZE + 8 * i, id); } - value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH); + value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH, id); if (blk_no == 0) { if ((value & ISP3X_RAWAE3_SEL(3)) != ISP3X_RAWAE3_SEL(arg->rawae_sel)) { value &= ~(ISP3X_RAWAE3_SEL(3)); value |= ISP3X_RAWAE3_SEL(arg->rawae_sel); - isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH); + isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH, id); } } else { if ((value & ISP3X_RAWAE012_SEL(3)) != ISP3X_RAWAE012_SEL(arg->rawae_sel)) { value &= ~(ISP3X_RAWAE012_SEL(3)); value |= ISP3X_RAWAE012_SEL(arg->rawae_sel); - isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH); + isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH, id); } } } static void isp_rawaebig_enable(struct rkisp_isp_params_vdev *params_vdev, - bool en, u32 blk_no) + bool en, u32 blk_no, u32 id) { u32 exp_ctrl; u32 addr; @@ -1478,117 +1523,120 @@ isp_rawaebig_enable(struct rkisp_isp_params_vdev *params_vdev, break; } - exp_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL); + exp_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL, id); exp_ctrl &= ~ISP32_REG_WR_MASK; if (en) exp_ctrl |= ISP32_MODULE_EN; else exp_ctrl &= ~ISP32_MODULE_EN; - isp3_param_write(params_vdev, exp_ctrl, addr + ISP3X_RAWAE_BIG_CTRL); + isp3_param_write(params_vdev, exp_ctrl, addr + ISP3X_RAWAE_BIG_CTRL, id); } static void isp_rawae1_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_rawaebig_meas_cfg *arg) + const struct isp2x_rawaebig_meas_cfg *arg, u32 id) { - isp_rawaebig_config(params_vdev, arg, 1); + isp_rawaebig_config(params_vdev, arg, 1, id); } static void -isp_rawae1_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_rawae1_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { - isp_rawaebig_enable(params_vdev, en, 1); + isp_rawaebig_enable(params_vdev, en, 1, id); } static void isp_rawae2_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_rawaebig_meas_cfg *arg) + const struct isp2x_rawaebig_meas_cfg *arg, u32 id) { - isp_rawaebig_config(params_vdev, arg, 2); + isp_rawaebig_config(params_vdev, arg, 2, id); } static void -isp_rawae2_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_rawae2_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { - isp_rawaebig_enable(params_vdev, en, 2); + isp_rawaebig_enable(params_vdev, en, 2, id); } static void isp_rawae3_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_rawaebig_meas_cfg *arg) + const struct isp2x_rawaebig_meas_cfg *arg, u32 id) { - isp_rawaebig_config(params_vdev, arg, 0); + isp_rawaebig_config(params_vdev, arg, 0, id); } static void -isp_rawae3_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_rawae3_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { - isp_rawaebig_enable(params_vdev, en, 0); + isp_rawaebig_enable(params_vdev, en, 0, id); } static void isp_rawawb_cfg_sram(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_rawawb_meas_cfg *arg, bool is_check) + const struct isp32_rawawb_meas_cfg *arg, bool is_check, u32 id) { u32 i, val = ISP32_MODULE_EN; if (params_vdev->dev->isp_ver == ISP_V32 && is_check && - !(isp3_param_read(params_vdev, ISP3X_RAWAWB_CTRL) & val)) + !(isp3_param_read(params_vdev, ISP3X_RAWAWB_CTRL, id) & val)) return; for (i = 0; i < ISP32_RAWAWB_WEIGHT_NUM / 5; i++) { - isp3_param_write(params_vdev, - (arg->wp_blk_wei_w[5 * i] & 0x3f) | - (arg->wp_blk_wei_w[5 * i + 1] & 0x3f) << 6 | - (arg->wp_blk_wei_w[5 * i + 2] & 0x3f) << 12 | - (arg->wp_blk_wei_w[5 * i + 3] & 0x3f) << 18 | - (arg->wp_blk_wei_w[5 * i + 4] & 0x3f) << 24, - ISP3X_RAWAWB_WRAM_DATA_BASE); + isp3_param_write_direct(params_vdev, + (arg->wp_blk_wei_w[5 * i] & 0x3f) | + (arg->wp_blk_wei_w[5 * i + 1] & 0x3f) << 6 | + (arg->wp_blk_wei_w[5 * i + 2] & 0x3f) << 12 | + (arg->wp_blk_wei_w[5 * i + 3] & 0x3f) << 18 | + (arg->wp_blk_wei_w[5 * i + 4] & 0x3f) << 24, + ISP3X_RAWAWB_WRAM_DATA_BASE); } } static void isp_rawawb_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_rawawb_meas_cfg *arg) + const struct isp32_rawawb_meas_cfg *arg, u32 id) { - struct isp32_isp_params_cfg *params_rec = params_vdev->isp32_params; + struct rkisp_device *dev = params_vdev->dev; + struct v4l2_rect *out_crop = &dev->isp_sdev.out_crop; + struct isp32_isp_params_cfg *params_rec = params_vdev->isp32_params + id; struct isp32_rawawb_meas_cfg *arg_rec = ¶ms_rec->meas.rawawb; const struct isp2x_bls_fixed_val *pval = &arg->bls2_val; - u32 value, val, mask, i; + u32 width = out_crop->width, height = out_crop->height; + u32 value, val, mask, i, h_size, v_size, h_offs, v_offs; - value = isp3_param_read(params_vdev, ISP3X_BLS_CTRL); + value = isp3_param_read(params_vdev, ISP3X_BLS_CTRL, id); value &= ~ISP32_BLS_BLS2_EN; if (arg->bls2_en) { switch (params_vdev->raw_type) { case RAW_BGGR: - isp3_param_write(params_vdev, pval->r, ISP32_BLS2_D_FIXED); - isp3_param_write(params_vdev, pval->gr, ISP32_BLS2_C_FIXED); - isp3_param_write(params_vdev, pval->gb, ISP32_BLS2_B_FIXED); - isp3_param_write(params_vdev, pval->b, ISP32_BLS2_A_FIXED); + isp3_param_write(params_vdev, pval->r, ISP32_BLS2_D_FIXED, id); + isp3_param_write(params_vdev, pval->gr, ISP32_BLS2_C_FIXED, id); + isp3_param_write(params_vdev, pval->gb, ISP32_BLS2_B_FIXED, id); + isp3_param_write(params_vdev, pval->b, ISP32_BLS2_A_FIXED, id); break; case RAW_GBRG: - isp3_param_write(params_vdev, pval->r, ISP32_BLS2_C_FIXED); - isp3_param_write(params_vdev, pval->gr, ISP32_BLS2_D_FIXED); - isp3_param_write(params_vdev, pval->gb, ISP32_BLS2_A_FIXED); - isp3_param_write(params_vdev, pval->b, ISP32_BLS2_B_FIXED); + isp3_param_write(params_vdev, pval->r, ISP32_BLS2_C_FIXED, id); + isp3_param_write(params_vdev, pval->gr, ISP32_BLS2_D_FIXED, id); + isp3_param_write(params_vdev, pval->gb, ISP32_BLS2_A_FIXED, id); + isp3_param_write(params_vdev, pval->b, ISP32_BLS2_B_FIXED, id); break; case RAW_GRBG: - isp3_param_write(params_vdev, pval->r, ISP32_BLS2_B_FIXED); - isp3_param_write(params_vdev, pval->gr, ISP32_BLS2_A_FIXED); - isp3_param_write(params_vdev, pval->gb, ISP32_BLS2_D_FIXED); - isp3_param_write(params_vdev, pval->b, ISP32_BLS2_C_FIXED); + isp3_param_write(params_vdev, pval->r, ISP32_BLS2_B_FIXED, id); + isp3_param_write(params_vdev, pval->gr, ISP32_BLS2_A_FIXED, id); + isp3_param_write(params_vdev, pval->gb, ISP32_BLS2_D_FIXED, id); + isp3_param_write(params_vdev, pval->b, ISP32_BLS2_C_FIXED, id); break; case RAW_RGGB: default: - isp3_param_write(params_vdev, pval->r, ISP32_BLS2_A_FIXED); - isp3_param_write(params_vdev, pval->gr, ISP32_BLS2_B_FIXED); - isp3_param_write(params_vdev, pval->gb, ISP32_BLS2_C_FIXED); - isp3_param_write(params_vdev, pval->b, ISP32_BLS2_D_FIXED); + isp3_param_write(params_vdev, pval->r, ISP32_BLS2_A_FIXED, id); + isp3_param_write(params_vdev, pval->gr, ISP32_BLS2_B_FIXED, id); + isp3_param_write(params_vdev, pval->gb, ISP32_BLS2_C_FIXED, id); + isp3_param_write(params_vdev, pval->b, ISP32_BLS2_D_FIXED, id); } value |= ISP32_BLS_BLS2_EN; } - isp3_param_write(params_vdev, value, ISP3X_BLS_CTRL); + isp3_param_write(params_vdev, value, ISP3X_BLS_CTRL, id); value = arg->in_overexposure_threshold << 16 | !!arg->blk_with_luma_wei_en << 8 | @@ -1599,463 +1647,473 @@ isp_rawawb_config(struct rkisp_isp_params_vdev *params_vdev, !!arg->blk_measure_enable; if (params_vdev->dev->isp_ver == ISP_V32_L) value |= !!arg->ds16x8_mode_en << 7; - isp3_param_write(params_vdev, value, ISP3X_RAWAWB_BLK_CTRL); + isp3_param_write(params_vdev, value, ISP3X_RAWAWB_BLK_CTRL, id); - isp3_param_write(params_vdev, - ISP_PACK_2SHORT(arg->h_offs, arg->v_offs), - ISP3X_RAWAWB_WIN_OFFS); + h_offs = arg->h_offs & ~0x1; + v_offs = arg->v_offs & ~0x1; isp3_param_write(params_vdev, - ISP_PACK_2SHORT(arg->h_size, arg->v_size), - ISP3X_RAWAWB_WIN_SIZE); + ISP_PACK_2SHORT(h_offs, v_offs), + ISP3X_RAWAWB_WIN_OFFS, id); + + if (dev->hw_dev->unite) + width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL; + h_size = arg->h_size; + v_size = arg->v_size; + if (!h_size || h_size + h_offs > width) + h_size = width - h_offs; + if (!v_size || v_size + v_offs > height) + v_size = height - v_offs; + isp3_param_write(params_vdev, + ISP_PACK_2SHORT(h_size, v_size), + ISP3X_RAWAWB_WIN_SIZE, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->r_max, arg->g_max), - ISP3X_RAWAWB_LIMIT_RG_MAX); + ISP3X_RAWAWB_LIMIT_RG_MAX, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->b_max, arg->y_max), - ISP3X_RAWAWB_LIMIT_BY_MAX); + ISP3X_RAWAWB_LIMIT_BY_MAX, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->r_min, arg->g_min), - ISP3X_RAWAWB_LIMIT_RG_MIN); + ISP3X_RAWAWB_LIMIT_RG_MIN, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->b_min, arg->y_min), - ISP3X_RAWAWB_LIMIT_BY_MIN); + ISP3X_RAWAWB_LIMIT_BY_MIN, id); value = !!arg->wp_hist_xytype << 4 | !!arg->wp_blk_wei_en1 << 3 | !!arg->wp_blk_wei_en0 << 2 | !!arg->wp_luma_wei_en1 << 1 | !!arg->wp_luma_wei_en0; - isp3_param_write(params_vdev, value, ISP3X_RAWAWB_WEIGHT_CURVE_CTRL); + isp3_param_write(params_vdev, value, ISP3X_RAWAWB_WEIGHT_CURVE_CTRL, id); isp3_param_write(params_vdev, ISP_PACK_4BYTE(arg->wp_luma_weicurve_y0, arg->wp_luma_weicurve_y1, arg->wp_luma_weicurve_y2, arg->wp_luma_weicurve_y3), - ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR03); + ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR03, id); isp3_param_write(params_vdev, ISP_PACK_4BYTE(arg->wp_luma_weicurve_y4, arg->wp_luma_weicurve_y5, arg->wp_luma_weicurve_y6, arg->wp_luma_weicurve_y7), - ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR47); + ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR47, id); isp3_param_write(params_vdev, arg->wp_luma_weicurve_y8, - ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR8); + ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR8, id); isp3_param_write(params_vdev, ISP_PACK_4BYTE(arg->wp_luma_weicurve_w0, arg->wp_luma_weicurve_w1, arg->wp_luma_weicurve_w2, arg->wp_luma_weicurve_w3), - ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR03); + ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR03, id); isp3_param_write(params_vdev, ISP_PACK_4BYTE(arg->wp_luma_weicurve_w4, arg->wp_luma_weicurve_w5, arg->wp_luma_weicurve_w6, arg->wp_luma_weicurve_w7), - ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR47); + ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR47, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->wp_luma_weicurve_w8, arg->pre_wbgain_inv_r), - ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR8); + ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR8, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->pre_wbgain_inv_g, arg->pre_wbgain_inv_b), - ISP3X_RAWAWB_PRE_WBGAIN_INV); + ISP3X_RAWAWB_PRE_WBGAIN_INV, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->vertex0_u_0, arg->vertex0_v_0), - ISP3X_RAWAWB_UV_DETC_VERTEX0_0); + ISP3X_RAWAWB_UV_DETC_VERTEX0_0, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->vertex1_u_0, arg->vertex1_v_0), - ISP3X_RAWAWB_UV_DETC_VERTEX1_0); + ISP3X_RAWAWB_UV_DETC_VERTEX1_0, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->vertex2_u_0, arg->vertex2_v_0), - ISP3X_RAWAWB_UV_DETC_VERTEX2_0); + ISP3X_RAWAWB_UV_DETC_VERTEX2_0, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->vertex3_u_0, arg->vertex3_v_0), - ISP3X_RAWAWB_UV_DETC_VERTEX3_0); + ISP3X_RAWAWB_UV_DETC_VERTEX3_0, id); isp3_param_write(params_vdev, arg->islope01_0, - ISP3X_RAWAWB_UV_DETC_ISLOPE01_0); + ISP3X_RAWAWB_UV_DETC_ISLOPE01_0, id); isp3_param_write(params_vdev, arg->islope12_0, - ISP3X_RAWAWB_UV_DETC_ISLOPE12_0); + ISP3X_RAWAWB_UV_DETC_ISLOPE12_0, id); isp3_param_write(params_vdev, arg->islope23_0, - ISP3X_RAWAWB_UV_DETC_ISLOPE23_0); + ISP3X_RAWAWB_UV_DETC_ISLOPE23_0, id); isp3_param_write(params_vdev, arg->islope30_0, - ISP3X_RAWAWB_UV_DETC_ISLOPE30_0); + ISP3X_RAWAWB_UV_DETC_ISLOPE30_0, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->vertex0_u_1, arg->vertex0_v_1), - ISP3X_RAWAWB_UV_DETC_VERTEX0_1); + ISP3X_RAWAWB_UV_DETC_VERTEX0_1, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->vertex1_u_1, arg->vertex1_v_1), - ISP3X_RAWAWB_UV_DETC_VERTEX1_1); + ISP3X_RAWAWB_UV_DETC_VERTEX1_1, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->vertex2_u_1, arg->vertex2_v_1), - ISP3X_RAWAWB_UV_DETC_VERTEX2_1); + ISP3X_RAWAWB_UV_DETC_VERTEX2_1, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->vertex3_u_1, arg->vertex3_v_1), - ISP3X_RAWAWB_UV_DETC_VERTEX3_1); + ISP3X_RAWAWB_UV_DETC_VERTEX3_1, id); isp3_param_write(params_vdev, arg->islope01_1, - ISP3X_RAWAWB_UV_DETC_ISLOPE01_1); + ISP3X_RAWAWB_UV_DETC_ISLOPE01_1, id); isp3_param_write(params_vdev, arg->islope12_1, - ISP3X_RAWAWB_UV_DETC_ISLOPE12_1); + ISP3X_RAWAWB_UV_DETC_ISLOPE12_1, id); isp3_param_write(params_vdev, arg->islope23_1, - ISP3X_RAWAWB_UV_DETC_ISLOPE23_1); + ISP3X_RAWAWB_UV_DETC_ISLOPE23_1, id); isp3_param_write(params_vdev, arg->islope30_1, - ISP3X_RAWAWB_UV_DETC_ISLOPE30_1); + ISP3X_RAWAWB_UV_DETC_ISLOPE30_1, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->vertex0_u_2, arg->vertex0_v_2), - ISP3X_RAWAWB_UV_DETC_VERTEX0_2); + ISP3X_RAWAWB_UV_DETC_VERTEX0_2, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->vertex1_u_2, arg->vertex1_v_2), - ISP3X_RAWAWB_UV_DETC_VERTEX1_2); + ISP3X_RAWAWB_UV_DETC_VERTEX1_2, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->vertex2_u_2, arg->vertex2_v_2), - ISP3X_RAWAWB_UV_DETC_VERTEX2_2); + ISP3X_RAWAWB_UV_DETC_VERTEX2_2, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->vertex3_u_2, arg->vertex3_v_2), - ISP3X_RAWAWB_UV_DETC_VERTEX3_2); + ISP3X_RAWAWB_UV_DETC_VERTEX3_2, id); isp3_param_write(params_vdev, arg->islope01_2, - ISP3X_RAWAWB_UV_DETC_ISLOPE01_2); + ISP3X_RAWAWB_UV_DETC_ISLOPE01_2, id); isp3_param_write(params_vdev, arg->islope12_2, - ISP3X_RAWAWB_UV_DETC_ISLOPE12_2); + ISP3X_RAWAWB_UV_DETC_ISLOPE12_2, id); isp3_param_write(params_vdev, arg->islope23_2, - ISP3X_RAWAWB_UV_DETC_ISLOPE23_2); + ISP3X_RAWAWB_UV_DETC_ISLOPE23_2, id); isp3_param_write(params_vdev, arg->islope30_2, - ISP3X_RAWAWB_UV_DETC_ISLOPE30_2); + ISP3X_RAWAWB_UV_DETC_ISLOPE30_2, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->vertex0_u_3, arg->vertex0_v_3), - ISP3X_RAWAWB_UV_DETC_VERTEX0_3); + ISP3X_RAWAWB_UV_DETC_VERTEX0_3, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->vertex1_u_3, arg->vertex1_v_3), - ISP3X_RAWAWB_UV_DETC_VERTEX1_3); + ISP3X_RAWAWB_UV_DETC_VERTEX1_3, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->vertex2_u_3, arg->vertex2_v_3), - ISP3X_RAWAWB_UV_DETC_VERTEX2_3); + ISP3X_RAWAWB_UV_DETC_VERTEX2_3, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->vertex3_u_3, arg->vertex3_v_3), - ISP3X_RAWAWB_UV_DETC_VERTEX3_3); + ISP3X_RAWAWB_UV_DETC_VERTEX3_3, id); isp3_param_write(params_vdev, arg->islope01_3, - ISP3X_RAWAWB_UV_DETC_ISLOPE01_3); + ISP3X_RAWAWB_UV_DETC_ISLOPE01_3, id); isp3_param_write(params_vdev, arg->islope12_3, - ISP3X_RAWAWB_UV_DETC_ISLOPE12_3); + ISP3X_RAWAWB_UV_DETC_ISLOPE12_3, id); isp3_param_write(params_vdev, arg->islope23_3, - ISP3X_RAWAWB_UV_DETC_ISLOPE23_3); + ISP3X_RAWAWB_UV_DETC_ISLOPE23_3, id); isp3_param_write(params_vdev, arg->islope30_3, - ISP3X_RAWAWB_UV_DETC_ISLOPE30_3); + ISP3X_RAWAWB_UV_DETC_ISLOPE30_3, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->rgb2ryuvmat0_y, arg->rgb2ryuvmat1_y), - ISP3X_RAWAWB_YUV_RGB2ROTY_0); + ISP3X_RAWAWB_YUV_RGB2ROTY_0, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->rgb2ryuvmat2_y, arg->rgb2ryuvofs_y), - ISP3X_RAWAWB_YUV_RGB2ROTY_1); + ISP3X_RAWAWB_YUV_RGB2ROTY_1, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->rgb2ryuvmat0_u, arg->rgb2ryuvmat1_u), - ISP3X_RAWAWB_YUV_RGB2ROTU_0); + ISP3X_RAWAWB_YUV_RGB2ROTU_0, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->rgb2ryuvmat2_u, arg->rgb2ryuvofs_u), - ISP3X_RAWAWB_YUV_RGB2ROTU_1); + ISP3X_RAWAWB_YUV_RGB2ROTU_1, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->rgb2ryuvmat0_v, arg->rgb2ryuvmat1_v), - ISP3X_RAWAWB_YUV_RGB2ROTV_0); + ISP3X_RAWAWB_YUV_RGB2ROTV_0, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->rgb2ryuvmat2_v, arg->rgb2ryuvofs_v), - ISP3X_RAWAWB_YUV_RGB2ROTV_1); + ISP3X_RAWAWB_YUV_RGB2ROTV_1, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->coor_x1_ls0_y, arg->vec_x21_ls0_y), - ISP3X_RAWAWB_YUV_X_COOR_Y_0); + ISP3X_RAWAWB_YUV_X_COOR_Y_0, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->coor_x1_ls0_u, arg->vec_x21_ls0_u), - ISP3X_RAWAWB_YUV_X_COOR_U_0); + ISP3X_RAWAWB_YUV_X_COOR_U_0, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->coor_x1_ls0_v, arg->vec_x21_ls0_v), - ISP3X_RAWAWB_YUV_X_COOR_V_0); + ISP3X_RAWAWB_YUV_X_COOR_V_0, id); isp3_param_write(params_vdev, ISP_PACK_4BYTE(arg->dis_x1x2_ls0, 0, arg->rotu0_ls0, arg->rotu1_ls0), - ISP3X_RAWAWB_YUV_X1X2_DIS_0); + ISP3X_RAWAWB_YUV_X1X2_DIS_0, id); isp3_param_write(params_vdev, ISP_PACK_4BYTE(arg->rotu2_ls0, arg->rotu3_ls0, arg->rotu4_ls0, arg->rotu5_ls0), - ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_0); + ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_0, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->th0_ls0, arg->th1_ls0), - ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_0); + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_0, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->th2_ls0, arg->th3_ls0), - ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_0); + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_0, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->th4_ls0, arg->th5_ls0), - ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_0); + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_0, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->coor_x1_ls1_y, arg->vec_x21_ls1_y), - ISP3X_RAWAWB_YUV_X_COOR_Y_1); + ISP3X_RAWAWB_YUV_X_COOR_Y_1, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->coor_x1_ls1_u, arg->vec_x21_ls1_u), - ISP3X_RAWAWB_YUV_X_COOR_U_1); + ISP3X_RAWAWB_YUV_X_COOR_U_1, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->coor_x1_ls1_v, arg->vec_x21_ls1_v), - ISP3X_RAWAWB_YUV_X_COOR_V_1); + ISP3X_RAWAWB_YUV_X_COOR_V_1, id); isp3_param_write(params_vdev, ISP_PACK_4BYTE(arg->dis_x1x2_ls1, 0, arg->rotu0_ls1, arg->rotu1_ls1), - ISP3X_RAWAWB_YUV_X1X2_DIS_1); + ISP3X_RAWAWB_YUV_X1X2_DIS_1, id); isp3_param_write(params_vdev, ISP_PACK_4BYTE(arg->rotu2_ls1, arg->rotu3_ls1, arg->rotu4_ls1, arg->rotu5_ls1), - ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_1); + ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_1, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->th0_ls1, arg->th1_ls1), - ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_1); + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_1, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->th2_ls1, arg->th3_ls1), - ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_1); + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_1, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->th4_ls1, arg->th5_ls1), - ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_1); + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_1, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->coor_x1_ls2_y, arg->vec_x21_ls2_y), - ISP3X_RAWAWB_YUV_X_COOR_Y_2); + ISP3X_RAWAWB_YUV_X_COOR_Y_2, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->coor_x1_ls2_u, arg->vec_x21_ls2_u), - ISP3X_RAWAWB_YUV_X_COOR_U_2); + ISP3X_RAWAWB_YUV_X_COOR_U_2, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->coor_x1_ls2_v, arg->vec_x21_ls2_v), - ISP3X_RAWAWB_YUV_X_COOR_V_2); + ISP3X_RAWAWB_YUV_X_COOR_V_2, id); isp3_param_write(params_vdev, ISP_PACK_4BYTE(arg->dis_x1x2_ls2, 0, arg->rotu0_ls2, arg->rotu1_ls2), - ISP3X_RAWAWB_YUV_X1X2_DIS_2); + ISP3X_RAWAWB_YUV_X1X2_DIS_2, id); isp3_param_write(params_vdev, ISP_PACK_4BYTE(arg->rotu2_ls2, arg->rotu3_ls2, arg->rotu4_ls2, arg->rotu5_ls2), - ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_2); + ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_2, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->th0_ls2, arg->th1_ls2), - ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_2); + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_2, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->th2_ls2, arg->th3_ls2), - ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_2); + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_2, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->th4_ls2, arg->th5_ls2), - ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_2); + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_2, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->coor_x1_ls3_y, arg->vec_x21_ls3_y), - ISP3X_RAWAWB_YUV_X_COOR_Y_3); + ISP3X_RAWAWB_YUV_X_COOR_Y_3, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->coor_x1_ls3_u, arg->vec_x21_ls3_u), - ISP3X_RAWAWB_YUV_X_COOR_U_3); + ISP3X_RAWAWB_YUV_X_COOR_U_3, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->coor_x1_ls3_v, arg->vec_x21_ls3_v), - ISP3X_RAWAWB_YUV_X_COOR_V_3); + ISP3X_RAWAWB_YUV_X_COOR_V_3, id); isp3_param_write(params_vdev, ISP_PACK_4BYTE(arg->dis_x1x2_ls3, 0, arg->rotu0_ls3, arg->rotu1_ls3), - ISP3X_RAWAWB_YUV_X1X2_DIS_3); + ISP3X_RAWAWB_YUV_X1X2_DIS_3, id); isp3_param_write(params_vdev, ISP_PACK_4BYTE(arg->rotu2_ls3, arg->rotu3_ls3, arg->rotu4_ls3, arg->rotu5_ls3), - ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_3); + ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_3, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->th0_ls3, arg->th1_ls3), - ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_3); + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_3, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->th2_ls3, arg->th3_ls3), - ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_3); + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_3, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->th4_ls3, arg->th5_ls3), - ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_3); + ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_3, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->wt0, arg->wt1), - ISP3X_RAWAWB_RGB2XY_WT01); + ISP3X_RAWAWB_RGB2XY_WT01, id); - isp3_param_write(params_vdev, arg->wt2, - ISP3X_RAWAWB_RGB2XY_WT2); + isp3_param_write(params_vdev, arg->wt2, ISP3X_RAWAWB_RGB2XY_WT2, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->mat0_x, arg->mat0_y), - ISP3X_RAWAWB_RGB2XY_MAT0_XY); + ISP3X_RAWAWB_RGB2XY_MAT0_XY, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->mat1_x, arg->mat1_y), - ISP3X_RAWAWB_RGB2XY_MAT1_XY); + ISP3X_RAWAWB_RGB2XY_MAT1_XY, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->mat2_x, arg->mat2_y), - ISP3X_RAWAWB_RGB2XY_MAT2_XY); + ISP3X_RAWAWB_RGB2XY_MAT2_XY, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->nor_x0_0, arg->nor_x1_0), - ISP3X_RAWAWB_XY_DETC_NOR_X_0); + ISP3X_RAWAWB_XY_DETC_NOR_X_0, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->nor_y0_0, arg->nor_y1_0), - ISP3X_RAWAWB_XY_DETC_NOR_Y_0); + ISP3X_RAWAWB_XY_DETC_NOR_Y_0, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->big_x0_0, arg->big_x1_0), - ISP3X_RAWAWB_XY_DETC_BIG_X_0); + ISP3X_RAWAWB_XY_DETC_BIG_X_0, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->big_y0_0, arg->big_y1_0), - ISP3X_RAWAWB_XY_DETC_BIG_Y_0); + ISP3X_RAWAWB_XY_DETC_BIG_Y_0, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->nor_x0_1, arg->nor_x1_1), - ISP3X_RAWAWB_XY_DETC_NOR_X_1); + ISP3X_RAWAWB_XY_DETC_NOR_X_1, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->nor_y0_1, arg->nor_y1_1), - ISP3X_RAWAWB_XY_DETC_NOR_Y_1); + ISP3X_RAWAWB_XY_DETC_NOR_Y_1, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->big_x0_1, arg->big_x1_1), - ISP3X_RAWAWB_XY_DETC_BIG_X_1); + ISP3X_RAWAWB_XY_DETC_BIG_X_1, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->big_y0_1, arg->big_y1_1), - ISP3X_RAWAWB_XY_DETC_BIG_Y_1); + ISP3X_RAWAWB_XY_DETC_BIG_Y_1, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->nor_x0_2, arg->nor_x1_2), - ISP3X_RAWAWB_XY_DETC_NOR_X_2); + ISP3X_RAWAWB_XY_DETC_NOR_X_2, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->nor_y0_2, arg->nor_y1_2), - ISP3X_RAWAWB_XY_DETC_NOR_Y_2); + ISP3X_RAWAWB_XY_DETC_NOR_Y_2, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->big_x0_2, arg->big_x1_2), - ISP3X_RAWAWB_XY_DETC_BIG_X_2); + ISP3X_RAWAWB_XY_DETC_BIG_X_2, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->big_y0_2, arg->big_y1_2), - ISP3X_RAWAWB_XY_DETC_BIG_Y_2); + ISP3X_RAWAWB_XY_DETC_BIG_Y_2, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->nor_x0_3, arg->nor_x1_3), - ISP3X_RAWAWB_XY_DETC_NOR_X_3); + ISP3X_RAWAWB_XY_DETC_NOR_X_3, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->nor_y0_3, arg->nor_y1_3), - ISP3X_RAWAWB_XY_DETC_NOR_Y_3); + ISP3X_RAWAWB_XY_DETC_NOR_Y_3, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->big_x0_3, arg->big_x1_3), - ISP3X_RAWAWB_XY_DETC_BIG_X_3); + ISP3X_RAWAWB_XY_DETC_BIG_X_3, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->big_y0_3, arg->big_y1_3), - ISP3X_RAWAWB_XY_DETC_BIG_Y_3); + ISP3X_RAWAWB_XY_DETC_BIG_Y_3, id); value = (arg->exc_wp_region0_excen & 0x3) | !!arg->exc_wp_region0_measen << 2 | @@ -2076,138 +2134,138 @@ isp_rawawb_config(struct rkisp_isp_params_vdev *params_vdev, (arg->exc_wp_region6_excen & 0x3) << 24 | !!arg->exc_wp_region6_domain << 27 | !!arg->multiwindow_en << 31; - isp3_param_write(params_vdev, value, ISP3X_RAWAWB_MULTIWINDOW_EXC_CTRL); + isp3_param_write(params_vdev, value, ISP3X_RAWAWB_MULTIWINDOW_EXC_CTRL, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->multiwindow0_h_offs, arg->multiwindow0_v_offs), - ISP3X_RAWAWB_MULTIWINDOW0_OFFS); + ISP3X_RAWAWB_MULTIWINDOW0_OFFS, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->multiwindow0_h_size, arg->multiwindow0_v_size), - ISP3X_RAWAWB_MULTIWINDOW0_SIZE); + ISP3X_RAWAWB_MULTIWINDOW0_SIZE, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->multiwindow1_h_offs, arg->multiwindow1_v_offs), - ISP3X_RAWAWB_MULTIWINDOW1_OFFS); + ISP3X_RAWAWB_MULTIWINDOW1_OFFS, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->multiwindow1_h_size, arg->multiwindow1_v_size), - ISP3X_RAWAWB_MULTIWINDOW1_SIZE); + ISP3X_RAWAWB_MULTIWINDOW1_SIZE, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->multiwindow2_h_offs, arg->multiwindow2_v_offs), - ISP3X_RAWAWB_MULTIWINDOW2_OFFS); + ISP3X_RAWAWB_MULTIWINDOW2_OFFS, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->multiwindow2_h_size, arg->multiwindow2_v_size), - ISP3X_RAWAWB_MULTIWINDOW2_SIZE); + ISP3X_RAWAWB_MULTIWINDOW2_SIZE, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->multiwindow3_h_offs, arg->multiwindow3_v_offs), - ISP3X_RAWAWB_MULTIWINDOW3_OFFS); + ISP3X_RAWAWB_MULTIWINDOW3_OFFS, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->multiwindow3_h_size, arg->multiwindow3_v_size), - ISP3X_RAWAWB_MULTIWINDOW3_SIZE); + ISP3X_RAWAWB_MULTIWINDOW3_SIZE, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->exc_wp_region0_xu0, arg->exc_wp_region0_xu1), - ISP3X_RAWAWB_EXC_WP_REGION0_XU); + ISP3X_RAWAWB_EXC_WP_REGION0_XU, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->exc_wp_region0_yv0, arg->exc_wp_region0_yv1), - ISP3X_RAWAWB_EXC_WP_REGION0_YV); + ISP3X_RAWAWB_EXC_WP_REGION0_YV, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->exc_wp_region1_xu0, arg->exc_wp_region1_xu1), - ISP3X_RAWAWB_EXC_WP_REGION1_XU); + ISP3X_RAWAWB_EXC_WP_REGION1_XU, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->exc_wp_region1_yv0, arg->exc_wp_region1_yv1), - ISP3X_RAWAWB_EXC_WP_REGION1_YV); + ISP3X_RAWAWB_EXC_WP_REGION1_YV, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->exc_wp_region2_xu0, arg->exc_wp_region2_xu1), - ISP3X_RAWAWB_EXC_WP_REGION2_XU); + ISP3X_RAWAWB_EXC_WP_REGION2_XU, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->exc_wp_region2_yv0, arg->exc_wp_region2_yv1), - ISP3X_RAWAWB_EXC_WP_REGION2_YV); + ISP3X_RAWAWB_EXC_WP_REGION2_YV, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->exc_wp_region3_xu0, arg->exc_wp_region3_xu1), - ISP3X_RAWAWB_EXC_WP_REGION3_XU); + ISP3X_RAWAWB_EXC_WP_REGION3_XU, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->exc_wp_region3_yv0, arg->exc_wp_region3_yv1), - ISP3X_RAWAWB_EXC_WP_REGION3_YV); + ISP3X_RAWAWB_EXC_WP_REGION3_YV, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->exc_wp_region4_xu0, arg->exc_wp_region4_xu1), - ISP3X_RAWAWB_EXC_WP_REGION4_XU); + ISP3X_RAWAWB_EXC_WP_REGION4_XU, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->exc_wp_region4_yv0, arg->exc_wp_region4_yv1), - ISP3X_RAWAWB_EXC_WP_REGION4_YV); + ISP3X_RAWAWB_EXC_WP_REGION4_YV, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->exc_wp_region5_xu0, arg->exc_wp_region5_xu1), - ISP3X_RAWAWB_EXC_WP_REGION5_XU); + ISP3X_RAWAWB_EXC_WP_REGION5_XU, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->exc_wp_region5_yv0, arg->exc_wp_region5_yv1), - ISP3X_RAWAWB_EXC_WP_REGION5_YV); + ISP3X_RAWAWB_EXC_WP_REGION5_YV, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->exc_wp_region6_xu0, arg->exc_wp_region6_xu1), - ISP3X_RAWAWB_EXC_WP_REGION6_XU); + ISP3X_RAWAWB_EXC_WP_REGION6_XU, id); isp3_param_write(params_vdev, ISP_PACK_2SHORT(arg->exc_wp_region6_yv0, arg->exc_wp_region6_yv1), - ISP3X_RAWAWB_EXC_WP_REGION6_YV); + ISP3X_RAWAWB_EXC_WP_REGION6_YV, id); isp3_param_write(params_vdev, ISP_PACK_4BYTE(arg->exc_wp_region0_weight, arg->exc_wp_region1_weight, arg->exc_wp_region2_weight, arg->exc_wp_region3_weight), - ISP32_RAWAWB_EXC_WP_WEIGHT0_3); + ISP32_RAWAWB_EXC_WP_WEIGHT0_3, id); isp3_param_write(params_vdev, ISP_PACK_4BYTE(arg->exc_wp_region4_weight, arg->exc_wp_region5_weight, arg->exc_wp_region6_weight, 0), - ISP32_RAWAWB_EXC_WP_WEIGHT4_6); + ISP32_RAWAWB_EXC_WP_WEIGHT4_6, id); if (params_vdev->dev->isp_ver == ISP_V32) { if (params_vdev->dev->hw_dev->is_single) - isp_rawawb_cfg_sram(params_vdev, arg, false); + isp_rawawb_cfg_sram(params_vdev, arg, false, id); else memcpy(arg_rec->wp_blk_wei_w, arg->wp_blk_wei_w, ISP32_RAWAWB_WEIGHT_NUM); } else { for (i = 0; i < ISP32L_RAWAWB_WEIGHT_NUM; i++) isp3_param_write(params_vdev, arg->win_weight[i], - ISP32L_RAWAWB_WIN_WEIGHT_0 + i * 4); + ISP32L_RAWAWB_WIN_WEIGHT_0 + i * 4, id); } /* avoid to override the old enable value */ - value = isp3_param_read_cache(params_vdev, ISP3X_RAWAWB_CTRL); + value = isp3_param_read_cache(params_vdev, ISP3X_RAWAWB_CTRL, id); value &= (ISP32_MODULE_EN | ISP32_RAWAWB_2DDR_PATH_EN | ISP32_RAWAWB_2DDR_PATH_DS); @@ -2227,45 +2285,46 @@ isp_rawawb_config(struct rkisp_isp_params_vdev *params_vdev, !!arg->yuv3d_en0 << 3 | !!arg->xy_en0 << 2 | !!arg->uv_en0 << 1; - isp3_param_write(params_vdev, value, ISP3X_RAWAWB_CTRL); + isp3_param_write(params_vdev, value, ISP3X_RAWAWB_CTRL, id); mask = ISP32_DRC2AWB_SEL | ISP32_BNR2AWB_SEL | ISP3X_RAWAWB_SEL(3); val = ISP3X_RAWAWB_SEL(arg->rawawb_sel) | (arg->bnr2awb_sel & 0x1) << 26 | (arg->drc2awb_sel & 0x1) << 27; - value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH); + value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH, id); if ((value & mask) != val) { value &= ~mask; value |= val; - isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH); + isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH, id); } } static void -isp_rawawb_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_rawawb_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { u32 awb_ctrl; - awb_ctrl = isp3_param_read_cache(params_vdev, ISP3X_RAWAWB_CTRL); + awb_ctrl = isp3_param_read_cache(params_vdev, ISP3X_RAWAWB_CTRL, id); awb_ctrl &= ~ISP32_REG_WR_MASK; if (en) awb_ctrl |= ISP32_MODULE_EN; else awb_ctrl &= ~ISP32_MODULE_EN; - isp3_param_write(params_vdev, awb_ctrl, ISP3X_RAWAWB_CTRL); + isp3_param_write(params_vdev, awb_ctrl, ISP3X_RAWAWB_CTRL, id); } static void isp_rawhstlite_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_rawhistlite_cfg *arg) + const struct isp2x_rawhistlite_cfg *arg, u32 id) { - u32 i; - u32 value; - u32 hist_ctrl; - u32 block_hsize, block_vsize; + struct rkisp_device *ispdev = params_vdev->dev; + struct v4l2_rect *out_crop = &ispdev->isp_sdev.out_crop; + u32 width = out_crop->width, height = out_crop->height; + u32 i, value, hist_ctrl, block_hsize, block_vsize; + u32 h_size, v_size, h_offs, v_offs; /* avoid to override the old enable value */ - hist_ctrl = isp3_param_read(params_vdev, ISP3X_RAWHIST_LITE_CTRL); + hist_ctrl = isp3_param_read(params_vdev, ISP3X_RAWHIST_LITE_CTRL, id); hist_ctrl &= ISP3X_RAWHIST_EN; hist_ctrl = hist_ctrl | ISP3X_RAWHIST_MODE(arg->mode) | @@ -2273,23 +2332,31 @@ isp_rawhstlite_config(struct rkisp_isp_params_vdev *params_vdev, if (params_vdev->dev->isp_ver == ISP_V32) hist_ctrl |= ISP3X_RAWHIST_DATASEL(arg->data_sel) | ISP3X_RAWHIST_WATERLINE(arg->waterline); - isp3_param_write(params_vdev, hist_ctrl, ISP3X_RAWHIST_LITE_CTRL); + isp3_param_write(params_vdev, hist_ctrl, ISP3X_RAWHIST_LITE_CTRL, id); + h_offs = arg->win.h_offs & ~0x1; + v_offs = arg->win.v_offs & ~0x1; isp3_param_write(params_vdev, - ISP_PACK_2SHORT(arg->win.h_offs, arg->win.v_offs), - ISP3X_RAWHIST_LITE_OFFS); + ISP_PACK_2SHORT(h_offs, v_offs), + ISP3X_RAWHIST_LITE_OFFS, id); - block_hsize = arg->win.h_size / ISP32_RAWHISTLITE_ROW_NUM - 1; - block_vsize = arg->win.v_size / ISP32_RAWHISTLITE_COLUMN_NUM - 1; - block_hsize &= 0xFFFE; - block_vsize &= 0xFFFE; + if (ispdev->hw_dev->unite) + width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL; + h_size = arg->win.h_size; + v_size = arg->win.v_size; + if (!h_size || h_size + h_offs + 1 > width) + h_size = width - h_offs - 1; + if (!v_size || v_size + v_offs + 1 > height) + v_size = height - v_offs - 1; + block_hsize = (h_size / ISP32_RAWHISTLITE_ROW_NUM) & ~0x1; + block_vsize = (v_size / ISP32_RAWHISTLITE_COLUMN_NUM) & ~0x1; isp3_param_write(params_vdev, ISP_PACK_2SHORT(block_hsize, block_vsize), - ISP3X_RAWHIST_LITE_SIZE); + ISP3X_RAWHIST_LITE_SIZE, id); isp3_param_write(params_vdev, ISP_PACK_4BYTE(arg->rcc, arg->gcc, arg->bcc, arg->off), - ISP3X_RAWHIST_LITE_RAW2Y_CC); + ISP3X_RAWHIST_LITE_RAW2Y_CC, id); for (i = 0; i < (ISP32_RAWHISTLITE_WEIGHT_REG_SIZE / 4); i++) { value = ISP_PACK_4BYTE(arg->weight[4 * i + 0], @@ -2297,32 +2364,32 @@ isp_rawhstlite_config(struct rkisp_isp_params_vdev *params_vdev, arg->weight[4 * i + 2], arg->weight[4 * i + 3]); isp3_param_write(params_vdev, value, - ISP3X_RAWHIST_LITE_WEIGHT + 4 * i); + ISP3X_RAWHIST_LITE_WEIGHT + 4 * i, id); } value = ISP_PACK_4BYTE(arg->weight[4 * i + 0], 0, 0, 0); isp3_param_write(params_vdev, value, - ISP3X_RAWHIST_LITE_WEIGHT + 4 * i); + ISP3X_RAWHIST_LITE_WEIGHT + 4 * i, id); } static void -isp_rawhstlite_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_rawhstlite_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { u32 hist_ctrl; - hist_ctrl = isp3_param_read(params_vdev, ISP3X_RAWHIST_LITE_CTRL); + hist_ctrl = isp3_param_read(params_vdev, ISP3X_RAWHIST_LITE_CTRL, id); hist_ctrl &= ~(ISP32_MODULE_EN | ISP32_REG_WR_MASK); if (en) hist_ctrl |= ISP32_MODULE_EN; - isp3_param_write(params_vdev, hist_ctrl, ISP3X_RAWHIST_LITE_CTRL); + isp3_param_write(params_vdev, hist_ctrl, ISP3X_RAWHIST_LITE_CTRL, id); } static void isp_rawhstbig_cfg_sram(struct rkisp_isp_params_vdev *params_vdev, const struct isp2x_rawhistbig_cfg *arg, - u32 blk_no, bool is_check) + u32 blk_no, bool is_check, u32 id) { u32 i, j, wnd_num_idx, value; u8 weight15x15[ISP32_RAWHISTBIG_WEIGHT_REG_SIZE]; @@ -2344,7 +2411,7 @@ isp_rawhstbig_cfg_sram(struct rkisp_isp_params_vdev *params_vdev, value = ISP3X_RAWHIST_EN; if (is_check && - !(isp3_param_read(params_vdev, addr + ISP3X_RAWHIST_BIG_CTRL) & value)) + !(isp3_param_read(params_vdev, addr + ISP3X_RAWHIST_BIG_CTRL, id) & value)) return; wnd_num_idx = arg->wnd_num; @@ -2369,13 +2436,16 @@ isp_rawhstbig_cfg_sram(struct rkisp_isp_params_vdev *params_vdev, static void isp_rawhstbig_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_rawhistbig_cfg *arg, u32 blk_no) + const struct isp2x_rawhistbig_cfg *arg, u32 blk_no, u32 id) { - struct isp32_isp_params_cfg *params_rec = params_vdev->isp32_params; + struct isp32_isp_params_cfg *params_rec = params_vdev->isp32_params + id; struct rkisp_device *dev = params_vdev->dev; + struct v4l2_rect *out_crop = &dev->isp_sdev.out_crop; + u32 width = out_crop->width, height = out_crop->height; struct isp2x_rawhistbig_cfg *arg_rec; u32 hist_ctrl, block_hsize, block_vsize, wnd_num_idx; const u32 hist_wnd_num[] = {5, 5, 15, 15}; + u32 h_size, v_size, h_offs, v_offs; u32 addr; switch (blk_no) { @@ -2396,7 +2466,7 @@ isp_rawhstbig_config(struct rkisp_isp_params_vdev *params_vdev, wnd_num_idx = arg->wnd_num; /* avoid to override the old enable value */ - hist_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWHIST_BIG_CTRL); + hist_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWHIST_BIG_CTRL, id); hist_ctrl &= ISP3X_RAWHIST_EN; hist_ctrl = hist_ctrl | ISP3X_RAWHIST_MODE(arg->mode) | @@ -2405,33 +2475,41 @@ isp_rawhstbig_config(struct rkisp_isp_params_vdev *params_vdev, if (params_vdev->dev->isp_ver == ISP_V32) hist_ctrl |= ISP3X_RAWHIST_DATASEL(arg->data_sel) | ISP3X_RAWHIST_WATERLINE(arg->waterline); - isp3_param_write(params_vdev, hist_ctrl, addr + ISP3X_RAWHIST_BIG_CTRL); + isp3_param_write(params_vdev, hist_ctrl, addr + ISP3X_RAWHIST_BIG_CTRL, id); + h_offs = arg->win.h_offs & ~0x1; + v_offs = arg->win.v_offs & ~0x1; isp3_param_write(params_vdev, - ISP_PACK_2SHORT(arg->win.h_offs, arg->win.v_offs), - addr + ISP3X_RAWHIST_BIG_OFFS); + ISP_PACK_2SHORT(h_offs, v_offs), + addr + ISP3X_RAWHIST_BIG_OFFS, id); - block_hsize = arg->win.h_size / hist_wnd_num[wnd_num_idx] - 1; - block_vsize = arg->win.v_size / hist_wnd_num[wnd_num_idx] - 1; - block_hsize &= 0xFFFE; - block_vsize &= 0xFFFE; + if (dev->hw_dev->unite) + width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL; + h_size = arg->win.h_size; + v_size = arg->win.v_size; + if (!h_size || h_size + h_offs + 1 > width) + h_size = width - h_offs - 1; + if (!v_size || v_size + v_offs + 1 > height) + v_size = height - v_offs - 1; + block_hsize = (h_size / hist_wnd_num[wnd_num_idx]) & ~0x1; + block_vsize = (v_size / hist_wnd_num[wnd_num_idx]) & ~0x1; isp3_param_write(params_vdev, ISP_PACK_2SHORT(block_hsize, block_vsize), - addr + ISP3X_RAWHIST_BIG_SIZE); + addr + ISP3X_RAWHIST_BIG_SIZE, id); isp3_param_write(params_vdev, ISP_PACK_4BYTE(arg->rcc, arg->gcc, arg->bcc, arg->off), - addr + ISP3X_RAWHIST_BIG_RAW2Y_CC); + addr + ISP3X_RAWHIST_BIG_RAW2Y_CC, id); if (dev->hw_dev->is_single) - isp_rawhstbig_cfg_sram(params_vdev, arg, blk_no, false); + isp_rawhstbig_cfg_sram(params_vdev, arg, blk_no, false, id); else *arg_rec = *arg; } static void isp_rawhstbig_enable(struct rkisp_isp_params_vdev *params_vdev, - bool en, u32 blk_no) + bool en, u32 blk_no, u32 id) { u32 hist_ctrl; u32 addr; @@ -2449,72 +2527,72 @@ isp_rawhstbig_enable(struct rkisp_isp_params_vdev *params_vdev, break; } - hist_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWHIST_BIG_CTRL); + hist_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWHIST_BIG_CTRL, id); hist_ctrl &= ~(ISP3X_RAWHIST_EN | ISP32_REG_WR_MASK); if (en) hist_ctrl |= ISP3X_RAWHIST_EN; - isp3_param_write(params_vdev, hist_ctrl, addr + ISP3X_RAWHIST_BIG_CTRL); + isp3_param_write(params_vdev, hist_ctrl, addr + ISP3X_RAWHIST_BIG_CTRL, id); } static void isp_rawhst1_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_rawhistbig_cfg *arg) + const struct isp2x_rawhistbig_cfg *arg, u32 id) { - isp_rawhstbig_config(params_vdev, arg, 1); + isp_rawhstbig_config(params_vdev, arg, 1, id); } static void -isp_rawhst1_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_rawhst1_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { - isp_rawhstbig_enable(params_vdev, en, 1); + isp_rawhstbig_enable(params_vdev, en, 1, id); } static void isp_rawhst2_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_rawhistbig_cfg *arg) + const struct isp2x_rawhistbig_cfg *arg, u32 id) { - isp_rawhstbig_config(params_vdev, arg, 2); + isp_rawhstbig_config(params_vdev, arg, 2, id); } static void -isp_rawhst2_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_rawhst2_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { - isp_rawhstbig_enable(params_vdev, en, 2); + isp_rawhstbig_enable(params_vdev, en, 2, id); } static void isp_rawhst3_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_rawhistbig_cfg *arg) + const struct isp2x_rawhistbig_cfg *arg, u32 id) { - isp_rawhstbig_config(params_vdev, arg, 0); + isp_rawhstbig_config(params_vdev, arg, 0, id); } static void -isp_rawhst3_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_rawhst3_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { - isp_rawhstbig_enable(params_vdev, en, 0); + isp_rawhstbig_enable(params_vdev, en, 0, id); } static void isp_hdrmge_config(struct rkisp_isp_params_vdev *params_vdev, const struct isp32_hdrmge_cfg *arg, - enum rkisp_params_type type) + enum rkisp_params_type type, u32 id) { u32 value; int i; if (type == RKISP_PARAMS_SHD || type == RKISP_PARAMS_ALL) { value = ISP_PACK_2SHORT(arg->gain0, arg->gain0_inv); - isp3_param_write(params_vdev, value, ISP3X_HDRMGE_GAIN0); + isp3_param_write(params_vdev, value, ISP3X_HDRMGE_GAIN0, id); value = ISP_PACK_2SHORT(arg->gain1, arg->gain1_inv); - isp3_param_write(params_vdev, value, ISP3X_HDRMGE_GAIN1); + isp3_param_write(params_vdev, value, ISP3X_HDRMGE_GAIN1, id); value = arg->gain2; - isp3_param_write(params_vdev, value, ISP3X_HDRMGE_GAIN2); + isp3_param_write(params_vdev, value, ISP3X_HDRMGE_GAIN2, id); - value = isp3_param_read_cache(params_vdev, ISP3X_HDRMGE_CTRL); + value = isp3_param_read_cache(params_vdev, ISP3X_HDRMGE_CTRL, id); if (arg->s_base) value |= BIT(1); else @@ -2523,48 +2601,48 @@ isp_hdrmge_config(struct rkisp_isp_params_vdev *params_vdev, value |= BIT(6); else value &= ~BIT(6); - isp3_param_write(params_vdev, value, ISP3X_HDRMGE_CTRL); + isp3_param_write(params_vdev, value, ISP3X_HDRMGE_CTRL, id); } if (type == RKISP_PARAMS_IMD || type == RKISP_PARAMS_ALL) { value = ISP_PACK_4BYTE(arg->ms_dif_0p8, arg->ms_diff_0p15, arg->lm_dif_0p9, arg->lm_dif_0p15); - isp3_param_write(params_vdev, value, ISP3X_HDRMGE_LIGHTZ); + isp3_param_write(params_vdev, value, ISP3X_HDRMGE_LIGHTZ, id); value = (arg->ms_scl & 0x7ff) | (arg->ms_thd0 & 0x3ff) << 12 | (arg->ms_thd1 & 0x3ff) << 22; - isp3_param_write(params_vdev, value, ISP3X_HDRMGE_MS_DIFF); + isp3_param_write(params_vdev, value, ISP3X_HDRMGE_MS_DIFF, id); value = (arg->lm_scl & 0x7ff) | (arg->lm_thd0 & 0x3ff) << 12 | (arg->lm_thd1 & 0x3ff) << 22; - isp3_param_write(params_vdev, value, ISP3X_HDRMGE_LM_DIFF); + isp3_param_write(params_vdev, value, ISP3X_HDRMGE_LM_DIFF, id); for (i = 0; i < ISP32_HDRMGE_L_CURVE_NUM; i++) { value = ISP_PACK_2SHORT(arg->curve.curve_0[i], arg->curve.curve_1[i]); - isp3_param_write(params_vdev, value, ISP3X_HDRMGE_DIFF_Y0 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_HDRMGE_DIFF_Y0 + 4 * i, id); } for (i = 0; i < ISP32_HDRMGE_E_CURVE_NUM; i++) { value = (arg->l_raw1[i] & 0x3ff) << 20 | (arg->l_raw0[i] & 0x3ff) << 10 | (arg->e_y[i] & 0x3ff); - isp3_param_write(params_vdev, value, ISP3X_HDRMGE_OVER_Y0 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_HDRMGE_OVER_Y0 + 4 * i, id); } value = ISP_PACK_2SHORT(arg->each_raw_gain0, arg->each_raw_gain1); - isp3_param_write(params_vdev, value, ISP32_HDRMGE_EACH_GAIN); + isp3_param_write(params_vdev, value, ISP32_HDRMGE_EACH_GAIN, id); } } static void -isp_hdrmge_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_hdrmge_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { } static void isp_hdrdrc_config(struct rkisp_isp_params_vdev *params_vdev, const struct isp32_drc_cfg *arg, - enum rkisp_params_type type) + enum rkisp_params_type type, u32 id) { u32 i, value; @@ -2574,76 +2652,76 @@ isp_hdrdrc_config(struct rkisp_isp_params_vdev *params_vdev, value = (arg->offset_pow2 & 0x0F) << 28 | (arg->compres_scl & 0x1FFF) << 14 | (arg->position & 0x03FFF); - isp3_param_write(params_vdev, value, ISP3X_DRC_CTRL1); + isp3_param_write(params_vdev, value, ISP3X_DRC_CTRL1, id); value = arg->delta_scalein << 24 | (arg->hpdetail_ratio & 0xFFF) << 12 | (arg->lpdetail_ratio & 0xFFF); - isp3_param_write(params_vdev, value, ISP3X_DRC_LPRATIO); + isp3_param_write(params_vdev, value, ISP3X_DRC_LPRATIO, id); value = ISP_PACK_4BYTE(arg->bilat_wt_off, 0, arg->weipre_frame, arg->weicur_pix); - isp3_param_write(params_vdev, value, ISP3X_DRC_EXPLRATIO); + isp3_param_write(params_vdev, value, ISP3X_DRC_EXPLRATIO, id); value = (arg->force_sgm_inv0 & 0xFFFF) << 16 | arg->motion_scl << 8 | arg->edge_scl; - isp3_param_write(params_vdev, value, ISP3X_DRC_SIGMA); + isp3_param_write(params_vdev, value, ISP3X_DRC_SIGMA, id); value = ISP_PACK_2SHORT(arg->space_sgm_inv0, arg->space_sgm_inv1); - isp3_param_write(params_vdev, value, ISP3X_DRC_SPACESGM); + isp3_param_write(params_vdev, value, ISP3X_DRC_SPACESGM, id); value = ISP_PACK_2SHORT(arg->range_sgm_inv0, arg->range_sgm_inv1); - isp3_param_write(params_vdev, value, ISP3X_DRC_RANESGM); + isp3_param_write(params_vdev, value, ISP3X_DRC_RANESGM, id); value = (arg->weig_bilat & 0x1f) | (arg->weig_maxl & 0x1f) << 8 | (arg->bilat_soft_thd & 0x3fff) << 16; if (arg->enable_soft_thd) value |= BIT(31); - isp3_param_write(params_vdev, value, ISP3X_DRC_BILAT); + isp3_param_write(params_vdev, value, ISP3X_DRC_BILAT, id); for (i = 0; i < ISP32_DRC_Y_NUM / 2; i++) { value = ISP_PACK_2SHORT(arg->gain_y[2 * i], arg->gain_y[2 * i + 1]); - isp3_param_write(params_vdev, value, ISP3X_DRC_GAIN_Y0 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_DRC_GAIN_Y0 + 4 * i, id); } value = ISP_PACK_2SHORT(arg->gain_y[2 * i], 0); - isp3_param_write(params_vdev, value, ISP3X_DRC_GAIN_Y0 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_DRC_GAIN_Y0 + 4 * i, id); for (i = 0; i < ISP32_DRC_Y_NUM / 2; i++) { value = ISP_PACK_2SHORT(arg->compres_y[2 * i], arg->compres_y[2 * i + 1]); - isp3_param_write(params_vdev, value, ISP3X_DRC_COMPRES_Y0 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_DRC_COMPRES_Y0 + 4 * i, id); } value = ISP_PACK_2SHORT(arg->compres_y[2 * i], 0); - isp3_param_write(params_vdev, value, ISP3X_DRC_COMPRES_Y0 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_DRC_COMPRES_Y0 + 4 * i, id); for (i = 0; i < ISP32_DRC_Y_NUM / 2; i++) { value = ISP_PACK_2SHORT(arg->scale_y[2 * i], arg->scale_y[2 * i + 1]); - isp3_param_write(params_vdev, value, ISP3X_DRC_SCALE_Y0 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_DRC_SCALE_Y0 + 4 * i, id); } value = ISP_PACK_2SHORT(arg->scale_y[2 * i], 0); - isp3_param_write(params_vdev, value, ISP3X_DRC_SCALE_Y0 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_DRC_SCALE_Y0 + 4 * i, id); if (params_vdev->dev->isp_ver == ISP_V32) value = ISP_PACK_2SHORT(arg->min_ogain, arg->iir_weight); else value = ISP_PACK_2SHORT(arg->min_ogain, 0); - isp3_param_write(params_vdev, value, ISP3X_DRC_IIRWG_GAIN); + isp3_param_write(params_vdev, value, ISP3X_DRC_IIRWG_GAIN, id); value = arg->gas_t & 0x1fff; - isp3_param_write(params_vdev, value, ISP32_DRC_LUM3X2_CTRL); + isp3_param_write(params_vdev, value, ISP32_DRC_LUM3X2_CTRL, id); value = ISP_PACK_4BYTE(arg->gas_l0, arg->gas_l1, arg->gas_l2, arg->gas_l3); - isp3_param_write(params_vdev, value, ISP32_DRC_LUM3X2_GAS); + isp3_param_write(params_vdev, value, ISP32_DRC_LUM3X2_GAS, id); } static void -isp_hdrdrc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_hdrdrc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { u32 value; bool real_en; - value = isp3_param_read(params_vdev, ISP3X_DRC_CTRL0); + value = isp3_param_read(params_vdev, ISP3X_DRC_CTRL0, id); real_en = !!(value & ISP32_MODULE_EN); if ((en && real_en) || (!en && !real_en)) return; @@ -2651,17 +2729,17 @@ isp_hdrdrc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) if (en) { value |= ISP32_MODULE_EN; isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1, - ISP3X_ADRC_FST_FRAME); + ISP3X_ADRC_FST_FRAME, id); } else { value = 0; - isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(12)); + isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(12), id); } - isp3_param_write(params_vdev, value, ISP3X_DRC_CTRL0); + isp3_param_write(params_vdev, value, ISP3X_DRC_CTRL0, id); } static void isp_gic_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp21_gic_cfg *arg) + const struct isp21_gic_cfg *arg, u32 id) { u32 value; s32 i; @@ -2669,12 +2747,12 @@ isp_gic_config(struct rkisp_isp_params_vdev *params_vdev, value = (arg->regmingradthrdark2 & 0x03FF) << 20 | (arg->regmingradthrdark1 & 0x03FF) << 10 | (arg->regminbusythre & 0x03FF); - isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA1); + isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA1, id); value = (arg->regdarkthre & 0x07FF) << 21 | (arg->regmaxcorvboth & 0x03FF) << 11 | (arg->regdarktthrehi & 0x07FF); - isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA2); + isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA2, id); value = (arg->regkgrad2dark & 0x0F) << 28 | (arg->regkgrad1dark & 0x0F) << 24 | @@ -2683,46 +2761,46 @@ isp_gic_config(struct rkisp_isp_params_vdev *params_vdev, (arg->regkgrad2 & 0x0F) << 8 | (arg->regkgrad1 & 0x0F) << 4 | (arg->reggbthre & 0x0F); - isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA3); + isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA3, id); value = (arg->regmaxcorv & 0x03FF) << 20 | (arg->regmingradthr2 & 0x03FF) << 10 | (arg->regmingradthr1 & 0x03FF); - isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA4); + isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA4, id); value = (arg->gr_ratio & 0x03) << 28 | (arg->noise_scale & 0x7F) << 12 | (arg->noise_base & 0xFFF); - isp3_param_write(params_vdev, value, ISP3X_GIC_NOISE_PARA1); + isp3_param_write(params_vdev, value, ISP3X_GIC_NOISE_PARA1, id); value = arg->diff_clip & 0x7fff; - isp3_param_write(params_vdev, value, ISP3X_GIC_NOISE_PARA2); + isp3_param_write(params_vdev, value, ISP3X_GIC_NOISE_PARA2, id); for (i = 0; i < ISP32_GIC_SIGMA_Y_NUM / 2; i++) { value = ISP_PACK_2SHORT(arg->sigma_y[2 * i], arg->sigma_y[2 * i + 1]); - isp3_param_write(params_vdev, value, ISP3X_GIC_SIGMA_VALUE0 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_GIC_SIGMA_VALUE0 + 4 * i, id); } value = ISP_PACK_2SHORT(arg->sigma_y[2 * i], 0); - isp3_param_write(params_vdev, value, ISP3X_GIC_SIGMA_VALUE0 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_GIC_SIGMA_VALUE0 + 4 * i, id); } static void -isp_gic_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_gic_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { u32 value = 0; if (en) value |= ISP32_MODULE_EN; - isp3_param_write(params_vdev, value, ISP3X_GIC_CONTROL); + isp3_param_write(params_vdev, value, ISP3X_GIC_CONTROL, id); } static void isp_dhaz_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_dhaz_cfg *arg) + const struct isp32_dhaz_cfg *arg, u32 id) { u32 i, value, ctrl; - ctrl = isp3_param_read(params_vdev, ISP3X_DHAZ_CTRL); + ctrl = isp3_param_read(params_vdev, ISP3X_DHAZ_CTRL, id); ctrl &= ISP3X_DHAZ_ENMUX; ctrl |= !!arg->enh_luma_en << 28 | !!arg->color_deviate_en << 27 | @@ -2736,109 +2814,109 @@ isp_dhaz_config(struct rkisp_isp_params_vdev *params_vdev, value = (arg->hist_wr[i * 3] & 0x3ff) | (arg->hist_wr[i * 3 + 1] & 0x3ff) << 10 | (arg->hist_wr[i * 3 + 2] & 0x3ff) << 20; - isp3_param_write(params_vdev, value, ISP3X_DHAZ_HIST_WR0 + i * 4); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_HIST_WR0 + i * 4, id); } value = arg->hist_wr[i * 3] & 0x3ff; - isp3_param_write(params_vdev, value, ISP3X_DHAZ_HIST_WR0 + i * 4); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_HIST_WR0 + i * 4, id); } - isp3_param_write(params_vdev, ctrl, ISP3X_DHAZ_CTRL); + isp3_param_write(params_vdev, ctrl, ISP3X_DHAZ_CTRL, id); value = ISP_PACK_4BYTE(arg->dc_min_th, arg->dc_max_th, arg->yhist_th, arg->yblk_th); - isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP0); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP0, id); value = ISP_PACK_4BYTE(arg->bright_min, arg->bright_max, arg->wt_max, 0); - isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP1); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP1, id); value = ISP_PACK_4BYTE(arg->air_min, arg->air_max, arg->dark_th, arg->tmax_base); - isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP2); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP2, id); value = ISP_PACK_2SHORT(arg->tmax_off, arg->tmax_max); - isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP_TMAX); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP_TMAX, id); value = (arg->hist_min & 0xFFFF) << 16 | (arg->hist_th_off & 0xFF) << 8 | (arg->hist_k & 0x1F); - isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP_HIST0); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP_HIST0, id); value = ISP_PACK_2SHORT(arg->hist_scale, arg->hist_gratio); - isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP_HIST1); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP_HIST1, id); value = ISP_PACK_2SHORT(arg->enhance_chroma, arg->enhance_value); - isp3_param_write(params_vdev, value, ISP3X_DHAZ_ENHANCE); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_ENHANCE, id); value = (arg->iir_wt_sigma & 0x07FF) << 16 | (arg->iir_sigma & 0xFF) << 8 | (arg->stab_fnum & 0x1F); - isp3_param_write(params_vdev, value, ISP3X_DHAZ_IIR0); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_IIR0, id); value = (arg->iir_pre_wet & 0x0F) << 24 | (arg->iir_tmax_sigma & 0x7FF) << 8 | (arg->iir_air_sigma & 0xFF); - isp3_param_write(params_vdev, value, ISP3X_DHAZ_IIR1); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_IIR1, id); value = (arg->cfg_wt & 0x01FF) << 16 | (arg->cfg_air & 0xFF) << 8 | (arg->cfg_alpha & 0xFF); - isp3_param_write(params_vdev, value, ISP3X_DHAZ_SOFT_CFG0); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_SOFT_CFG0, id); value = ISP_PACK_2SHORT(arg->cfg_tmax, arg->cfg_gratio); - isp3_param_write(params_vdev, value, ISP3X_DHAZ_SOFT_CFG1); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_SOFT_CFG1, id); value = (arg->range_sima & 0x01FF) << 16 | (arg->space_sigma_pre & 0xFF) << 8 | (arg->space_sigma_cur & 0xFF); - isp3_param_write(params_vdev, value, ISP3X_DHAZ_BF_SIGMA); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_BF_SIGMA, id); value = ISP_PACK_2SHORT(arg->bf_weight, arg->dc_weitcur); - isp3_param_write(params_vdev, value, ISP3X_DHAZ_BF_WET); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_BF_WET, id); for (i = 0; i < ISP32_DHAZ_ENH_CURVE_NUM / 2; i++) { value = ISP_PACK_2SHORT(arg->enh_curve[2 * i], arg->enh_curve[2 * i + 1]); - isp3_param_write(params_vdev, value, ISP3X_DHAZ_ENH_CURVE0 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_ENH_CURVE0 + 4 * i, id); } value = ISP_PACK_2SHORT(arg->enh_curve[2 * i], 0); - isp3_param_write(params_vdev, value, ISP3X_DHAZ_ENH_CURVE0 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_ENH_CURVE0 + 4 * i, id); value = ISP_PACK_4BYTE(arg->gaus_h0, arg->gaus_h1, arg->gaus_h2, 0); - isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAUS); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAUS, id); for (i = 0; i < ISP32_DHAZ_SIGMA_IDX_NUM / 4; i++) { value = ISP_PACK_4BYTE(arg->sigma_idx[i * 4], arg->sigma_idx[i * 4 + 1], arg->sigma_idx[i * 4 + 2], arg->sigma_idx[i * 4 + 3]); - isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_IDX0 + i * 4); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_IDX0 + i * 4, id); } value = ISP_PACK_4BYTE(arg->sigma_idx[i * 4], arg->sigma_idx[i * 4 + 1], arg->sigma_idx[i * 4 + 2], 0); - isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_IDX0 + i * 4); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_IDX0 + i * 4, id); for (i = 0; i < ISP32_DHAZ_SIGMA_LUT_NUM / 2; i++) { value = ISP_PACK_2SHORT(arg->sigma_lut[i * 2], arg->sigma_lut[i * 2 + 1]); - isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_LUT0 + i * 4); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_LUT0 + i * 4, id); } value = ISP_PACK_2SHORT(arg->sigma_lut[i * 2], 0); - isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_LUT0 + i * 4); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_LUT0 + i * 4, id); for (i = 0; i < ISP32_DHAZ_ENH_LUMA_NUM / 3; i++) { value = (arg->enh_luma[i * 3 + 2] & 0x3ff) << 20 | (arg->enh_luma[i * 3 + 1] & 0x3ff) << 10 | (arg->enh_luma[i * 3] & 0x3ff); - isp3_param_write(params_vdev, value, ISP32_DHAZ_ENH_LUMA0 + i * 4); + isp3_param_write(params_vdev, value, ISP32_DHAZ_ENH_LUMA0 + i * 4, id); } value = (arg->enh_luma[i * 3 + 1] & 0x3ff) << 10 | (arg->enh_luma[i * 3] & 0x3ff); - isp3_param_write(params_vdev, value, ISP32_DHAZ_ENH_LUMA0 + i * 4); + isp3_param_write(params_vdev, value, ISP32_DHAZ_ENH_LUMA0 + i * 4, id); } static void -isp_dhaz_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_dhaz_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { u32 value; bool real_en; - value = isp3_param_read(params_vdev, ISP3X_DHAZ_CTRL); + value = isp3_param_read(params_vdev, ISP3X_DHAZ_CTRL, id); real_en = !!(value & ISP3X_DHAZ_ENMUX); if ((en && real_en) || (!en && !real_en)) return; @@ -2846,17 +2924,17 @@ isp_dhaz_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) if (en) { value |= ISP32_SELF_FORCE_UPD | ISP3X_DHAZ_ENMUX; isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1, - ISP3X_DHAZ_FST_FRAME); + ISP3X_DHAZ_FST_FRAME, id); } else { value &= ~ISP3X_DHAZ_ENMUX; - isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(16)); + isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(16), id); } - isp3_param_write(params_vdev, value, ISP3X_DHAZ_CTRL); + isp3_param_write(params_vdev, value, ISP3X_DHAZ_CTRL, id); } static void isp_3dlut_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_3dlut_cfg *arg) + const struct isp2x_3dlut_cfg *arg, u32 id) { struct rkisp_device *dev = params_vdev->dev; struct rkisp_isp_params_val_v32 *priv_val; @@ -2864,58 +2942,58 @@ isp_3dlut_config(struct rkisp_isp_params_vdev *params_vdev, u32 *data; priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; - buf_idx = (priv_val->buf_3dlut_idx++) % ISP32_3DLUT_BUF_NUM; + buf_idx = (priv_val->buf_3dlut_idx[id]++) % ISP32_3DLUT_BUF_NUM; - if (!priv_val->buf_3dlut[buf_idx].vaddr) { + if (!priv_val->buf_3dlut[id][buf_idx].vaddr) { dev_err(dev->dev, "no find 3dlut buf\n"); return; } - data = (u32 *)priv_val->buf_3dlut[buf_idx].vaddr; + data = (u32 *)priv_val->buf_3dlut[id][buf_idx].vaddr; for (i = 0; i < arg->actual_size; i++) data[i] = (arg->lut_b[i] & 0x3FF) | (arg->lut_g[i] & 0xFFF) << 10 | (arg->lut_r[i] & 0x3FF) << 22; - rkisp_prepare_buffer(params_vdev->dev, &priv_val->buf_3dlut[buf_idx]); - value = priv_val->buf_3dlut[buf_idx].dma_addr; - isp3_param_write(params_vdev, value, ISP3X_MI_LUT_3D_RD_BASE); - isp3_param_write(params_vdev, arg->actual_size, ISP3X_MI_LUT_3D_RD_WSIZE); + rkisp_prepare_buffer(params_vdev->dev, &priv_val->buf_3dlut[id][buf_idx]); + value = priv_val->buf_3dlut[id][buf_idx].dma_addr; + isp3_param_write(params_vdev, value, ISP3X_MI_LUT_3D_RD_BASE, id); + isp3_param_write(params_vdev, arg->actual_size, ISP3X_MI_LUT_3D_RD_WSIZE, id); - value = isp3_param_read(params_vdev, ISP3X_3DLUT_CTRL); + value = isp3_param_read(params_vdev, ISP3X_3DLUT_CTRL, id); value &= ISP3X_3DLUT_EN; if (value) - isp3_param_set_bits(params_vdev, ISP3X_3DLUT_UPDATE, 0x01); + isp3_param_set_bits(params_vdev, ISP3X_3DLUT_UPDATE, 0x01, id); - isp3_param_write(params_vdev, value, ISP3X_3DLUT_CTRL); + isp3_param_write(params_vdev, value, ISP3X_3DLUT_CTRL, id); } static void -isp_3dlut_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_3dlut_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { u32 value; bool en_state; struct rkisp_isp_params_val_v32 *priv_val; - value = isp3_param_read(params_vdev, ISP3X_3DLUT_CTRL); + value = isp3_param_read(params_vdev, ISP3X_3DLUT_CTRL, id); en_state = (value & ISP3X_3DLUT_EN) ? true : false; if (en == en_state) return; priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; - if (en && priv_val->buf_3dlut[0].vaddr) { - isp3_param_set_bits(params_vdev, ISP3X_3DLUT_CTRL, 0x01); - isp3_param_set_bits(params_vdev, ISP3X_3DLUT_UPDATE, 0x01); + if (en && priv_val->buf_3dlut[id][0].vaddr) { + isp3_param_set_bits(params_vdev, ISP3X_3DLUT_CTRL, 0x01, id); + isp3_param_set_bits(params_vdev, ISP3X_3DLUT_UPDATE, 0x01, id); } else { - isp3_param_clear_bits(params_vdev, ISP3X_3DLUT_CTRL, 0x01); - isp3_param_clear_bits(params_vdev, ISP3X_3DLUT_UPDATE, 0x01); - isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(20)); + isp3_param_clear_bits(params_vdev, ISP3X_3DLUT_CTRL, 0x01, id); + isp3_param_clear_bits(params_vdev, ISP3X_3DLUT_UPDATE, 0x01, id); + isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(20), id); } } static void isp_ldch_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_ldch_cfg *arg) + const struct isp32_ldch_cfg *arg, u32 id) { struct rkisp_device *dev = params_vdev->dev; struct rkisp_isp_params_val_v32 *priv_val; @@ -2923,7 +3001,7 @@ isp_ldch_config(struct rkisp_isp_params_vdev *params_vdev, int buf_idx, i; u32 value; - value = isp3_param_read(params_vdev, ISP3X_LDCH_STS); + value = isp3_param_read(params_vdev, ISP3X_LDCH_STS, id); value &= ISP32_MODULE_EN; value |= !!arg->map13p3_en << 7 | !!arg->force_map_en << 6 | @@ -2931,20 +3009,20 @@ isp_ldch_config(struct rkisp_isp_params_vdev *params_vdev, !!arg->sample_avr_en << 3 | !!arg->zero_interp_en << 2 | !!arg->frm_end_dis << 1; - isp3_param_write(params_vdev, value, ISP3X_LDCH_STS); + isp3_param_write(params_vdev, value, ISP3X_LDCH_STS, id); if (arg->bic_mode_en) { for (i = 0; i < ISP32_LDCH_BIC_NUM / 4; i++) { value = ISP_PACK_4BYTE(arg->bicubic[i * 4], arg->bicubic[i * 4 + 1], arg->bicubic[i * 4 + 2], arg->bicubic[i * 4 + 3]); - isp3_param_write(params_vdev, value, ISP32_LDCH_BIC_TABLE0 + i * 4); + isp3_param_write(params_vdev, value, ISP32_LDCH_BIC_TABLE0 + i * 4, id); } } priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; for (i = 0; i < ISP32_MESH_BUF_NUM; i++) { - if (!priv_val->buf_ldch[i].mem_priv) + if (!priv_val->buf_ldch[id][i].mem_priv) continue; - if (arg->buf_fd == priv_val->buf_ldch[i].dma_fd) + if (arg->buf_fd == priv_val->buf_ldch[id][i].dma_fd) break; } if (i == ISP32_MESH_BUF_NUM) { @@ -2952,28 +3030,28 @@ isp_ldch_config(struct rkisp_isp_params_vdev *params_vdev, return; } - if (!priv_val->buf_ldch[i].vaddr) { + if (!priv_val->buf_ldch[id][i].vaddr) { dev_err(dev->dev, "no ldch buffer allocated\n"); return; } - buf_idx = priv_val->buf_ldch_idx; - head = (struct isp2x_mesh_head *)priv_val->buf_ldch[buf_idx].vaddr; + buf_idx = priv_val->buf_ldch_idx[id]; + head = (struct isp2x_mesh_head *)priv_val->buf_ldch[id][buf_idx].vaddr; head->stat = MESH_BUF_INIT; buf_idx = i; - head = (struct isp2x_mesh_head *)priv_val->buf_ldch[buf_idx].vaddr; + head = (struct isp2x_mesh_head *)priv_val->buf_ldch[id][buf_idx].vaddr; head->stat = MESH_BUF_CHIPINUSE; - priv_val->buf_ldch_idx = buf_idx; - rkisp_prepare_buffer(dev, &priv_val->buf_ldch[buf_idx]); - value = priv_val->buf_ldch[buf_idx].dma_addr + head->data_oft; - isp3_param_write(params_vdev, value, ISP3X_MI_LUT_LDCH_RD_BASE); - isp3_param_write(params_vdev, arg->hsize, ISP3X_MI_LUT_LDCH_RD_H_WSIZE); - isp3_param_write(params_vdev, arg->vsize, ISP3X_MI_LUT_LDCH_RD_V_SIZE); + priv_val->buf_ldch_idx[id] = buf_idx; + rkisp_prepare_buffer(dev, &priv_val->buf_ldch[id][buf_idx]); + value = priv_val->buf_ldch[id][buf_idx].dma_addr + head->data_oft; + isp3_param_write(params_vdev, value, ISP3X_MI_LUT_LDCH_RD_BASE, id); + isp3_param_write(params_vdev, arg->hsize, ISP3X_MI_LUT_LDCH_RD_H_WSIZE, id); + isp3_param_write(params_vdev, arg->vsize, ISP3X_MI_LUT_LDCH_RD_V_SIZE, id); } static void -isp_ldch_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_ldch_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { struct rkisp_device *dev = params_vdev->dev; struct rkisp_isp_params_val_v32 *priv_val; @@ -2981,24 +3059,24 @@ isp_ldch_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; if (en) { - buf_idx = priv_val->buf_ldch_idx; - if (!priv_val->buf_ldch[buf_idx].vaddr) { + buf_idx = priv_val->buf_ldch_idx[id]; + if (!priv_val->buf_ldch[id][buf_idx].vaddr) { dev_err(dev->dev, "no ldch buffer allocated\n"); return; } - isp3_param_set_bits(params_vdev, ISP3X_LDCH_STS, 0x01); + isp3_param_set_bits(params_vdev, ISP3X_LDCH_STS, 0x01, id); } else { - isp3_param_clear_bits(params_vdev, ISP3X_LDCH_STS, 0x01); + isp3_param_clear_bits(params_vdev, ISP3X_LDCH_STS, 0x01, id); } } static void isp_ynr_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_ynr_cfg *arg) + const struct isp32_ynr_cfg *arg, u32 id) { u32 i, value; - value = isp3_param_read(params_vdev, ISP3X_YNR_GLOBAL_CTRL); + value = isp3_param_read(params_vdev, ISP3X_YNR_GLOBAL_CTRL, id); value &= ISP32_MODULE_EN; value |= !!arg->rnr_en << 26 | @@ -3011,96 +3089,96 @@ isp_ynr_config(struct rkisp_isp_params_vdev *params_vdev, !!arg->lgft3x3_bypass << 3 | !!arg->lbft5x5_bypass << 2 | !!arg->bft3x3_bypass << 1; - isp3_param_write(params_vdev, value, ISP3X_YNR_GLOBAL_CTRL); + isp3_param_write(params_vdev, value, ISP3X_YNR_GLOBAL_CTRL, id); value = ISP_PACK_2SHORT(arg->rnr_max_r, arg->local_gainscale); - isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_MAX_R); + isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_MAX_R, id); value = ISP_PACK_2SHORT(arg->rnr_center_coorh, arg->rnr_center_coorv); - isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_CENTER_COOR); + isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_CENTER_COOR, id); value = ISP_PACK_2SHORT(arg->loclagain_adj_thresh, arg->localgain_adj); - isp3_param_write(params_vdev, value, ISP3X_YNR_LOCAL_GAIN_CTRL); + isp3_param_write(params_vdev, value, ISP3X_YNR_LOCAL_GAIN_CTRL, id); value = ISP_PACK_2SHORT(arg->low_bf_inv0, arg->low_bf_inv1); - isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL0); + isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL0, id); value = ISP_PACK_2SHORT(arg->low_thred_adj, arg->low_peak_supress); - isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL1); + isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL1, id); value = ISP_PACK_2SHORT(arg->low_edge_adj_thresh, arg->low_dist_adj); - isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL2); + isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL2, id); value = (arg->low_bi_weight & 0xFF) << 24 | (arg->low_weight & 0xFF) << 16 | (arg->low_center_weight & 0xFFFF); - isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL3); + isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL3, id); value = ISP_PACK_2SHORT(arg->lbf_weight_thres, arg->frame_full_size); if (params_vdev->dev->isp_ver == ISP_V32_L) value |= (arg->frame_add4line & 0xf) << 12; - isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL4); + isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL4, id); value = (arg->low_gauss1_coeff2 & 0xFFFF) << 16 | (arg->low_gauss1_coeff1 & 0xFF) << 8 | (arg->low_gauss1_coeff0 & 0xFF); - isp3_param_write(params_vdev, value, ISP3X_YNR_GAUSS1_COEFF); + isp3_param_write(params_vdev, value, ISP3X_YNR_GAUSS1_COEFF, id); value = (arg->low_gauss2_coeff2 & 0xFFFF) << 16 | (arg->low_gauss2_coeff1 & 0xFF) << 8 | (arg->low_gauss2_coeff0 & 0xFF); - isp3_param_write(params_vdev, value, ISP3X_YNR_GAUSS2_COEFF); + isp3_param_write(params_vdev, value, ISP3X_YNR_GAUSS2_COEFF, id); for (i = 0; i < ISP32_YNR_XY_NUM / 2; i++) { value = ISP_PACK_2SHORT(arg->luma_points_x[2 * i], arg->luma_points_x[2 * i + 1]); - isp3_param_write(params_vdev, value, ISP3X_YNR_SGM_DX_0_1 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_YNR_SGM_DX_0_1 + 4 * i, id); } value = ISP_PACK_2SHORT(arg->luma_points_x[2 * i], 0); - isp3_param_write(params_vdev, value, ISP3X_YNR_SGM_DX_0_1 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_YNR_SGM_DX_0_1 + 4 * i, id); for (i = 0; i < ISP32_YNR_XY_NUM / 2; i++) { value = ISP_PACK_2SHORT(arg->lsgm_y[2 * i], arg->lsgm_y[2 * i + 1]); - isp3_param_write(params_vdev, value, ISP3X_YNR_LSGM_Y_0_1 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_YNR_LSGM_Y_0_1 + 4 * i, id); } value = ISP_PACK_2SHORT(arg->lsgm_y[2 * i], 0); - isp3_param_write(params_vdev, value, ISP3X_YNR_LSGM_Y_0_1 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_YNR_LSGM_Y_0_1 + 4 * i, id); for (i = 0; i < ISP32_YNR_XY_NUM / 4; i++) { value = ISP_PACK_4BYTE(arg->rnr_strength3[4 * i], arg->rnr_strength3[4 * i + 1], arg->rnr_strength3[4 * i + 2], arg->rnr_strength3[4 * i + 3]); - isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_STRENGTH03 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_STRENGTH03 + 4 * i, id); } value = ISP_PACK_4BYTE(arg->rnr_strength3[4 * i], 0, 0, 0); - isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_STRENGTH03 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_STRENGTH03 + 4 * i, id); value = (arg->nlm_hi_bf_scale & 0x3ff) << 16 | (arg->nlm_hi_gain_alpha & 0x1f) << 11 | (arg->nlm_min_sigma & 0x7ff); - isp3_param_write(params_vdev, value, ISP32_YNR_NLM_SIGMA_GAIN); + isp3_param_write(params_vdev, value, ISP32_YNR_NLM_SIGMA_GAIN, id); value = (arg->nlm_coe[5] & 0xf) << 20 | (arg->nlm_coe[4] & 0xf) << 16 | (arg->nlm_coe[3] & 0xf) << 12 | (arg->nlm_coe[2] & 0xf) << 8 | (arg->nlm_coe[1] & 0xf) << 4 | (arg->nlm_coe[0] & 0xf); - isp3_param_write(params_vdev, value, ISP32_YNR_NLM_COE); + isp3_param_write(params_vdev, value, ISP32_YNR_NLM_COE, id); value = (arg->nlm_center_weight & 0x3ffff) << 10 | (arg->nlm_weight_offset & 0x3ff); - isp3_param_write(params_vdev, value, ISP32_YNR_NLM_WEIGHT); + isp3_param_write(params_vdev, value, ISP32_YNR_NLM_WEIGHT, id); value = arg->nlm_nr_weight & 0x7ff; - isp3_param_write(params_vdev, value, ISP32_YNR_NLM_NR_WEIGHT); + isp3_param_write(params_vdev, value, ISP32_YNR_NLM_NR_WEIGHT, id); } static void -isp_ynr_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_ynr_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { u32 ynr_ctrl; bool real_en; - ynr_ctrl = isp3_param_read_cache(params_vdev, ISP3X_YNR_GLOBAL_CTRL); + ynr_ctrl = isp3_param_read_cache(params_vdev, ISP3X_YNR_GLOBAL_CTRL, id); real_en = !!(ynr_ctrl & ISP32_MODULE_EN); if ((en && real_en) || (!en && !real_en)) return; @@ -3108,22 +3186,22 @@ isp_ynr_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) if (en) { ynr_ctrl |= ISP32_MODULE_EN; isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1, - ISP3X_YNR_FST_FRAME); + ISP3X_YNR_FST_FRAME, id); } else { ynr_ctrl &= ~ISP32_MODULE_EN; } - isp3_param_write(params_vdev, ynr_ctrl, ISP3X_YNR_GLOBAL_CTRL); + isp3_param_write(params_vdev, ynr_ctrl, ISP3X_YNR_GLOBAL_CTRL, id); } static void isp_cnr_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_cnr_cfg *arg) + const struct isp32_cnr_cfg *arg, u32 id) { u32 i, value, ctrl, gain_ctrl; - gain_ctrl = isp3_param_read(params_vdev, ISP3X_GAIN_CTRL); - ctrl = isp3_param_read(params_vdev, ISP3X_CNR_CTRL); + gain_ctrl = isp3_param_read(params_vdev, ISP3X_GAIN_CTRL, id); + ctrl = isp3_param_read(params_vdev, ISP3X_CNR_CTRL, id); ctrl &= ISP32_MODULE_EN; ctrl |= !!arg->bf3x3_wgt0_sel << 8 | @@ -3139,63 +3217,63 @@ isp_cnr_config(struct rkisp_isp_params_vdev *params_vdev, value &= ~ISP3X_CNR_GLOBAL_GAIN_ALPHA_MAX; value |= BIT(15); } - isp3_param_write(params_vdev, ctrl, ISP3X_CNR_CTRL); - isp3_param_write(params_vdev, value, ISP3X_CNR_EXGAIN); + isp3_param_write(params_vdev, ctrl, ISP3X_CNR_CTRL, id); + isp3_param_write(params_vdev, value, ISP3X_CNR_EXGAIN, id); value = ISP_PACK_2SHORT(arg->thumb_sigma_c, arg->thumb_sigma_y); - isp3_param_write(params_vdev, value, ISP32_CNR_THUMB1); + isp3_param_write(params_vdev, value, ISP32_CNR_THUMB1, id); value = arg->thumb_bf_ratio & 0x7ff; - isp3_param_write(params_vdev, value, ISP32_CNR_THUMB_BF_RATIO); + isp3_param_write(params_vdev, value, ISP32_CNR_THUMB_BF_RATIO, id); value = ISP_PACK_4BYTE(arg->lbf1x7_weit_d0, arg->lbf1x7_weit_d1, arg->lbf1x7_weit_d2, arg->lbf1x7_weit_d3); - isp3_param_write(params_vdev, value, ISP32_CNR_LBF_WEITD); + isp3_param_write(params_vdev, value, ISP32_CNR_LBF_WEITD, id); value = (arg->wgt_slope & 0x3ff) << 20 | (arg->exp_shift & 0x3f) << 12 | arg->iir_strength << 4 | (arg->iir_uvgain & 0xf); - isp3_param_write(params_vdev, value, ISP32_CNR_IIR_PARA1); + isp3_param_write(params_vdev, value, ISP32_CNR_IIR_PARA1, id); value = ISP_PACK_4BYTE(arg->chroma_ghost, arg->iir_uv_clip, 0, 0); - isp3_param_write(params_vdev, value, ISP32_CNR_IIR_PARA2); + isp3_param_write(params_vdev, value, ISP32_CNR_IIR_PARA2, id); value = ISP_PACK_4BYTE(arg->gaus_coe[0], arg->gaus_coe[1], arg->gaus_coe[2], arg->gaus_coe[3]); - isp3_param_write(params_vdev, value, ISP32_CNR_GAUS_COE1); + isp3_param_write(params_vdev, value, ISP32_CNR_GAUS_COE1, id); value = ISP_PACK_4BYTE(arg->gaus_coe[4], arg->gaus_coe[5], 0, 0); - isp3_param_write(params_vdev, value, ISP32_CNR_GAUS_COE2); + isp3_param_write(params_vdev, value, ISP32_CNR_GAUS_COE2, id); value = (arg->global_alpha & 0x7ff) << 20 | arg->bf_wgt_clip << 12 | (arg->gaus_ratio & 0x7ff); - isp3_param_write(params_vdev, value, ISP32_CNR_GAUS_RATIO); + isp3_param_write(params_vdev, value, ISP32_CNR_GAUS_RATIO, id); value = arg->bf_ratio << 24 | (arg->sigma_r & 0x3fff) << 8 | (arg->uv_gain & 0x7f); - isp3_param_write(params_vdev, value, ISP32_CNR_BF_PARA1); + isp3_param_write(params_vdev, value, ISP32_CNR_BF_PARA1, id); value = (arg->adj_ratio & 0x7fff) << 16 | (arg->adj_offset & 0x1ff); - isp3_param_write(params_vdev, value, ISP32_CNR_BF_PARA2); + isp3_param_write(params_vdev, value, ISP32_CNR_BF_PARA2, id); for (i = 0; i < ISP32_CNR_SIGMA_Y_NUM / 4; i++) { value = ISP_PACK_4BYTE(arg->sigma_y[i * 4], arg->sigma_y[i * 4 + 1], arg->sigma_y[i * 4 + 2], arg->sigma_y[i * 4 + 3]); - isp3_param_write(params_vdev, value, ISP32_CNR_SIGMA0 + i * 4); + isp3_param_write(params_vdev, value, ISP32_CNR_SIGMA0 + i * 4, id); } value = arg->sigma_y[i * 4]; - isp3_param_write(params_vdev, value, ISP32_CNR_SIGMA0 + i * 4); + isp3_param_write(params_vdev, value, ISP32_CNR_SIGMA0 + i * 4, id); value = (arg->iir_gain_alpha & 0xf) << 8 | arg->iir_global_gain; - isp3_param_write(params_vdev, value, ISP32_CNR_IIR_GLOBAL_GAIN); + isp3_param_write(params_vdev, value, ISP32_CNR_IIR_GLOBAL_GAIN, id); } static void -isp_cnr_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_cnr_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { u32 cnr_ctrl; bool real_en; - cnr_ctrl = isp3_param_read_cache(params_vdev, ISP3X_CNR_CTRL); + cnr_ctrl = isp3_param_read_cache(params_vdev, ISP3X_CNR_CTRL, id); real_en = !!(cnr_ctrl & ISP32_MODULE_EN); if ((en && real_en) || (!en && !real_en)) return; @@ -3203,21 +3281,21 @@ isp_cnr_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) if (en) { cnr_ctrl |= ISP32_MODULE_EN; isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1, - ISP3X_CNR_FST_FRAME); + ISP3X_CNR_FST_FRAME, id); } else { cnr_ctrl &= ~ISP32_MODULE_EN; } - isp3_param_write(params_vdev, cnr_ctrl, ISP3X_CNR_CTRL); + isp3_param_write(params_vdev, cnr_ctrl, ISP3X_CNR_CTRL, id); } static void isp_sharp_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_sharp_cfg *arg) + const struct isp32_sharp_cfg *arg, u32 id) { u32 i, value; - value = isp3_param_read(params_vdev, ISP3X_SHARP_EN); + value = isp3_param_read(params_vdev, ISP3X_SHARP_EN, id); value &= ISP32_MODULE_EN; value |= !!arg->bypass << 1 | @@ -3229,11 +3307,11 @@ isp_sharp_config(struct rkisp_isp_params_vdev *params_vdev, else value |= !!arg->clip_hf_mode << 6 | !!arg->add_mode << 7; - isp3_param_write(params_vdev, value, ISP3X_SHARP_EN); + isp3_param_write(params_vdev, value, ISP3X_SHARP_EN, id); value = ISP_PACK_4BYTE(arg->pbf_ratio, arg->gaus_ratio, arg->bf_ratio, arg->sharp_ratio); - isp3_param_write(params_vdev, value, ISP3X_SHARP_RATIO); + isp3_param_write(params_vdev, value, ISP3X_SHARP_RATIO, id); value = (arg->luma_dx[6] & 0x0F) << 24 | (arg->luma_dx[5] & 0x0F) << 20 | @@ -3242,123 +3320,123 @@ isp_sharp_config(struct rkisp_isp_params_vdev *params_vdev, (arg->luma_dx[2] & 0x0F) << 8 | (arg->luma_dx[1] & 0x0F) << 4 | (arg->luma_dx[0] & 0x0F); - isp3_param_write(params_vdev, value, ISP3X_SHARP_LUMA_DX); + isp3_param_write(params_vdev, value, ISP3X_SHARP_LUMA_DX, id); value = (arg->pbf_sigma_inv[2] & 0x3FF) << 20 | (arg->pbf_sigma_inv[1] & 0x3FF) << 10 | (arg->pbf_sigma_inv[0] & 0x3FF); - isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_SIGMA_INV_0); + isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_SIGMA_INV_0, id); value = (arg->pbf_sigma_inv[5] & 0x3FF) << 20 | (arg->pbf_sigma_inv[4] & 0x3FF) << 10 | (arg->pbf_sigma_inv[3] & 0x3FF); - isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_SIGMA_INV_1); + isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_SIGMA_INV_1, id); value = (arg->pbf_sigma_inv[7] & 0x3FF) << 10 | (arg->pbf_sigma_inv[6] & 0x3FF); - isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_SIGMA_INV_2); + isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_SIGMA_INV_2, id); value = (arg->bf_sigma_inv[2] & 0x3FF) << 20 | (arg->bf_sigma_inv[1] & 0x3FF) << 10 | (arg->bf_sigma_inv[0] & 0x3FF); - isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_SIGMA_INV_0); + isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_SIGMA_INV_0, id); value = (arg->bf_sigma_inv[5] & 0x3FF) << 20 | (arg->bf_sigma_inv[4] & 0x3FF) << 10 | (arg->bf_sigma_inv[3] & 0x3FF); - isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_SIGMA_INV_1); + isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_SIGMA_INV_1, id); value = (arg->bf_sigma_inv[7] & 0x3FF) << 10 | (arg->bf_sigma_inv[6] & 0x3FF); - isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_SIGMA_INV_2); + isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_SIGMA_INV_2, id); value = (arg->bf_sigma_shift & 0x0F) << 4 | (arg->pbf_sigma_shift & 0x0F); - isp3_param_write(params_vdev, value, ISP3X_SHARP_SIGMA_SHIFT); + isp3_param_write(params_vdev, value, ISP3X_SHARP_SIGMA_SHIFT, id); value = (arg->clip_hf[2] & 0x3FF) << 20 | (arg->clip_hf[1] & 0x3FF) << 10 | (arg->clip_hf[0] & 0x3FF); - isp3_param_write(params_vdev, value, ISP3X_SHARP_CLIP_HF_0); + isp3_param_write(params_vdev, value, ISP3X_SHARP_CLIP_HF_0, id); value = (arg->clip_hf[5] & 0x3FF) << 20 | (arg->clip_hf[4] & 0x3FF) << 10 | (arg->clip_hf[3] & 0x3FF); - isp3_param_write(params_vdev, value, ISP3X_SHARP_CLIP_HF_1); + isp3_param_write(params_vdev, value, ISP3X_SHARP_CLIP_HF_1, id); value = (arg->clip_hf[7] & 0x3FF) << 10 | (arg->clip_hf[6] & 0x3FF); - isp3_param_write(params_vdev, value, ISP3X_SHARP_CLIP_HF_2); + isp3_param_write(params_vdev, value, ISP3X_SHARP_CLIP_HF_2, id); value = ISP_PACK_4BYTE(arg->pbf_coef0, arg->pbf_coef1, arg->pbf_coef2, 0); - isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_COEF); + isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_COEF, id); value = ISP_PACK_4BYTE(arg->bf_coef0, arg->bf_coef1, arg->bf_coef2, 0); - isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_COEF); + isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_COEF, id); value = ISP_PACK_4BYTE(arg->gaus_coef[0], arg->gaus_coef[1], arg->gaus_coef[2], 0); - isp3_param_write(params_vdev, value, ISP3X_SHARP_GAUS_COEF0); + isp3_param_write(params_vdev, value, ISP3X_SHARP_GAUS_COEF0, id); value = ISP_PACK_4BYTE(arg->gaus_coef[3], arg->gaus_coef[4], arg->gaus_coef[5], 0); - isp3_param_write(params_vdev, value, ISP3X_SHARP_GAUS_COEF1); + isp3_param_write(params_vdev, value, ISP3X_SHARP_GAUS_COEF1, id); value = arg->local_gainscale << 24 | (arg->global_gain_alpha & 0xf) << 16 | (arg->global_gain & 0x3ff); - isp3_param_write(params_vdev, value, ISP32_SHARP_GAIN); + isp3_param_write(params_vdev, value, ISP32_SHARP_GAIN, id); for (i = 0; i < ISP32_SHARP_GAIN_ADJ_NUM / 2; i++) { value = ISP_PACK_2SHORT(arg->gain_adj[i * 2], arg->gain_adj[i * 2 + 1]); - isp3_param_write(params_vdev, value, ISP32_SHARP_GAIN_ADJUST0 + i * 4); + isp3_param_write(params_vdev, value, ISP32_SHARP_GAIN_ADJUST0 + i * 4, id); } value = ISP_PACK_2SHORT(arg->center_wid, arg->center_het); - isp3_param_write(params_vdev, value, ISP32_SHARP_CENTER); + isp3_param_write(params_vdev, value, ISP32_SHARP_CENTER, id); for (i = 0; i < ISP32_SHARP_STRENGTH_NUM / 4; i++) { value = ISP_PACK_4BYTE(arg->strength[i * 4], arg->strength[i * 4 + 1], arg->strength[i * 4 + 2], arg->strength[i * 4 + 3]); - isp3_param_write(params_vdev, value, ISP32_SHARP_GAIN_DIS_STRENGTH0 + i * 4); + isp3_param_write(params_vdev, value, ISP32_SHARP_GAIN_DIS_STRENGTH0 + i * 4, id); } value = ISP_PACK_4BYTE(arg->strength[i * 4], arg->strength[i * 4 + 1], 0, 0); - isp3_param_write(params_vdev, value, ISP32_SHARP_GAIN_DIS_STRENGTH0 + i * 4); + isp3_param_write(params_vdev, value, ISP32_SHARP_GAIN_DIS_STRENGTH0 + i * 4, id); if (params_vdev->dev->isp_ver == ISP_V32) { value = (arg->noise_strength & 0x3fff) << 16 | (arg->enhance_bit & 0xf) << 12 | (arg->noise_sigma & 0x3ff); - isp3_param_write(params_vdev, value, ISP32_SHARP_TEXTURE); + isp3_param_write(params_vdev, value, ISP32_SHARP_TEXTURE, id); } else { value = (arg->ehf_th[2] & 0x3FF) << 20 | (arg->ehf_th[1] & 0x3FF) << 10 | (arg->ehf_th[0] & 0x3FF); - isp3_param_write(params_vdev, value, ISP3X_SHARP_EHF_TH_0); + isp3_param_write(params_vdev, value, ISP3X_SHARP_EHF_TH_0, id); value = (arg->ehf_th[5] & 0x3FF) << 20 | (arg->ehf_th[4] & 0x3FF) << 10 | (arg->ehf_th[3] & 0x3FF); - isp3_param_write(params_vdev, value, ISP3X_SHARP_EHF_TH_1); + isp3_param_write(params_vdev, value, ISP3X_SHARP_EHF_TH_1, id); value = (arg->ehf_th[7] & 0x3FF) << 10 | (arg->ehf_th[6] & 0x3FF); - isp3_param_write(params_vdev, value, ISP3X_SHARP_EHF_TH_2); + isp3_param_write(params_vdev, value, ISP3X_SHARP_EHF_TH_2, id); value = (arg->clip_neg[2] & 0x3FF) << 20 | (arg->clip_neg[1] & 0x3FF) << 10 | (arg->clip_neg[0] & 0x3FF); - isp3_param_write(params_vdev, value, ISP32L_SHARP_CLIP_NEG_0); + isp3_param_write(params_vdev, value, ISP32L_SHARP_CLIP_NEG_0, id); value = (arg->clip_neg[5] & 0x3FF) << 20 | (arg->clip_neg[4] & 0x3FF) << 10 | (arg->clip_neg[3] & 0x3FF); - isp3_param_write(params_vdev, value, ISP32L_SHARP_CLIP_NEG_1); + isp3_param_write(params_vdev, value, ISP32L_SHARP_CLIP_NEG_1, id); value = (arg->clip_neg[7] & 0x3FF) << 10 | (arg->clip_neg[6] & 0x3FF); - isp3_param_write(params_vdev, value, ISP32L_SHARP_CLIP_NEG_2); + isp3_param_write(params_vdev, value, ISP32L_SHARP_CLIP_NEG_2, id); } } static void -isp_sharp_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_sharp_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { u32 value; - value = isp3_param_read_cache(params_vdev, ISP3X_SHARP_EN); + value = isp3_param_read_cache(params_vdev, ISP3X_SHARP_EN, id); if ((en && (value & ISP32_MODULE_EN)) || (!en && !(value & ISP32_MODULE_EN))) return; @@ -3366,98 +3444,98 @@ isp_sharp_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) value &= ~ISP32_MODULE_EN; if (en) { isp3_param_set_bits(params_vdev, - ISP3X_ISP_CTRL1, ISP32_SHP_FST_FRAME); + ISP3X_ISP_CTRL1, ISP32_SHP_FST_FRAME, id); value |= ISP32_MODULE_EN; } - isp3_param_write(params_vdev, value, ISP3X_SHARP_EN); + isp3_param_write(params_vdev, value, ISP3X_SHARP_EN, id); } static void isp_baynr_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_baynr_cfg *arg) + const struct isp32_baynr_cfg *arg, u32 id) { u32 i, value; - value = isp3_param_read(params_vdev, ISP3X_BAYNR_CTRL); + value = isp3_param_read(params_vdev, ISP3X_BAYNR_CTRL, id); value &= ISP32_MODULE_EN; value |= !!arg->bay3d_gain_en << 16 | (arg->lg2_mode & 0x3) << 12 | !!arg->gauss_en << 8 | !!arg->log_bypass << 4; - isp3_param_write(params_vdev, value, ISP3X_BAYNR_CTRL); + isp3_param_write(params_vdev, value, ISP3X_BAYNR_CTRL, id); value = ISP_PACK_2SHORT(arg->dgain0, arg->dgain1); - isp3_param_write(params_vdev, value, ISP3X_BAYNR_DGAIN0); + isp3_param_write(params_vdev, value, ISP3X_BAYNR_DGAIN0, id); - isp3_param_write(params_vdev, arg->dgain2, ISP3X_BAYNR_DGAIN1); - isp3_param_write(params_vdev, arg->pix_diff, ISP3X_BAYNR_PIXDIFF); + isp3_param_write(params_vdev, arg->dgain2, ISP3X_BAYNR_DGAIN1, id); + isp3_param_write(params_vdev, arg->pix_diff, ISP3X_BAYNR_PIXDIFF, id); value = ISP_PACK_2SHORT(arg->softthld, arg->diff_thld); - isp3_param_write(params_vdev, value, ISP3X_BAYNR_THLD); + isp3_param_write(params_vdev, value, ISP3X_BAYNR_THLD, id); value = ISP_PACK_2SHORT(arg->reg_w1, arg->bltflt_streng); - isp3_param_write(params_vdev, value, ISP3X_BAYNR_W1_STRENG); + isp3_param_write(params_vdev, value, ISP3X_BAYNR_W1_STRENG, id); for (i = 0; i < ISP32_BAYNR_XY_NUM / 2; i++) { value = ISP_PACK_2SHORT(arg->sigma_x[2 * i], arg->sigma_x[2 * i + 1]); - isp3_param_write(params_vdev, value, ISP3X_BAYNR_SIGMAX01 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_BAYNR_SIGMAX01 + 4 * i, id); } for (i = 0; i < ISP32_BAYNR_XY_NUM / 2; i++) { value = ISP_PACK_2SHORT(arg->sigma_y[2 * i], arg->sigma_y[2 * i + 1]); - isp3_param_write(params_vdev, value, ISP3X_BAYNR_SIGMAY01 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_BAYNR_SIGMAY01 + 4 * i, id); } value = (arg->weit_d2 & 0x3FF) << 20 | (arg->weit_d1 & 0x3FF) << 10 | (arg->weit_d0 & 0x3FF); - isp3_param_write(params_vdev, value, ISP3X_BAYNR_WRIT_D); + isp3_param_write(params_vdev, value, ISP3X_BAYNR_WRIT_D, id); value = ISP_PACK_2SHORT(arg->lg2_off, arg->lg2_lgoff); - isp3_param_write(params_vdev, value, ISP3X_BAYNR_LG_OFF); + isp3_param_write(params_vdev, value, ISP3X_BAYNR_LG_OFF, id); value = arg->dat_max & 0xfffff; - isp3_param_write(params_vdev, value, ISP3X_BAYNR_DAT_MAX); + isp3_param_write(params_vdev, value, ISP3X_BAYNR_DAT_MAX, id); value = ISP_PACK_2SHORT(arg->rgain_off, arg->bgain_off); - isp3_param_write(params_vdev, value, ISP32_BAYNR_SIGOFF); + isp3_param_write(params_vdev, value, ISP32_BAYNR_SIGOFF, id); for (i = 0; i < ISP32_BAYNR_GAIN_NUM / 4; i++) { value = ISP_PACK_4BYTE(arg->gain_x[i * 4], arg->gain_x[i * 4 + 1], arg->gain_x[i * 4 + 2], arg->gain_x[i * 4 + 3]); - isp3_param_write(params_vdev, value, ISP32_BAYNR_GAINX03 + i * 4); + isp3_param_write(params_vdev, value, ISP32_BAYNR_GAINX03 + i * 4, id); } for (i = 0; i < ISP32_BAYNR_GAIN_NUM / 2; i++) { value = ISP_PACK_2SHORT(arg->gain_y[i * 2], arg->gain_y[i * 2 + 1]); - isp3_param_write(params_vdev, value, ISP32_BAYNR_GAINY01 + i * 4); + isp3_param_write(params_vdev, value, ISP32_BAYNR_GAINY01 + i * 4, id); } } static void -isp_baynr_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_baynr_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { u32 value; - value = isp3_param_read_cache(params_vdev, ISP3X_BAYNR_CTRL); + value = isp3_param_read_cache(params_vdev, ISP3X_BAYNR_CTRL, id); value &= ~ISP32_MODULE_EN; if (en) value |= ISP32_MODULE_EN; - isp3_param_write(params_vdev, value, ISP3X_BAYNR_CTRL); + isp3_param_write(params_vdev, value, ISP3X_BAYNR_CTRL, id); } static void isp_bay3d_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_bay3d_cfg *arg) + const struct isp32_bay3d_cfg *arg, u32 id) { struct rkisp_isp_params_val_v32 *priv_val; u32 i, value; priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; - value = isp3_param_read(params_vdev, ISP3X_BAY3D_CTRL); + value = isp3_param_read(params_vdev, ISP3X_BAY3D_CTRL, id); value &= (ISP32_MODULE_EN | ISP32_BAY3D_BWSAVING(1)); value |= !!arg->loswitch_protect << 12 | @@ -3483,7 +3561,7 @@ isp_bay3d_config(struct rkisp_isp_params_vdev *params_vdev, "bwsaving to %d no support change for bay3d en\n", arg->bwsaving_en); } - isp3_param_write(params_vdev, value, ISP3X_BAY3D_CTRL); + isp3_param_write(params_vdev, value, ISP3X_BAY3D_CTRL, id); value = !!arg->wgtmix_opt_en << 12 | !!arg->curds_high_en << 8 | @@ -3505,72 +3583,72 @@ isp_bay3d_config(struct rkisp_isp_params_vdev *params_vdev, value &= ~(BIT(3) | BIT(4)); else if (!(value & (BIT(3) | BIT(4)))) value |= BIT(3); - isp3_param_write(params_vdev, value, ISP32_BAY3D_CTRL1); + isp3_param_write(params_vdev, value, ISP32_BAY3D_CTRL1, id); value = ISP_PACK_2SHORT(arg->softwgt, arg->hidif_th); - isp3_param_write(params_vdev, value, ISP3X_BAY3D_KALRATIO); + isp3_param_write(params_vdev, value, ISP3X_BAY3D_KALRATIO, id); - isp3_param_write(params_vdev, arg->glbpk2, ISP3X_BAY3D_GLBPK2); + isp3_param_write(params_vdev, arg->glbpk2, ISP3X_BAY3D_GLBPK2, id); value = ISP_PACK_2SHORT(arg->wgtlmt, arg->wgtratio); - isp3_param_write(params_vdev, value, ISP3X_BAY3D_WGTLMT); + isp3_param_write(params_vdev, value, ISP3X_BAY3D_WGTLMT, id); for (i = 0; i < ISP32_BAY3D_XY_NUM / 2; i++) { value = ISP_PACK_2SHORT(arg->sig0_x[2 * i], arg->sig0_x[2 * i + 1]); - isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG0_X0 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG0_X0 + 4 * i, id); value = ISP_PACK_2SHORT(arg->sig1_x[2 * i], arg->sig1_x[2 * i + 1]); - isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG1_X0 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG1_X0 + 4 * i, id); } for (i = 0; i < ISP32_BAY3D_XY_NUM / 2; i++) { value = ISP_PACK_2SHORT(arg->sig0_y[2 * i], arg->sig0_y[2 * i + 1]); - isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG0_Y0 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG0_Y0 + 4 * i, id); value = ISP_PACK_2SHORT(arg->sig1_y[2 * i], arg->sig1_y[2 * i + 1]); - isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG1_Y0 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG1_Y0 + 4 * i, id); value = ISP_PACK_2SHORT(arg->sig2_y[2 * i], arg->sig2_y[2 * i + 1]); - isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG2_Y0 + 4 * i); + isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG2_Y0 + 4 * i, id); } if (params_vdev->dev->isp_ver == ISP_V32_L) { value = ISP_PACK_2SHORT(0, arg->wgtmin); - isp3_param_write(params_vdev, value, ISP3X_BAY3D_LODIF_STAT1); + isp3_param_write(params_vdev, value, ISP3X_BAY3D_LODIF_STAT1, id); } value = ISP_PACK_2SHORT(arg->hisigrat0, arg->hisigrat1); - isp3_param_write(params_vdev, value, ISP32_BAY3D_HISIGRAT); + isp3_param_write(params_vdev, value, ISP32_BAY3D_HISIGRAT, id); value = ISP_PACK_2SHORT(arg->hisigoff0, arg->hisigoff1); - isp3_param_write(params_vdev, value, ISP32_BAY3D_HISIGOFF); + isp3_param_write(params_vdev, value, ISP32_BAY3D_HISIGOFF, id); value = ISP_PACK_2SHORT(arg->losigoff, arg->losigrat); - isp3_param_write(params_vdev, value, ISP32_BAY3D_LOSIG); + isp3_param_write(params_vdev, value, ISP32_BAY3D_LOSIG, id); value = ISP_PACK_2SHORT(arg->rgain_off, arg->bgain_off); - isp3_param_write(params_vdev, value, ISP32_BAY3D_SIGPK); + isp3_param_write(params_vdev, value, ISP32_BAY3D_SIGPK, id); value = ISP_PACK_4BYTE(arg->siggaus0, arg->siggaus1, arg->siggaus2, 0); if (params_vdev->dev->isp_ver == ISP_V32) value |= (arg->siggaus3 << 24); - isp3_param_write(params_vdev, value, ISP32_BAY3D_SIGGAUS); + isp3_param_write(params_vdev, value, ISP32_BAY3D_SIGGAUS, id); } static void -isp_bay3d_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_bay3d_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { struct rkisp_device *ispdev = params_vdev->dev; struct rkisp_isp_params_val_v32 *priv_val; u32 value, bay3d_ctrl; priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; - bay3d_ctrl = isp3_param_read_cache(params_vdev, ISP3X_BAY3D_CTRL); + bay3d_ctrl = isp3_param_read_cache(params_vdev, ISP3X_BAY3D_CTRL, id); if ((en && (bay3d_ctrl & ISP32_MODULE_EN)) || (!en && !(bay3d_ctrl & ISP32_MODULE_EN))) return; @@ -3581,85 +3659,85 @@ isp_bay3d_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) return; } - value = priv_val->buf_3dnr_iir.size; - isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_WR_SIZE); - value = priv_val->buf_3dnr_iir.dma_addr; - isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_WR_BASE); - isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_RD_BASE); + value = priv_val->bay3d_iir_size; + isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_WR_SIZE, id); + value = priv_val->buf_3dnr_iir.dma_addr + value * id; + isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_WR_BASE, id); + isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_RD_BASE, id); - value = priv_val->buf_3dnr_ds.size; - isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_DS_WR_SIZE); - value = priv_val->buf_3dnr_ds.dma_addr; - isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_DS_WR_BASE); - isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_DS_RD_BASE); + value = priv_val->bay3d_ds_size; + isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_DS_WR_SIZE, id); + value = priv_val->buf_3dnr_ds.dma_addr + value * id; + isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_DS_WR_BASE, id); + isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_DS_RD_BASE, id); value = priv_val->is_sram ? ispdev->hw_dev->sram.dma_addr : priv_val->buf_3dnr_cur.dma_addr; - isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_WR_BASE); - isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_RD_BASE); + isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_WR_BASE, id); + isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_RD_BASE, id); value = priv_val->bay3d_cur_size; - isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_WR_SIZE); - isp3_param_write(params_vdev, value, ISP32_MI_BAY3D_CUR_RD_SIZE); + isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_WR_SIZE, id); + isp3_param_write(params_vdev, value, ISP32_MI_BAY3D_CUR_RD_SIZE, id); value = priv_val->bay3d_cur_wsize; - isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_WR_LENGTH); - isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_RD_LENGTH); + isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_WR_LENGTH, id); + isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_RD_LENGTH, id); value = priv_val->bay3d_cur_wrap_line << 16 | (ispdev->isp_ver == ISP_V32 ? 28 : 20); - isp3_param_write(params_vdev, value, ISP3X_BAY3D_MI_ST); + isp3_param_write(params_vdev, value, ISP3X_BAY3D_MI_ST, id); /* mibuf_size for fifo_cur_full, set to max: (3072 - 2) / 2, 2 align */ if (ispdev->isp_ver == ISP_V32) { value = 0x5fe << 16; - isp3_param_set_bits(params_vdev, ISP3X_BAY3D_IN_IRQ_LINECNT, value); + isp3_param_set_bits(params_vdev, ISP3X_BAY3D_IN_IRQ_LINECNT, value, id); } - value = isp3_param_read_cache(params_vdev, ISP32_BAY3D_CTRL1); + value = isp3_param_read_cache(params_vdev, ISP32_BAY3D_CTRL1, id); if (priv_val->is_lo8x8) { if (value & (BIT(3) | BIT(4))) { value &= ~(BIT(3) | BIT(4)); - isp3_param_write(params_vdev, value, ISP32_BAY3D_CTRL1); + isp3_param_write(params_vdev, value, ISP32_BAY3D_CTRL1, id); } } else if (!(value & (BIT(3) | BIT(4)))) { value |= BIT(3); - isp3_param_write(params_vdev, value, ISP32_BAY3D_CTRL1); + isp3_param_write(params_vdev, value, ISP32_BAY3D_CTRL1, id); } bay3d_ctrl |= ISP32_MODULE_EN; - isp3_param_write(params_vdev, bay3d_ctrl, ISP3X_BAY3D_CTRL); + isp3_param_write(params_vdev, bay3d_ctrl, ISP3X_BAY3D_CTRL, id); value = ISP3X_BAY3D_IIR_WR_AUTO_UPD | ISP3X_BAY3D_CUR_WR_AUTO_UPD | ISP3X_BAY3D_DS_WR_AUTO_UPD | ISP3X_BAY3D_IIRSELF_UPD | ISP3X_BAY3D_CURSELF_UPD | ISP3X_BAY3D_DSSELF_UPD | ISP3X_BAY3D_RDSELF_UPD; - isp3_param_set_bits(params_vdev, MI_WR_CTRL2, value); + isp3_param_set_bits(params_vdev, MI_WR_CTRL2, value, id); - isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1, ISP3X_RAW3D_FST_FRAME); + isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1, ISP3X_RAW3D_FST_FRAME, id); } else { bay3d_ctrl &= ~ISP32_MODULE_EN; - isp3_param_write(params_vdev, bay3d_ctrl, ISP3X_BAY3D_CTRL); - isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(4)); + isp3_param_write(params_vdev, bay3d_ctrl, ISP3X_BAY3D_CTRL, id); + isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(4), id); } } static void isp_gain_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp3x_gain_cfg *arg) + const struct isp3x_gain_cfg *arg, u32 id) { u32 val; val = arg->g0 & 0x3ffff; - isp3_param_write(params_vdev, val, ISP3X_GAIN_G0); + isp3_param_write(params_vdev, val, ISP3X_GAIN_G0, id); val = ISP_PACK_2SHORT(arg->g1, arg->g2); - isp3_param_write(params_vdev, val, ISP3X_GAIN_G1_G2); + isp3_param_write(params_vdev, val, ISP3X_GAIN_G1_G2, id); } static void -isp_gain_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_gain_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { struct rkisp_isp_params_val_v32 *priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; u32 val = 0; - val = isp3_param_read_cache(params_vdev, ISP3X_GAIN_CTRL); + val = isp3_param_read_cache(params_vdev, ISP3X_GAIN_CTRL, id); if (en) { if (params_vdev->dev->isp_ver == ISP_V32) { val |= priv_val->lut3d_en << 20 | @@ -3667,7 +3745,7 @@ isp_gain_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) priv_val->drc_en << 12 | priv_val->lsc_en << 8 | priv_val->bay3d_en << 4; - if (isp3_param_read(params_vdev, ISP3X_HDRMGE_CTRL) & BIT(0)) + if (isp3_param_read(params_vdev, ISP3X_HDRMGE_CTRL, id) & BIT(0)) val |= BIT(1); if (val) val |= ISP32_MODULE_EN; @@ -3675,12 +3753,12 @@ isp_gain_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) val |= ISP32_MODULE_EN; } } - isp3_param_write(params_vdev, val, ISP3X_GAIN_CTRL); + isp3_param_write(params_vdev, val, ISP3X_GAIN_CTRL, id); } static void isp_cac_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_cac_cfg *arg) + const struct isp32_cac_cfg *arg, u32 id) { struct rkisp_device *dev = params_vdev->dev; struct rkisp_isp_params_val_v32 *priv_val; @@ -3689,7 +3767,7 @@ isp_cac_config(struct rkisp_isp_params_vdev *params_vdev, priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; - ctrl = isp3_param_read(params_vdev, ISP3X_CAC_CTRL); + ctrl = isp3_param_read(params_vdev, ISP3X_CAC_CTRL, id); ctrl &= ISP3X_CAC_EN; ctrl |= !!arg->bypass_en << 1 | !!arg->center_en << 3 | (arg->clip_g_mode & 0x3) << 5 | !!arg->edge_detect_en << 7 | @@ -3697,38 +3775,38 @@ isp_cac_config(struct rkisp_isp_params_vdev *params_vdev, val = (arg->psf_sft_bit & 0xff) | (arg->cfg_num & 0x7ff) << 8; - isp3_param_write(params_vdev, val, ISP3X_CAC_PSF_PARA); + isp3_param_write(params_vdev, val, ISP3X_CAC_PSF_PARA, id); val = ISP_PACK_2SHORT(arg->center_width, arg->center_height); - isp3_param_write(params_vdev, val, ISP3X_CAC_STRENGTH_CENTER); + isp3_param_write(params_vdev, val, ISP3X_CAC_STRENGTH_CENTER, id); for (i = 0; i < ISP32_CAC_STRENGTH_NUM / 2; i++) { val = ISP_PACK_2SHORT(arg->strength[2 * i], arg->strength[2 * i + 1]); - isp3_param_write(params_vdev, val, ISP3X_CAC_STRENGTH0 + i * 4); + isp3_param_write(params_vdev, val, ISP3X_CAC_STRENGTH0 + i * 4, id); } val = (arg->flat_thed_r & 0x1f) << 8 | (arg->flat_thed_b & 0x1f); - isp3_param_write(params_vdev, val, ISP32_CAC_FLAT_THED); + isp3_param_write(params_vdev, val, ISP32_CAC_FLAT_THED, id); val = ISP_PACK_2SHORT(arg->offset_b, arg->offset_r); - isp3_param_write(params_vdev, val, ISP32_CAC_OFFSET); + isp3_param_write(params_vdev, val, ISP32_CAC_OFFSET, id); val = arg->expo_thed_b & 0x1fffff; - isp3_param_write(params_vdev, val, ISP32_CAC_EXPO_THED_B); + isp3_param_write(params_vdev, val, ISP32_CAC_EXPO_THED_B, id); val = arg->expo_thed_r & 0x1fffff; - isp3_param_write(params_vdev, val, ISP32_CAC_EXPO_THED_R); + isp3_param_write(params_vdev, val, ISP32_CAC_EXPO_THED_R, id); val = arg->expo_adj_b & 0xfffff; - isp3_param_write(params_vdev, val, ISP32_CAC_EXPO_ADJ_B); + isp3_param_write(params_vdev, val, ISP32_CAC_EXPO_ADJ_B, id); val = arg->expo_adj_r & 0xfffff; - isp3_param_write(params_vdev, val, ISP32_CAC_EXPO_ADJ_R); + isp3_param_write(params_vdev, val, ISP32_CAC_EXPO_ADJ_R, id); for (i = 0; i < ISP32_MESH_BUF_NUM; i++) { - if (!priv_val->buf_cac[i].mem_priv) + if (!priv_val->buf_cac[id][i].mem_priv) continue; - if (arg->buf_fd == priv_val->buf_cac[i].dma_fd) + if (arg->buf_fd == priv_val->buf_cac[id][i].dma_fd) break; } @@ -3737,44 +3815,53 @@ isp_cac_config(struct rkisp_isp_params_vdev *params_vdev, return; } - if (!priv_val->buf_cac[i].vaddr) { + if (!priv_val->buf_cac[id][i].vaddr) { dev_err(dev->dev, "no cac buffer allocated\n"); return; } - val = priv_val->buf_cac_idx; - head = (struct isp2x_mesh_head *)priv_val->buf_cac[val].vaddr; + val = priv_val->buf_cac_idx[id]; + head = (struct isp2x_mesh_head *)priv_val->buf_cac[id][val].vaddr; head->stat = MESH_BUF_INIT; - head = (struct isp2x_mesh_head *)priv_val->buf_cac[i].vaddr; + head = (struct isp2x_mesh_head *)priv_val->buf_cac[id][i].vaddr; head->stat = MESH_BUF_CHIPINUSE; - priv_val->buf_cac_idx = i; - rkisp_prepare_buffer(dev, &priv_val->buf_cac[i]); - val = priv_val->buf_cac[i].dma_addr + head->data_oft; - isp3_param_write(params_vdev, val, ISP3X_MI_LUT_CAC_RD_BASE); - isp3_param_write(params_vdev, arg->hsize, ISP3X_MI_LUT_CAC_RD_H_WSIZE); - isp3_param_write(params_vdev, arg->vsize, ISP3X_MI_LUT_CAC_RD_V_SIZE); + priv_val->buf_cac_idx[id] = i; + rkisp_prepare_buffer(dev, &priv_val->buf_cac[id][i]); + val = priv_val->buf_cac[id][i].dma_addr + head->data_oft; + isp3_param_write(params_vdev, val, ISP3X_MI_LUT_CAC_RD_BASE, id); + isp3_param_write(params_vdev, arg->hsize, ISP3X_MI_LUT_CAC_RD_H_WSIZE, id); + isp3_param_write(params_vdev, arg->vsize, ISP3X_MI_LUT_CAC_RD_V_SIZE, id); if (ctrl & ISP3X_CAC_EN) ctrl |= ISP3X_CAC_LUT_EN | ISP32_SELF_FORCE_UPD | ISP3X_CAC_LUT_MODE(3); - isp3_param_write(params_vdev, ctrl, ISP3X_CAC_CTRL); + isp3_param_write(params_vdev, ctrl, ISP3X_CAC_CTRL, id); } static void -isp_cac_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_cac_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id) { + struct rkisp_device *dev = params_vdev->dev; + struct rkisp_isp_params_val_v32 *priv_val; u32 val; - val = isp3_param_read(params_vdev, ISP3X_CAC_CTRL); + priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; + val = priv_val->buf_cac_idx[id]; + if (en && !priv_val->buf_cac[id][val].vaddr) { + dev_err(dev->dev, "no cac buffer allocated\n"); + return; + } + + val = isp3_param_read(params_vdev, ISP3X_CAC_CTRL, id); val &= ~(ISP3X_CAC_EN | ISP3X_CAC_LUT_EN | ISP32_SELF_FORCE_UPD); if (en) val |= ISP3X_CAC_EN | ISP3X_CAC_LUT_EN | ISP32_SELF_FORCE_UPD | ISP3X_CAC_LUT_MODE(3); - isp3_param_write(params_vdev, val, ISP3X_CAC_CTRL); + isp3_param_write(params_vdev, val, ISP3X_CAC_CTRL, id); } static void isp_csm_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp21_csm_cfg *arg) + const struct isp21_csm_cfg *arg, u32 id) { u32 i, val; @@ -3785,19 +3872,19 @@ isp_csm_config(struct rkisp_isp_params_vdev *params_vdev, (arg->csm_coeff[i] & 0x1ff); else val = arg->csm_coeff[i] & 0x1ff; - isp3_param_write(params_vdev, val, ISP3X_ISP_CC_COEFF_0 + i * 4); + isp3_param_write(params_vdev, val, ISP3X_ISP_CC_COEFF_0 + i * 4, id); } - val = isp3_param_read_cache(params_vdev, ISP3X_ISP_CTRL0); + val = isp3_param_read_cache(params_vdev, ISP3X_ISP_CTRL0, id); val |= CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA | CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA; - isp3_param_write(params_vdev, val, ISP3X_ISP_CTRL0); + isp3_param_write(params_vdev, val, ISP3X_ISP_CTRL0, id); } static void isp_cgc_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp21_cgc_cfg *arg) + const struct isp21_cgc_cfg *arg, u32 id) { - u32 val = isp3_param_read_cache(params_vdev, ISP3X_ISP_CTRL0); + u32 val = isp3_param_read_cache(params_vdev, ISP3X_ISP_CTRL0, id); u32 eff_ctrl, cproc_ctrl; params_vdev->quantization = V4L2_QUANTIZATION_FULL_RANGE; @@ -3808,31 +3895,31 @@ isp_cgc_config(struct rkisp_isp_params_vdev *params_vdev, } if (arg->ratio_en) val |= ISP3X_SW_CGC_RATIO_EN; - isp3_param_write(params_vdev, val, ISP3X_ISP_CTRL0); + isp3_param_write(params_vdev, val, ISP3X_ISP_CTRL0, id); - cproc_ctrl = isp3_param_read(params_vdev, ISP3X_CPROC_CTRL); + cproc_ctrl = isp3_param_read(params_vdev, ISP3X_CPROC_CTRL, id); if (cproc_ctrl & CIF_C_PROC_CTR_ENABLE) { val = CIF_C_PROC_YOUT_FULL | CIF_C_PROC_YIN_FULL | CIF_C_PROC_COUT_FULL; if (arg->yuv_limit) cproc_ctrl &= ~val; else cproc_ctrl |= val; - isp3_param_write(params_vdev, cproc_ctrl, ISP3X_CPROC_CTRL); + isp3_param_write(params_vdev, cproc_ctrl, ISP3X_CPROC_CTRL, id); } - eff_ctrl = isp3_param_read(params_vdev, ISP3X_IMG_EFF_CTRL); + eff_ctrl = isp3_param_read(params_vdev, ISP3X_IMG_EFF_CTRL, id); if (eff_ctrl & CIF_IMG_EFF_CTRL_ENABLE) { if (arg->yuv_limit) eff_ctrl &= ~CIF_IMG_EFF_CTRL_YCBCR_FULL; else eff_ctrl |= CIF_IMG_EFF_CTRL_YCBCR_FULL; - isp3_param_write(params_vdev, eff_ctrl, ISP3X_IMG_EFF_CTRL); + isp3_param_write(params_vdev, eff_ctrl, ISP3X_IMG_EFF_CTRL, id); } } static void isp_vsm_config(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_vsm_cfg *arg) + const struct isp32_vsm_cfg *arg, u32 id) { struct rkisp_device *ispdev = params_vdev->dev; struct v4l2_rect *out_crop = &ispdev->isp_sdev.out_crop; @@ -3841,38 +3928,38 @@ isp_vsm_config(struct rkisp_isp_params_vdev *params_vdev, u32 val, h, v; val = arg->h_offs; - isp3_param_write(params_vdev, val, ISP32_VSM_H_OFFS); + isp3_param_write(params_vdev, val, ISP32_VSM_H_OFFS, id); val = arg->v_offs; - isp3_param_write(params_vdev, val, ISP32_VSM_V_OFFS); + isp3_param_write(params_vdev, val, ISP32_VSM_V_OFFS, id); h = arg->h_size; if (h > width - arg->h_offs) h = width - arg->h_offs; h &= ~1; - isp3_param_write(params_vdev, h, ISP32_VSM_H_SIZE); + isp3_param_write(params_vdev, h, ISP32_VSM_H_SIZE, id); v = arg->v_size; if (v > height - arg->v_offs) v = height - arg->v_offs; v &= ~1; - isp3_param_write(params_vdev, v, ISP32_VSM_V_SIZE); + isp3_param_write(params_vdev, v, ISP32_VSM_V_SIZE, id); val = arg->h_segments; if (val > (h - 48) / 16) val = (h - 48) / 16; - isp3_param_write(params_vdev, val, ISP32_VSM_H_SEGMENTS); + isp3_param_write(params_vdev, val, ISP32_VSM_H_SEGMENTS, id); val = arg->v_segments; if (val > (v - 48) / 16) val = (v - 48) / 16; - isp3_param_write(params_vdev, val, ISP32_VSM_V_SEGMENTS); + isp3_param_write(params_vdev, val, ISP32_VSM_V_SEGMENTS, id); } static void isp_vsm_enable(struct rkisp_isp_params_vdev *params_vdev, - bool en) + bool en, u32 id) { - isp3_param_write(params_vdev, en, ISP32_VSM_MODE); + isp3_param_write(params_vdev, en, ISP32_VSM_MODE, id); } struct rkisp_isp_params_ops_v32 isp_params_ops_v32 = { @@ -3951,7 +4038,7 @@ struct rkisp_isp_params_ops_v32 isp_params_ops_v32 = { static __maybe_unused void __isp_isr_other_config(struct rkisp_isp_params_vdev *params_vdev, const struct isp32_isp_params_cfg *new_params, - enum rkisp_params_type type) + enum rkisp_params_type type, u32 id) { struct rkisp_isp_params_ops_v32 *ops = (struct rkisp_isp_params_ops_v32 *)params_vdev->priv_ops; @@ -3963,101 +4050,101 @@ void __isp_isr_other_config(struct rkisp_isp_params_vdev *params_vdev, if (type == RKISP_PARAMS_SHD) { if ((module_cfg_update & ISP32_MODULE_HDRMGE)) - ops->hdrmge_config(params_vdev, &new_params->others.hdrmge_cfg, type); + ops->hdrmge_config(params_vdev, &new_params->others.hdrmge_cfg, type, id); if ((module_cfg_update & ISP32_MODULE_DRC)) - ops->hdrdrc_config(params_vdev, &new_params->others.drc_cfg, type); + ops->hdrdrc_config(params_vdev, &new_params->others.drc_cfg, type, id); return; } v4l2_dbg(4, rkisp_debug, ¶ms_vdev->dev->v4l2_dev, - "%s seq:%d module_cfg_update:0x%llx\n", - __func__, new_params->frame_id, module_cfg_update); + "%s id:%d seq:%d module_cfg_update:0x%llx\n", + __func__, id, new_params->frame_id, module_cfg_update); if (module_cfg_update & ISP32_MODULE_LSC) - ops->lsc_config(params_vdev, &new_params->others.lsc_cfg); + ops->lsc_config(params_vdev, &new_params->others.lsc_cfg, id); if (module_cfg_update & ISP32_MODULE_DPCC) - ops->dpcc_config(params_vdev, &new_params->others.dpcc_cfg); + ops->dpcc_config(params_vdev, &new_params->others.dpcc_cfg, id); if (module_cfg_update & ISP32_MODULE_BLS) - ops->bls_config(params_vdev, &new_params->others.bls_cfg); + ops->bls_config(params_vdev, &new_params->others.bls_cfg, id); if (module_cfg_update & ISP32_MODULE_SDG) - ops->sdg_config(params_vdev, &new_params->others.sdg_cfg); + ops->sdg_config(params_vdev, &new_params->others.sdg_cfg, id); if (module_cfg_update & ISP32_MODULE_AWB_GAIN) - ops->awbgain_config(params_vdev, &new_params->others.awb_gain_cfg); + ops->awbgain_config(params_vdev, &new_params->others.awb_gain_cfg, id); if (module_cfg_update & ISP32_MODULE_DEBAYER) - ops->debayer_config(params_vdev, &new_params->others.debayer_cfg); + ops->debayer_config(params_vdev, &new_params->others.debayer_cfg, id); if (module_cfg_update & ISP32_MODULE_CCM) - ops->ccm_config(params_vdev, &new_params->others.ccm_cfg); + ops->ccm_config(params_vdev, &new_params->others.ccm_cfg, id); if (module_cfg_update & ISP32_MODULE_GOC) - ops->goc_config(params_vdev, &new_params->others.gammaout_cfg); + ops->goc_config(params_vdev, &new_params->others.gammaout_cfg, id); /* range csm->cgc->cproc->ie */ if (module_cfg_update & ISP3X_MODULE_CSM) - ops->csm_config(params_vdev, &new_params->others.csm_cfg); + ops->csm_config(params_vdev, &new_params->others.csm_cfg, id); if (module_cfg_update & ISP3X_MODULE_CGC) - ops->cgc_config(params_vdev, &new_params->others.cgc_cfg); + ops->cgc_config(params_vdev, &new_params->others.cgc_cfg, id); if (module_cfg_update & ISP32_MODULE_CPROC) - ops->cproc_config(params_vdev, &new_params->others.cproc_cfg); + ops->cproc_config(params_vdev, &new_params->others.cproc_cfg, id); if (module_cfg_update & ISP32_MODULE_IE) - ops->ie_config(params_vdev, &new_params->others.ie_cfg); + ops->ie_config(params_vdev, &new_params->others.ie_cfg, id); if (module_cfg_update & ISP32_MODULE_HDRMGE) - ops->hdrmge_config(params_vdev, &new_params->others.hdrmge_cfg, type); + ops->hdrmge_config(params_vdev, &new_params->others.hdrmge_cfg, type, id); if (module_cfg_update & ISP32_MODULE_DRC) - ops->hdrdrc_config(params_vdev, &new_params->others.drc_cfg, type); + ops->hdrdrc_config(params_vdev, &new_params->others.drc_cfg, type, id); if (module_cfg_update & ISP32_MODULE_GIC) - ops->gic_config(params_vdev, &new_params->others.gic_cfg); + ops->gic_config(params_vdev, &new_params->others.gic_cfg, id); if (module_cfg_update & ISP32_MODULE_DHAZ) - ops->dhaz_config(params_vdev, &new_params->others.dhaz_cfg); + ops->dhaz_config(params_vdev, &new_params->others.dhaz_cfg, id); if (module_cfg_update & ISP32_MODULE_3DLUT) - ops->isp3dlut_config(params_vdev, &new_params->others.isp3dlut_cfg); + ops->isp3dlut_config(params_vdev, &new_params->others.isp3dlut_cfg, id); if (module_cfg_update & ISP32_MODULE_LDCH) - ops->ldch_config(params_vdev, &new_params->others.ldch_cfg); + ops->ldch_config(params_vdev, &new_params->others.ldch_cfg, id); if (module_cfg_update & ISP32_MODULE_YNR) - ops->ynr_config(params_vdev, &new_params->others.ynr_cfg); + ops->ynr_config(params_vdev, &new_params->others.ynr_cfg, id); if (module_cfg_update & ISP32_MODULE_CNR) - ops->cnr_config(params_vdev, &new_params->others.cnr_cfg); + ops->cnr_config(params_vdev, &new_params->others.cnr_cfg, id); if (module_cfg_update & ISP32_MODULE_SHARP) - ops->sharp_config(params_vdev, &new_params->others.sharp_cfg); + ops->sharp_config(params_vdev, &new_params->others.sharp_cfg, id); if (module_cfg_update & ISP32_MODULE_BAYNR) - ops->baynr_config(params_vdev, &new_params->others.baynr_cfg); + ops->baynr_config(params_vdev, &new_params->others.baynr_cfg, id); if (module_cfg_update & ISP32_MODULE_BAY3D) - ops->bay3d_config(params_vdev, &new_params->others.bay3d_cfg); + ops->bay3d_config(params_vdev, &new_params->others.bay3d_cfg, id); if (module_cfg_update & ISP32_MODULE_CAC) - ops->cac_config(params_vdev, &new_params->others.cac_cfg); + ops->cac_config(params_vdev, &new_params->others.cac_cfg, id); if (module_cfg_update & ISP32_MODULE_GAIN) - ops->gain_config(params_vdev, &new_params->others.gain_cfg); + ops->gain_config(params_vdev, &new_params->others.gain_cfg, id); if (module_cfg_update & ISP32_MODULE_VSM) - ops->vsm_config(params_vdev, &new_params->others.vsm_cfg); + ops->vsm_config(params_vdev, &new_params->others.vsm_cfg, id); } static __maybe_unused void __isp_isr_other_en(struct rkisp_isp_params_vdev *params_vdev, const struct isp32_isp_params_cfg *new_params, - enum rkisp_params_type type) + enum rkisp_params_type type, u32 id) { struct rkisp_isp_params_ops_v32 *ops = (struct rkisp_isp_params_ops_v32 *)params_vdev->priv_ops; @@ -4075,110 +4162,110 @@ void __isp_isr_other_en(struct rkisp_isp_params_vdev *params_vdev, return; v4l2_dbg(4, rkisp_debug, ¶ms_vdev->dev->v4l2_dev, - "%s seq:%d module_en_update:0x%llx module_ens:0x%llx\n", - __func__, new_params->frame_id, module_en_update, module_ens); + "%s id:%d seq:%d module_en_update:0x%llx module_ens:0x%llx\n", + __func__, id, new_params->frame_id, module_en_update, module_ens); if (module_en_update & ISP32_MODULE_DPCC) - ops->dpcc_enable(params_vdev, !!(module_ens & ISP32_MODULE_DPCC)); + ops->dpcc_enable(params_vdev, !!(module_ens & ISP32_MODULE_DPCC), id); if (module_en_update & ISP32_MODULE_BLS) - ops->bls_enable(params_vdev, !!(module_ens & ISP32_MODULE_BLS)); + ops->bls_enable(params_vdev, !!(module_ens & ISP32_MODULE_BLS), id); if (module_en_update & ISP32_MODULE_SDG) - ops->sdg_enable(params_vdev, !!(module_ens & ISP32_MODULE_SDG)); + ops->sdg_enable(params_vdev, !!(module_ens & ISP32_MODULE_SDG), id); if (module_en_update & ISP32_MODULE_LSC) { - ops->lsc_enable(params_vdev, !!(module_ens & ISP32_MODULE_LSC)); + ops->lsc_enable(params_vdev, !!(module_ens & ISP32_MODULE_LSC), id); priv_val->lsc_en = !!(module_ens & ISP32_MODULE_LSC); } if (module_en_update & ISP32_MODULE_AWB_GAIN) - ops->awbgain_enable(params_vdev, !!(module_ens & ISP32_MODULE_AWB_GAIN)); + ops->awbgain_enable(params_vdev, !!(module_ens & ISP32_MODULE_AWB_GAIN), id); if (module_en_update & ISP32_MODULE_DEBAYER) - ops->debayer_enable(params_vdev, !!(module_ens & ISP32_MODULE_DEBAYER)); + ops->debayer_enable(params_vdev, !!(module_ens & ISP32_MODULE_DEBAYER), id); if (module_en_update & ISP32_MODULE_CCM) - ops->ccm_enable(params_vdev, !!(module_ens & ISP32_MODULE_CCM)); + ops->ccm_enable(params_vdev, !!(module_ens & ISP32_MODULE_CCM), id); if (module_en_update & ISP32_MODULE_GOC) - ops->goc_enable(params_vdev, !!(module_ens & ISP32_MODULE_GOC)); + ops->goc_enable(params_vdev, !!(module_ens & ISP32_MODULE_GOC), id); if (module_en_update & ISP32_MODULE_CPROC) - ops->cproc_enable(params_vdev, !!(module_ens & ISP32_MODULE_CPROC)); + ops->cproc_enable(params_vdev, !!(module_ens & ISP32_MODULE_CPROC), id); if (module_en_update & ISP32_MODULE_IE) - ops->ie_enable(params_vdev, !!(module_ens & ISP32_MODULE_IE)); + ops->ie_enable(params_vdev, !!(module_ens & ISP32_MODULE_IE), id); if (module_en_update & ISP32_MODULE_HDRMGE) { - ops->hdrmge_enable(params_vdev, !!(module_ens & ISP32_MODULE_HDRMGE)); + ops->hdrmge_enable(params_vdev, !!(module_ens & ISP32_MODULE_HDRMGE), id); priv_val->mge_en = !!(module_ens & ISP32_MODULE_HDRMGE); } if (module_en_update & ISP32_MODULE_DRC) { - ops->hdrdrc_enable(params_vdev, !!(module_ens & ISP32_MODULE_DRC)); + ops->hdrdrc_enable(params_vdev, !!(module_ens & ISP32_MODULE_DRC), id); priv_val->drc_en = !!(module_ens & ISP32_MODULE_DRC); } if (module_en_update & ISP32_MODULE_GIC) - ops->gic_enable(params_vdev, !!(module_ens & ISP32_MODULE_GIC)); + ops->gic_enable(params_vdev, !!(module_ens & ISP32_MODULE_GIC), id); if (module_en_update & ISP32_MODULE_DHAZ) { - ops->dhaz_enable(params_vdev, !!(module_ens & ISP32_MODULE_DHAZ)); + ops->dhaz_enable(params_vdev, !!(module_ens & ISP32_MODULE_DHAZ), id); priv_val->dhaz_en = !!(module_ens & ISP32_MODULE_DHAZ); } if (module_en_update & ISP32_MODULE_3DLUT) { - ops->isp3dlut_enable(params_vdev, !!(module_ens & ISP32_MODULE_3DLUT)); + ops->isp3dlut_enable(params_vdev, !!(module_ens & ISP32_MODULE_3DLUT), id); priv_val->lut3d_en = !!(module_ens & ISP32_MODULE_3DLUT); } if (module_en_update & ISP32_MODULE_LDCH) - ops->ldch_enable(params_vdev, !!(module_ens & ISP32_MODULE_LDCH)); + ops->ldch_enable(params_vdev, !!(module_ens & ISP32_MODULE_LDCH), id); if (module_en_update & ISP32_MODULE_YNR) - ops->ynr_enable(params_vdev, !!(module_ens & ISP32_MODULE_YNR)); + ops->ynr_enable(params_vdev, !!(module_ens & ISP32_MODULE_YNR), id); if (module_en_update & ISP32_MODULE_CNR) - ops->cnr_enable(params_vdev, !!(module_ens & ISP32_MODULE_CNR)); + ops->cnr_enable(params_vdev, !!(module_ens & ISP32_MODULE_CNR), id); if (module_en_update & ISP32_MODULE_SHARP) - ops->sharp_enable(params_vdev, !!(module_ens & ISP32_MODULE_SHARP)); + ops->sharp_enable(params_vdev, !!(module_ens & ISP32_MODULE_SHARP), id); if (module_en_update & ISP32_MODULE_BAYNR) - ops->baynr_enable(params_vdev, !!(module_ens & ISP32_MODULE_BAYNR)); + ops->baynr_enable(params_vdev, !!(module_ens & ISP32_MODULE_BAYNR), id); if (module_en_update & ISP32_MODULE_BAY3D) { - ops->bay3d_enable(params_vdev, !!(module_ens & ISP32_MODULE_BAY3D)); + ops->bay3d_enable(params_vdev, !!(module_ens & ISP32_MODULE_BAY3D), id); priv_val->bay3d_en = !!(module_ens & ISP32_MODULE_BAY3D); } if (module_en_update & ISP32_MODULE_CAC) - ops->cac_enable(params_vdev, !!(module_ens & ISP32_MODULE_CAC)); + ops->cac_enable(params_vdev, !!(module_ens & ISP32_MODULE_CAC), id); if (module_en_update & ISP32_MODULE_GAIN || ((priv_val->buf_info_owner == RKISP_INFO2DRR_OWNER_GAIN) && - !(isp3_param_read(params_vdev, ISP3X_GAIN_CTRL) & ISP3X_GAIN_2DDR_EN))) - ops->gain_enable(params_vdev, !!(module_ens & ISP32_MODULE_GAIN)); + !(isp3_param_read(params_vdev, ISP3X_GAIN_CTRL, id) & ISP3X_GAIN_2DDR_EN))) + ops->gain_enable(params_vdev, !!(module_ens & ISP32_MODULE_GAIN), id); if (module_en_update & ISP32_MODULE_VSM) - ops->vsm_enable(params_vdev, !!(module_ens & ISP32_MODULE_VSM)); + ops->vsm_enable(params_vdev, !!(module_ens & ISP32_MODULE_VSM), id); /* gain disable, using global gain for cnr */ - gain_ctrl = isp3_param_read_cache(params_vdev, ISP3X_GAIN_CTRL); - cnr_ctrl = isp3_param_read_cache(params_vdev, ISP3X_CNR_CTRL); + gain_ctrl = isp3_param_read_cache(params_vdev, ISP3X_GAIN_CTRL, id); + cnr_ctrl = isp3_param_read_cache(params_vdev, ISP3X_CNR_CTRL, id); if (!(gain_ctrl & ISP32_MODULE_EN) && cnr_ctrl & ISP32_MODULE_EN) { cnr_ctrl |= BIT(1); - isp3_param_write(params_vdev, cnr_ctrl, ISP3X_CNR_CTRL); - val = isp3_param_read(params_vdev, ISP3X_CNR_EXGAIN) & 0x3ff; - isp3_param_write(params_vdev, val | 0x8000, ISP3X_CNR_EXGAIN); + isp3_param_write(params_vdev, cnr_ctrl, ISP3X_CNR_CTRL, id); + val = isp3_param_read(params_vdev, ISP3X_CNR_EXGAIN, id) & 0x3ff; + isp3_param_write(params_vdev, val | 0x8000, ISP3X_CNR_EXGAIN, id); } } static __maybe_unused void __isp_isr_meas_config(struct rkisp_isp_params_vdev *params_vdev, struct isp32_isp_params_cfg *new_params, - enum rkisp_params_type type) + enum rkisp_params_type type, u32 id) { struct rkisp_isp_params_ops_v32 *ops = (struct rkisp_isp_params_ops_v32 *)params_vdev->priv_ops; @@ -4195,48 +4282,48 @@ void __isp_isr_meas_config(struct rkisp_isp_params_vdev *params_vdev, return; v4l2_dbg(4, rkisp_debug, ¶ms_vdev->dev->v4l2_dev, - "%s seq:%d module_cfg_update:0x%llx\n", - __func__, new_params->frame_id, module_cfg_update); + "%s id:%d seq:%d module_cfg_update:0x%llx\n", + __func__, id, new_params->frame_id, module_cfg_update); if ((module_cfg_update & ISP32_MODULE_RAWAF)) - ops->rawaf_config(params_vdev, &new_params->meas.rawaf); + ops->rawaf_config(params_vdev, &new_params->meas.rawaf, id); if ((module_cfg_update & ISP32_MODULE_RAWAE0) && !(params_vdev->afaemode_en && params_vdev->dev->isp_ver == ISP_V32_L)) - ops->rawae0_config(params_vdev, &new_params->meas.rawae0); + ops->rawae0_config(params_vdev, &new_params->meas.rawae0, id); if ((module_cfg_update & ISP32_MODULE_RAWAE1)) - ops->rawae1_config(params_vdev, &new_params->meas.rawae1); + ops->rawae1_config(params_vdev, &new_params->meas.rawae1, id); if ((module_cfg_update & ISP32_MODULE_RAWAE2)) - ops->rawae2_config(params_vdev, &new_params->meas.rawae2); + ops->rawae2_config(params_vdev, &new_params->meas.rawae2, id); if ((module_cfg_update & ISP32_MODULE_RAWAE3) && !(params_vdev->afaemode_en && params_vdev->dev->isp_ver == ISP_V32)) - ops->rawae3_config(params_vdev, &new_params->meas.rawae3); + ops->rawae3_config(params_vdev, &new_params->meas.rawae3, id); if ((module_cfg_update & ISP32_MODULE_RAWHIST0)) - ops->rawhst0_config(params_vdev, &new_params->meas.rawhist0); + ops->rawhst0_config(params_vdev, &new_params->meas.rawhist0, id); if ((module_cfg_update & ISP32_MODULE_RAWHIST1)) - ops->rawhst1_config(params_vdev, &new_params->meas.rawhist1); + ops->rawhst1_config(params_vdev, &new_params->meas.rawhist1, id); if ((module_cfg_update & ISP32_MODULE_RAWHIST2)) - ops->rawhst2_config(params_vdev, &new_params->meas.rawhist2); + ops->rawhst2_config(params_vdev, &new_params->meas.rawhist2, id); if ((module_cfg_update & ISP32_MODULE_RAWHIST3)) - ops->rawhst3_config(params_vdev, &new_params->meas.rawhist3); + ops->rawhst3_config(params_vdev, &new_params->meas.rawhist3, id); if ((module_cfg_update & ISP32_MODULE_RAWAWB) || ((priv_val->buf_info_owner == RKISP_INFO2DRR_OWNER_AWB) && - !(isp3_param_read(params_vdev, ISP3X_RAWAWB_CTRL) & ISP32_RAWAWB_2DDR_PATH_EN))) - ops->rawawb_config(params_vdev, &new_params->meas.rawawb); + !(isp3_param_read(params_vdev, ISP3X_RAWAWB_CTRL, id) & ISP32_RAWAWB_2DDR_PATH_EN))) + ops->rawawb_config(params_vdev, &new_params->meas.rawawb, id); } static __maybe_unused void __isp_isr_meas_en(struct rkisp_isp_params_vdev *params_vdev, struct isp32_isp_params_cfg *new_params, - enum rkisp_params_type type) + enum rkisp_params_type type, u32 id) { struct rkisp_isp_params_ops_v32 *ops = (struct rkisp_isp_params_ops_v32 *)params_vdev->priv_ops; @@ -4250,52 +4337,53 @@ void __isp_isr_meas_en(struct rkisp_isp_params_vdev *params_vdev, return; v4l2_dbg(4, rkisp_debug, ¶ms_vdev->dev->v4l2_dev, - "%s seq:%d module_en_update:0x%llx module_ens:0x%llx\n", - __func__, new_params->frame_id, module_en_update, module_ens); + "%s id:%d seq:%d module_en_update:0x%llx module_ens:0x%llx\n", + __func__, id, new_params->frame_id, module_en_update, module_ens); if (module_en_update & ISP32_MODULE_RAWAF) - ops->rawaf_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAF)); + ops->rawaf_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAF), id); if ((module_en_update & ISP32_MODULE_RAWAE0) && !(params_vdev->afaemode_en && params_vdev->dev->isp_ver == ISP_V32_L)) - ops->rawae0_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAE0)); + ops->rawae0_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAE0), id); if (module_en_update & ISP32_MODULE_RAWAE1) - ops->rawae1_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAE1)); + ops->rawae1_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAE1), id); if (module_en_update & ISP32_MODULE_RAWAE2) - ops->rawae2_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAE2)); + ops->rawae2_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAE2), id); if ((module_en_update & ISP32_MODULE_RAWAE3) && !(params_vdev->afaemode_en && params_vdev->dev->isp_ver == ISP_V32)) - ops->rawae3_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAE3)); + ops->rawae3_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAE3), id); if (module_en_update & ISP32_MODULE_RAWHIST0) - ops->rawhst0_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWHIST0)); + ops->rawhst0_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWHIST0), id); if (module_en_update & ISP32_MODULE_RAWHIST1) - ops->rawhst1_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWHIST1)); + ops->rawhst1_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWHIST1), id); if (module_en_update & ISP32_MODULE_RAWHIST2) - ops->rawhst2_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWHIST2)); + ops->rawhst2_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWHIST2), id); if (module_en_update & ISP32_MODULE_RAWHIST3) - ops->rawhst3_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWHIST3)); + ops->rawhst3_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWHIST3), id); if (module_en_update & ISP32_MODULE_RAWAWB) - ops->rawawb_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAWB)); + ops->rawawb_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAWB), id); } static void rkisp_params_cfgsram_v32(struct rkisp_isp_params_vdev *params_vdev) { - struct isp32_isp_params_cfg *params = params_vdev->isp32_params; + u32 id = params_vdev->dev->unite_index; + struct isp32_isp_params_cfg *params = params_vdev->isp32_params + id; - isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true); - isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist1, 1, true); - isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist2, 2, true); - isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist3, 0, true); - isp_rawawb_cfg_sram(params_vdev, ¶ms->meas.rawawb, true); + isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true, id); + isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist1, 1, true, id); + isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist2, 2, true, id); + isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist3, 0, true, id); + isp_rawawb_cfg_sram(params_vdev, ¶ms->meas.rawawb, true, id); } static int @@ -4306,22 +4394,24 @@ rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev, struct rkisp_isp_subdev *isp_sdev = &dev->isp_sdev; struct rkisp_isp_params_val_v32 *priv_val; u64 module_en_update, module_ens; - int ret, i; + int ret, i, id; priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; module_en_update = new_params->module_en_update; module_ens = new_params->module_ens; - priv_val->buf_3dlut_idx = 0; - for (i = 0; i < ISP32_3DLUT_BUF_NUM; i++) { - if (priv_val->buf_3dlut[i].mem_priv) - continue; - priv_val->buf_3dlut[i].is_need_vaddr = true; - priv_val->buf_3dlut[i].size = ISP32_3DLUT_BUF_SIZE; - ret = rkisp_alloc_buffer(dev, &priv_val->buf_3dlut[i]); - if (ret) { - dev_err(dev->dev, "alloc 3dlut buf fail:%d\n", ret); - goto err_3dlut; + for (id = 0; id <= !!dev->hw_dev->unite; id++) { + priv_val->buf_3dlut_idx[id] = 0; + for (i = 0; i < ISP32_3DLUT_BUF_NUM; i++) { + if (priv_val->buf_3dlut[id][i].mem_priv) + continue; + priv_val->buf_3dlut[id][i].is_need_vaddr = true; + priv_val->buf_3dlut[id][i].size = ISP32_3DLUT_BUF_SIZE; + ret = rkisp_alloc_buffer(dev, &priv_val->buf_3dlut[id][i]); + if (ret) { + dev_err(dev->dev, "alloc 3dlut buf fail:%d\n", ret); + goto err_3dlut; + } } } @@ -4337,6 +4427,9 @@ rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev, u32 val, wrap_line, wsize, div; bool is_alloc; + if (dev->hw_dev->unite) + w = ALIGN(isp_sdev->in_crop.width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL, 16); + priv_val->is_lo8x8 = (!new_params->others.bay3d_cfg.lo4x8_en && !new_params->others.bay3d_cfg.lo4x4_en); @@ -4354,6 +4447,9 @@ rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev, wsize *= 2; div = is_bwopt_dis ? 1 : 2; val = ALIGN(wsize * h / div, 16); + priv_val->bay3d_iir_size = val; + if (dev->hw_dev->unite) + val *= 2; is_alloc = true; if (priv_val->buf_3dnr_iir.mem_priv) { if (val > priv_val->buf_3dnr_iir.size) @@ -4374,6 +4470,9 @@ rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev, val = w * h / div; /* pixel to Byte and align */ val = ALIGN(val * 2, 16); + priv_val->bay3d_ds_size = val; + if (dev->hw_dev->unite) + val *= 2; is_alloc = true; if (priv_val->buf_3dnr_ds.mem_priv) { if (val > priv_val->buf_3dnr_ds.size) @@ -4406,8 +4505,7 @@ rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev, val = ALIGN(wsize * wrap_line / div, 16); is_alloc = true; if (priv_val->buf_3dnr_cur.mem_priv) { - if (val > priv_val->buf_3dnr_cur.size || - val < dev->hw_dev->sram.size) + if (val > priv_val->buf_3dnr_cur.size || val < dev->hw_dev->sram.size) rkisp_free_buffer(dev, &priv_val->buf_3dnr_cur); else is_alloc = false; @@ -4433,6 +4531,8 @@ rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev, if (dev->isp_ver == ISP_V32_L) { if (dev->hw_dev->is_frm_buf && !priv_val->buf_frm.mem_priv) { priv_val->buf_frm.size = ISP32_LITE_FRM_BUF_SIZE; + if (dev->hw_dev->unite) + priv_val->buf_frm.size *= 2; ret = rkisp_alloc_buffer(dev, &priv_val->buf_frm); if (ret) { dev_err(dev->dev, "alloc frm buf fail:%d\n", ret); @@ -4462,10 +4562,14 @@ free_3dnr: rkisp_free_buffer(dev, &priv_val->buf_3dnr_iir); rkisp_free_buffer(dev, &priv_val->buf_3dnr_ds); err_3dnr: + id = dev->hw_dev->unite ? 1 : 0; i = ISP32_3DLUT_BUF_NUM; err_3dlut: - for (i -= 1; i >= 0; i--) - rkisp_free_buffer(dev, &priv_val->buf_3dlut[i]); + for (; id >= 0; id--) { + for (i -= 1; i >= 0; i--) + rkisp_free_buffer(dev, &priv_val->buf_3dlut[id][i]); + i = ISP32_3DLUT_BUF_NUM; + } return ret; } @@ -4657,6 +4761,8 @@ rkisp_params_check_bigmode_v32(struct rkisp_isp_params_vdev *params_vdev) if (ispdev->isp_ver == ISP_V32_L) return rkisp_params_check_bigmode_v32_lite(params_vdev); + if (hw->unite == ISP_UNITE_ONE) + hw->is_multi_overflow = true; multi_overflow: if (hw->is_multi_overflow) { ispdev->multi_index = 0; @@ -4824,6 +4930,7 @@ static void rkisp_params_first_cfg_v32(struct rkisp_isp_params_vdev *params_vdev) { struct rkisp_device *dev = params_vdev->dev; + struct rkisp_hw_dev *hw = dev->hw_dev; struct rkisp_isp_params_val_v32 *priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; @@ -4840,20 +4947,39 @@ rkisp_params_first_cfg_v32(struct rkisp_isp_params_vdev *params_vdev) priv_val->lsc_en = 0; priv_val->mge_en = 0; priv_val->lut3d_en = 0; + if (hw->unite) { + if (dev->is_bigmode) + rkisp_next_set_bits(dev, ISP3X_ISP_CTRL1, 0, + ISP3X_BIGMODE_MANUAL | ISP3X_BIGMODE_FORCE_EN, false); + __isp_isr_meas_config(params_vdev, params_vdev->isp32_params + 1, RKISP_PARAMS_ALL, 1); + __isp_isr_other_config(params_vdev, params_vdev->isp32_params + 1, RKISP_PARAMS_ALL, 1); + __isp_isr_other_en(params_vdev, params_vdev->isp32_params + 1, RKISP_PARAMS_ALL, 1); + __isp_isr_meas_en(params_vdev, params_vdev->isp32_params + 1, RKISP_PARAMS_ALL, 1); + } if (dev->is_bigmode) - rkisp_set_bits(params_vdev->dev, ISP3X_ISP_CTRL1, 0, + rkisp_set_bits(dev, ISP3X_ISP_CTRL1, 0, ISP3X_BIGMODE_MANUAL | ISP3X_BIGMODE_FORCE_EN, false); - __isp_isr_meas_config(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL); - __isp_isr_other_config(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL); - __isp_isr_other_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL); - __isp_isr_meas_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL); + __isp_isr_meas_config(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL, 0); + __isp_isr_other_config(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL, 0); + __isp_isr_other_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL, 0); + __isp_isr_meas_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL, 0); + spin_unlock(¶ms_vdev->config_lock); if (dev->hw_dev->is_frm_buf && priv_val->buf_frm.mem_priv) { - isp3_param_write(params_vdev, priv_val->buf_frm.size, ISP32L_FRM_BUF_WR_SIZE); - isp3_param_write(params_vdev, priv_val->buf_frm.dma_addr, ISP32L_FRM_BUF_WR_BASE); - isp3_param_write(params_vdev, priv_val->buf_frm.dma_addr, ISP32L_FRM_BUF_RD_BASE); + u32 size = priv_val->buf_frm.size; + u32 addr = priv_val->buf_frm.dma_addr; + + if (hw->unite) { + size /= 2; + isp3_param_write(params_vdev, size, ISP32L_FRM_BUF_WR_SIZE, 1); + isp3_param_write(params_vdev, addr + size, ISP32L_FRM_BUF_WR_BASE, 1); + isp3_param_write(params_vdev, addr + size, ISP32L_FRM_BUF_RD_BASE, 1); + } + isp3_param_write(params_vdev, size, ISP32L_FRM_BUF_WR_SIZE, 0); + isp3_param_write(params_vdev, addr, ISP32L_FRM_BUF_WR_BASE, 0); + isp3_param_write(params_vdev, addr, ISP32L_FRM_BUF_RD_BASE, 0); } if (dev->hw_dev->is_single && (dev->isp_state & ISP_START)) rkisp_set_bits(dev, ISP3X_ISP_CTRL0, 0, CIF_ISP_CTRL_ISP_CFG_UPD, true); @@ -4867,11 +4993,15 @@ static void rkisp_save_first_param_v32(struct rkisp_isp_params_vdev *params_vdev static void rkisp_clear_first_param_v32(struct rkisp_isp_params_vdev *params_vdev) { - memset(params_vdev->isp32_params, 0, sizeof(struct isp32_isp_params_cfg)); + u32 size = sizeof(struct isp32_isp_params_cfg); + + if (params_vdev->dev->hw_dev->unite) + size *= 2; + memset(params_vdev->isp32_params, 0, size); } static void rkisp_deinit_mesh_buf(struct rkisp_isp_params_vdev *params_vdev, - u64 module_id) + u64 module_id, u32 id) { struct rkisp_isp_params_val_v32 *priv_val; struct rkisp_dummy_buffer *buf; @@ -4883,11 +5013,11 @@ static void rkisp_deinit_mesh_buf(struct rkisp_isp_params_vdev *params_vdev, switch (module_id) { case ISP32_MODULE_CAC: - buf = priv_val->buf_cac; + buf = priv_val->buf_cac[id]; break; case ISP32_MODULE_LDCH: default: - buf = priv_val->buf_ldch; + buf = priv_val->buf_ldch[id]; break; } @@ -4907,6 +5037,7 @@ static int rkisp_init_mesh_buf(struct rkisp_isp_params_vdev *params_vdev, u32 mesh_h = meshsize->meas_height; u32 mesh_size, buf_size; int i, ret, buf_cnt = meshsize->buf_cnt; + int id = meshsize->unite_isp_id; bool is_alloc; priv_val = params_vdev->priv_val; @@ -4917,16 +5048,16 @@ static int rkisp_init_mesh_buf(struct rkisp_isp_params_vdev *params_vdev, switch (meshsize->module_id) { case ISP32_MODULE_CAC: - priv_val->buf_cac_idx = 0; - buf = priv_val->buf_cac; + priv_val->buf_cac_idx[id] = 0; + buf = priv_val->buf_cac[id]; mesh_w = (mesh_w + 62) / 64 * 9; mesh_h = (mesh_h + 62) / 64 * 2; mesh_size = mesh_w * 4 * mesh_h; break; case ISP32_MODULE_LDCH: default: - priv_val->buf_ldch_idx = 0; - buf = priv_val->buf_ldch; + priv_val->buf_ldch_idx[id] = 0; + buf = priv_val->buf_ldch[id]; mesh_w = ((mesh_w + 15) / 16 + 2) / 2; mesh_h = (mesh_h + 7) / 8 + 1; mesh_size = mesh_w * 4 * mesh_h; @@ -4967,7 +5098,7 @@ static int rkisp_init_mesh_buf(struct rkisp_isp_params_vdev *params_vdev, return 0; err: - rkisp_deinit_mesh_buf(params_vdev, meshsize->module_id); + rkisp_deinit_mesh_buf(params_vdev, meshsize->module_id, id); return -ENOMEM; } @@ -4975,7 +5106,9 @@ static void rkisp_get_param_size_v32(struct rkisp_isp_params_vdev *params_vdev, unsigned int sizes[]) { - sizes[0] = sizeof(struct isp32_isp_params_cfg); + u32 mult = params_vdev->dev->hw_dev->unite ? 2 : 1; + + sizes[0] = sizeof(struct isp32_isp_params_cfg) * mult; } static void @@ -4985,18 +5118,18 @@ rkisp_params_get_meshbuf_inf_v32(struct rkisp_isp_params_vdev *params_vdev, struct rkisp_isp_params_val_v32 *priv_val; struct rkisp_meshbuf_info *meshbuf = meshbuf_inf; struct rkisp_dummy_buffer *buf; - int i; + int i, id = meshbuf->unite_isp_id; priv_val = params_vdev->priv_val; switch (meshbuf->module_id) { case ISP32_MODULE_CAC: - priv_val->buf_cac_idx = 0; - buf = priv_val->buf_cac; + priv_val->buf_cac_idx[id] = 0; + buf = priv_val->buf_cac[id]; break; case ISP32_MODULE_LDCH: default: - priv_val->buf_ldch_idx = 0; - buf = priv_val->buf_ldch; + priv_val->buf_ldch_idx[id] = 0; + buf = priv_val->buf_ldch[id]; break; } @@ -5018,6 +5151,8 @@ rkisp_params_set_meshbuf_size_v32(struct rkisp_isp_params_vdev *params_vdev, { struct rkisp_meshbuf_size *meshsize = size; + if (!params_vdev->dev->hw_dev->unite) + meshsize->unite_isp_id = 0; return rkisp_init_mesh_buf(params_vdev, meshsize); } @@ -5025,7 +5160,10 @@ static void rkisp_params_free_meshbuf_v32(struct rkisp_isp_params_vdev *params_vdev, u64 module_id) { - rkisp_deinit_mesh_buf(params_vdev, module_id); + int id; + + for (id = 0; id <= !!params_vdev->dev->hw_dev->unite; id++) + rkisp_deinit_mesh_buf(params_vdev, module_id, id); } static int @@ -5122,9 +5260,9 @@ rkisp_params_info2ddr_cfg_v32(struct rkisp_isp_params_vdev *params_vdev, void *a cfg->buf_fd[i] = buf->dma_fd; } buf = &priv_val->buf_info[0]; - isp3_param_write(params_vdev, buf->dma_addr, ISP3X_MI_GAIN_WR_BASE); - isp3_param_write(params_vdev, buf->size, ISP3X_MI_GAIN_WR_SIZE); - isp3_param_write(params_vdev, wsize, ISP3X_MI_GAIN_WR_LENGTH); + isp3_param_write(params_vdev, buf->dma_addr, ISP3X_MI_GAIN_WR_BASE, 0); + isp3_param_write(params_vdev, buf->size, ISP3X_MI_GAIN_WR_SIZE, 0); + isp3_param_write(params_vdev, wsize, ISP3X_MI_GAIN_WR_LENGTH, 0); if (dev->hw_dev->is_single) rkisp_write(dev, ISP3X_MI_WR_CTRL2, ISP3X_GAINSELF_UPD, true); rkisp_set_reg_cache_bits(dev, reg, mask, ctrl); @@ -5152,7 +5290,7 @@ rkisp_params_stream_stop_v32(struct rkisp_isp_params_vdev *params_vdev) { struct rkisp_device *ispdev = params_vdev->dev; struct rkisp_isp_params_val_v32 *priv_val; - int i; + int i, id; priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; rkisp_free_buffer(ispdev, &priv_val->buf_frm); @@ -5161,10 +5299,12 @@ rkisp_params_stream_stop_v32(struct rkisp_isp_params_vdev *params_vdev) rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_ds); for (i = 0; i < ISP32_LSC_LUT_BUF_NUM; i++) rkisp_free_buffer(ispdev, &priv_val->buf_lsclut[i]); - for (i = 0; i < ISP32_3DLUT_BUF_NUM; i++) - rkisp_free_buffer(ispdev, &priv_val->buf_3dlut[i]); for (i = 0; i < RKISP_STATS_DDR_BUF_NUM; i++) rkisp_free_buffer(ispdev, &ispdev->stats_vdev.stats_buf[i]); + for (id = 0; id <= !!ispdev->hw_dev->unite; id++) { + for (i = 0; i < ISP32_3DLUT_BUF_NUM; i++) + rkisp_free_buffer(ispdev, &priv_val->buf_3dlut[id][i]); + } priv_val->buf_info_owner = 0; priv_val->buf_info_cnt = 0; priv_val->buf_info_idx = -1; @@ -5175,8 +5315,12 @@ rkisp_params_stream_stop_v32(struct rkisp_isp_params_vdev *params_vdev) static void rkisp_params_fop_release_v32(struct rkisp_isp_params_vdev *params_vdev) { - rkisp_deinit_mesh_buf(params_vdev, ISP32_MODULE_LDCH); - rkisp_deinit_mesh_buf(params_vdev, ISP32_MODULE_CAC); + int id; + + for (id = 0; id <= !!params_vdev->dev->hw_dev->unite; id++) { + rkisp_deinit_mesh_buf(params_vdev, ISP32_MODULE_LDCH, id); + rkisp_deinit_mesh_buf(params_vdev, ISP32_MODULE_CAC, id); + } } /* Not called when the camera active, thus not isr protection. */ @@ -5186,13 +5330,17 @@ rkisp_params_disable_isp_v32(struct rkisp_isp_params_vdev *params_vdev) params_vdev->isp32_params->module_ens = 0; params_vdev->isp32_params->module_en_update = 0x7ffffffffff; - __isp_isr_other_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL); - __isp_isr_meas_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL); + __isp_isr_other_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL, 0); + __isp_isr_meas_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL, 0); + if (params_vdev->dev->hw_dev->unite) { + __isp_isr_other_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL, 1); + __isp_isr_meas_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL, 1); + } } static void module_data_abandon(struct rkisp_isp_params_vdev *params_vdev, - struct isp32_isp_params_cfg *params) + struct isp32_isp_params_cfg *params, u32 id) { struct rkisp_isp_params_val_v32 *priv_val; struct isp2x_mesh_head *mesh_head; @@ -5203,9 +5351,9 @@ module_data_abandon(struct rkisp_isp_params_vdev *params_vdev, const struct isp32_ldch_cfg *arg = ¶ms->others.ldch_cfg; for (i = 0; i < ISP32_MESH_BUF_NUM; i++) { - if (priv_val->buf_ldch[i].vaddr && - arg->buf_fd == priv_val->buf_ldch[i].dma_fd) { - mesh_head = (struct isp2x_mesh_head *)priv_val->buf_ldch[i].vaddr; + if (priv_val->buf_ldch[id][i].vaddr && + arg->buf_fd == priv_val->buf_ldch[id][i].dma_fd) { + mesh_head = (struct isp2x_mesh_head *)priv_val->buf_ldch[id][i].vaddr; mesh_head->stat = MESH_BUF_CHIPINUSE; break; } @@ -5216,9 +5364,9 @@ module_data_abandon(struct rkisp_isp_params_vdev *params_vdev, const struct isp32_cac_cfg *arg = ¶ms->others.cac_cfg; for (i = 0; i < ISP32_MESH_BUF_NUM; i++) { - if (priv_val->buf_cac[i].vaddr && - arg->buf_fd == priv_val->buf_cac[i].dma_fd) { - mesh_head = (struct isp2x_mesh_head *)priv_val->buf_cac[i].vaddr; + if (priv_val->buf_cac[id][i].vaddr && + arg->buf_fd == priv_val->buf_cac[id][i].dma_fd) { + mesh_head = (struct isp2x_mesh_head *)priv_val->buf_cac[id][i].vaddr; mesh_head->stat = MESH_BUF_CHIPINUSE; break; } @@ -5230,6 +5378,7 @@ static void rkisp_params_cfg_v32(struct rkisp_isp_params_vdev *params_vdev, u32 frame_id, enum rkisp_params_type type) { + struct rkisp_hw_dev *hw = params_vdev->dev->hw_dev; struct isp32_isp_params_cfg *new_params = NULL; struct rkisp_buffer *cur_buf = params_vdev->cur_buf; @@ -5250,15 +5399,27 @@ rkisp_params_cfg_v32(struct rkisp_isp_params_vdev *params_vdev, else if (new_params->module_en_update || (new_params->module_cfg_update & ISP32_MODULE_FORCE)) { /* update en immediately */ - __isp_isr_meas_config(params_vdev, new_params, type); - __isp_isr_other_config(params_vdev, new_params, type); - __isp_isr_other_en(params_vdev, new_params, type); - __isp_isr_meas_en(params_vdev, new_params, type); + __isp_isr_meas_config(params_vdev, new_params, type, 0); + __isp_isr_other_config(params_vdev, new_params, type, 0); + __isp_isr_other_en(params_vdev, new_params, type, 0); + __isp_isr_meas_en(params_vdev, new_params, type, 0); new_params->module_cfg_update = 0; + if (hw->unite) { + struct isp32_isp_params_cfg *params = new_params + 1; + + __isp_isr_meas_config(params_vdev, params, type, 1); + __isp_isr_other_config(params_vdev, params, type, 1); + __isp_isr_other_en(params_vdev, params, type, 1); + __isp_isr_meas_en(params_vdev, params, type, 1); + params->module_cfg_update = 0; + } } if (new_params->module_cfg_update & (ISP32_MODULE_LDCH | ISP32_MODULE_CAC)) { - module_data_abandon(params_vdev, new_params); + module_data_abandon(params_vdev, new_params, 0); + if (hw->unite) + module_data_abandon(params_vdev, new_params, 1); + } vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); cur_buf = NULL; @@ -5275,13 +5436,21 @@ rkisp_params_cfg_v32(struct rkisp_isp_params_vdev *params_vdev, goto unlock; new_params = (struct isp32_isp_params_cfg *)(cur_buf->vaddr[0]); - __isp_isr_meas_config(params_vdev, new_params, type); - __isp_isr_other_config(params_vdev, new_params, type); - __isp_isr_other_en(params_vdev, new_params, type); - __isp_isr_meas_en(params_vdev, new_params, type); + if (hw->unite) { + __isp_isr_meas_config(params_vdev, new_params + 1, type, 1); + __isp_isr_other_config(params_vdev, new_params + 1, type, 1); + __isp_isr_other_en(params_vdev, new_params + 1, type, 1); + __isp_isr_meas_en(params_vdev, new_params + 1, type, 1); + } + __isp_isr_meas_config(params_vdev, new_params, type, 0); + __isp_isr_other_config(params_vdev, new_params, type, 0); + __isp_isr_other_en(params_vdev, new_params, type, 0); + __isp_isr_meas_en(params_vdev, new_params, type, 0); if (type != RKISP_PARAMS_IMD) { new_params->module_cfg_update = 0; + if (hw->unite) + (new_params++)->module_cfg_update = 0; vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); cur_buf = NULL; } @@ -5294,13 +5463,15 @@ unlock: static void rkisp_params_clear_fstflg(struct rkisp_isp_params_vdev *params_vdev) { - u32 value = isp3_param_read(params_vdev, ISP3X_ISP_CTRL1); + u32 value = isp3_param_read(params_vdev, ISP3X_ISP_CTRL1, 0); value &= (ISP3X_YNR_FST_FRAME | ISP3X_ADRC_FST_FRAME | ISP3X_DHAZ_FST_FRAME | ISP3X_CNR_FST_FRAME | ISP3X_RAW3D_FST_FRAME | ISP32_SHP_FST_FRAME); if (value) { - isp3_param_clear_bits(params_vdev, ISP3X_ISP_CTRL1, value); + isp3_param_clear_bits(params_vdev, ISP3X_ISP_CTRL1, value, 0); + if (params_vdev->dev->hw_dev->unite) + isp3_param_clear_bits(params_vdev, ISP3X_ISP_CTRL1, value, 1); } } @@ -5359,6 +5530,8 @@ int rkisp_init_params_vdev_v32(struct rkisp_isp_params_vdev *params_vdev) return -ENOMEM; size = sizeof(struct isp32_isp_params_cfg); + if (params_vdev->dev->hw_dev->unite) + size *= 2; params_vdev->isp32_params = vmalloc(size); if (!params_vdev->isp32_params) { kfree(priv_val); diff --git a/drivers/media/platform/rockchip/isp/isp_params_v32.h b/drivers/media/platform/rockchip/isp/isp_params_v32.h index ac658806a584..e1d91488d177 100644 --- a/drivers/media/platform/rockchip/isp/isp_params_v32.h +++ b/drivers/media/platform/rockchip/isp/isp_params_v32.h @@ -29,169 +29,171 @@ struct rkisp_isp_params_vdev; struct rkisp_isp_params_ops_v32 { void (*dpcc_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_dpcc_cfg *arg); + const struct isp2x_dpcc_cfg *arg, u32 id); void (*dpcc_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*bls_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_bls_cfg *arg); + const struct isp32_bls_cfg *arg, u32 id); void (*bls_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*sdg_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_sdg_cfg *arg); + const struct isp2x_sdg_cfg *arg, u32 id); void (*sdg_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*lsc_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp3x_lsc_cfg *arg); + const struct isp3x_lsc_cfg *arg, u32 id); void (*lsc_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*awbgain_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_awb_gain_cfg *arg); + const struct isp32_awb_gain_cfg *arg, u32 id); void (*awbgain_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*debayer_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_debayer_cfg *arg); + const struct isp32_debayer_cfg *arg, u32 id); void (*debayer_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*ccm_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_ccm_cfg *arg); + const struct isp32_ccm_cfg *arg, u32 id); void (*ccm_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*goc_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp3x_gammaout_cfg *arg); + const struct isp3x_gammaout_cfg *arg, u32 id); void (*goc_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*cproc_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_cproc_cfg *arg); + const struct isp2x_cproc_cfg *arg, u32 id); void (*cproc_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*ie_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_ie_cfg *arg); + const struct isp2x_ie_cfg *arg, u32 id); void (*ie_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*rawaf_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_rawaf_meas_cfg *arg); + const struct isp32_rawaf_meas_cfg *arg, u32 id); void (*rawaf_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*rawae0_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_rawaelite_meas_cfg *arg); + const struct isp2x_rawaelite_meas_cfg *arg, u32 id); void (*rawae0_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*rawae1_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_rawaebig_meas_cfg *arg); + const struct isp2x_rawaebig_meas_cfg *arg, u32 id); void (*rawae1_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*rawae2_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_rawaebig_meas_cfg *arg); + const struct isp2x_rawaebig_meas_cfg *arg, u32 id); void (*rawae2_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*rawae3_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_rawaebig_meas_cfg *arg); + const struct isp2x_rawaebig_meas_cfg *arg, u32 id); void (*rawae3_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*rawawb_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_rawawb_meas_cfg *arg); + const struct isp32_rawawb_meas_cfg *arg, u32 id); void (*rawawb_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*rawhst0_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_rawhistlite_cfg *arg); + const struct isp2x_rawhistlite_cfg *arg, u32 id); void (*rawhst0_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*rawhst1_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_rawhistbig_cfg *arg); + const struct isp2x_rawhistbig_cfg *arg, u32 id); void (*rawhst1_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*rawhst2_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_rawhistbig_cfg *arg); + const struct isp2x_rawhistbig_cfg *arg, u32 id); void (*rawhst2_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*rawhst3_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_rawhistbig_cfg *arg); + const struct isp2x_rawhistbig_cfg *arg, u32 id); void (*rawhst3_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*hdrdrc_config)(struct rkisp_isp_params_vdev *params_vdev, const struct isp32_drc_cfg *arg, - enum rkisp_params_type type); + enum rkisp_params_type type, u32 id); void (*hdrdrc_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*hdrmge_config)(struct rkisp_isp_params_vdev *params_vdev, const struct isp32_hdrmge_cfg *arg, - enum rkisp_params_type type); + enum rkisp_params_type type, u32 id); void (*hdrmge_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*gic_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp21_gic_cfg *arg); + const struct isp21_gic_cfg *arg, u32 id); void (*gic_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*dhaz_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_dhaz_cfg *arg); + const struct isp32_dhaz_cfg *arg, u32 id); void (*dhaz_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*isp3dlut_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp2x_3dlut_cfg *arg); + const struct isp2x_3dlut_cfg *arg, u32 id); void (*isp3dlut_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*ldch_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_ldch_cfg *arg); + const struct isp32_ldch_cfg *arg, u32 id); void (*ldch_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*ynr_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_ynr_cfg *arg); + const struct isp32_ynr_cfg *arg, u32 id); void (*ynr_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*cnr_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_cnr_cfg *arg); + const struct isp32_cnr_cfg *arg, u32 id); void (*cnr_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*sharp_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_sharp_cfg *arg); + const struct isp32_sharp_cfg *arg, u32 id); void (*sharp_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*baynr_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_baynr_cfg *arg); + const struct isp32_baynr_cfg *arg, u32 id); void (*baynr_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*bay3d_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_bay3d_cfg *arg); + const struct isp32_bay3d_cfg *arg, u32 id); void (*bay3d_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*gain_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp3x_gain_cfg *arg); + const struct isp3x_gain_cfg *arg, u32 id); void (*gain_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*cac_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_cac_cfg *arg); + const struct isp32_cac_cfg *arg, u32 id); void (*cac_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); void (*csm_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp21_csm_cfg *arg); + const struct isp21_csm_cfg *arg, u32 id); void (*cgc_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp21_cgc_cfg *arg); + const struct isp21_cgc_cfg *arg, u32 id); void (*vsm_config)(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_vsm_cfg *arg); + const struct isp32_vsm_cfg *arg, u32 id); void (*vsm_enable)(struct rkisp_isp_params_vdev *params_vdev, - bool en); + bool en, u32 id); }; struct rkisp_isp_params_val_v32 { struct tasklet_struct lsc_tasklet; - struct rkisp_dummy_buffer buf_3dlut[ISP32_3DLUT_BUF_NUM]; - u32 buf_3dlut_idx; + struct rkisp_dummy_buffer buf_3dlut[ISP3_UNITE_MAX][ISP32_3DLUT_BUF_NUM]; + u32 buf_3dlut_idx[ISP3_UNITE_MAX]; + + struct rkisp_dummy_buffer buf_ldch[ISP3_UNITE_MAX][ISP3X_MESH_BUF_NUM]; + u32 buf_ldch_idx[ISP3_UNITE_MAX]; + + struct rkisp_dummy_buffer buf_cac[ISP3_UNITE_MAX][ISP3X_MESH_BUF_NUM]; + u32 buf_cac_idx[ISP3_UNITE_MAX]; struct rkisp_dummy_buffer buf_lsclut[ISP32_LSC_LUT_BUF_NUM]; u32 buf_lsclut_idx; - struct rkisp_dummy_buffer buf_ldch[ISP3X_MESH_BUF_NUM]; - u32 buf_ldch_idx; - - struct rkisp_dummy_buffer buf_cac[ISP3X_MESH_BUF_NUM]; - u32 buf_cac_idx; - struct rkisp_dummy_buffer buf_info[RKISP_INFO2DDR_BUF_MAX]; u32 buf_info_owner; u32 buf_info_cnt; int buf_info_idx; + u32 bay3d_ds_size; + u32 bay3d_iir_size; u32 bay3d_cur_size; u32 bay3d_cur_wsize; u32 bay3d_cur_wrap_line; diff --git a/drivers/media/platform/rockchip/isp/isp_params_v3x.c b/drivers/media/platform/rockchip/isp/isp_params_v3x.c index cf9385a7368e..bd1e557eb5e8 100644 --- a/drivers/media/platform/rockchip/isp/isp_params_v3x.c +++ b/drivers/media/platform/rockchip/isp/isp_params_v3x.c @@ -591,7 +591,7 @@ isp_lsc_cfg_sram_task(unsigned long data) struct isp3x_isp_params_cfg *params = params_vdev->isp3x_params; isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true, 0); - if (params_vdev->dev->hw_dev->is_unite) { + if (params_vdev->dev->hw_dev->unite) { params++; isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true, 1); } @@ -1223,7 +1223,7 @@ isp_rawaelite_config(struct rkisp_isp_params_vdev *params_vdev, block_hsize = arg->win.h_size / ae_wnd_num[wnd_num_idx]; value = block_hsize * ae_wnd_num[wnd_num_idx] + arg->win.h_offs; - if (ispdev->hw_dev->is_unite) + if (ispdev->hw_dev->unite) width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL; if (value + 1 > width) block_hsize -= 1; @@ -1310,7 +1310,7 @@ isp_rawaebig_config(struct rkisp_isp_params_vdev *params_vdev, block_hsize = arg->win.h_size / ae_wnd_num[wnd_num_idx]; value = block_hsize * ae_wnd_num[wnd_num_idx] + arg->win.h_offs; - if (ispdev->hw_dev->is_unite) + if (ispdev->hw_dev->unite) width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL; if (value + 1 > width) block_hsize -= 1; @@ -2887,7 +2887,7 @@ isp_dhaz_config(struct rkisp_isp_params_vdev *params_vdev, value = ISP_PACK_2SHORT(arg->sigma_lut[i * 2], 0); isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_LUT0 + i * 4, id); - if (dev->hw_dev->is_unite && + if (dev->hw_dev->unite && dev->hw_dev->is_single && ctrl & ISP3X_DHAZ_ENMUX) ctrl |= ISP3X_SELF_FORCE_UPD; @@ -4105,7 +4105,7 @@ void rkisp_params_cfgsram_v3x(struct rkisp_isp_params_vdev *params_vdev) isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist2, 2, true, 0); isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist3, 0, true, 0); isp_rawawb_cfg_sram(params_vdev, ¶ms->meas.rawawb, true, 0); - if (params_vdev->dev->hw_dev->is_unite) { + if (params_vdev->dev->hw_dev->unite) { params++; isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true, 1); isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist1, 1, true, 1); @@ -4129,7 +4129,7 @@ rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev, module_en_update = new_params->module_en_update; module_ens = new_params->module_ens; - for (id = 0; id <= ispdev->hw_dev->is_unite; id++) { + for (id = 0; id <= !!ispdev->hw_dev->unite; id++) { priv_val->buf_3dlut_idx[id] = 0; for (i = 0; i < ISP3X_3DLUT_BUF_NUM; i++) { priv_val->buf_3dlut[id][i].is_need_vaddr = true; @@ -4146,10 +4146,10 @@ rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev, (module_ens & ISP3X_MODULE_BAY3D)) { w = ALIGN(isp_sdev->in_crop.width, 16); h = ALIGN(isp_sdev->in_crop.height, 16); - if (ispdev->hw_dev->is_unite) + if (ispdev->hw_dev->unite) w = ALIGN(isp_sdev->in_crop.width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL, 16); - for (id = 0; id <= ispdev->hw_dev->is_unite; id++) { + for (id = 0; id <= !!ispdev->hw_dev->unite; id++) { size = ALIGN((w + w / 8) * h * 2, 16); priv_val->buf_3dnr_iir[id].size = size; @@ -4185,7 +4185,7 @@ err_3dnr: rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_cur[id]); rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_ds[id]); } - id = ispdev->hw_dev->is_unite ? 1 : 0; + id = ispdev->hw_dev->unite ? 1 : 0; i = ISP3X_3DLUT_BUF_NUM; err_3dlut: for (; id >= 0; id--) { @@ -4240,7 +4240,7 @@ multi_overflow: continue; dev_warn(dev, "isp%d %dx%d over four vir isp max:%dx1536\n", i, hw->isp_size[i].w, hw->isp_size[i].h, - hw->is_unite ? (2560 - RKMOUDLE_UNITE_EXTEND_PIXEL) * 2 : 2560); + hw->unite ? (2560 - RKMOUDLE_UNITE_EXTEND_PIXEL) * 2 : 2560); hw->is_multi_overflow = true; goto multi_overflow; } @@ -4282,7 +4282,7 @@ multi_overflow: (hw->isp_size[idx1[0]].size > ISP3X_VIR2_MAX_SIZE)) { dev_warn(dev, "isp%d %dx%d over three vir isp max:%dx1536\n", idx1[0], hw->isp_size[idx1[0]].w, hw->isp_size[idx1[0]].h, - hw->is_unite ? (2560 - RKMOUDLE_UNITE_EXTEND_PIXEL) * 2 : 2560); + hw->unite ? (2560 - RKMOUDLE_UNITE_EXTEND_PIXEL) * 2 : 2560); hw->is_multi_overflow = true; goto multi_overflow; } else { @@ -4341,7 +4341,7 @@ multi_overflow: hw->isp_size[idx1[k - 1]].size > (ISP3X_VIR4_MAX_SIZE + ISP3X_VIR2_MAX_SIZE)) { dev_warn(dev, "isp%d %dx%d over two vir isp max:%dx2160\n", idx1[k - 1], hw->isp_size[idx1[k - 1]].w, hw->isp_size[idx1[k - 1]].h, - hw->is_unite ? (3840 - RKMOUDLE_UNITE_EXTEND_PIXEL) * 2 : 3840); + hw->unite ? (3840 - RKMOUDLE_UNITE_EXTEND_PIXEL) * 2 : 3840); hw->is_multi_overflow = true; goto multi_overflow; } else { @@ -4363,7 +4363,7 @@ multi_overflow: ispdev->multi_mode = 0; ispdev->multi_index = 0; width = crop->width; - if (hw->is_unite) + if (hw->unite) width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL; height = crop->height; size = width * height; @@ -4400,7 +4400,7 @@ rkisp_params_first_cfg_v3x(struct rkisp_isp_params_vdev *params_vdev) priv_val->lsc_en = 0; priv_val->mge_en = 0; priv_val->lut3d_en = 0; - if (hw->is_unite) { + if (hw->unite) { if (dev->is_bigmode) rkisp_next_set_bits(params_vdev->dev, ISP3X_ISP_CTRL1, 0, ISP3X_BIGMODE_MANUAL | ISP3X_BIGMODE_FORCE_EN, false); @@ -4431,7 +4431,7 @@ static void rkisp_save_first_param_v3x(struct rkisp_isp_params_vdev *params_vdev static void rkisp_clear_first_param_v3x(struct rkisp_isp_params_vdev *params_vdev) { - u32 mult = params_vdev->dev->hw_dev->is_unite ? ISP3_UNITE_MAX : 1; + u32 mult = params_vdev->dev->hw_dev->unite ? ISP3_UNITE_MAX : 1; u32 size = sizeof(struct isp3x_isp_params_cfg) * mult; memset(params_vdev->isp3x_params, 0, size); @@ -4530,7 +4530,7 @@ static void rkisp_get_param_size_v3x(struct rkisp_isp_params_vdev *params_vdev, unsigned int sizes[]) { - u32 mult = params_vdev->dev->hw_dev->is_unite ? ISP3_UNITE_MAX : 1; + u32 mult = params_vdev->dev->hw_dev->unite ? ISP3_UNITE_MAX : 1; sizes[0] = sizeof(struct isp3x_isp_params_cfg) * mult; } @@ -4575,7 +4575,7 @@ rkisp_params_set_meshbuf_size_v3x(struct rkisp_isp_params_vdev *params_vdev, { struct rkisp_meshbuf_size *meshsize = size; - if (!params_vdev->dev->hw_dev->is_unite) + if (!params_vdev->dev->hw_dev->unite) meshsize->unite_isp_id = 0; rkisp_deinit_mesh_buf(params_vdev, meshsize->module_id, meshsize->unite_isp_id); return rkisp_init_mesh_buf(params_vdev, meshsize); @@ -4587,7 +4587,7 @@ rkisp_params_free_meshbuf_v3x(struct rkisp_isp_params_vdev *params_vdev, { int id; - for (id = 0; id <= params_vdev->dev->hw_dev->is_unite; id++) + for (id = 0; id <= !!params_vdev->dev->hw_dev->unite; id++) rkisp_deinit_mesh_buf(params_vdev, module_id, id); } @@ -4600,7 +4600,7 @@ rkisp_params_stream_stop_v3x(struct rkisp_isp_params_vdev *params_vdev) priv_val = (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val; tasklet_disable(&priv_val->lsc_tasklet); - for (id = 0; id <= ispdev->hw_dev->is_unite; id++) { + for (id = 0; id <= !!ispdev->hw_dev->unite; id++) { rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir[id]); rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_cur[id]); rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_ds[id]); @@ -4616,7 +4616,7 @@ rkisp_params_fop_release_v3x(struct rkisp_isp_params_vdev *params_vdev) { int id; - for (id = 0; id <= params_vdev->dev->hw_dev->is_unite; id++) { + for (id = 0; id <= !!params_vdev->dev->hw_dev->unite; id++) { rkisp_deinit_mesh_buf(params_vdev, ISP3X_MODULE_LDCH, id); rkisp_deinit_mesh_buf(params_vdev, ISP3X_MODULE_CAC, id); } @@ -4631,7 +4631,7 @@ rkisp_params_disable_isp_v3x(struct rkisp_isp_params_vdev *params_vdev) __isp_isr_other_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 0); __isp_isr_meas_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 0); - if (params_vdev->dev->hw_dev->is_unite) { + if (params_vdev->dev->hw_dev->unite) { __isp_isr_other_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 1); __isp_isr_meas_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 1); } @@ -4704,7 +4704,7 @@ rkisp_params_cfg_v3x(struct rkisp_isp_params_vdev *params_vdev, __isp_isr_other_en(params_vdev, new_params, type, 0); __isp_isr_meas_en(params_vdev, new_params, type, 0); new_params->module_cfg_update = 0; - if (hw_dev->is_unite) { + if (hw_dev->unite) { struct isp3x_isp_params_cfg *params = new_params + 1; __isp_isr_meas_config(params_vdev, params, type, 1); @@ -4717,7 +4717,7 @@ rkisp_params_cfg_v3x(struct rkisp_isp_params_vdev *params_vdev, if (new_params->module_cfg_update & (ISP3X_MODULE_LDCH | ISP3X_MODULE_CAC)) { module_data_abandon(params_vdev, new_params, 0); - if (hw_dev->is_unite) + if (hw_dev->unite) module_data_abandon(params_vdev, new_params, 1); } vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); @@ -4735,7 +4735,7 @@ rkisp_params_cfg_v3x(struct rkisp_isp_params_vdev *params_vdev, goto unlock; new_params = (struct isp3x_isp_params_cfg *)(cur_buf->vaddr[0]); - if (hw_dev->is_unite) { + if (hw_dev->unite) { __isp_isr_meas_config(params_vdev, new_params + 1, type, 1); __isp_isr_other_config(params_vdev, new_params + 1, type, 1); __isp_isr_other_en(params_vdev, new_params + 1, type, 1); @@ -4748,7 +4748,7 @@ rkisp_params_cfg_v3x(struct rkisp_isp_params_vdev *params_vdev, if (type != RKISP_PARAMS_IMD) { new_params->module_cfg_update = 0; - if (hw_dev->is_unite) + if (hw_dev->unite) (new_params++)->module_cfg_update = 0; vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); cur_buf = NULL; @@ -4782,7 +4782,7 @@ rkisp_params_clear_fstflg(struct rkisp_isp_params_vdev *params_vdev) if (value & ISP3X_RAW3D_FST_FRAME) rkisp_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1, ISP3X_RAW3D_FST_FRAME, false); - if (hw_dev->is_unite) { + if (hw_dev->unite) { value = rkisp_next_read(dev, ISP3X_ISP_CTRL1, false); if (value & ISP3X_YNR_FST_FRAME) rkisp_next_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1, @@ -4857,7 +4857,7 @@ int rkisp_init_params_vdev_v3x(struct rkisp_isp_params_vdev *params_vdev) return -ENOMEM; size = sizeof(struct isp3x_isp_params_cfg); - if (ispdev->hw_dev->is_unite) + if (ispdev->hw_dev->unite) size *= 2; params_vdev->isp3x_params = vmalloc(size); if (!params_vdev->isp3x_params) { diff --git a/drivers/media/platform/rockchip/isp/isp_stats_v32.c b/drivers/media/platform/rockchip/isp/isp_stats_v32.c index bfc9624b45bd..cd0a4907846d 100644 --- a/drivers/media/platform/rockchip/isp/isp_stats_v32.c +++ b/drivers/media/platform/rockchip/isp/isp_stats_v32.c @@ -428,6 +428,8 @@ rkisp_stats_update_buf(struct rkisp_isp_stats_vdev *stats_vdev) struct rkisp_device *dev = stats_vdev->dev; struct rkisp_buffer *buf; unsigned long flags; + u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize; + u32 val = 0; spin_lock_irqsave(&stats_vdev->rd_lock, flags); if (!stats_vdev->nxt_buf && !list_empty(&stats_vdev->stat)) { @@ -439,18 +441,23 @@ rkisp_stats_update_buf(struct rkisp_isp_stats_vdev *stats_vdev) spin_unlock_irqrestore(&stats_vdev->rd_lock, flags); if (stats_vdev->nxt_buf) { - rkisp_write(dev, ISP3X_MI_3A_WR_BASE, stats_vdev->nxt_buf->buff_addr[0], false); + val = stats_vdev->nxt_buf->buff_addr[0]; v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev, "%s BASE:0x%x SHD:0x%x\n", - __func__, stats_vdev->nxt_buf->buff_addr[0], + __func__, val, isp3_stats_read(stats_vdev, ISP3X_MI_3A_WR_BASE)); if (!dev->hw_dev->is_single) { stats_vdev->cur_buf = stats_vdev->nxt_buf; stats_vdev->nxt_buf = NULL; } } else if (stats_vdev->stats_buf[0].mem_priv) { - rkisp_write(dev, ISP3X_MI_3A_WR_BASE, - stats_vdev->stats_buf[0].dma_addr, false); + val = stats_vdev->stats_buf[0].dma_addr; + } + + if (val) { + rkisp_write(dev, ISP3X_MI_3A_WR_BASE, val, false); + if (dev->hw_dev->unite) + rkisp_next_write(dev, ISP3X_MI_3A_WR_BASE, val + size / 2, false); } } @@ -533,14 +540,15 @@ static void rkisp_stats_send_meas(struct rkisp_isp_stats_vdev *stats_vdev, struct rkisp_isp_readout_work *meas_work) { - unsigned int cur_frame_id = -1; + struct rkisp_device *dev = stats_vdev->dev; + struct rkisp_hw_dev *hw = dev->hw_dev; + struct rkisp_isp_params_vdev *params_vdev = &dev->params_vdev; struct rkisp_buffer *cur_buf = stats_vdev->cur_buf; struct rkisp32_isp_stat_buffer *cur_stat_buf = NULL; struct rkisp_stats_ops_v32 *ops = (struct rkisp_stats_ops_v32 *)stats_vdev->priv_ops; - struct rkisp_isp_params_vdev *params_vdev = &stats_vdev->dev->params_vdev; - u32 size = sizeof(struct rkisp32_isp_stat_buffer); - int ret = 0; + u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize; + u32 cur_frame_id = meas_work->frame_id; bool is_dummy = false; unsigned long flags; @@ -548,97 +556,107 @@ rkisp_stats_send_meas(struct rkisp_isp_stats_vdev *stats_vdev, if (!cur_buf && stats_vdev->stats_buf[0].mem_priv) { rkisp_finish_buffer(stats_vdev->dev, &stats_vdev->stats_buf[0]); cur_stat_buf = stats_vdev->stats_buf[0].vaddr; - cur_stat_buf->frame_id = -1; + cur_stat_buf->frame_id = cur_frame_id; + cur_stat_buf->params_id = params_vdev->cur_frame_id; is_dummy = true; } else if (cur_buf) { cur_stat_buf = cur_buf->vaddr[0]; + cur_stat_buf->frame_id = cur_frame_id; + cur_stat_buf->params_id = params_vdev->cur_frame_id; } - /* config buf for next frame */ - stats_vdev->cur_buf = NULL; - if (stats_vdev->nxt_buf) { - stats_vdev->cur_buf = stats_vdev->nxt_buf; - stats_vdev->nxt_buf = NULL; - } - rkisp_stats_update_buf(stats_vdev); - cur_frame_id = meas_work->frame_id; + /* buffer done when frame of right handle */ + if (hw->unite == ISP_UNITE_ONE) { + if (dev->unite_index == ISP_UNITE_LEFT) { + cur_buf = NULL; + is_dummy = false; + } else if (cur_stat_buf) { + cur_stat_buf = (void *)cur_stat_buf + size / 2; + cur_stat_buf->frame_id = cur_frame_id; + cur_stat_buf->params_id = params_vdev->cur_frame_id; + } + } + + if (hw->unite != ISP_UNITE_ONE || dev->unite_index == ISP_UNITE_RIGHT) { + /* config buf for next frame */ + stats_vdev->cur_buf = NULL; + if (stats_vdev->nxt_buf) { + stats_vdev->cur_buf = stats_vdev->nxt_buf; + stats_vdev->nxt_buf = NULL; + } + rkisp_stats_update_buf(stats_vdev); + } } else { cur_buf = NULL; } if (meas_work->isp3a_ris & ISP3X_3A_RAWAWB) - ret |= ops->get_rawawb_meas(stats_vdev, cur_stat_buf); + ops->get_rawawb_meas(stats_vdev, cur_stat_buf); if (meas_work->isp3a_ris & ISP3X_3A_RAWAF || stats_vdev->af_meas_done_next) - ret |= ops->get_rawaf_meas(stats_vdev, cur_stat_buf); + ops->get_rawaf_meas(stats_vdev, cur_stat_buf); if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_BIG || stats_vdev->ae_meas_done_next) - ret |= ops->get_rawae3_meas(stats_vdev, cur_stat_buf); + ops->get_rawae3_meas(stats_vdev, cur_stat_buf); if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_BIG) - ret |= ops->get_rawhst3_meas(stats_vdev, cur_stat_buf); + ops->get_rawhst3_meas(stats_vdev, cur_stat_buf); if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_CH0) - ret |= ops->get_rawae0_meas(stats_vdev, cur_stat_buf); + ops->get_rawae0_meas(stats_vdev, cur_stat_buf); if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_CH1) - ret |= ops->get_rawae1_meas(stats_vdev, cur_stat_buf); + ops->get_rawae1_meas(stats_vdev, cur_stat_buf); if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_CH2) - ret |= ops->get_rawae2_meas(stats_vdev, cur_stat_buf); + ops->get_rawae2_meas(stats_vdev, cur_stat_buf); if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_CH0) - ret |= ops->get_rawhst0_meas(stats_vdev, cur_stat_buf); + ops->get_rawhst0_meas(stats_vdev, cur_stat_buf); if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_CH1) - ret |= ops->get_rawhst1_meas(stats_vdev, cur_stat_buf); + ops->get_rawhst1_meas(stats_vdev, cur_stat_buf); if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_CH2) - ret |= ops->get_rawhst2_meas(stats_vdev, cur_stat_buf); + ops->get_rawhst2_meas(stats_vdev, cur_stat_buf); if (meas_work->isp_ris & ISP3X_FRAME) { - ret |= ops->get_bls_stats(stats_vdev, cur_stat_buf); - ret |= ops->get_dhaz_stats(stats_vdev, cur_stat_buf); - ret |= ops->get_vsm_stats(stats_vdev, cur_stat_buf); + ops->get_bls_stats(stats_vdev, cur_stat_buf); + ops->get_dhaz_stats(stats_vdev, cur_stat_buf); + ops->get_vsm_stats(stats_vdev, cur_stat_buf); } - if (ret || (cur_stat_buf && !cur_stat_buf->meas_type)) { + if (is_dummy) { + spin_lock_irqsave(&stats_vdev->rd_lock, flags); + if (!list_empty(&stats_vdev->stat)) { + cur_buf = list_first_entry(&stats_vdev->stat, struct rkisp_buffer, queue); + list_del(&cur_buf->queue); + } + spin_unlock_irqrestore(&stats_vdev->rd_lock, flags); if (cur_buf) { - spin_lock_irqsave(&stats_vdev->rd_lock, flags); - list_add_tail(&cur_buf->queue, &stats_vdev->stat); - spin_unlock_irqrestore(&stats_vdev->rd_lock, flags); - } - } else { - if (is_dummy) { - spin_lock_irqsave(&stats_vdev->rd_lock, flags); - if (!list_empty(&stats_vdev->stat)) { - cur_buf = list_first_entry(&stats_vdev->stat, struct rkisp_buffer, queue); - list_del(&cur_buf->queue); - } else { - cur_stat_buf->frame_id = cur_frame_id; - cur_stat_buf->params_id = params_vdev->cur_frame_id; - } - spin_unlock_irqrestore(&stats_vdev->rd_lock, flags); - if (cur_buf) { - memcpy(cur_buf->vaddr[0], cur_stat_buf, size); - cur_stat_buf = cur_buf->vaddr[0]; - } - } - if (cur_buf && cur_stat_buf) { - cur_stat_buf->frame_id = cur_frame_id; - cur_stat_buf->params_id = params_vdev->cur_frame_id; - cur_stat_buf->params.info2ddr.buf_fd = -1; - cur_stat_buf->params.info2ddr.owner = 0; - rkisp_stats_info2ddr(stats_vdev, cur_stat_buf); - - vb2_set_plane_payload(&cur_buf->vb.vb2_buf, 0, size); - cur_buf->vb.sequence = cur_frame_id; - cur_buf->vb.vb2_buf.timestamp = meas_work->timestamp; - vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + memcpy(cur_buf->vaddr[0], stats_vdev->stats_buf[0].vaddr, size); + cur_stat_buf = cur_buf->vaddr[0]; } } + if (cur_buf && cur_stat_buf) { + cur_stat_buf->frame_id = cur_frame_id; + cur_stat_buf->params_id = params_vdev->cur_frame_id; + cur_stat_buf->params.info2ddr.buf_fd = -1; + cur_stat_buf->params.info2ddr.owner = 0; + rkisp_stats_info2ddr(stats_vdev, cur_stat_buf); + + vb2_set_plane_payload(&cur_buf->vb.vb2_buf, 0, size); + cur_buf->vb.sequence = cur_frame_id; + cur_buf->vb.vb2_buf.timestamp = meas_work->timestamp; + vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + } + v4l2_dbg(4, rkisp_debug, &dev->v4l2_dev, + "%s id:%d seq:%d params_id:%d ris:0x%x buf:%p meas_type:0x%x\n", + __func__, dev->unite_index, + cur_frame_id, params_vdev->cur_frame_id, meas_work->isp3a_ris, + cur_buf, !cur_stat_buf ? 0 : cur_stat_buf->meas_type); } static int @@ -890,12 +908,12 @@ static void rkisp_stats_send_meas_lite(struct rkisp_isp_stats_vdev *stats_vdev, struct rkisp_isp_readout_work *meas_work) { - struct rkisp_isp_params_vdev *params_vdev = &stats_vdev->dev->params_vdev; + struct rkisp_device *dev = stats_vdev->dev; + struct rkisp_isp_params_vdev *params_vdev = &dev->params_vdev; unsigned int cur_frame_id = meas_work->frame_id; struct rkisp_buffer *cur_buf = NULL; struct rkisp32_lite_stat_buffer *cur_stat_buf = NULL; u32 size = sizeof(struct rkisp32_lite_stat_buffer); - int ret = 0; spin_lock(&stats_vdev->rd_lock); if (!list_empty(&stats_vdev->stat)) { @@ -913,45 +931,42 @@ rkisp_stats_send_meas_lite(struct rkisp_isp_stats_vdev *stats_vdev, } if (meas_work->isp3a_ris & ISP3X_3A_RAWAWB) - ret |= rkisp_stats_get_rawawb_meas_lite(stats_vdev, cur_stat_buf); + rkisp_stats_get_rawawb_meas_lite(stats_vdev, cur_stat_buf); if (meas_work->isp3a_ris & ISP3X_3A_RAWAF || stats_vdev->af_meas_done_next) - ret |= rkisp_stats_get_rawaf_meas_lite(stats_vdev, cur_stat_buf); + rkisp_stats_get_rawaf_meas_lite(stats_vdev, cur_stat_buf); if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_BIG || stats_vdev->ae_meas_done_next) - ret |= rkisp_stats_get_rawae3_meas_lite(stats_vdev, cur_stat_buf); + rkisp_stats_get_rawae3_meas_lite(stats_vdev, cur_stat_buf); if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_BIG) - ret |= rkisp_stats_get_rawhst3_meas_lite(stats_vdev, cur_stat_buf); + rkisp_stats_get_rawhst3_meas_lite(stats_vdev, cur_stat_buf); if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_CH0) - ret |= rkisp_stats_get_rawaelite_meas_lite(stats_vdev, cur_stat_buf); + rkisp_stats_get_rawaelite_meas_lite(stats_vdev, cur_stat_buf); if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_CH0) - ret |= rkisp_stats_get_rawhstlite_meas_lite(stats_vdev, cur_stat_buf); + rkisp_stats_get_rawhstlite_meas_lite(stats_vdev, cur_stat_buf); if (meas_work->isp_ris & ISP3X_FRAME) { - ret |= rkisp_stats_get_bls_stats(stats_vdev, cur_stat_buf); - ret |= rkisp_stats_get_dhaz_stats(stats_vdev, cur_stat_buf); + rkisp_stats_get_bls_stats(stats_vdev, cur_stat_buf); + rkisp_stats_get_dhaz_stats(stats_vdev, cur_stat_buf); } if (cur_buf) { - if (ret || !cur_stat_buf->meas_type) { - unsigned long flags; - - spin_lock_irqsave(&stats_vdev->rd_lock, flags); - list_add_tail(&cur_buf->queue, &stats_vdev->stat); - spin_unlock_irqrestore(&stats_vdev->rd_lock, flags); - } else { - rkisp_stats_info2ddr(stats_vdev, cur_stat_buf); - vb2_set_plane_payload(&cur_buf->vb.vb2_buf, 0, size); - cur_buf->vb.sequence = cur_frame_id; - cur_buf->vb.vb2_buf.timestamp = meas_work->timestamp; - vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); - } + rkisp_stats_info2ddr(stats_vdev, cur_stat_buf); + vb2_set_plane_payload(&cur_buf->vb.vb2_buf, 0, size); + cur_buf->vb.sequence = cur_frame_id; + cur_buf->vb.vb2_buf.timestamp = meas_work->timestamp; + vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); } + v4l2_dbg(4, rkisp_debug, &dev->v4l2_dev, + "%s seq:%d params_id:%d ris:0x%x buf:%p meas_type:0x%x\n", + __func__, + cur_frame_id, params_vdev->cur_frame_id, meas_work->isp_ris, + cur_buf, !cur_stat_buf ? 0 : cur_stat_buf->meas_type); } static void @@ -1048,6 +1063,7 @@ void rkisp_stats_first_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev) { struct rkisp_device *dev = stats_vdev->dev; u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize; + u32 div = dev->hw_dev->unite ? 2 : 1; if (dev->isp_sdev.in_fmt.fmt_type == FMT_YUV) return; @@ -1059,8 +1075,8 @@ void rkisp_stats_first_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev) else memset(stats_vdev->stats_buf[0].vaddr, 0, size); rkisp_stats_update_buf(stats_vdev); - rkisp_write(dev, ISP3X_MI_DBR_WR_SIZE, size, false); - rkisp_set_bits(dev, ISP3X_SWS_CFG, 0, ISP3X_3A_DDR_WRITE_EN, false); + rkisp_unite_write(dev, ISP3X_MI_DBR_WR_SIZE, size / div, false); + rkisp_unite_set_bits(dev, ISP3X_SWS_CFG, 0, ISP3X_3A_DDR_WRITE_EN, false); if (stats_vdev->nxt_buf) { stats_vdev->cur_buf = stats_vdev->nxt_buf; stats_vdev->nxt_buf = NULL; @@ -1080,6 +1096,7 @@ void rkisp_stats_next_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev) void rkisp_init_stats_vdev_v32(struct rkisp_isp_stats_vdev *stats_vdev) { + int mult = stats_vdev->dev->hw_dev->unite ? 2 : 1; u32 size; stats_vdev->vdev_fmt.fmt.meta.dataformat = @@ -1087,13 +1104,13 @@ void rkisp_init_stats_vdev_v32(struct rkisp_isp_stats_vdev *stats_vdev) if (stats_vdev->dev->isp_ver == ISP_V32) { stats_vdev->priv_ops = &stats_ddr_ops_v32; stats_vdev->rd_stats_from_ddr = true; - size = sizeof(struct rkisp32_isp_stat_buffer); + size = ALIGN(sizeof(struct rkisp32_isp_stat_buffer), 16); } else { stats_vdev->priv_ops = NULL; stats_vdev->rd_stats_from_ddr = false; size = sizeof(struct rkisp32_lite_stat_buffer); } - stats_vdev->vdev_fmt.fmt.meta.buffersize = size; + stats_vdev->vdev_fmt.fmt.meta.buffersize = size * mult; stats_vdev->ops = &rkisp_isp_stats_ops_tbl; } diff --git a/drivers/media/platform/rockchip/isp/isp_stats_v3x.c b/drivers/media/platform/rockchip/isp/isp_stats_v3x.c index 7b21a80b038b..12bac619bb88 100644 --- a/drivers/media/platform/rockchip/isp/isp_stats_v3x.c +++ b/drivers/media/platform/rockchip/isp/isp_stats_v3x.c @@ -1038,7 +1038,7 @@ rkisp_stats_send_meas_v3x(struct rkisp_isp_stats_vdev *stats_vdev, ret |= ops->get_dhaz_stats(stats_vdev, cur_stat_buf, 0); } - if (stats_vdev->dev->hw_dev->is_unite) { + if (stats_vdev->dev->hw_dev->unite) { size *= 2; if (cur_buf) { cur_stat_buf++; @@ -1086,7 +1086,7 @@ rkisp_stats_isr_v3x(struct rkisp_isp_stats_vdev *stats_vdev, { struct rkisp_device *dev = stats_vdev->dev; struct rkisp_hw_dev *hw = dev->hw_dev; - void __iomem *base = !hw->is_unite ? + void __iomem *base = hw->unite != ISP_UNITE_TWO ? hw->base_addr : hw->base_next_addr; struct rkisp_isp_readout_work work; u32 iq_isr_mask = ISP3X_SIAWB_DONE | ISP3X_SIAF_FIN | @@ -1138,7 +1138,7 @@ rkisp_stats_isr_v3x(struct rkisp_isp_stats_vdev *stats_vdev, rkisp_write(dev, ISP3X_MI_3A_WR_BASE, stats_vdev->stats_buf[wr_buf_idx].dma_addr, false); - if (dev->hw_dev->is_unite) + if (dev->hw_dev->unite) rkisp_next_write(dev, ISP3X_MI_3A_WR_BASE, stats_vdev->stats_buf[wr_buf_idx].dma_addr + ISP3X_RD_STATS_BUF_SIZE, false); @@ -1178,7 +1178,7 @@ static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = { void rkisp_stats_first_ddr_config_v3x(struct rkisp_isp_stats_vdev *stats_vdev) { struct rkisp_device *dev = stats_vdev->dev; - int i, mult = dev->hw_dev->is_unite ? 2 : 1; + int i, mult = dev->hw_dev->unite ? 2 : 1; if (dev->isp_sdev.in_fmt.fmt_type == FMT_YUV) return; @@ -1199,14 +1199,12 @@ void rkisp_stats_first_ddr_config_v3x(struct rkisp_isp_stats_vdev *stats_vdev) stats_vdev->wr_buf_idx = 0; rkisp_unite_write(dev, ISP3X_MI_DBR_WR_SIZE, - ISP3X_RD_STATS_BUF_SIZE, - false, dev->hw_dev->is_unite); + ISP3X_RD_STATS_BUF_SIZE, false); rkisp_unite_set_bits(dev, ISP3X_SWS_CFG, 0, - ISP3X_3A_DDR_WRITE_EN, false, - dev->hw_dev->is_unite); + ISP3X_3A_DDR_WRITE_EN, false); rkisp_write(dev, ISP3X_MI_3A_WR_BASE, stats_vdev->stats_buf[0].dma_addr, false); - if (dev->hw_dev->is_unite) + if (dev->hw_dev->unite) rkisp_next_write(dev, ISP3X_MI_3A_WR_BASE, stats_vdev->stats_buf[0].dma_addr + ISP3X_RD_STATS_BUF_SIZE, false); @@ -1220,7 +1218,7 @@ err: void rkisp_init_stats_vdev_v3x(struct rkisp_isp_stats_vdev *stats_vdev) { - int mult = stats_vdev->dev->hw_dev->is_unite ? 2 : 1; + int mult = stats_vdev->dev->hw_dev->unite ? 2 : 1; stats_vdev->vdev_fmt.fmt.meta.dataformat = V4L2_META_FMT_RK_ISP1_STAT_3A; diff --git a/drivers/media/platform/rockchip/isp/procfs.c b/drivers/media/platform/rockchip/isp/procfs.c index 6a8e9b2906d7..a0b38ff1f97a 100644 --- a/drivers/media/platform/rockchip/isp/procfs.c +++ b/drivers/media/platform/rockchip/isp/procfs.c @@ -933,7 +933,7 @@ static int isp_show(struct seq_file *p, void *v) break; case ISP_V30: if (IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V30)) { - if (dev->hw_dev->is_unite) + if (dev->hw_dev->unite) isp30_unite_show(dev, p); else isp30_show(dev, p); @@ -963,7 +963,7 @@ static int isp_show(struct seq_file *p, void *v) msecs_to_jiffies(1000)); seq_printf(p, "****************HW REG*Ret:%d**************\n", ret); for (i = 0; i < ISP3X_RAWAWB_RAM_DATA_BASE; i += 16) { - if (!dev->hw_dev->is_unite) { + if (dev->hw_dev->unite != ISP_UNITE_TWO) { seq_printf(p, "%04x: %08x %08x %08x %08x\n", i, rkisp_read(dev, i, true), rkisp_read(dev, i + 4, true), diff --git a/drivers/media/platform/rockchip/isp/regs.c b/drivers/media/platform/rockchip/isp/regs.c index a808d34f6d65..17af5ef7349b 100644 --- a/drivers/media/platform/rockchip/isp/regs.c +++ b/drivers/media/platform/rockchip/isp/regs.c @@ -45,8 +45,7 @@ void rkisp_disable_dcrop(struct rkisp_stream *stream, bool async) if (async && dev->hw_dev->is_single) val = CIF_DUAL_CROP_GEN_CFG_UPD; - rkisp_unite_set_bits(dev, stream->config->dual_crop.ctrl, - mask, val, false, dev->hw_dev->is_unite); + rkisp_unite_set_bits(dev, stream->config->dual_crop.ctrl, mask, val, false); } void rkisp_config_dcrop(struct rkisp_stream *stream, @@ -54,7 +53,7 @@ void rkisp_config_dcrop(struct rkisp_stream *stream, { struct rkisp_device *dev = stream->ispdev; u32 val = stream->config->dual_crop.yuvmode_mask; - bool is_unite = dev->hw_dev->is_unite; + bool is_unite = !!dev->hw_dev->unite; struct v4l2_rect tmp = *rect; u32 reg; @@ -69,9 +68,9 @@ void rkisp_config_dcrop(struct rkisp_stream *stream, rkisp_write(dev, reg, tmp.width, false); reg = stream->config->dual_crop.v_offset; - rkisp_unite_write(dev, reg, tmp.top, false, is_unite); + rkisp_unite_write(dev, reg, tmp.top, false); reg = stream->config->dual_crop.v_size; - rkisp_unite_write(dev, reg, tmp.height, false, is_unite); + rkisp_unite_write(dev, reg, tmp.height, false); if (async && dev->hw_dev->is_single) val |= CIF_DUAL_CROP_GEN_CFG_UPD; @@ -149,8 +148,7 @@ static void update_rsz_shadow(struct rkisp_stream *stream, bool async) if (async && dev->hw_dev->is_single) val = CIF_RSZ_CTRL_CFG_UPD_AUTO; - rkisp_unite_set_bits(dev, stream->config->rsz.ctrl, 0, - val, false, dev->hw_dev->is_unite); + rkisp_unite_set_bits(dev, stream->config->rsz.ctrl, 0, val, false); } static void set_scale(struct rkisp_stream *stream, struct v4l2_rect *in_y, @@ -220,17 +218,8 @@ static void set_scale(struct rkisp_stream *stream, struct v4l2_rect *in_y, rkisp_write(dev, scale_vc_addr, scale_vc, false); } - if (dev->hw_dev->is_unite) { - u32 hy_size_reg = stream->id == RKISP_STREAM_MP ? - ISP3X_MAIN_RESIZE_HY_SIZE : ISP3X_SELF_RESIZE_HY_SIZE; - u32 hc_size_reg = stream->id == RKISP_STREAM_MP ? - ISP3X_MAIN_RESIZE_HC_SIZE : ISP3X_SELF_RESIZE_HC_SIZE; - u32 hy_offs_mi_reg = stream->id == RKISP_STREAM_MP ? - ISP3X_MAIN_RESIZE_HY_OFFS_MI : ISP3X_SELF_RESIZE_HY_OFFS_MI; - u32 hc_offs_mi_reg = stream->id == RKISP_STREAM_MP ? - ISP3X_MAIN_RESIZE_HC_OFFS_MI : ISP3X_SELF_RESIZE_HC_OFFS_MI; - u32 in_crop_offs_reg = stream->id == RKISP_STREAM_MP ? - ISP3X_MAIN_RESIZE_IN_CROP_OFFSET : ISP3X_SELF_RESIZE_IN_CROP_OFFSET; + if (dev->hw_dev->unite) { + u32 hy_size_reg, hc_size_reg, hy_offs_mi_reg, hc_offs_mi_reg, in_crop_offs_reg; u32 isp_in_w = in_y->width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL; u32 scl_w = out_y->width / 2; u32 left_y = scale_hy == 1 ? scl_w : DIV_ROUND_UP(scl_w * 65536, scale_hy); @@ -249,6 +238,34 @@ static void set_scale(struct rkisp_stream *stream, struct v4l2_rect *in_y, u32 right_scl_in_y; u32 right_scl_in_c; + switch (stream->id) { + case RKISP_STREAM_MP: + hy_size_reg = ISP3X_MAIN_RESIZE_HY_SIZE; + hc_size_reg = ISP3X_MAIN_RESIZE_HC_SIZE; + hy_offs_mi_reg = ISP3X_MAIN_RESIZE_HY_OFFS_MI; + hc_offs_mi_reg = ISP3X_MAIN_RESIZE_HC_OFFS_MI; + in_crop_offs_reg = ISP3X_MAIN_RESIZE_IN_CROP_OFFSET; + break; + case RKISP_STREAM_SP: + hy_size_reg = ISP3X_SELF_RESIZE_HY_SIZE; + hc_size_reg = ISP3X_SELF_RESIZE_HC_SIZE; + hy_offs_mi_reg = ISP3X_SELF_RESIZE_HY_OFFS_MI; + hc_offs_mi_reg = ISP3X_SELF_RESIZE_HC_OFFS_MI; + in_crop_offs_reg = ISP3X_SELF_RESIZE_IN_CROP_OFFSET; + break; + case RKISP_STREAM_BP: + hy_size_reg = ISP32_BP_RESIZE_HY_SIZE; + hc_size_reg = ISP32_BP_RESIZE_HC_SIZE; + hy_offs_mi_reg = ISP32_BP_RESIZE_HY_OFFS_MI; + hc_offs_mi_reg = ISP32_BP_RESIZE_HC_OFFS_MI; + in_crop_offs_reg = ISP32_BP_RESIZE_IN_CROP_OFFSET; + break; + default: + v4l2_warn(&dev->v4l2_dev, "%s no support unite for stream:%d\n", + __func__, stream->id); + return; + } + if (right_crop_y < RKMOUDLE_UNITE_EXTEND_PIXEL) { u32 reg; @@ -362,7 +379,6 @@ void rkisp_config_rsz(struct rkisp_stream *stream, struct v4l2_rect *in_y, { struct rkisp_device *dev = stream->ispdev; int i = 0; - bool is_unite = dev->hw_dev->is_unite; if (dev->isp_ver == ISP_V32_L && stream->id == RKISP_STREAM_SP) { set_bilinear_scale(stream, in_y, in_c, out_y, out_c, async); @@ -377,8 +393,8 @@ void rkisp_config_rsz(struct rkisp_stream *stream, struct v4l2_rect *in_y, /* Linear interpolation */ for (i = 0; i < 64; i++) { - rkisp_unite_write(dev, stream->config->rsz.scale_lut_addr, i, true, is_unite); - rkisp_unite_write(dev, stream->config->rsz.scale_lut, i, true, is_unite); + rkisp_unite_write(dev, stream->config->rsz.scale_lut_addr, i, true); + rkisp_unite_write(dev, stream->config->rsz.scale_lut, i, true); } set_scale(stream, in_y, in_c, out_y, out_c); @@ -388,9 +404,7 @@ void rkisp_config_rsz(struct rkisp_stream *stream, struct v4l2_rect *in_y, void rkisp_disable_rsz(struct rkisp_stream *stream, bool async) { - bool is_unite = stream->ispdev->hw_dev->is_unite; - - rkisp_unite_write(stream->ispdev, stream->config->rsz.ctrl, 0, false, is_unite); + rkisp_unite_write(stream->ispdev, stream->config->rsz.ctrl, 0, false); if (stream->ispdev->isp_ver == ISP_V32_L && stream->id == RKISP_STREAM_SP) return; update_rsz_shadow(stream, async); diff --git a/drivers/media/platform/rockchip/isp/regs.h b/drivers/media/platform/rockchip/isp/regs.h index b24eba03f57c..d263a640a154 100644 --- a/drivers/media/platform/rockchip/isp/regs.h +++ b/drivers/media/platform/rockchip/isp/regs.h @@ -1753,7 +1753,7 @@ static inline void mi_set_cr_offset(struct rkisp_stream *stream, int val) static inline void mi_frame_end_int_enable(struct rkisp_stream *stream) { struct rkisp_hw_dev *hw = stream->ispdev->hw_dev; - void __iomem *base = !hw->is_unite ? + void __iomem *base = hw->unite != ISP_UNITE_TWO ? hw->base_addr : hw->base_next_addr; void __iomem *addr = base + CIF_MI_IMSC; @@ -1763,7 +1763,7 @@ static inline void mi_frame_end_int_enable(struct rkisp_stream *stream) static inline void mi_frame_end_int_disable(struct rkisp_stream *stream) { struct rkisp_hw_dev *hw = stream->ispdev->hw_dev; - void __iomem *base = !hw->is_unite ? + void __iomem *base = hw->unite != ISP_UNITE_TWO ? hw->base_addr : hw->base_next_addr; void __iomem *addr = base + CIF_MI_IMSC; @@ -1773,7 +1773,7 @@ static inline void mi_frame_end_int_disable(struct rkisp_stream *stream) static inline void mi_frame_end_int_clear(struct rkisp_stream *stream) { struct rkisp_hw_dev *hw = stream->ispdev->hw_dev; - void __iomem *base = !hw->is_unite ? + void __iomem *base = hw->unite != ISP_UNITE_TWO ? hw->base_addr : hw->base_next_addr; void __iomem *addr = base + CIF_MI_ICR; @@ -1783,7 +1783,6 @@ static inline void mi_frame_end_int_clear(struct rkisp_stream *stream) static inline void stream_data_path(struct rkisp_stream *stream) { struct rkisp_device *dev = stream->ispdev; - bool is_unite = dev->hw_dev->is_unite; u32 dpcl = 0; if (stream->id == RKISP_STREAM_MP) @@ -1792,7 +1791,7 @@ static inline void stream_data_path(struct rkisp_stream *stream) dpcl |= CIF_VI_DPCL_CHAN_MODE_SP; if (dpcl) - rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true, is_unite); + rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true); } static inline void mp_set_uv_swap(void __iomem *base) @@ -1914,16 +1913,15 @@ static inline void sp_mi_ctrl_autoupdate_en(void __iomem *base) static inline void force_cfg_update(struct rkisp_device *dev) { u32 val = CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_CTRL_INIT_BASE_EN; - bool is_unite = dev->hw_dev->is_unite; if (dev->isp_ver == ISP_V21) { val |= rkisp_read_reg_cache(dev, CIF_MI_CTRL); rkisp_write(dev, CIF_MI_CTRL, val, true); } dev->hw_dev->is_mi_update = true; - rkisp_unite_set_bits(dev, CIF_MI_CTRL, 0, val, false, is_unite); + rkisp_unite_set_bits(dev, CIF_MI_CTRL, 0, val, false); val = CIF_MI_INIT_SOFT_UPD; - rkisp_unite_write(dev, CIF_MI_INIT, val, true, is_unite); + rkisp_unite_write(dev, CIF_MI_INIT, val, true); } static inline void dmatx0_ctrl(void __iomem *base, u32 val) diff --git a/drivers/media/platform/rockchip/isp/regs_v2x.h b/drivers/media/platform/rockchip/isp/regs_v2x.h index e4800632890f..2f3c1009ae4e 100644 --- a/drivers/media/platform/rockchip/isp/regs_v2x.h +++ b/drivers/media/platform/rockchip/isp/regs_v2x.h @@ -2700,7 +2700,7 @@ static inline void mi_raw_length(struct rkisp_stream *stream) stream->out_fmt.plane_fmt[0].bytesperline, is_direct); if (stream->ispdev->isp_ver == ISP_V21 || stream->ispdev->isp_ver == ISP_V30) rkisp_set_bits(stream->ispdev, MI_RD_CTRL2, 0, BIT(30), false); - if (stream->ispdev->hw_dev->is_unite) { + if (stream->ispdev->hw_dev->unite) { rkisp_next_write(stream->ispdev, stream->config->mi.length, stream->out_fmt.plane_fmt[0].bytesperline, is_direct); rkisp_next_set_bits(stream->ispdev, MI_RD_CTRL2, 0, BIT(30), false); diff --git a/drivers/media/platform/rockchip/isp/regs_v3x.h b/drivers/media/platform/rockchip/isp/regs_v3x.h index af325bd17a46..5e4c85710ee1 100644 --- a/drivers/media/platform/rockchip/isp/regs_v3x.h +++ b/drivers/media/platform/rockchip/isp/regs_v3x.h @@ -343,6 +343,15 @@ #define ISP32_BP_RESIZE_PHASE_HC_SHD (ISP32_BP_RESIZE_BASE + 0x0004c) #define ISP32_BP_RESIZE_PHASE_VY_SHD (ISP32_BP_RESIZE_BASE + 0x00050) #define ISP32_BP_RESIZE_PHASE_VC_SHD (ISP32_BP_RESIZE_BASE + 0x00054) +#define ISP32_BP_RESIZE_HY_SIZE (ISP32_BP_RESIZE_BASE + 0x00058) +#define ISP32_BP_RESIZE_HC_SIZE (ISP32_BP_RESIZE_BASE + 0x0005c) +#define ISP32_BP_RESIZE_HY_OFFS_MI (ISP32_BP_RESIZE_BASE + 0x00060) +#define ISP32_BP_RESIZE_HC_OFFS_MI (ISP32_BP_RESIZE_BASE + 0x00064) +#define ISP32_BP_RESIZE_HY_SIZE_SHD (ISP32_BP_RESIZE_BASE + 0x00068) +#define ISP32_BP_RESIZE_HC_SIZE_SHD (ISP32_BP_RESIZE_BASE + 0x0006c) +#define ISP32_BP_RESIZE_HY_OFFS_MI_SHD (ISP32_BP_RESIZE_BASE + 0x00070) +#define ISP32_BP_RESIZE_HC_OFFS_MI_SHD (ISP32_BP_RESIZE_BASE + 0x00074) +#define ISP32_BP_RESIZE_IN_CROP_OFFSET (ISP32_BP_RESIZE_BASE + 0x00078) #define ISP3X_SELF_RESIZE_BASE 0x00001000 #define ISP3X_SELF_RESIZE_CTRL (ISP3X_SELF_RESIZE_BASE + 0x00000) diff --git a/drivers/media/platform/rockchip/isp/rkisp.c b/drivers/media/platform/rockchip/isp/rkisp.c index fb65cd1b11dd..6bab4e5c3a07 100644 --- a/drivers/media/platform/rockchip/isp/rkisp.c +++ b/drivers/media/platform/rockchip/isp/rkisp.c @@ -213,17 +213,16 @@ int rkisp_align_sensor_resolution(struct rkisp_device *dev, max_h = CIF_ISP_INPUT_H_MAX_V21; break; case ISP_V30: - if (dev->hw_dev->is_unite) { - max_w = CIF_ISP_INPUT_W_MAX_V30_UNITE; - max_h = CIF_ISP_INPUT_H_MAX_V30_UNITE; - } else { - max_w = CIF_ISP_INPUT_W_MAX_V30; - max_h = CIF_ISP_INPUT_H_MAX_V30; - } + max_w = dev->hw_dev->unite ? + CIF_ISP_INPUT_W_MAX_V30_UNITE : CIF_ISP_INPUT_W_MAX_V30; + max_h = dev->hw_dev->unite ? + CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30; break; case ISP_V32: - max_w = CIF_ISP_INPUT_W_MAX_V32; - max_h = CIF_ISP_INPUT_H_MAX_V32; + max_w = dev->hw_dev->unite ? + CIF_ISP_INPUT_W_MAX_V32_UNITE : CIF_ISP_INPUT_W_MAX_V32; + max_h = dev->hw_dev->unite ? + CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32; break; case ISP_V32_L: max_w = CIF_ISP_INPUT_W_MAX_V32_L; @@ -530,7 +529,7 @@ static void rkisp_dvfs(struct rkisp_device *dev) /* set isp clock rate */ rkisp_set_clk_rate(hw->clks[0], hw->clk_rate_tbl[i].clk_rate * 1000000UL); - if (hw->is_unite) + if (hw->unite == ISP_UNITE_TWO) rkisp_set_clk_rate(hw->clks[5], hw->clk_rate_tbl[i].clk_rate * 1000000UL); /* aclk equal to core clk */ if (dev->isp_ver == ISP_V32) @@ -563,7 +562,7 @@ static void rkisp_multi_overflow_hdl(struct rkisp_device *dev, bool on) writel(0, hw->base_addr + ISP3X_MPFBC_CTRL); writel(0, hw->base_addr + ISP3X_MI_BP_WR_CTRL); writel(0xc, hw->base_addr + ISP3X_SWS_CFG); - if (hw->is_unite) { + if (hw->unite == ISP_UNITE_TWO) { writel(0, hw->base_next_addr + ISP3X_MI_WR_CTRL); writel(0, hw->base_next_addr + ISP3X_MPFBC_CTRL); writel(0, hw->base_next_addr + ISP3X_MI_BP_WR_CTRL); @@ -575,7 +574,7 @@ static void rkisp_multi_overflow_hdl(struct rkisp_device *dev, bool on) writel(0, hw->base_addr + ISP32_MI_MPDS_WR_CTRL); } } - rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true, hw->is_unite); + rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true); } /* @@ -595,7 +594,8 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo hw->cur_dev_id = dev->dev_id; rkisp_dmarx_get_frame(dev, &cur_frame_id, NULL, NULL, true); - if (hw->is_multi_overflow && is_try) + /* isp process the same frame */ + if (is_try) goto run_next; val = 0; @@ -625,13 +625,12 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo } if (rd_mode != dev->rd_mode) { - rkisp_unite_set_bits(dev, ISP_HDRMGE_BASE, ISP_HDRMGE_MODE_MASK, - val, false, hw->is_unite); + rkisp_unite_set_bits(dev, ISP_HDRMGE_BASE, ISP_HDRMGE_MODE_MASK, val, false); dev->skip_frame = 2; is_upd = true; } - if (dev->isp_ver == ISP_V20 && dev->dmarx_dev.trigger == T_MANUAL && !is_try) { + if (dev->isp_ver == ISP_V20 && dev->dmarx_dev.trigger == T_MANUAL) { if (dev->rd_mode != rd_mode && dev->br_dev.en) { tmp = dev->isp_sdev.in_crop.height; val = rkisp_read(dev, CIF_DUAL_CROP_CTRL, false); @@ -652,12 +651,15 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo } dev->rd_mode = rd_mode; - rkisp_params_first_cfg(&dev->params_vdev, &dev->isp_sdev.in_fmt, - dev->isp_sdev.quantization); - rkisp_params_cfg(params_vdev, cur_frame_id); - rkisp_config_cmsk(dev); - rkisp_stream_frame_start(dev, 0); - if (!hw->is_single && !is_try) { + if (hw->unite != ISP_UNITE_ONE || dev->unite_index == ISP_UNITE_LEFT) { + rkisp_params_first_cfg(&dev->params_vdev, &dev->isp_sdev.in_fmt, + dev->isp_sdev.quantization); + rkisp_params_cfg(params_vdev, cur_frame_id); + rkisp_config_cmsk(dev); + rkisp_stream_frame_start(dev, 0); + } + + if (!hw->is_single) { /* multi sensor need to reset isp resize mode if scale up */ val = 0; if (rkisp_read(dev, ISP3X_MAIN_RESIZE_CTRL, true) & 0xf0) @@ -693,7 +695,7 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo } else { if (dev->isp_ver == ISP_V32_L) rkisp_write(dev, ISP32_SELF_SCALE_UPDATE, ISP32_SCALE_FORCE_UPD, true); - rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true, hw->is_unite); + rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true); } /* sensor mode & index */ if (dev->isp_ver >= ISP_V21) { @@ -704,7 +706,7 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo else val |= ISP21_SENSOR_MODE(dev->multi_mode); writel(val, hw->base_addr + ISP_ACQ_H_OFFS); - if (hw->is_unite) + if (hw->unite == ISP_UNITE_TWO) writel(val, hw->base_next_addr + ISP_ACQ_H_OFFS); v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev, "sensor mode:%d index:%d | 0x%x\n", @@ -724,49 +726,15 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo else dev->rdbk_cnt_x1++; dev->rdbk_cnt++; - - rkisp_params_cfgsram(params_vdev); - params_vdev->rdbk_times = dma2frm + 1; + if (dev->isp_ver == ISP_V20) + params_vdev->rdbk_times = dma2frm + 1; run_next: - if (hw->is_multi_overflow && !dev->is_first_double) { - stats_vdev->rdbk_drop = false; - if (dev->sw_rd_cnt) { - /* the frame first running to off mi to save bandwidth */ - rkisp_multi_overflow_hdl(dev, false); - - /* FST_FRAME no to read sram thumb */ - val = ISP3X_YNR_FST_FRAME | ISP3X_DHAZ_FST_FRAME; - if (dev->isp_ver == ISP_V32) - val |= ISP32_SHP_FST_FRAME; - else - val |= ISP3X_CNR_FST_FRAME; - rkisp_unite_set_bits(dev, ISP3X_ISP_CTRL1, 0, val, false, hw->is_unite); - /* ADRC low iir thumb weight for first sensor switch */ - val = rkisp_read_reg_cache(dev, ISP3X_DRC_IIRWG_GAIN); - val &= ~ISP3X_DRC_IIR_WEIGHT_MASK; - writel(val, hw->base_addr + ISP3X_DRC_IIRWG_GAIN); - /* ADRC iir5x5 and cur3x3 weight */ - val = rkisp_read_reg_cache(dev, ISP3X_DRC_EXPLRATIO); - val &= ~ISP3X_DRC_WEIPRE_FRAME_MASK; - writel(val, hw->base_addr + ISP3X_DRC_EXPLRATIO); - /* YNR_THUMB_MIX_CUR_EN for thumb read addr to 0 */ - val = rkisp_read_reg_cache(dev, ISP3X_YNR_GLOBAL_CTRL); - val |= ISP3X_YNR_THUMB_MIX_CUR_EN; - writel(val, hw->base_addr + ISP3X_YNR_GLOBAL_CTRL); - if (dev->isp_ver == ISP_V21 || dev->isp_ver == ISP_V30) { - /* CNR_THUMB_MIX_CUR_EN for thumb read addr to 0 */ - val = rkisp_read_reg_cache(dev, ISP3X_CNR_CTRL); - val |= ISP3X_CNR_THUMB_MIX_CUR_EN; - writel(val, hw->base_addr + ISP3X_CNR_CTRL); - if (hw->is_unite) - writel(val, hw->base_next_addr + ISP3X_CNR_CTRL); - } - - params_vdev->rdbk_times += dev->sw_rd_cnt; - stats_vdev->rdbk_drop = true; - is_upd = true; - } else if (is_try) { + rkisp_params_cfgsram(params_vdev); + stats_vdev->rdbk_drop = false; + if (dev->is_frame_double) { + is_upd = true; + if (is_try) { /* the frame second running to on mi */ rkisp_multi_overflow_hdl(dev, true); rkisp_update_regs(dev, ISP_LDCH_BASE, ISP_LDCH_BASE); @@ -776,13 +744,53 @@ run_next: val |= ISP32_SHP_FST_FRAME; else val |= ISP3X_CNR_FST_FRAME; - rkisp_unite_clear_bits(dev, ISP3X_ISP_CTRL1, val, false, hw->is_unite); + rkisp_unite_clear_bits(dev, ISP3X_ISP_CTRL1, val, false); val = rkisp_read_reg_cache(dev, ISP3X_DRC_IIRWG_GAIN); writel(val, hw->base_addr + ISP3X_DRC_IIRWG_GAIN); + if (hw->unite == ISP_UNITE_TWO) + writel(val, hw->base_next_addr + ISP3X_DRC_IIRWG_GAIN); val = rkisp_read_reg_cache(dev, ISP3X_DRC_EXPLRATIO); writel(val, hw->base_addr + ISP3X_DRC_EXPLRATIO); + if (hw->unite == ISP_UNITE_TWO) + writel(val, hw->base_next_addr + ISP3X_DRC_EXPLRATIO); + } else { + /* the frame first running to off mi to save bandwidth */ + rkisp_multi_overflow_hdl(dev, false); - is_upd = true; + /* FST_FRAME no to read sram thumb */ + val = ISP3X_YNR_FST_FRAME | ISP3X_DHAZ_FST_FRAME; + if (dev->isp_ver == ISP_V32) + val |= ISP32_SHP_FST_FRAME; + else + val |= ISP3X_CNR_FST_FRAME; + rkisp_unite_set_bits(dev, ISP3X_ISP_CTRL1, 0, val, false); + /* ADRC low iir thumb weight for first sensor switch */ + val = rkisp_read_reg_cache(dev, ISP3X_DRC_IIRWG_GAIN); + val &= ~ISP3X_DRC_IIR_WEIGHT_MASK; + writel(val, hw->base_addr + ISP3X_DRC_IIRWG_GAIN); + if (hw->unite == ISP_UNITE_TWO) + writel(val, hw->base_next_addr + ISP3X_DRC_IIRWG_GAIN); + /* ADRC iir5x5 and cur3x3 weight */ + val = rkisp_read_reg_cache(dev, ISP3X_DRC_EXPLRATIO); + val &= ~ISP3X_DRC_WEIPRE_FRAME_MASK; + writel(val, hw->base_addr + ISP3X_DRC_EXPLRATIO); + if (hw->unite == ISP_UNITE_TWO) + writel(val, hw->base_next_addr + ISP3X_DRC_EXPLRATIO); + /* YNR_THUMB_MIX_CUR_EN for thumb read addr to 0 */ + val = rkisp_read_reg_cache(dev, ISP3X_YNR_GLOBAL_CTRL); + val |= ISP3X_YNR_THUMB_MIX_CUR_EN; + writel(val, hw->base_addr + ISP3X_YNR_GLOBAL_CTRL); + if (hw->unite == ISP_UNITE_TWO) + writel(val, hw->base_next_addr + ISP3X_YNR_GLOBAL_CTRL); + if (dev->isp_ver == ISP_V21 || dev->isp_ver == ISP_V30) { + /* CNR_THUMB_MIX_CUR_EN for thumb read addr to 0 */ + val = rkisp_read_reg_cache(dev, ISP3X_CNR_CTRL); + val |= ISP3X_CNR_THUMB_MIX_CUR_EN; + writel(val, hw->base_addr + ISP3X_CNR_CTRL); + if (hw->unite == ISP_UNITE_TWO) + writel(val, hw->base_next_addr + ISP3X_CNR_CTRL); + } + stats_vdev->rdbk_drop = true; } } @@ -791,13 +799,13 @@ run_next: */ if (hw->is_single && is_upd && rkisp_read_reg_cache(dev, ISP_3DLUT_UPDATE) & 0x1) { - rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 0, true, hw->is_unite); + rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 0, true); is_3dlut_upd = true; } if (is_upd) { val = rkisp_read(dev, ISP_CTRL, false); val |= CIF_ISP_CTRL_ISP_CFG_UPD; - rkisp_unite_write(dev, ISP_CTRL, val, true, hw->is_unite); + rkisp_unite_write(dev, ISP_CTRL, val, true); /* bayer pat after ISP_CFG_UPD for multi sensor to read lsc r/g/b table */ rkisp_update_regs(dev, ISP3X_ISP_CTRL1, ISP3X_ISP_CTRL1); /* fix ldch multi sensor case: @@ -810,12 +818,12 @@ run_next: udelay(50); val &= ~(BIT(0) | BIT(31)); writel(val, hw->base_addr + ISP_LDCH_BASE); - if (hw->is_unite) + if (hw->unite == ISP_UNITE_TWO) writel(val, hw->base_next_addr + ISP_LDCH_BASE); } } if (is_3dlut_upd) - rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 1, true, hw->is_unite); + rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 1, true); /* if output stream enable, wait it end */ val = rkisp_read(dev, CIF_MI_CTRL_SHD, true); @@ -849,10 +857,10 @@ run_next: if (dev->isp_ver > ISP_V20) dma2frm = dev->sw_rd_cnt; v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev, - "readback frame:%d time:%d 0x%x\n", - cur_frame_id, dma2frm + 1, val); + "readback frame:%d time:%d 0x%x try:%d\n", + cur_frame_id, dma2frm + 1, val, is_try); if (!hw->is_shutdown) - rkisp_unite_write(dev, CSI2RX_CTRL0, val, true, hw->is_unite); + rkisp_unite_write(dev, CSI2RX_CTRL0, val, true); } static void rkisp_fast_switch_rx_buf(struct rkisp_device *dev, bool is_current) @@ -906,6 +914,12 @@ static void rkisp_rdbk_trigger_handle(struct rkisp_device *dev, u32 cmd) isp = dev; is_try = true; times = 0; + if (hw->unite == ISP_UNITE_ONE) { + if (dev->sw_rd_cnt < 2) + isp->unite_index = ISP_UNITE_RIGHT; + if (!hw->is_multi_overflow || (dev->sw_rd_cnt & 0x1)) + is_try = false; + } goto end; } hw->is_idle = true; @@ -955,17 +969,40 @@ static void rkisp_rdbk_trigger_handle(struct rkisp_device *dev, u32 cmd) times = t.times; hw->cur_dev_id = id; hw->is_idle = false; + /* this frame will read count by isp */ isp->sw_rd_cnt = 0; - if (hw->is_multi_overflow && (hw->pre_dev_id != id)) { + /* frame double for multi camera resolution out of hardware limit + * first for HW save this camera information, and second to output image + */ + isp->is_frame_double = false; + if (hw->is_multi_overflow && + (hw->unite == ISP_UNITE_ONE || + (hw->pre_dev_id != -1 && hw->pre_dev_id != id))) { + isp->is_frame_double = true; isp->sw_rd_cnt = 1; times = 0; } + /* resolution out of hardware limit + * frame is vertically divided into left and right + */ + isp->unite_index = ISP_UNITE_LEFT; + if (hw->unite == ISP_UNITE_ONE) { + isp->sw_rd_cnt *= 2; + isp->sw_rd_cnt += 1; + } + /* first frame handle twice for thunderboot + * first output stats to AIQ and wait new params to run second + */ if (isp->is_pre_on && t.frame_id == 0) { isp->is_first_double = true; isp->skip_frame = 1; - isp->sw_rd_cnt = 0; + if (hw->unite != ISP_UNITE_ONE) { + isp->sw_rd_cnt = 0; + isp->is_frame_double = false; + } rkisp_fast_switch_rx_buf(isp, false); } + isp->params_vdev.rdbk_times = isp->sw_rd_cnt + 1; } end: spin_unlock_irqrestore(&hw->rdbk_lock, lock_flags); @@ -1023,12 +1060,6 @@ void rkisp_check_idle(struct rkisp_device *dev, u32 irq) { u32 val = 0; - if (dev->hw_dev->is_multi_overflow && - dev->sw_rd_cnt && - irq & ISP_FRAME_END && - !dev->is_first_double) - goto end; - dev->irq_ends |= (irq & dev->irq_ends_mask); v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev, "%s irq:0x%x ends:0x%x mask:0x%x\n", @@ -1043,6 +1074,9 @@ void rkisp_check_idle(struct rkisp_device *dev, u32 irq) !IS_HDR_RDBK(dev->rd_mode)) return; + if (dev->sw_rd_cnt) + goto end; + if (dev->is_first_double) { rkisp_fast_switch_rx_buf(dev, true); dev->skip_frame = 0; @@ -1109,26 +1143,25 @@ static void rkisp_config_ism(struct rkisp_device *dev) { struct v4l2_rect *out_crop = &dev->isp_sdev.out_crop; u32 width = out_crop->width, mult = 1; - bool is_unite = dev->hw_dev->is_unite; + u32 unite = dev->hw_dev->unite; /* isp2.0 no ism */ if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || dev->isp_ver == ISP_V32_L) return; - if (is_unite) + if (unite) width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL; - rkisp_unite_write(dev, CIF_ISP_IS_RECENTER, 0, false, is_unite); - rkisp_unite_write(dev, CIF_ISP_IS_MAX_DX, 0, false, is_unite); - rkisp_unite_write(dev, CIF_ISP_IS_MAX_DY, 0, false, is_unite); - rkisp_unite_write(dev, CIF_ISP_IS_DISPLACE, 0, false, is_unite); - rkisp_unite_write(dev, CIF_ISP_IS_H_OFFS, out_crop->left, false, is_unite); - rkisp_unite_write(dev, CIF_ISP_IS_V_OFFS, out_crop->top, false, is_unite); - rkisp_unite_write(dev, CIF_ISP_IS_H_SIZE, width, false, is_unite); + rkisp_unite_write(dev, CIF_ISP_IS_RECENTER, 0, false); + rkisp_unite_write(dev, CIF_ISP_IS_MAX_DX, 0, false); + rkisp_unite_write(dev, CIF_ISP_IS_MAX_DY, 0, false); + rkisp_unite_write(dev, CIF_ISP_IS_DISPLACE, 0, false); + rkisp_unite_write(dev, CIF_ISP_IS_H_OFFS, out_crop->left, false); + rkisp_unite_write(dev, CIF_ISP_IS_V_OFFS, out_crop->top, false); + rkisp_unite_write(dev, CIF_ISP_IS_H_SIZE, width, false); if (dev->cap_dev.stream[RKISP_STREAM_SP].interlaced) mult = 2; - rkisp_unite_write(dev, CIF_ISP_IS_V_SIZE, out_crop->height / mult, - false, is_unite); + rkisp_unite_write(dev, CIF_ISP_IS_V_SIZE, out_crop->height / mult, false); if (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) return; @@ -1430,20 +1463,18 @@ static void rkisp_config_color_space(struct rkisp_device *dev) for (i = 0; i < 9; i++) rkisp_unite_write(dev, CIF_ISP_CC_COEFF_0 + i * 4, - *(coeff + i), false, dev->hw_dev->is_unite); + *(coeff + i), false); val = rkisp_read_reg_cache(dev, CIF_ISP_CTRL); if (dev->isp_sdev.quantization == V4L2_QUANTIZATION_FULL_RANGE) rkisp_unite_write(dev, CIF_ISP_CTRL, val | CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA | - CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA, - false, dev->hw_dev->is_unite); + CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA, false); else rkisp_unite_write(dev, CIF_ISP_CTRL, val & ~(CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA | - CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA), - false, dev->hw_dev->is_unite); + CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA), false); } static void rkisp_config_cmsk_single(struct rkisp_device *dev, @@ -1642,7 +1673,7 @@ static void rkisp_config_cmsk(struct rkisp_device *dev) cfg = dev->cmsk_cfg; spin_unlock_irqrestore(&dev->cmsk_lock, lock_flags); - if (!dev->hw_dev->is_unite) + if (!dev->hw_dev->unite) rkisp_config_cmsk_single(dev, &cfg); else rkisp_config_cmsk_dual(dev, &cfg); @@ -1657,7 +1688,7 @@ static int rkisp_config_isp(struct rkisp_device *dev) struct ispsd_out_fmt *out_fmt; struct v4l2_rect *in_crop; struct rkisp_sensor_info *sensor; - bool is_unite = dev->hw_dev->is_unite; + bool is_unite = !!dev->hw_dev->unite; u32 isp_ctrl = 0; u32 irq_mask = 0; u32 signal = 0; @@ -1687,22 +1718,20 @@ static int rkisp_config_isp(struct rkisp_device *dev) in_fmt->mbus_code == MEDIA_BUS_FMT_Y10_1X10 || in_fmt->mbus_code == MEDIA_BUS_FMT_Y12_1X12) { if (dev->isp_ver >= ISP_V20) - rkisp_unite_write(dev, ISP_DEBAYER_CONTROL, - 0, false, is_unite); + rkisp_unite_write(dev, ISP_DEBAYER_CONTROL, 0, false); else rkisp_write(dev, CIF_ISP_DEMOSAIC, - CIF_ISP_DEMOSAIC_BYPASS | - CIF_ISP_DEMOSAIC_TH(0xc), false); + CIF_ISP_DEMOSAIC_BYPASS | + CIF_ISP_DEMOSAIC_TH(0xc), false); } else { if (dev->isp_ver >= ISP_V20) rkisp_unite_write(dev, ISP_DEBAYER_CONTROL, SW_DEBAYER_EN | SW_DEBAYER_FILTER_G_EN | - SW_DEBAYER_FILTER_C_EN, - false, is_unite); + SW_DEBAYER_FILTER_C_EN, false); else rkisp_write(dev, CIF_ISP_DEMOSAIC, - CIF_ISP_DEMOSAIC_TH(0xc), false); + CIF_ISP_DEMOSAIC_TH(0xc), false); } if (sensor && sensor->mbus.type == V4L2_MBUS_BT656) @@ -1755,38 +1784,31 @@ static int rkisp_config_isp(struct rkisp_device *dev) if (rkisp_read_reg_cache(dev, CIF_ISP_CTRL) & ISP32_MIR_ENABLE) isp_ctrl |= ISP32_MIR_ENABLE; - rkisp_unite_write(dev, CIF_ISP_CTRL, isp_ctrl, false, is_unite); + rkisp_unite_write(dev, CIF_ISP_CTRL, isp_ctrl, false); acq_prop |= signal | in_fmt->yuv_seq | CIF_ISP_ACQ_PROP_BAYER_PAT(in_fmt->bayer_pat) | CIF_ISP_ACQ_PROP_FIELD_SEL_ALL; - rkisp_unite_write(dev, CIF_ISP_ACQ_PROP, acq_prop, false, is_unite); - rkisp_unite_write(dev, CIF_ISP_ACQ_NR_FRAMES, 0, true, is_unite); + rkisp_unite_write(dev, CIF_ISP_ACQ_PROP, acq_prop, false); + rkisp_unite_write(dev, CIF_ISP_ACQ_NR_FRAMES, 0, true); if (is_unite) width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL; /* Acquisition Size */ - rkisp_unite_write(dev, CIF_ISP_ACQ_H_OFFS, acq_mult * in_crop->left, - false, is_unite); - rkisp_unite_write(dev, CIF_ISP_ACQ_V_OFFS, in_crop->top, - false, is_unite); - rkisp_unite_write(dev, CIF_ISP_ACQ_H_SIZE, acq_mult * width, - false, is_unite); + rkisp_unite_write(dev, CIF_ISP_ACQ_H_OFFS, acq_mult * in_crop->left, false); + rkisp_unite_write(dev, CIF_ISP_ACQ_V_OFFS, in_crop->top, false); + rkisp_unite_write(dev, CIF_ISP_ACQ_H_SIZE, acq_mult * width, false); /* ISP Out Area differ with ACQ is only FIFO, so don't crop in this */ - rkisp_unite_write(dev, CIF_ISP_OUT_H_OFFS, 0, true, is_unite); - rkisp_unite_write(dev, CIF_ISP_OUT_V_OFFS, 0, true, is_unite); - rkisp_unite_write(dev, CIF_ISP_OUT_H_SIZE, width, false, is_unite); + rkisp_unite_write(dev, CIF_ISP_OUT_H_OFFS, 0, true); + rkisp_unite_write(dev, CIF_ISP_OUT_V_OFFS, 0, true); + rkisp_unite_write(dev, CIF_ISP_OUT_H_SIZE, width, false); if (dev->cap_dev.stream[RKISP_STREAM_SP].interlaced) { - rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height / 2, - false, is_unite); - rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height / 2, - false, is_unite); + rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height / 2, false); + rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height / 2, false); } else { - rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height + extend_line, - false, is_unite); - rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height + extend_line, - false, is_unite); + rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height + extend_line, false); + rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height + extend_line, false); } /* interrupt mask */ @@ -1795,7 +1817,7 @@ static int rkisp_config_isp(struct rkisp_device *dev) irq_mask |= ISP2X_LSC_LUT_ERR; if (dev->is_pre_on) irq_mask |= CIF_ISP_FRAME_IN; - rkisp_unite_write(dev, CIF_ISP_IMSC, irq_mask, true, is_unite); + rkisp_unite_write(dev, CIF_ISP_IMSC, irq_mask, true); if ((dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21) && @@ -1950,8 +1972,7 @@ static int rkisp_config_path(struct rkisp_device *dev) if (dev->isp_ver == ISP_V32) dpcl |= BIT(0); - rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true, - dev->hw_dev->is_unite); + rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true); return ret; } @@ -2048,9 +2069,9 @@ static int rkisp_isp_stop(struct rkisp_device *dev) v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev, "%s refcnt:%d\n", __func__, - atomic_read(&dev->hw_dev->refcnt)); + atomic_read(&hw->refcnt)); - if (atomic_read(&dev->hw_dev->refcnt) > 1) + if (atomic_read(&hw->refcnt) > 1) goto end; /* * ISP(mi) stop in mi frame end -> Stop ISP(mipi) -> @@ -2106,7 +2127,7 @@ static int rkisp_isp_stop(struct rkisp_device *dev) val = readl(base + CIF_ISP_CTRL); writel(val | CIF_ISP_CTRL_ISP_CFG_UPD, base + CIF_ISP_CTRL); - if (hw->is_unite) + if (hw->unite == ISP_UNITE_TWO) rkisp_next_write(dev, CIF_ISP_CTRL, val | CIF_ISP_CTRL_ISP_CFG_UPD, true); @@ -2123,11 +2144,11 @@ static int rkisp_isp_stop(struct rkisp_device *dev) safe_rate = hw->clk_rate_tbl[0].clk_rate * 1000000UL; if (old_rate > safe_rate) { rkisp_set_clk_rate(hw->clks[0], safe_rate); - if (hw->is_unite) + if (hw->unite == ISP_UNITE_TWO) rkisp_set_clk_rate(hw->clks[5], safe_rate); udelay(100); } - rkisp_soft_reset(dev->hw_dev, false); + rkisp_soft_reset(hw, false); } if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) { @@ -2138,14 +2159,15 @@ static int rkisp_isp_stop(struct rkisp_device *dev) writel(0, base + CIF_ISP_CSI0_MASK3); } else if (dev->isp_ver >= ISP_V20) { writel(0, base + CSI2RX_CSI2_RESETN); - if (hw->is_unite) + if (hw->unite == ISP_UNITE_TWO) rkisp_next_write(dev, CSI2RX_CSI2_RESETN, 0, true); } hw->is_dvfs = false; hw->is_runing = false; - dev->hw_dev->is_idle = true; - dev->hw_dev->is_mi_update = false; + hw->is_idle = true; + hw->is_mi_update = false; + hw->pre_dev_id = -1; end: dev->irq_ends_mask = 0; dev->hdr.op_mode = 0; @@ -2196,12 +2218,9 @@ static int rkisp_isp_start(struct rkisp_device *dev) val = dev->isp_sdev.out_crop.height / 15; val = dev->cap_dev.wait_line / val; val = ISP3X_RAWAF_INELINE0(val) | ISP3X_RAWAF_INTLINE0_EN; - rkisp_unite_write(dev, ISP3X_RAWAF_INT_LINE, - val, false, dev->hw_dev->is_unite); - rkisp_unite_set_bits(dev, ISP_ISP3A_IMSC, 0, - ISP2X_3A_RAWAF, false, dev->hw_dev->is_unite); - rkisp_unite_clear_bits(dev, CIF_ISP_IMSC, - ISP2X_LSC_LUT_ERR, false, dev->hw_dev->is_unite); + rkisp_unite_write(dev, ISP3X_RAWAF_INT_LINE, val, false); + rkisp_unite_set_bits(dev, ISP_ISP3A_IMSC, 0, ISP2X_3A_RAWAF, false); + rkisp_unite_clear_bits(dev, CIF_ISP_IMSC, ISP2X_LSC_LUT_ERR, false); dev->rawaf_irq_cnt = 0; } } @@ -2229,7 +2248,7 @@ static int rkisp_isp_start(struct rkisp_device *dev) val |= NOC_HURRY_PRIORITY(2) | NOC_HURRY_W_MODE(2) | NOC_HURRY_R_MODE(1); if (atomic_read(&dev->hw_dev->refcnt) > 1) is_direct = false; - rkisp_unite_write(dev, CIF_ISP_CTRL, val, is_direct, dev->hw_dev->is_unite); + rkisp_unite_write(dev, CIF_ISP_CTRL, val, is_direct); rkisp_clear_reg_cache_bits(dev, CIF_ISP_CTRL, CIF_ISP_CTRL_ISP_CFG_UPD); dev->isp_err_cnt = 0; @@ -2709,14 +2728,16 @@ static int rkisp_isp_sd_get_selection(struct v4l2_subdev *sd, max_h = CIF_ISP_INPUT_H_MAX_V21; break; case ISP_V30: - max_w = dev->hw_dev->is_unite ? + max_w = dev->hw_dev->unite ? CIF_ISP_INPUT_W_MAX_V30_UNITE : CIF_ISP_INPUT_W_MAX_V30; - max_h = dev->hw_dev->is_unite ? + max_h = dev->hw_dev->unite ? CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30; break; case ISP_V32: - max_w = CIF_ISP_INPUT_W_MAX_V32; - max_h = CIF_ISP_INPUT_H_MAX_V32; + max_w = dev->hw_dev->unite ? + CIF_ISP_INPUT_W_MAX_V32_UNITE : CIF_ISP_INPUT_W_MAX_V32; + max_h = dev->hw_dev->unite ? + CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32; break; case ISP_V32_L: max_w = CIF_ISP_INPUT_W_MAX_V32_L; @@ -2978,7 +2999,7 @@ static void rkisp_rx_qbuf_online(struct rkisp_stream *stream, u32 val = pool->buf.buff_addr[RKISP_PLANE_Y]; rkisp_write(dev, stream->config->mi.y_base_ad_init, val, false); - if (dev->hw_dev->is_unite) { + if (dev->hw_dev->unite == ISP_UNITE_TWO) { u32 offs = stream->out_fmt.width / 2 - RKMOUDLE_UNITE_EXTEND_PIXEL; if (stream->memory) @@ -3454,7 +3475,7 @@ static int rkisp_get_info(struct rkisp_device *dev, struct rkisp_isp_info *info) if (dev->is_bigmode) mode |= RKISP_ISP_BIGMODE; info->mode = mode; - if (dev->hw_dev->is_unite) + if (dev->hw_dev->unite) info->act_width = in_crop->width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL; else info->act_width = in_crop->width; @@ -3741,7 +3762,7 @@ static void rkisp_isp_sd_init_default_fmt(struct rkisp_isp_subdev *isp_sd) struct ispsd_in_fmt *in_fmt = &isp_sd->in_fmt; struct ispsd_out_fmt *out_fmt = &isp_sd->out_fmt; - *in_fmt = rkisp_isp_input_formats[0]; + *in_fmt = rkisp_isp_input_formats[8]; in_frm->width = RKISP_DEFAULT_WIDTH; in_frm->height = RKISP_DEFAULT_HEIGHT; in_frm->code = in_fmt->mbus_code; @@ -4068,7 +4089,7 @@ void rkisp_isp_isr(unsigned int isp_mis, struct rkisp_device *dev) { struct rkisp_hw_dev *hw = dev->hw_dev; - void __iomem *base = !hw->is_unite ? + void __iomem *base = hw->unite != ISP_UNITE_TWO ? hw->base_addr : hw->base_next_addr; unsigned int isp_mis_tmp = 0; unsigned int isp_err = 0; @@ -4089,7 +4110,7 @@ void rkisp_isp_isr(unsigned int isp_mis, if (isp3a_mis & ISP2X_3A_RAWAE_BIG && dev->params_vdev.rdbk_times > 0) writel(BIT(31), base + RAWAE_BIG1_BASE + RAWAE_BIG_CTRL); - if (hw->is_unite) { + if (hw->unite == ISP_UNITE_TWO) { u32 val = rkisp_read(dev, ISP3X_ISP_RIS, true); if (val) { @@ -4125,7 +4146,7 @@ void rkisp_isp_isr(unsigned int isp_mis, */ if (!dev->hw_dev->is_single) { writel(0, hw->base_addr + ISP_3DLUT_UPDATE); - if (hw->is_unite) + if (hw->unite == ISP_UNITE_TWO) writel(0, hw->base_next_addr + ISP_3DLUT_UPDATE); } rkisp_stats_rdbk_enable(&dev->stats_vdev, true); diff --git a/drivers/media/platform/rockchip/isp/rkisp.h b/drivers/media/platform/rockchip/isp/rkisp.h index 0522163e7f4a..54f32b9685c3 100644 --- a/drivers/media/platform/rockchip/isp/rkisp.h +++ b/drivers/media/platform/rockchip/isp/rkisp.h @@ -57,6 +57,8 @@ #define CIF_ISP_INPUT_H_MAX_V30_UNITE 6144 #define CIF_ISP_INPUT_W_MAX_V32 3072 #define CIF_ISP_INPUT_H_MAX_V32 1728 +#define CIF_ISP_INPUT_W_MAX_V32_UNITE 3840 +#define CIF_ISP_INPUT_H_MAX_V32_UNITE 2160 #define CIF_ISP_INPUT_W_MAX_V32_L 4224 #define CIF_ISP_INPUT_H_MAX_V32_L 3136 #define CIF_ISP_INPUT_W_MIN 272 From 09647ffee6834d65e49ece37ede1b64c057e9e2b Mon Sep 17 00:00:00 2001 From: Weiwen Chen Date: Thu, 7 Sep 2023 14:19:02 +0800 Subject: [PATCH 14/17] ARM: configs: rockchip: Update rv1106-tb-nofastae.config Updated by: make ARCH=arm rv1106_defconfig cp .config rv1106.config make ARCH=arm rv1106_defconfig rv1106-tb.config rv1106-battery-ipc.config rv1106-tb-nofastae.config make ARCH=arm menuconfig ./scripts/diffconfig -m rv1106.config .config > arch/arm/configs/rv1106-tb-nofastae.config Signed-off-by: Weiwen Chen Change-Id: Id29b5d03d011497f7e7e479cae4edc77e04e0902 --- arch/arm/configs/rv1106-tb-nofastae.config | 418 +++++++++++++++++++++ 1 file changed, 418 insertions(+) diff --git a/arch/arm/configs/rv1106-tb-nofastae.config b/arch/arm/configs/rv1106-tb-nofastae.config index c0142d4101f3..ec668078748d 100644 --- a/arch/arm/configs/rv1106-tb-nofastae.config +++ b/arch/arm/configs/rv1106-tb-nofastae.config @@ -1,3 +1,421 @@ +CONFIG_BLK_DEV_INITRD=y +CONFIG_CRC16=m +CONFIG_CRYPTO=y +CONFIG_DAX=y +CONFIG_EROFS_FS=y +# CONFIG_ETHERNET is not set +CONFIG_EXT4_FS=m +CONFIG_FILE_LOCKING=y +CONFIG_JFFS2_FS=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_XZ is not set +CONFIG_LIBCRC32C=y +CONFIG_MAILBOX=y +# CONFIG_MDIO_DEVICE is not set +CONFIG_MMC=y +CONFIG_MSDOS_FS=m +CONFIG_MSDOS_PARTITION=y +CONFIG_MTD_BLOCK=m +CONFIG_NLS_CODEPAGE_936=m +# CONFIG_PHYLIB is not set +CONFIG_PHY_ROCKCHIP_CSI2_DPHY=y +CONFIG_PRINTK_TIME_FROM_ARM_ARCH_TIMER=y +CONFIG_ROCKCHIP_DVBM=y +CONFIG_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_ROCKCHIP_MULTI_RGA=y +CONFIG_ROCKCHIP_RAMDISK=y +CONFIG_ROCKCHIP_RGA_PROC_FS=y +CONFIG_ROCKCHIP_THUNDER_BOOT=y +CONFIG_ROCKCHIP_VENDOR_STORAGE=m +# CONFIG_SLUB_SYSFS is not set +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SND_SIMPLE_CARD_UTILS=m +CONFIG_SND_SOC_ROCKCHIP=m +CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m +CONFIG_SND_SOC_RV1106=m +CONFIG_SPI=y +CONFIG_VFAT_FS=m +CONFIG_VIDEO_ROCKCHIP_CIF=y +CONFIG_VIDEO_ROCKCHIP_ISP=y +CONFIG_VIDEO_SC230AI=y +CONFIG_VIDEO_SC301IOT=y +CONFIG_VIDEO_SC3338=y +# CONFIG_AD2S1200 is not set +# CONFIG_AD2S1210 is not set +# CONFIG_AD2S90 is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5449 is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5592R is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_AD5686_SPI is not set +# CONFIG_AD5755 is not set +# CONFIG_AD5758 is not set +# CONFIG_AD5761 is not set +# CONFIG_AD5764 is not set +# CONFIG_AD5770R is not set +# CONFIG_AD5791 is not set +# CONFIG_AD7124 is not set +# CONFIG_AD7192 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7280 is not set +# CONFIG_AD7292 is not set +# CONFIG_AD7298 is not set +# CONFIG_AD7303 is not set +# CONFIG_AD7476 is not set +# CONFIG_AD7606_IFACE_SPI is not set +# CONFIG_AD7766 is not set +# CONFIG_AD7768_1 is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7816 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +# CONFIG_AD7949 is not set +# CONFIG_AD8366 is not set +# CONFIG_AD8801 is not set +# CONFIG_AD9523 is not set +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# CONFIG_ADF4350 is not set +# CONFIG_ADF4371 is not set +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADIS16240 is not set +# CONFIG_ADIS16260 is not set +# CONFIG_ADIS16400 is not set +# CONFIG_ADIS16460 is not set +# CONFIG_ADIS16475 is not set +# CONFIG_ADIS16480 is not set +# CONFIG_ADXL345_SPI is not set +# CONFIG_ADXL372_SPI is not set +# CONFIG_ADXRS290 is not set +# CONFIG_ADXRS450 is not set +# CONFIG_AFE4403 is not set +# CONFIG_ALTERA_MBOX is not set +# CONFIG_ARM_CRYPTO is not set +# CONFIG_ARM_MHU is not set +# CONFIG_ARM_SCMI_PROTOCOL is not set +# CONFIG_ARM_SCPI_PROTOCOL is not set +# CONFIG_AS3935 is not set +# CONFIG_BMA220 is not set +# CONFIG_BMC150_MAGN_SPI is not set +# CONFIG_BMI160_SPI is not set +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_AEGIS128 is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_AES_TI is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_BLAKE2B is not set +# CONFIG_CRYPTO_BLAKE2S is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_CFB is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_CMAC is not set +# CONFIG_CRYPTO_CRC32 is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_CURVE25519 is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_DRBG_MENU is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_ECDH is not set +# CONFIG_CRYPTO_ECHAINIV is not set +# CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_ESSIV is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_CRYPTO_JITTERENTROPY is not set +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_LIB_CHACHA is not set +# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_MANAGER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEQIV is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SM2 is not set +# CONFIG_CRYPTO_SM3 is not set +# CONFIG_CRYPTO_SM4 is not set +# CONFIG_CRYPTO_STREEBOG is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_USER is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_VMAC is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_XXHASH is not set +# CONFIG_CRYPTO_ZSTD is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EROFS_FS_DEBUG is not set +# CONFIG_EROFS_FS_XATTR is not set +# CONFIG_EROFS_FS_ZIP is not set +# CONFIG_EXT4_DEBUG is not set +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +CONFIG_EXT4_USE_FOR_EXT2=y +# CONFIG_EZX_PCAP is not set +CONFIG_FAT_DEFAULT_CODEPAGE=936 +CONFIG_FAT_DEFAULT_IOCHARSET="cp936" +CONFIG_FAT_DEFAULT_UTF8=y +CONFIG_FAT_FS=m +CONFIG_FS_DAX=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=m +# CONFIG_FXOS8700_SPI is not set +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX3191X is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_XRA1403 is not set +# CONFIG_HI8435 is not set +# CONFIG_IIO_SSP_SENSORHUB is not set +# CONFIG_INITCALL_ASYNC is not set +# CONFIG_INITRAMFS_FORCE is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INITRD_ASYNC=y +# CONFIG_INV_ICM42600_SPI is not set +# CONFIG_INV_MPU6050_SPI is not set +CONFIG_JBD2=m +# CONFIG_JBD2_DEBUG is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_LZO is not set +# CONFIG_JFFS2_RTIME is not set +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_JFFS2_SUMMARY is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_LATTICE_ECP3_CONFIG is not set +CONFIG_LIB_MEMNEQ=y +# CONFIG_LTC1660 is not set +# CONFIG_LTC2496 is not set +# CONFIG_LTC2632 is not set +# CONFIG_LTC2983 is not set +# CONFIG_MAILBOX_TEST is not set +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_MAX1027 is not set +# CONFIG_MAX11100 is not set +# CONFIG_MAX1118 is not set +# CONFIG_MAX1241 is not set +# CONFIG_MAX31856 is not set +# CONFIG_MAX5481 is not set +# CONFIG_MAX5487 is not set +# CONFIG_MAXIM_THERMOCOUPLE is not set +# CONFIG_MCP320X is not set +# CONFIG_MCP3911 is not set +# CONFIG_MCP41010 is not set +# CONFIG_MCP4131 is not set +# CONFIG_MCP4922 is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_INTEL_M10_BMC is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_RK806_SPI is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_MMA7455_SPI is not set +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_MINORS=32 +# CONFIG_MMC_CQHCI is not set +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_DW=m +# CONFIG_MMC_DW_BLUEFIELD is not set +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set +# CONFIG_MMC_DW_K3 is not set +CONFIG_MMC_DW_PLTFM=m +CONFIG_MMC_DW_ROCKCHIP=m +# CONFIG_MMC_HSQ is not set +# CONFIG_MMC_MTK is not set +CONFIG_MMC_QUEUE_DEPTH=1 +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_TEST is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MOXTET is not set +# CONFIG_MPL115_SPI is not set +CONFIG_MTD_BLKDEVS=m +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_SPI_NAND is not set +CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_SPI_NOR_MISC=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_PI433 is not set +# CONFIG_PL320_MBOX is not set +# CONFIG_PLATFORM_MHU is not set +# CONFIG_PWRSEQ_EMMC is not set +# CONFIG_PWRSEQ_SIMPLE is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_GZIP is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_ZSTD is not set +CONFIG_REGMAP_SPI=y +# CONFIG_REGULATOR_TPS6524X is not set # CONFIG_ROCKCHIP_MBOX is not set +# CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE is not set +CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE=m +CONFIG_ROCKCHIP_RGA_DEBUGGER=y +CONFIG_ROCKCHIP_THUNDER_BOOT_MMC=y # CONFIG_ROCKCHIP_THUNDER_BOOT_SERVICE is not set +CONFIG_ROCKCHIP_THUNDER_BOOT_SFC=y +# CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_SCA3000 is not set +# CONFIG_SDIO_UART is not set +# CONFIG_SENSORS_HMC5843_SPI is not set +# CONFIG_SENSORS_RM3100_SPI is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SND_SOC_ADAU1761_SPI is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_ES8328_SPI is not set +# CONFIG_SND_SOC_PCM179X_SPI is not set +# CONFIG_SND_SOC_PCM186X_SPI is not set +# CONFIG_SND_SOC_PCM3060_SPI is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_ZL38060 is not set +# CONFIG_SND_SPI is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AMD is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_DEBUG is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SPI_MUX is not set +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_NXP_FLEXSPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_ROCKCHIP is not set +CONFIG_SPI_ROCKCHIP_SFC=y +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_SIFIVE is not set +# CONFIG_SPI_SLAVE is not set +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set +# CONFIG_TI_ADC0832 is not set +# CONFIG_TI_ADC084S021 is not set +# CONFIG_TI_ADC108S102 is not set +# CONFIG_TI_ADC12138 is not set +# CONFIG_TI_ADC128S052 is not set +# CONFIG_TI_ADC161S626 is not set +# CONFIG_TI_ADS124S08 is not set +# CONFIG_TI_ADS7950 is not set +# CONFIG_TI_ADS8344 is not set +# CONFIG_TI_ADS8688 is not set +# CONFIG_TI_DAC082S085 is not set +# CONFIG_TI_DAC7311 is not set +# CONFIG_TI_DAC7612 is not set +# CONFIG_TI_TLC4541 is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_VIDEO_GS1662 is not set +# CONFIG_VIDEO_ROCKCHIP_PREISP is not set # CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP is not set +# CONFIG_VIDEO_S5C73M3 is not set +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y From f3c467eca054dce58701cd4b845419abfd26ea01 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Fri, 1 Sep 2023 18:33:24 +0800 Subject: [PATCH 15/17] media: rockchip: vicap: fixes rv1126/rk3568 bt1120/bt656 buffer timestamp due to rv1126/rk3566 dvp only support one channel of frame start interrupt, unable to obtain accurate timestamp for each channel, change it to use frame end time Signed-off-by: Zefa Chen Change-Id: I564a9235e684f5558d7cc8a1e2665952b750a9c0 --- drivers/media/platform/rockchip/cif/capture.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/rockchip/cif/capture.c b/drivers/media/platform/rockchip/cif/capture.c index 6f2df9432e16..bbd2731382ee 100644 --- a/drivers/media/platform/rockchip/cif/capture.c +++ b/drivers/media/platform/rockchip/cif/capture.c @@ -8586,7 +8586,11 @@ static void rkcif_buf_done_prepare(struct rkcif_stream *stream, if (active_buf) { vb_done = &active_buf->vb; - vb_done->vb2_buf.timestamp = stream->readout.fs_timestamp; + if (cif_dev->chip_id < CHIP_RK3588_CIF && + cif_dev->active_sensor->mbus.type == V4L2_MBUS_BT656) + vb_done->vb2_buf.timestamp = stream->readout.fe_timestamp; + else + vb_done->vb2_buf.timestamp = stream->readout.fs_timestamp; vb_done->sequence = stream->frame_idx - 1; active_buf->fe_timestamp = ktime_get_ns(); if (stream->is_line_wake_up) { @@ -8907,6 +8911,10 @@ static void rkcif_update_stream(struct rkcif_device *cif_dev, if (ret && cif_dev->chip_id < CHIP_RK3588_CIF) return; } + if (cif_dev->chip_id < CHIP_RK3588_CIF && + cif_dev->active_sensor->mbus.type == V4L2_MBUS_BT656 && + stream->id != 0) + stream->frame_idx++; if (!stream->is_line_wake_up && stream->dma_en & RKCIF_DMAEN_BY_VICAP) rkcif_buf_done_prepare(stream, active_buf, mipi_id, 0); From 3f737cad2df6cb08fdc38dbb5af7bc2ec7cb5b6b Mon Sep 17 00:00:00 2001 From: Steven Liu Date: Thu, 7 Sep 2023 19:56:13 +0800 Subject: [PATCH 16/17] arm64: dts: rockchip: rk3562: Add arm_pmu label Signed-off-by: Steven Liu Change-Id: Idd6448f7121c021848f6b848bd27bd0c520ae9b1 --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index 30faecda68e2..ecb54d453df0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -352,7 +352,7 @@ }; }; - arm-pmu { + arm_pmu: arm-pmu { compatible = "arm,cortex-a53-pmu"; interrupts = , , From abd61db9d69e17126436259705e58fd6cc74a8f5 Mon Sep 17 00:00:00 2001 From: Zhihuan He Date: Thu, 4 Feb 2021 09:18:35 +0800 Subject: [PATCH 17/17] edac: rockchip: add edac driver Signed-off-by: Zhihuan He Change-Id: I56a568718e47f86f7f152ec38f66e0ccbe99c6c1 --- drivers/edac/Kconfig | 7 + drivers/edac/Makefile | 1 + drivers/edac/rockchip_edac.c | 358 ++++++++++++++++++++++++++++ include/soc/rockchip/rockchip_sip.h | 1 + 4 files changed, 367 insertions(+) create mode 100644 drivers/edac/rockchip_edac.c diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 7a47680d6f07..68a58c139d89 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -537,4 +537,11 @@ config EDAC_DMC520 Support for error detection and correction on the SoCs with ARM DMC-520 DRAM controller. +config EDAC_ROCKCHIP + tristate "Rockchip DDR ECC" + depends on ARCH_ROCKCHIP && HAVE_ARM_SMCCC + help + Support for error detection and correction on the + rockchip family of SOCs. + endif # EDAC diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 3a849168780d..e25719ff1e19 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -89,3 +89,4 @@ obj-$(CONFIG_EDAC_QCOM) += qcom_edac.o obj-$(CONFIG_EDAC_ASPEED) += aspeed_edac.o obj-$(CONFIG_EDAC_BLUEFIELD) += bluefield_edac.o obj-$(CONFIG_EDAC_DMC520) += dmc520_edac.o +obj-$(CONFIG_EDAC_ROCKCHIP) += rockchip_edac.o diff --git a/drivers/edac/rockchip_edac.c b/drivers/edac/rockchip_edac.c new file mode 100644 index 000000000000..4b1317bed1d0 --- /dev/null +++ b/drivers/edac/rockchip_edac.c @@ -0,0 +1,358 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include + +#include "edac_module.h" + +#define MAX_CS (4) + +#define MAX_CH (1) + +#define RK_EDAC_MOD "1" + +/* ECCCADDR0 */ +#define ECC_CORR_RANK_SHIFT (24) +#define ECC_CORR_RANK_MASK (0x3) +#define ECC_CORR_ROW_MASK (0x3ffff) +/* ECCCADDR1 */ +#define ECC_CORR_CID_SHIFT (28) +#define ECC_CORR_CID_MASK (0x3) +#define ECC_CORR_BG_SHIFT (24) +#define ECC_CORR_BG_MASK (0x3) +#define ECC_CORR_BANK_SHIFT (16) +#define ECC_CORR_BANK_MASK (0x7) +#define ECC_CORR_COL_MASK (0xfff) +/* ECCUADDR0 */ +#define ECC_UNCORR_RANK_SHIFT (24) +#define ECC_UNCORR_RANK_MASK (0x3) +#define ECC_UNCORR_ROW_MASK (0x3ffff) +/* ECCUADDR1 */ +#define ECC_UNCORR_CID_SHIFT (28) +#define ECC_UNCORR_CID_MASK (0x3) +#define ECC_UNCORR_BG_SHIFT (24) +#define ECC_UNCORR_BG_MASK (0x3) +#define ECC_UNCORR_BANK_SHIFT (16) +#define ECC_UNCORR_BANK_MASK (0x7) +#define ECC_UNCORR_COL_MASK (0xfff) + +/** + * struct ddr_ecc_error_info - DDR ECC error log information + * @err_cnt: error count + * @rank: Rank number + * @row: Row number + * @chip_id: Chip id number + * @bank_group: Bank Group number + * @bank: Bank number + * @col: Column number + * @bitpos: Bit position + */ +struct ddr_ecc_error_info { + u32 err_cnt; + u32 rank; + u32 row; + u32 chip_id; + u32 bank_group; + u32 bank; + u32 col; + u32 bitpos; +}; + +/** + * struct ddr_ecc_status - DDR ECC status information to report + * @ceinfo: Correctable error log information + * @ueinfo: Uncorrectable error log information + */ +struct ddr_ecc_status { + struct ddr_ecc_error_info ceinfo; + struct ddr_ecc_error_info ueinfo; +}; + +/** + * struct rk_edac_priv - RK DDR memory controller private instance data + * @name: EDAC name + * @stat: DDR ECC status information + * @ce_cnt: Correctable Error count + * @ue_cnt: Uncorrectable Error count + * @irq_ce: Corrected interrupt number + * @irq_ue: Uncorrected interrupt number + */ +struct rk_edac_priv { + char *name; + struct ddr_ecc_status stat; + u32 ce_cnt; + u32 ue_cnt; + int irq_ce; + int irq_ue; +}; + +static struct ddr_ecc_status *ddr_edac_info; + +static inline void opstate_init_int(void) +{ + switch (edac_op_state) { + case EDAC_OPSTATE_POLL: + case EDAC_OPSTATE_INT: + break; + default: + edac_op_state = EDAC_OPSTATE_INT; + break; + } +} + +static void rockchip_edac_handle_ce_error(struct mem_ctl_info *mci, + struct ddr_ecc_status *p) +{ + struct ddr_ecc_error_info *pinf; + + if (p->ceinfo.err_cnt) { + pinf = &p->ceinfo; + edac_mc_printk(mci, KERN_ERR, + "DDR ECC CE error: CS%d, Row 0x%x, Bg 0x%x, Bk 0x%x, Col 0x%x bit 0x%x\n", + pinf->rank, pinf->row, pinf->bank_group, + pinf->bank, pinf->col, + pinf->bitpos); + edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, + p->ceinfo.err_cnt, 0, 0, 0, 0, 0, -1, + mci->ctl_name, ""); + } +} + +static void rockchip_edac_handle_ue_error(struct mem_ctl_info *mci, + struct ddr_ecc_status *p) +{ + struct ddr_ecc_error_info *pinf; + + if (p->ueinfo.err_cnt) { + pinf = &p->ueinfo; + edac_mc_printk(mci, KERN_ERR, + "DDR ECC UE error: CS%d, Row 0x%x, Bg 0x%x, Bk 0x%x, Col 0x%x\n", + pinf->rank, pinf->row, + pinf->bank_group, pinf->bank, pinf->col); + edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, + p->ueinfo.err_cnt, 0, 0, 0, 0, 0, -1, + mci->ctl_name, ""); + } +} + +static int rockchip_edac_get_error_info(struct mem_ctl_info *mci) +{ + struct arm_smccc_res res; + + res = sip_smc_dram(SHARE_PAGE_TYPE_DDRECC, 0, + ROCKCHIP_SIP_CONFIG_DRAM_ECC); + if ((res.a0) || (res.a1)) { + edac_mc_printk(mci, KERN_ERR, "ROCKCHIP_SIP_CONFIG_DRAM_ECC not support: 0x%lx\n", + res.a0); + return -ENXIO; + } + + return 0; +} + +static void rockchip_edac_check(struct mem_ctl_info *mci) +{ + struct rk_edac_priv *priv = mci->pvt_info; + int ret; + + ret = rockchip_edac_get_error_info(mci); + if (ret) + return; + + priv->ce_cnt += ddr_edac_info->ceinfo.err_cnt; + priv->ue_cnt += ddr_edac_info->ceinfo.err_cnt; + rockchip_edac_handle_ce_error(mci, ddr_edac_info); + rockchip_edac_handle_ue_error(mci, ddr_edac_info); +} + +static irqreturn_t rockchip_edac_mc_ce_isr(int irq, void *dev_id) +{ + struct mem_ctl_info *mci = dev_id; + struct rk_edac_priv *priv = mci->pvt_info; + int ret; + + ret = rockchip_edac_get_error_info(mci); + if (ret) + return IRQ_NONE; + + priv->ce_cnt += ddr_edac_info->ceinfo.err_cnt; + + rockchip_edac_handle_ce_error(mci, ddr_edac_info); + + return IRQ_HANDLED; +} + +static irqreturn_t rockchip_edac_mc_ue_isr(int irq, void *dev_id) +{ + struct mem_ctl_info *mci = dev_id; + struct rk_edac_priv *priv = mci->pvt_info; + int ret; + + ret = rockchip_edac_get_error_info(mci); + if (ret) + return IRQ_NONE; + + priv->ue_cnt += ddr_edac_info->ueinfo.err_cnt; + + rockchip_edac_handle_ue_error(mci, ddr_edac_info); + + return IRQ_HANDLED; +} + +static int rockchip_edac_mc_init(struct mem_ctl_info *mci, + struct platform_device *pdev) +{ + struct rk_edac_priv *priv = mci->pvt_info; + struct arm_smccc_res res; + int ret; + + mci->pdev = &pdev->dev; + dev_set_drvdata(mci->pdev, mci); + mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR4; + mci->edac_ctl_cap = EDAC_FLAG_SECDED; + mci->scrub_cap = SCRUB_NONE; + mci->scrub_mode = SCRUB_NONE; + + mci->edac_cap = EDAC_FLAG_SECDED; + mci->ctl_name = priv->name; + mci->dev_name = priv->name; + mci->mod_name = RK_EDAC_MOD; + + if (edac_op_state == EDAC_OPSTATE_POLL) + mci->edac_check = rockchip_edac_check; + mci->ctl_page_to_phys = NULL; + + res = sip_smc_request_share_mem(1, SHARE_PAGE_TYPE_DDRECC); + if (res.a0 != 0) { + dev_err(&pdev->dev, "no ATF memory for init, ret 0x%lx\n", res.a0); + return -ENOMEM; + } + ddr_edac_info = (struct ddr_ecc_status *)res.a1; + memset(ddr_edac_info, 0, sizeof(struct ddr_ecc_status)); + + ret = rockchip_edac_get_error_info(mci); + if (ret) + return ret; + + return 0; +} + +static int rockchip_edac_probe(struct platform_device *pdev) +{ + struct mem_ctl_info *mci; + struct edac_mc_layer layers[2]; + struct rk_edac_priv *priv; + int ret; + + opstate_init_int(); + layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; + layers[0].size = MAX_CS; + layers[0].is_virt_csrow = true; + layers[1].type = EDAC_MC_LAYER_CHANNEL; + layers[1].size = MAX_CH; + layers[1].is_virt_csrow = false; + + mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, + sizeof(struct rk_edac_priv)); + if (!mci) { + edac_printk(KERN_ERR, EDAC_MC, + "Failed memory allocation for mc instance\n"); + return -ENOMEM; + } + + priv = mci->pvt_info; + priv->name = "rk_edac_ecc"; + ret = rockchip_edac_mc_init(mci, pdev); + if (ret) { + edac_printk(KERN_ERR, EDAC_MC, + "Failed to initialize instance\n"); + goto free_edac_mc; + } + + ret = edac_mc_add_mc(mci); + if (ret) { + edac_printk(KERN_ERR, EDAC_MC, + "Failed edac_mc_add_mc()\n"); + goto free_edac_mc; + } + + if (edac_op_state == EDAC_OPSTATE_INT) { + /* register interrupts */ + priv->irq_ce = platform_get_irq_byname(pdev, "ce"); + ret = devm_request_irq(&pdev->dev, priv->irq_ce, + rockchip_edac_mc_ce_isr, + 0, + "[EDAC] MC err", mci); + if (ret < 0) { + edac_printk(KERN_ERR, EDAC_MC, + "%s: Unable to request ce irq %d for RK EDAC\n", + __func__, priv->irq_ce); + goto del_mc; + } + + edac_printk(KERN_INFO, EDAC_MC, + "acquired ce irq %d for MC\n", + priv->irq_ce); + + priv->irq_ue = platform_get_irq_byname(pdev, "ue"); + ret = devm_request_irq(&pdev->dev, priv->irq_ue, + rockchip_edac_mc_ue_isr, + 0, + "[EDAC] MC err", mci); + if (ret < 0) { + edac_printk(KERN_ERR, EDAC_MC, + "%s: Unable to request ue irq %d for RK EDAC\n", + __func__, priv->irq_ue); + goto del_mc; + } + + edac_printk(KERN_INFO, EDAC_MC, + "acquired ue irq %d for MC\n", + priv->irq_ue); + } + + return 0; + +del_mc: + edac_mc_del_mc(&pdev->dev); +free_edac_mc: + edac_mc_free(mci); + + return -ENODEV; +} + +static int rockchip_edac_remove(struct platform_device *pdev) +{ + struct mem_ctl_info *mci = dev_get_drvdata(&pdev->dev); + + edac_mc_del_mc(&pdev->dev); + edac_mc_free(mci); + + return 0; +} + +static const struct of_device_id rk_ddr_mc_err_of_match[] = { + { .compatible = "rockchip,rk3568-edac", }, + {}, +}; +MODULE_DEVICE_TABLE(of, rk_ddr_mc_err_of_match); + +static struct platform_driver rockchip_edac_driver = { + .probe = rockchip_edac_probe, + .remove = rockchip_edac_remove, + .driver = { + .name = "rk_edac", + .of_match_table = rk_ddr_mc_err_of_match, + }, +}; +module_platform_driver(rockchip_edac_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("He Zhihuan \n"); +MODULE_DESCRIPTION("ROCKCHIP EDAC kernel module"); diff --git a/include/soc/rockchip/rockchip_sip.h b/include/soc/rockchip/rockchip_sip.h index 4afba01c6628..1ae20d88250d 100644 --- a/include/soc/rockchip/rockchip_sip.h +++ b/include/soc/rockchip/rockchip_sip.h @@ -20,6 +20,7 @@ #define ROCKCHIP_SIP_CONFIG_DRAM_SET_MSCH_RL 0x0a #define ROCKCHIP_SIP_CONFIG_DRAM_DEBUG 0x0b #define ROCKCHIP_SIP_CONFIG_MCU_START 0x0c +#define ROCKCHIP_SIP_CONFIG_DRAM_ECC 0x0d #define ROCKCHIP_SIP_CONFIG_DRAM_GET_FREQ_INFO 0x0e #define ROCKCHIP_SIP_CONFIG_DRAM_ADDRMAP_GET 0x10