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clk: rockchip: rk3576: remove CLK_IS_CRITICAL for lpll and bpll

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litcore and bigcore use pvtpll, lpll and bpll if not used allow disabled.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I1a625ccd2d9f299400ccaa518bb0496fdbf07f11
This commit is contained in:
Elaine Zhang
2024-03-28 11:42:22 +08:00
committed by zhangqing
parent 6f07080e05
commit a84d45aa54
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk-rk3576.c
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@@ -361,10 +361,10 @@ PNAME(clk_aupll_ref_src_p) = { "xin24m", "clk_aupll_ref_io" };
static struct rockchip_pll_clock rk3576_pll_clks[] __initdata = {
[bpll] = PLL(pll_rk3588_core, PLL_BPLL, "bpll", mux_pll_p,
CLK_IS_CRITICAL, RK3576_PLL_CON(0),
0, RK3576_PLL_CON(0),
RK3576_BPLL_MODE_CON0, 0, 15, 0, rk3576_pll_rates),
[lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p,
CLK_IS_CRITICAL, RK3576_LPLL_CON(16),
0, RK3576_LPLL_CON(16),
RK3576_LPLL_MODE_CON0, 0, 15, 0, rk3576_pll_rates),
[vpll] = PLL(pll_rk3588, PLL_VPLL, "vpll", mux_pll_p,
0, RK3576_PLL_CON(88),