From a84d45aa54308feae3692cd33a671f67388bcb82 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Thu, 28 Mar 2024 11:42:22 +0800 Subject: [PATCH] clk: rockchip: rk3576: remove CLK_IS_CRITICAL for lpll and bpll litcore and bigcore use pvtpll, lpll and bpll if not used allow disabled. Signed-off-by: Elaine Zhang Change-Id: I1a625ccd2d9f299400ccaa518bb0496fdbf07f11 --- drivers/clk/rockchip/clk-rk3576.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3576.c b/drivers/clk/rockchip/clk-rk3576.c index bfd539847adc..19f3c94e8202 100644 --- a/drivers/clk/rockchip/clk-rk3576.c +++ b/drivers/clk/rockchip/clk-rk3576.c @@ -361,10 +361,10 @@ PNAME(clk_aupll_ref_src_p) = { "xin24m", "clk_aupll_ref_io" }; static struct rockchip_pll_clock rk3576_pll_clks[] __initdata = { [bpll] = PLL(pll_rk3588_core, PLL_BPLL, "bpll", mux_pll_p, - CLK_IS_CRITICAL, RK3576_PLL_CON(0), + 0, RK3576_PLL_CON(0), RK3576_BPLL_MODE_CON0, 0, 15, 0, rk3576_pll_rates), [lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p, - CLK_IS_CRITICAL, RK3576_LPLL_CON(16), + 0, RK3576_LPLL_CON(16), RK3576_LPLL_MODE_CON0, 0, 15, 0, rk3576_pll_rates), [vpll] = PLL(pll_rk3588, PLL_VPLL, "vpll", mux_pll_p, 0, RK3576_PLL_CON(88),