Merge commit 'ce5da098c4cd46deb075845111383d9fd34afa7a'

* commit 'ce5da098c4cd46deb075845111383d9fd34afa7a': (27 commits) drm/rockchip: vop2: update rk3568 max height limit drm/rockchip: lvds: update MEDIA_BUS_FMT_RGB666_1X7X3_SPWG description mmc: sdhci-of-dwcmshc: support HS400ES for RK3568 Revert "arm64: rockchip_defconfig: enable CONFIG_ROCKCHIP_DRM_CUBIC_LUT" Revert "FROMLIST: drm: Extend color correction to support 3D-CLU" drm/rockchip: vop2: move cubic lut to rockchip drm driver media: i2c: add ar0822 driver media: i2c: max96722: version 1.00.00 video: rockchip: rga3: add mm_flag 'RGA_MEM_FORCE_FLUSH_CACHE' arm64: dts: rockchip: rk3528 boards: btsco enable 16k pcm support arm64: dts: rockchip: rk356x boards: btsco enable 16k pcm support arm64: dts: rockchip: rk3588 boards: btsco enable 16k pcm support arm64: dts: rockchip: rk3562-evb: enable logo display for rgb board nvme-pci: add NVME_QUIRK_LIMIT_IOQD32 to fix Phison E15 NVMe controller video: rockchip: mpp: fix crash issue when no iommu soc: rockchip: mtd_vendor_storage: force config spi nor erase size to 64KB PCI: rockchip: dw_ep: Delaying the link training after hot reset video: rockchip: rga3: adapt to kernel-6.1/5.10/4.19 ARM: dts: rockchip: rmii_phy use increment 0 for rv1106-evb arm64: dts: rockchip: rk3588: Add opp-info support ... Conflicts: drivers/gpu/drm/drm_atomic_helper.c drivers/media/i2c/Kconfig drivers/media/i2c/Makefile drivers/media/i2c/max96722.c drivers/nvme/host/pci.c drivers/pci/controller/dwc/pcie-dw-rockchip.c Ignore: commit 49520417ba ("PCIe: dw: rockchip: Disabled BAR0 and BAR1"). Change-Id: I41d947eda90f8b547ef2af30c3b093f556521803 Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2026-01-06 11:08:10 -08:00 · 2023-06-28 10:17:44 +08:00
parent 7abaac5a04 ce5da098c4
commit 1ce4377b68
43 changed files with 7069 additions and 549 deletions
--- a/arch/arm/boot/dts/rv1106-evb.dtsi
+++ b/arch/arm/boot/dts/rv1106-evb.dtsi
@@ -72,6 +72,10 @@
 	status = "okay";
 };

+&rmii_phy {
+	bgs,increment = <0>;
+};
+
 &rng {
 	status = "okay";
 };
--- a/arch/arm/boot/dts/rv1106.dtsi
+++ b/arch/arm/boot/dts/rv1106.dtsi
@@ -1014,6 +1014,8 @@
 		#size-cells = <0>;
 		clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
 		clock-names = "spiclk", "apb_pclk";
+		assigned-clocks = <&cru CLK_SPI1>;
+		assigned-clock-rates = <200000000>;
 		dmas = <&dmac 3>, <&dmac 2>;
 		dma-names = "tx", "rx";
 		pinctrl-names = "default";
--- a/arch/arm64/boot/dts/rockchip/rk3528-demo.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528-demo.dtsi
@@ -43,7 +43,7 @@
 	bt_sco: bt-sco {
 		status = "disabled";
 		compatible = "delta,dfbmcs320";
-		#sound-dai-cells = <0>;
+		#sound-dai-cells = <1>;
 	};

 	bt_sound: bt-sound {
@@ -57,7 +57,7 @@
 			sound-dai = <&sai0>;
 		};
 		simple-audio-card,codec {
-			sound-dai = <&bt_sco>;
+			sound-dai = <&bt_sco 1>;
 		};
 	};

--- a/arch/arm64/boot/dts/rockchip/rk3528-evb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528-evb.dtsi
@@ -42,7 +42,7 @@
 	bt_sco: bt-sco {
 		status = "disabled";
 		compatible = "delta,dfbmcs320";
-		#sound-dai-cells = <0>;
+		#sound-dai-cells = <1>;
 	};

 	bt_sound: bt-sound {
@@ -56,7 +56,7 @@
 			sound-dai = <&sai0>;
 		};
 		simple-audio-card,codec {
-			sound-dai = <&bt_sco>;
+			sound-dai = <&bt_sco 1>;
 		};
 	};

--- a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb-k350c4516t.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb-k350c4516t.dts
@@ -19,6 +19,7 @@
 		#size-cells = <0x0>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&spi_gpio_pins>;
+		spi-delay-us = <10>;
 		status = "okay";

 		sck-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
@@ -44,6 +45,7 @@
 			disable-delay-ms = <20>;
 			width-mm = <217>;
 			height-mm = <136>;
+			rockchip,cmd-type = "spi";
 			status = "okay";

 			// type:0 is cmd, 1 is data
@@ -235,7 +237,7 @@
 };

 &route_rgb {
-	status = "disabled";
+	status = "okay";
 	connect = <&vp0_out_rgb>;
 };

--- a/arch/arm64/boot/dts/rockchip/rk3566-box.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566-box.dtsi
@@ -35,7 +35,7 @@
 	bt_sco: bt-sco {
 		status = "disabled";
 		compatible = "delta,dfbmcs320";
-		#sound-dai-cells = <0>;
+		#sound-dai-cells = <1>;
 	};

 	bt_sound: bt-sound {
@@ -49,7 +49,7 @@
 			sound-dai = <&i2s2_2ch>;
 		};
 		simple-audio-card,codec {
-			sound-dai = <&bt_sco>;
+			sound-dai = <&bt_sco 1>;
 		};
 	};

--- a/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi
@@ -144,7 +144,7 @@
 	bt_sco: bt-sco {
 		status = "disabled";
 		compatible = "delta,dfbmcs320";
-		#sound-dai-cells = <0>;
+		#sound-dai-cells = <1>;
 	};

 	bt_sound: bt-sound {
@@ -158,7 +158,7 @@
 			sound-dai = <&i2s3_2ch>;
 		};
 		simple-audio-card,codec {
-			sound-dai = <&bt_sco>;
+			sound-dai = <&bt_sco 1>;
 		};
 	};

--- a/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi
@@ -87,7 +87,7 @@
 	bt_sco: bt-sco {
 		status = "disabled";
 		compatible = "delta,dfbmcs320";
-		#sound-dai-cells = <0>;
+		#sound-dai-cells = <1>;
 	};

 	bt_sound: bt-sound {
@@ -101,7 +101,7 @@
 			sound-dai = <&i2s2_2ch>;
 		};
 		simple-audio-card,codec {
-			sound-dai = <&bt_sco>;
+			sound-dai = <&bt_sco 1>;
 		};
 	};

--- a/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi
@@ -85,7 +85,7 @@
 	bt_sco: bt-sco {
 		status = "disabled";
 		compatible = "delta,dfbmcs320";
-		#sound-dai-cells = <0>;
+		#sound-dai-cells = <1>;
 	};

 	bt_sound: bt-sound {
@@ -99,7 +99,7 @@
 			sound-dai = <&i2s2_2ch>;
 		};
 		simple-audio-card,codec {
-			sound-dai = <&bt_sco>;
+			sound-dai = <&bt_sco 1>;
 		};
 	};

--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -642,8 +642,8 @@
 		compatible = "operating-points-v2";
 		opp-shared;

-		nvmem-cells = <&cpul_leakage>, <&specification_serial_number>;
-		nvmem-cell-names = "leakage", "specification_serial_number";
+		nvmem-cells = <&cpul_leakage>, <&cpul_opp_info>, <&specification_serial_number>;
+		nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
 		rockchip,supported-hw;
 		rockchip,opp-shared-dsu;

@@ -813,8 +813,8 @@
 		compatible = "operating-points-v2";
 		opp-shared;

-		nvmem-cells = <&cpub0_leakage>, <&specification_serial_number>;
-		nvmem-cell-names = "leakage", "specification_serial_number";
+		nvmem-cells = <&cpub0_leakage>, <&cpub01_opp_info>, <&specification_serial_number>;
+		nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
 		rockchip,supported-hw;

 		rockchip,pvtm-voltage-sel = <
@@ -1026,8 +1026,8 @@
 		compatible = "operating-points-v2";
 		opp-shared;

-		nvmem-cells = <&cpub1_leakage>, <&specification_serial_number>;
-		nvmem-cell-names = "leakage", "specification_serial_number";
+		nvmem-cells = <&cpub1_leakage>, <&cpub23_opp_info>, <&specification_serial_number>;
+		nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
 		rockchip,supported-hw;

 		rockchip,pvtm-voltage-sel = <
@@ -1379,8 +1379,8 @@
 	dmc_opp_table: dmc-opp-table {
 		compatible = "operating-points-v2";

-		nvmem-cells = <&log_leakage>;
-		nvmem-cell-names = "leakage";
+		nvmem-cells = <&log_leakage>, <&dmc_opp_info>;
+		nvmem-cell-names = "leakage", "opp-info";
 		rockchip,leakage-voltage-sel = <
 			1	31	0
 			32	44	1
@@ -1908,8 +1908,8 @@
 	gpu_opp_table: gpu-opp-table {
 		compatible = "operating-points-v2";

-		nvmem-cells = <&gpu_leakage>, <&specification_serial_number>;
-		nvmem-cell-names = "leakage", "specification_serial_number";
+		nvmem-cells = <&gpu_leakage>, <&gpu_opp_info>, <&specification_serial_number>;
+		nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
 		rockchip,supported-hw;

 		rockchip,pvtm-voltage-sel = <
@@ -2897,8 +2897,8 @@
 	npu_opp_table: npu-opp-table {
 		compatible = "operating-points-v2";

-		nvmem-cells = <&npu_leakage>, <&specification_serial_number>;
-		nvmem-cell-names = "leakage", "specification_serial_number";
+		nvmem-cells = <&npu_leakage>, <&npu_opp_info>, <&specification_serial_number>;
+		nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
 		rockchip,supported-hw;

 		rockchip,pvtm-voltage-sel = <
@@ -3498,8 +3498,8 @@
 	venc_opp_table: venc-opp-table {
 		compatible = "operating-points-v2";

-		nvmem-cells = <&codec_leakage>;
-		nvmem-cell-names = "leakage";
+		nvmem-cells = <&codec_leakage>, <&venc_opp_info>;
+		nvmem-cell-names = "leakage", "opp-info";
 		rockchip,leakage-voltage-sel = <
 			1	8	0
 			9	20	1
@@ -5907,6 +5907,30 @@
 		codec_leakage: codec-leakage@29 {
 			reg = <0x29 0x1>;
 		};
+		cpul_opp_info: cpul-opp-info@3d {
+			reg = <0x3d 0x6>;
+		};
+		cpub01_opp_info: cpub01-opp-info@43 {
+			reg = <0x43 0x6>;
+		};
+		cpub23_opp_info: cpub23-opp-info@49 {
+			reg = <0x49 0x6>;
+		};
+		gpu_opp_info: gpu-opp-info@4f {
+			reg = <0x4f 0x6>;
+		};
+		npu_opp_info: npu-opp-info@55 {
+			reg = <0x55 0x6>;
+		};
+		dmc_opp_info: dmc-opp-info@5b {
+			reg = <0x5b 0x6>;
+		};
+		vop_opp_info: vop-opp-info@61 {
+			reg = <0x61 0x6>;
+		};
+		venc_opp_info: venc-opp-info@67 {
+			reg = <0x67 0x6>;
+		};
 	};

 	mailbox2: mailbox@fece0000 {
--- a/arch/arm64/configs/rockchip_defconfig
+++ b/arch/arm64/configs/rockchip_defconfig
@@ -619,7 +619,6 @@ CONFIG_DRM_IGNORE_IOTCL_PERMIT=y
 CONFIG_DRM_DP_AUX_CHARDEV=y
 CONFIG_DRM_LOAD_EDID_FIRMWARE=y
 CONFIG_DRM_ROCKCHIP=y
-CONFIG_ROCKCHIP_DRM_CUBIC_LUT=y
 CONFIG_ROCKCHIP_ANALOGIX_DP=y
 CONFIG_ROCKCHIP_CDN_DP=y
 CONFIG_ROCKCHIP_DRM_TVE=y
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -651,9 +651,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 	MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
 			RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
 	GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0,
-			RK3399_CLKGATE_CON(5), 6, GFLAGS),
-	GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0,
 			RK3399_CLKGATE_CON(5), 7, GFLAGS),
+	GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0,
+			RK3399_CLKGATE_CON(5), 6, GFLAGS),
 	GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0,
 			RK3399_CLKGATE_CON(5), 8, GFLAGS),
 	GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0,
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -143,10 +143,6 @@ void __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc,
 		drm_property_blob_get(state->ctm);
 	if (state->gamma_lut)
 		drm_property_blob_get(state->gamma_lut);
-#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
-	if (state->cubic_lut)
-		drm_property_blob_get(state->cubic_lut);
-#endif
 	state->mode_changed = false;
 	state->active_changed = false;
 	state->planes_changed = false;
@@ -219,9 +215,6 @@ void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc_state *state)
 	drm_property_blob_put(state->degamma_lut);
 	drm_property_blob_put(state->ctm);
 	drm_property_blob_put(state->gamma_lut);
-#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
-	drm_property_blob_put(state->cubic_lut);
-#endif
 }
 EXPORT_SYMBOL(__drm_atomic_helper_crtc_destroy_state);

--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -438,16 +438,6 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
 					&replaced);
 		state->color_mgmt_changed |= replaced;
 		return ret;
-#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
-	} else if (property == config->cubic_lut_property) {
-		ret = drm_atomic_replace_property_blob_from_id(dev,
-					&state->cubic_lut,
-					val,
-					-1, sizeof(struct drm_color_lut),
-					&replaced);
-		state->color_mgmt_changed |= replaced;
-		return ret;
-#endif
 	} else if (property == config->prop_out_fence_ptr) {
 		s32 __user *fence_ptr = u64_to_user_ptr(val);

@@ -493,10 +483,6 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc,
 		*val = (state->ctm) ? state->ctm->base.id : 0;
 	else if (property == config->gamma_lut_property)
 		*val = (state->gamma_lut) ? state->gamma_lut->base.id : 0;
-#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
-	else if (property == config->cubic_lut_property)
-		*val = (state->cubic_lut) ? state->cubic_lut->base.id : 0;
-#endif
 	else if (property == config->prop_out_fence_ptr)
 		*val = 0;
 	else if (property == crtc->scaling_filter_property)
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -34,7 +34,7 @@
 /**
 * DOC: overview
 *
- * Color management or color space adjustments is supported through a set of 7
+ * Color management or color space adjustments is supported through a set of 5
 * properties on the &drm_crtc object. They are set up by calling
 * drm_crtc_enable_color_mgmt().
 *
@@ -61,7 +61,7 @@
 * “CTM”:
 *	Blob property to set the current transformation matrix (CTM) apply to
 *	pixel data after the lookup through the degamma LUT and before the
- *	lookup through the cubic LUT. The data is interpreted as a struct
+ *	lookup through the gamma LUT. The data is interpreted as a struct
 *	&drm_color_ctm.
 *
 *	Setting this to NULL (blob property value set to 0) means a
@@ -69,40 +69,13 @@
 *	boot-up state too. Drivers can access the blob for the color conversion
 *	matrix through &drm_crtc_state.ctm.
 *
- * ”CUBIC_LUT”:
- *	Blob property to set the cubic (3D) lookup table performing color
- *	mapping after the transformation matrix and before the lookup through
- *	the gamma LUT. Unlike the degamma and gamma LUTs that map color
- *	components independently, the 3D LUT converts an input color to an
- *	output color by indexing into the 3D table using the color components
- *	as a 3D coordinate. The LUT is subsampled as 8-bit (or more) precision
- *	would require too much storage space in the hardware, so the precision
- *	of the color components is reduced before the look up, and the low
- *	order bits may be used to interpolate between the nearest points in 3D
- *	space.
- *
- *	The data is interpreted as an array of &struct drm_color_lut elements.
- *	Hardware might choose not to use the full precision of the LUT
- *	elements.
- *
- *	Setting this to NULL (blob property value set to 0) means the output
- *	color is identical to the input color. This is generally the driver
- *	boot-up state too. Drivers can access this blob through
- *	&drm_crtc_state.cubic_lut.
- *
- * ”CUBIC_LUT_SIZE”:
- *	Unsigned range property to give the size of the lookup table to be set
- *	on the CUBIC_LUT property (the size depends on the underlying hardware).
- *	If drivers support multiple LUT sizes then they should publish the
- *	largest size, and sub-sample smaller sized LUTs appropriately.
- *
 * “GAMMA_LUT”:
 *	Blob property to set the gamma lookup table (LUT) mapping pixel data
- *	after the cubic LUT to data sent to the connector. The data is
- *	interpreted as an array of &struct drm_color_lut elements. Hardware
- *	might choose not to use the full precision of the LUT elements nor use
- *	all the elements of the LUT (for example the hardware might choose to
- *	interpolate between LUT[0] and LUT[4]).
+ *	after the transformation matrix to data sent to the connector. The
+ *	data is interpreted as an array of &struct drm_color_lut elements.
+ *	Hardware might choose not to use the full precision of the LUT elements
+ *	nor use all the elements of the LUT (for example the hardware might
+ *	choose to interpolate between LUT[0] and LUT[4]).
 *
 *	Setting this to NULL (blob property value set to 0) means a
 *	linear/pass-thru gamma table should be used. This is generally the
@@ -359,9 +332,6 @@ static int drm_crtc_legacy_gamma_set(struct drm_crtc *crtc,
 	replaced |= drm_property_replace_blob(&crtc_state->ctm, NULL);
 	replaced |= drm_property_replace_blob(&crtc_state->gamma_lut,
 					      use_gamma_lut ? blob : NULL);
-#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
-	replaced |= drm_property_replace_blob(&crtc_state->cubic_lut, NULL);
-#endif
 	crtc_state->color_mgmt_changed |= replaced;

 	ret = drm_atomic_commit(state);
--- a/drivers/gpu/drm/drm_mode_config.c
+++ b/drivers/gpu/drm/drm_mode_config.c
@@ -365,22 +365,6 @@ static int drm_mode_create_standard_properties(struct drm_device *dev)
 		return -ENOMEM;
 	dev->mode_config.gamma_lut_size_property = prop;

-#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
-	prop = drm_property_create(dev,
-			DRM_MODE_PROP_BLOB,
-			"CUBIC_LUT", 0);
-	if (!prop)
-		return -ENOMEM;
-	dev->mode_config.cubic_lut_property = prop;
-
-	prop = drm_property_create_range(dev,
-			DRM_MODE_PROP_IMMUTABLE,
-			"CUBIC_LUT_SIZE", 0, UINT_MAX);
-	if (!prop)
-		return -ENOMEM;
-	dev->mode_config.cubic_lut_size_property = prop;
-#endif
-
 	prop = drm_property_create(dev,
 				   DRM_MODE_PROP_IMMUTABLE | DRM_MODE_PROP_BLOB,
 				   "IN_FORMATS", 0);
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -21,13 +21,6 @@ config DRM_ROCKCHIP

 if DRM_ROCKCHIP

-config ROCKCHIP_DRM_CUBIC_LUT
-	bool "Support 3D cubic LUT"
-	depends on NO_GKI
-	help
-	  This add properties to support provision of a 3D cubic
-	  look up table, allowing for color specific adjustments.
-
 config ROCKCHIP_DRM_DEBUG
 	bool "Rockchip DRM debug"
 	depends on DEBUG_FS
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
@@ -1345,6 +1345,9 @@ static int rockchip_drm_create_properties(struct drm_device *dev)
 	private->aclk_prop = drm_property_create_range(dev, 0, "ACLK", 0, UINT_MAX);
 	private->bg_prop = drm_property_create_range(dev, 0, "BACKGROUND", 0, UINT_MAX);
 	private->line_flag_prop = drm_property_create_range(dev, 0, "LINE_FLAG1", 0, UINT_MAX);
+	private->cubic_lut_prop = drm_property_create(dev, DRM_MODE_PROP_BLOB, "CUBIC_LUT", 0);
+	private->cubic_lut_size_prop = drm_property_create_range(dev, DRM_MODE_PROP_IMMUTABLE,
+								 "CUBIC_LUT_SIZE", 0, UINT_MAX);

 	return drm_mode_create_tv_properties(dev, 0, NULL);
 }
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -257,6 +257,7 @@ struct rockchip_crtc_state {
 	struct drm_property_blob *hdr_ext_data;
 	struct drm_property_blob *acm_lut_data;
 	struct drm_property_blob *post_csc_data;
+	struct drm_property_blob *cubic_lut_data;

 	int request_refresh_rate;
 	int max_refresh_rate;
@@ -455,6 +456,8 @@ struct rockchip_drm_private {
 	struct drm_property *aclk_prop;
 	struct drm_property *bg_prop;
 	struct drm_property *line_flag_prop;
+	struct drm_property *cubic_lut_prop;
+	struct drm_property *cubic_lut_size_prop;

 	/* private plane prop */
 	struct drm_property *eotf_prop;
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
@@ -3522,7 +3522,6 @@ static int vop2_crtc_atomic_gamma_set(struct drm_crtc *crtc,
 	return 0;
 }

-#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
 static int vop2_crtc_atomic_cubic_lut_set(struct drm_crtc *crtc,
 					  struct drm_crtc_state *old_state)
 {
@@ -3595,18 +3594,12 @@ static int vop2_crtc_atomic_cubic_lut_set(struct drm_crtc *crtc,
 	return 0;
 }

-static void drm_crtc_enable_cubic_lut(struct drm_crtc *crtc, unsigned int cubic_lut_size)
+static void vop2_attach_cubic_lut_prop(struct drm_crtc *crtc, unsigned int cubic_lut_size)
 {
-	struct drm_device *dev = crtc->dev;
-	struct drm_mode_config *config = &dev->mode_config;
+	struct rockchip_drm_private *private = crtc->dev->dev_private;

-	if (cubic_lut_size) {
-		drm_object_attach_property(&crtc->base,
-					   config->cubic_lut_property, 0);
-		drm_object_attach_property(&crtc->base,
-					   config->cubic_lut_size_property,
-					   cubic_lut_size);
-	}
+	drm_object_attach_property(&crtc->base, private->cubic_lut_prop, 0);
+	drm_object_attach_property(&crtc->base, private->cubic_lut_size_prop, cubic_lut_size);
 }

 static void vop2_cubic_lut_init(struct vop2 *vop2)
@@ -3626,12 +3619,9 @@ static void vop2_cubic_lut_init(struct vop2 *vop2)
 		vp->cubic_lut_len = vp_data->cubic_lut_len;

 		if (vp->cubic_lut_len)
-			drm_crtc_enable_cubic_lut(crtc, vp->cubic_lut_len);
+			vop2_attach_cubic_lut_prop(crtc, vp->cubic_lut_len);
 	}
 }
-#else
-static void vop2_cubic_lut_init(struct vop2 *vop2) { }
-#endif

 static int vop2_core_clks_prepare_enable(struct vop2 *vop2)
 {
@@ -9756,13 +9746,11 @@ static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_stat
 				vp->gamma_lut = crtc->state->gamma_lut->data;
 			vop2_crtc_atomic_gamma_set(crtc, crtc->state);
 		}
-#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
-		if (crtc->state->cubic_lut || vp->cubic_lut) {
-			if (crtc->state->cubic_lut)
-				vp->cubic_lut = crtc->state->cubic_lut->data;
+		if (vcstate->cubic_lut_data || vp->cubic_lut) {
+			if (vcstate->cubic_lut_data)
+				vp->cubic_lut = vcstate->cubic_lut_data->data;
 			vop2_crtc_atomic_cubic_lut_set(crtc, crtc->state);
 		}
-#endif
 	} else {
 		VOP_MODULE_SET(vop2, vp, cubic_lut_update_en, 0);
 	}
@@ -9875,6 +9863,8 @@ static struct drm_crtc_state *vop2_crtc_duplicate_state(struct drm_crtc *crtc)
 		drm_property_blob_get(vcstate->acm_lut_data);
 	if (vcstate->post_csc_data)
 		drm_property_blob_get(vcstate->post_csc_data);
+	if (vcstate->cubic_lut_data)
+		drm_property_blob_get(vcstate->cubic_lut_data);

 	__drm_atomic_helper_crtc_duplicate_state(crtc, &vcstate->base);
 	return &vcstate->base;
@@ -9889,6 +9879,7 @@ static void vop2_crtc_destroy_state(struct drm_crtc *crtc,
 	drm_property_blob_put(vcstate->hdr_ext_data);
 	drm_property_blob_put(vcstate->acm_lut_data);
 	drm_property_blob_put(vcstate->post_csc_data);
+	drm_property_blob_put(vcstate->cubic_lut_data);
 	kfree(vcstate);
 }

@@ -10035,6 +10026,11 @@ static int vop2_crtc_atomic_get_property(struct drm_crtc *crtc,
 		return 0;
 	}

+	if (property == private->cubic_lut_prop) {
+		*val = (vcstate->cubic_lut_data) ? vcstate->cubic_lut_data->base.id : 0;
+		return 0;
+	}
+
 	DRM_ERROR("failed to get vop2 crtc property: %s\n", property->name);

 	return -EINVAL;
@@ -10160,6 +10156,16 @@ static int vop2_crtc_atomic_set_property(struct drm_crtc *crtc,
 		return ret;
 	}

+	if (property == private->cubic_lut_prop) {
+		ret = vop2_atomic_replace_property_blob_from_id(drm_dev,
+								&vcstate->cubic_lut_data,
+								val,
+								-1, sizeof(struct drm_color_lut),
+								&replaced);
+		state->color_mgmt_changed |= replaced;
+		return ret;
+	}
+
 	DRM_ERROR("failed to set vop2 crtc property %s\n", property->name);

 	return -EINVAL;
--- a/Show More
+++ b/Show More