From 49520417bab688660d15ac9a8cb7d1164d77f9c0 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Thu, 1 Jun 2023 15:27:26 +0800 Subject: [PATCH 01/27] PCIe: dw: rockchip: Disabled BAR0 and BAR1 fix the following case: [ 2.143145] pci 0000:00:00.0: BAR 0: no space for [mem size 0x40000000] [ 2.143155] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x40000000] [ 2.143161] pci 0000:00:00.0: BAR 1: no space for [mem size 0x40000000] [ 2.143168] pci 0000:00:00.0: BAR 1: failed to assign [mem size 0x40000000] Change-Id: I5eca2adb49d83c775036df7e961dab5c9fbfffbb Signed-off-by: Jon Lin --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 87b71c8e96aa..2689d9df913d 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -1126,6 +1126,10 @@ static int rk_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); + /* Disable BAR0 BAR1 */ + dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + BAR_0 * 4, 0); + dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + BAR_1 * 4, 0); + ret = rk_pcie_establish_link(pci); if (pp->msi_irq > 0) From 5f69a5c6cd83b8cbc3dd3101d7ca605ed889e1c7 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 26 Jun 2023 09:24:11 +0800 Subject: [PATCH 02/27] clk: rockchip: rk3399: fix mac ref clk register description Signed-off-by: Elaine Zhang Change-Id: Ib8f21796a3527d74055ff847a2d36e99208d4772 --- drivers/clk/rockchip/clk-rk3399.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index f02f459acd22..6112951541a8 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -651,9 +651,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(19), 4, 1, MFLAGS), GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0, - RK3399_CLKGATE_CON(5), 6, GFLAGS), - GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0, RK3399_CLKGATE_CON(5), 7, GFLAGS), + GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0, + RK3399_CLKGATE_CON(5), 6, GFLAGS), GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0, RK3399_CLKGATE_CON(5), 8, GFLAGS), GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0, From 4c1df951f3a4ca891fae498800fc80a0dda8ab8c Mon Sep 17 00:00:00 2001 From: Huibin Hong Date: Sun, 25 Jun 2023 12:36:12 +0000 Subject: [PATCH 03/27] fiq_debugger: properly stop console thread when tty_fifo is not empty Console thread may run all the time after console_thread_stop is 1, and tty_fifo is not empty. Fixes: 33f4a5403759 ("fiq_debugger: tty write to tty fifo") Signed-off-by: Huibin Hong Change-Id: Ie5c94d61e4553b7ea78af440db6363f07fa827c3 --- drivers/soc/rockchip/fiq_debugger/rk_fiq_debugger.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/soc/rockchip/fiq_debugger/rk_fiq_debugger.c b/drivers/soc/rockchip/fiq_debugger/rk_fiq_debugger.c index 3c85c83e0320..c6299aebaf2f 100644 --- a/drivers/soc/rockchip/fiq_debugger/rk_fiq_debugger.c +++ b/drivers/soc/rockchip/fiq_debugger/rk_fiq_debugger.c @@ -334,7 +334,7 @@ static int console_thread(void *data) unsigned int dropped; set_current_state(TASK_INTERRUPTIBLE); - if (kfifo_is_empty(&fifo) && kfifo_is_empty(&tty_fifo)) { + if (console_thread_stop || (kfifo_is_empty(&fifo) && kfifo_is_empty(&tty_fifo))) { smp_store_mb(console_thread_running, false); schedule(); smp_store_mb(console_thread_running, true); @@ -344,13 +344,13 @@ static int console_thread(void *data) set_current_state(TASK_RUNNING); while (!console_thread_stop && (!kfifo_is_empty(&fifo) || !kfifo_is_empty(&tty_fifo))) { - while (kfifo_get(&fifo, &c)) { + while (!console_thread_stop && kfifo_get(&fifo, &c)) { console_put(pdev, &c, 1); if (c == '\n') break; } - while (kfifo_get(&tty_fifo, &c)) { + while (!console_thread_stop && kfifo_get(&tty_fifo, &c)) { console_putc(pdev, c); len_tty++; if (c == '\n') @@ -418,6 +418,8 @@ static int tty_write(struct platform_device *pdev, const char *s, int count) unsigned int ret = 0; struct rk_fiq_debugger *t; + if (console_thread_stop) + return count; t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata); if (count > 0) { From 98df9bf81927ec65ecbedc2da780304cfd8a97a2 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Thu, 22 Jun 2023 21:03:49 +0800 Subject: [PATCH 04/27] ARM: dts: rockchip: rv1106: Set spi1 sclk to 200MHz Change-Id: I810dead9d7b4967898776e6ee3908e55b1d9ceb6 Signed-off-by: Jon Lin --- arch/arm/boot/dts/rv1106.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/rv1106.dtsi b/arch/arm/boot/dts/rv1106.dtsi index f877096e8060..4bb093b80aa3 100644 --- a/arch/arm/boot/dts/rv1106.dtsi +++ b/arch/arm/boot/dts/rv1106.dtsi @@ -1014,6 +1014,8 @@ #size-cells = <0>; clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; clock-names = "spiclk", "apb_pclk"; + assigned-clocks = <&cru CLK_SPI1>; + assigned-clock-rates = <200000000>; dmas = <&dmac 3>, <&dmac 2>; dma-names = "tx", "rx"; pinctrl-names = "default"; From 04a51f4342eec2c8ceef307729e07e575060577b Mon Sep 17 00:00:00 2001 From: Wangqiang Guo Date: Mon, 26 Jun 2023 01:41:09 +0000 Subject: [PATCH 05/27] media: rockchip: hdmirx: enhanced compatibility. 1.check format when get timing. 2.if read wrong format, try multiple times. 3.disable interrupts once triggered, avoid multiple triggers. Change-Id: I2ac21723071dd89e74b0a854a3501ab8ea978aa1 Signed-off-by: Wangqiang Guo --- .../platform/rockchip/hdmirx/rk_hdmirx.c | 21 +++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c b/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c index 067314d49162..29a096af948b 100644 --- a/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c +++ b/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c @@ -269,6 +269,7 @@ static int hdmirx_set_cpu_limit_freq(struct rk_hdmirx_dev *hdmirx_dev); static void hdmirx_cancel_cpu_limit_freq(struct rk_hdmirx_dev *hdmirx_dev); static void hdmirx_plugout(struct rk_hdmirx_dev *hdmirx_dev); static void process_signal_change(struct rk_hdmirx_dev *hdmirx_dev); +static void hdmirx_interrupts_setup(struct rk_hdmirx_dev *hdmirx_dev, bool en); static u8 edid_init_data_340M[] = { 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, @@ -615,8 +616,10 @@ static void hdmirx_get_colordepth(struct rk_hdmirx_dev *hdmirx_dev) static void hdmirx_get_pix_fmt(struct rk_hdmirx_dev *hdmirx_dev) { u32 val; + int timeout = 10; struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; +try_loop: val = hdmirx_readl(hdmirx_dev, DMA_STATUS11); hdmirx_dev->pix_fmt = val & HDMIRX_FORMAT_MASK; @@ -635,11 +638,16 @@ static void hdmirx_get_pix_fmt(struct rk_hdmirx_dev *hdmirx_dev) break; default: + if (timeout-- > 0) { + usleep_range(200 * 1000, 200 * 1010); + v4l2_err(v4l2_dev, "%s: get format failed, read again!\n", __func__); + goto try_loop; + } + hdmirx_dev->pix_fmt = HDMIRX_RGB888; + hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24; v4l2_err(v4l2_dev, "%s: err pix_fmt: %d, set RGB888 as default\n", __func__, hdmirx_dev->pix_fmt); - hdmirx_dev->pix_fmt = HDMIRX_RGB888; - hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24; break; } @@ -880,9 +888,12 @@ static int hdmirx_try_to_get_timings(struct rk_hdmirx_dev *hdmirx_dev, struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; u32 last_w, last_h; struct v4l2_bt_timings *bt = &timings->bt; + enum hdmirx_pix_fmt last_fmt; last_w = 0; last_h = 0; + last_fmt = HDMIRX_RGB888; + for (i = 0; i < try_cnt; i++) { ret = hdmirx_get_detected_timings(hdmirx_dev, timings, from_dma); @@ -891,7 +902,8 @@ static int hdmirx_try_to_get_timings(struct rk_hdmirx_dev *hdmirx_dev, last_h = bt->height; } - if (ret || (last_w != bt->width) || (last_h != bt->height)) + if (ret || (last_w != bt->width) || (last_h != bt->height) + || (last_fmt != hdmirx_dev->pix_fmt)) cnt = 0; else cnt++; @@ -901,6 +913,7 @@ static int hdmirx_try_to_get_timings(struct rk_hdmirx_dev *hdmirx_dev, last_w = bt->width; last_h = bt->height; + last_fmt = hdmirx_dev->pix_fmt; usleep_range(10*1000, 10*1100); } @@ -2349,6 +2362,7 @@ static void process_signal_change(struct rk_hdmirx_dev *hdmirx_dev) FIFO_UNDERFLOW_INT_EN | HDMIRX_AXI_ERROR_INT_EN, 0); hdmirx_reset_dma(hdmirx_dev); + hdmirx_interrupts_setup(hdmirx_dev, false); v4l2_event_queue(&stream->vdev, &evt_signal_lost); if (hdmirx_dev->hdcp && hdmirx_dev->hdcp->hdcp_stop) hdmirx_dev->hdcp->hdcp_stop(hdmirx_dev->hdcp); @@ -3243,7 +3257,6 @@ static void hdmirx_delayed_work_res_change(struct work_struct *work) plugin = tx_5v_power_present(hdmirx_dev); v4l2_dbg(1, debug, v4l2_dev, "%s: plugin:%d\n", __func__, plugin); if (plugin) { - hdmirx_interrupts_setup(hdmirx_dev, false); hdmirx_submodule_init(hdmirx_dev); hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED, POWERPROVIDED); From dcc425f09c6102ae67fec9022628ef0fdb23c192 Mon Sep 17 00:00:00 2001 From: Herman Chen Date: Thu, 15 Jun 2023 16:21:28 +0800 Subject: [PATCH 06/27] video: rockchip: mpp: rkvenc2: Add check for error irq status Signed-off-by: Herman Chen Change-Id: I2f5e2909d189cb78052c85c89ac994fcdb586708 --- drivers/video/rockchip/mpp/mpp_common.c | 2 +- drivers/video/rockchip/mpp/mpp_rkvenc2.c | 57 +++++++++++++++++++++--- 2 files changed, 52 insertions(+), 7 deletions(-) diff --git a/drivers/video/rockchip/mpp/mpp_common.c b/drivers/video/rockchip/mpp/mpp_common.c index dbc625c2a491..2cb7194d940e 100644 --- a/drivers/video/rockchip/mpp/mpp_common.c +++ b/drivers/video/rockchip/mpp/mpp_common.c @@ -2266,7 +2266,7 @@ irqreturn_t mpp_dev_irq(int irq, void *param) irq_ret = mpp->dev_ops->irq(mpp); if (task) { - if (irq_ret != IRQ_NONE) { + if (irq_ret == IRQ_WAKE_THREAD) { /* if wait or delayed work timeout, abort request will turn on, * isr should not to response, and handle it in delayed work */ diff --git a/drivers/video/rockchip/mpp/mpp_rkvenc2.c b/drivers/video/rockchip/mpp/mpp_rkvenc2.c index 2dc50bb86179..1168ef5be0db 100644 --- a/drivers/video/rockchip/mpp/mpp_rkvenc2.c +++ b/drivers/video/rockchip/mpp/mpp_rkvenc2.c @@ -178,6 +178,12 @@ union rkvenc2_dual_core_handshake_id { #define RKVENC2_REG_SLICE_NUM_BASE (0x4034) #define RKVENC2_REG_SLICE_LEN_BASE (0x4038) +#define RKVENC2_REG_ST_BSB (0x402c) +#define RKVENC2_REG_ADR_BSBT (0x2b0) +#define RKVENC2_REG_ADR_BSBB (0x2b4) +#define RKVENC2_REG_ADR_BSBR (0x2b8) +#define RKVENC2_REG_ADR_BSBS (0x2bc) + union rkvenc2_slice_len_info { u32 val; @@ -283,6 +289,8 @@ struct rkvenc_dev { u32 sram_enabled; struct page *rcb_page; + u32 bs_overflow; + #ifdef CONFIG_PM_DEVFREQ struct rockchip_opp_info opp_info; struct monitor_dev_info *mdev_info; @@ -1290,6 +1298,8 @@ static int rkvenc_irq(struct mpp_dev *mpp) struct rkvenc_hw_info *hw = enc->hw_info; struct mpp_task *mpp_task = NULL; struct rkvenc_task *task = NULL; + u32 int_clear = 1; + u32 irq_mask = 0; int ret = IRQ_NONE; mpp_debug_enter(); @@ -1311,12 +1321,12 @@ static int rkvenc_irq(struct mpp_dev *mpp) wake_up(&mpp_task->wait); } - mpp_write(mpp, hw->int_mask_base, 0x100); - mpp_write(mpp, hw->int_clr_base, 0xffffffff); - udelay(5); - mpp_write(mpp, hw->int_sta_base, 0); - + irq_mask = INT_STA_ENC_DONE_STA; ret = IRQ_WAKE_THREAD; + if (enc->bs_overflow) { + mpp->irq_status |= INT_STA_BSF_OFLW_STA; + enc->bs_overflow = 0; + } } else if (mpp->irq_status & INT_STA_SLC_DONE_STA) { if (task && task->task_split) { mpp_time_part_diff(mpp_task); @@ -1325,7 +1335,42 @@ static int rkvenc_irq(struct mpp_dev *mpp) wake_up(&mpp_task->wait); } - mpp_write(mpp, hw->int_clr_base, INT_STA_SLC_DONE_STA); + irq_mask = INT_STA_ENC_DONE_STA; + int_clear = 0; + } else if (mpp->irq_status & INT_STA_BSF_OFLW_STA) { + u32 bs_rd = mpp_read(mpp, RKVENC2_REG_ADR_BSBR); + u32 bs_wr = mpp_read(mpp, RKVENC2_REG_ST_BSB); + u32 bs_top = mpp_read(mpp, RKVENC2_REG_ADR_BSBT); + u32 bs_bot = mpp_read(mpp, RKVENC2_REG_ADR_BSBB); + + if (mpp_task) + dev_err(mpp->dev, "task %d found bitstream overflow [%#08x %#08x %#08x %#08x]\n", + mpp_task->task_index, bs_top, bs_bot, bs_wr, bs_rd); + bs_wr += 128; + if (bs_wr >= bs_top) + bs_wr = bs_bot; + /* clear int first */ + mpp_write(mpp, hw->int_clr_base, mpp->irq_status); + /* update write addr for enc continue */ + mpp_write(mpp, RKVENC2_REG_ADR_BSBS, bs_wr); + enc->bs_overflow = 1; + irq_mask = 0; + int_clear = 0; + ret = IRQ_HANDLED; + } else { + dev_err(mpp->dev, "found error status %08x\n", mpp->irq_status); + + irq_mask = mpp->irq_status; + ret = IRQ_WAKE_THREAD; + } + + if (irq_mask) + mpp_write(mpp, hw->int_mask_base, irq_mask); + + if (int_clear) { + mpp_write(mpp, hw->int_clr_base, mpp->irq_status); + udelay(5); + mpp_write(mpp, hw->int_sta_base, 0); } mpp_debug_leave(); From 924d577057538e703db959d26945ea3bb26fec4c Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Mon, 26 Jun 2023 16:02:44 +0800 Subject: [PATCH 07/27] soc: rockchip: opp_select: adjust memory voltage by otp Signed-off-by: Finley Xiao Change-Id: Icfed6bd8766329b10ddb6d5d78e5306a013389cb --- drivers/soc/rockchip/rockchip_opp_select.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/soc/rockchip/rockchip_opp_select.c b/drivers/soc/rockchip/rockchip_opp_select.c index 82559daad5fb..40d1ec6dc0c0 100644 --- a/drivers/soc/rockchip/rockchip_opp_select.c +++ b/drivers/soc/rockchip/rockchip_opp_select.c @@ -1484,9 +1484,14 @@ static void rockchip_adjust_opp_by_otp(struct device *dev, if (opp->rate > opp_info.max_freq * 1000000) continue; - opp->supplies->u_volt += opp_info.volt * 1000; - if (opp->supplies->u_volt > opp->supplies->u_volt_max) - opp->supplies->u_volt = opp->supplies->u_volt_max; + opp->supplies[0].u_volt += opp_info.volt * 1000; + if (opp->supplies[0].u_volt > opp->supplies[0].u_volt_max) + opp->supplies[0].u_volt = opp->supplies[0].u_volt_max; + if (opp_table->regulator_count > 1) { + opp->supplies[1].u_volt += opp_info.volt * 1000; + if (opp->supplies[1].u_volt > opp->supplies[1].u_volt_max) + opp->supplies[1].u_volt = opp->supplies[1].u_volt_max; + } } mutex_unlock(&opp_table->lock); From 8fde0d8b6790d991f43ecd2c8cb63e220afe879a Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Mon, 26 Jun 2023 10:33:56 +0800 Subject: [PATCH 08/27] arm64: dts: rockchip: rk3588: Add opp-info support Signed-off-by: Finley Xiao Change-Id: I5f0fa938f78480712a2c4c313c368a48843eaef3 --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 52 +++++++++++++++++------ 1 file changed, 38 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index e1edc29d4fb9..35e1bcc7eb50 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -642,8 +642,8 @@ compatible = "operating-points-v2"; opp-shared; - nvmem-cells = <&cpul_leakage>, <&specification_serial_number>; - nvmem-cell-names = "leakage", "specification_serial_number"; + nvmem-cells = <&cpul_leakage>, <&cpul_opp_info>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; rockchip,supported-hw; rockchip,opp-shared-dsu; @@ -813,8 +813,8 @@ compatible = "operating-points-v2"; opp-shared; - nvmem-cells = <&cpub0_leakage>, <&specification_serial_number>; - nvmem-cell-names = "leakage", "specification_serial_number"; + nvmem-cells = <&cpub0_leakage>, <&cpub01_opp_info>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; rockchip,supported-hw; rockchip,pvtm-voltage-sel = < @@ -1026,8 +1026,8 @@ compatible = "operating-points-v2"; opp-shared; - nvmem-cells = <&cpub1_leakage>, <&specification_serial_number>; - nvmem-cell-names = "leakage", "specification_serial_number"; + nvmem-cells = <&cpub1_leakage>, <&cpub23_opp_info>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; rockchip,supported-hw; rockchip,pvtm-voltage-sel = < @@ -1379,8 +1379,8 @@ dmc_opp_table: dmc-opp-table { compatible = "operating-points-v2"; - nvmem-cells = <&log_leakage>; - nvmem-cell-names = "leakage"; + nvmem-cells = <&log_leakage>, <&dmc_opp_info>; + nvmem-cell-names = "leakage", "opp-info"; rockchip,leakage-voltage-sel = < 1 31 0 32 44 1 @@ -1854,8 +1854,8 @@ gpu_opp_table: gpu-opp-table { compatible = "operating-points-v2"; - nvmem-cells = <&gpu_leakage>, <&specification_serial_number>; - nvmem-cell-names = "leakage", "specification_serial_number"; + nvmem-cells = <&gpu_leakage>, <&gpu_opp_info>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; rockchip,supported-hw; rockchip,pvtm-voltage-sel = < @@ -2843,8 +2843,8 @@ npu_opp_table: npu-opp-table { compatible = "operating-points-v2"; - nvmem-cells = <&npu_leakage>, <&specification_serial_number>; - nvmem-cell-names = "leakage", "specification_serial_number"; + nvmem-cells = <&npu_leakage>, <&npu_opp_info>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; rockchip,supported-hw; rockchip,pvtm-voltage-sel = < @@ -3444,8 +3444,8 @@ venc_opp_table: venc-opp-table { compatible = "operating-points-v2"; - nvmem-cells = <&codec_leakage>; - nvmem-cell-names = "leakage"; + nvmem-cells = <&codec_leakage>, <&venc_opp_info>; + nvmem-cell-names = "leakage", "opp-info"; rockchip,leakage-voltage-sel = < 1 8 0 9 20 1 @@ -5853,6 +5853,30 @@ codec_leakage: codec-leakage@29 { reg = <0x29 0x1>; }; + cpul_opp_info: cpul-opp-info@3d { + reg = <0x3d 0x6>; + }; + cpub01_opp_info: cpub01-opp-info@43 { + reg = <0x43 0x6>; + }; + cpub23_opp_info: cpub23-opp-info@49 { + reg = <0x49 0x6>; + }; + gpu_opp_info: gpu-opp-info@4f { + reg = <0x4f 0x6>; + }; + npu_opp_info: npu-opp-info@55 { + reg = <0x55 0x6>; + }; + dmc_opp_info: dmc-opp-info@5b { + reg = <0x5b 0x6>; + }; + vop_opp_info: vop-opp-info@61 { + reg = <0x61 0x6>; + }; + venc_opp_info: venc-opp-info@67 { + reg = <0x67 0x6>; + }; }; mailbox2: mailbox@fece0000 { From 772d60102644a2127c7015a761edf04ce8d971f4 Mon Sep 17 00:00:00 2001 From: David Wu Date: Sun, 18 Jun 2023 17:59:54 +0800 Subject: [PATCH 09/27] ARM: dts: rockchip: rmii_phy use increment 0 for rv1106-evb Only network cables with waterproof wires require +2, otherwise 0. Signed-off-by: David Wu Change-Id: Ic00c06857a9f49d4648a2fa94d7630f7b293c4b9 --- arch/arm/boot/dts/rv1106-evb.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rv1106-evb.dtsi b/arch/arm/boot/dts/rv1106-evb.dtsi index 7b9f2d5f36ee..ca6038612a74 100644 --- a/arch/arm/boot/dts/rv1106-evb.dtsi +++ b/arch/arm/boot/dts/rv1106-evb.dtsi @@ -72,6 +72,10 @@ status = "okay"; }; +&rmii_phy { + bgs,increment = <0>; +}; + &rng { status = "okay"; }; From bfe46724a30a6ba1b08c98be398b9c6aea53cdb4 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Mon, 26 Jun 2023 07:02:25 +0000 Subject: [PATCH 10/27] video: rockchip: rga3: adapt to kernel-6.1/5.10/4.19 Signed-off-by: Yu Qiaowei Change-Id: Ie38ae6b0fc6037bfeee5b19077ff339f39933bc4 --- drivers/video/rockchip/rga3/include/rga_drv.h | 2 +- drivers/video/rockchip/rga3/rga_debugger.c | 17 +++++++++++++++ drivers/video/rockchip/rga3/rga_dma_buf.c | 21 ++++++++++++++----- drivers/video/rockchip/rga3/rga_job.c | 4 ++++ 4 files changed, 38 insertions(+), 6 deletions(-) diff --git a/drivers/video/rockchip/rga3/include/rga_drv.h b/drivers/video/rockchip/rga3/include/rga_drv.h index e42493b9bec1..29a64a6b5a89 100644 --- a/drivers/video/rockchip/rga3/include/rga_drv.h +++ b/drivers/video/rockchip/rga3/include/rga_drv.h @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -48,7 +49,6 @@ #include #include -#include #include #ifdef CONFIG_DMABUF_CACHE diff --git a/drivers/video/rockchip/rga3/rga_debugger.c b/drivers/video/rockchip/rga3/rga_debugger.c index 27357bc9bde5..fe2103147845 100644 --- a/drivers/video/rockchip/rga3/rga_debugger.c +++ b/drivers/video/rockchip/rga3/rga_debugger.c @@ -621,7 +621,11 @@ CREATE_FAIL: #ifdef CONFIG_ROCKCHIP_RGA_PROC_FS static int rga_procfs_open(struct inode *inode, struct file *file) { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0) + struct rga_debugger_node *node = pde_data(inode); +#else struct rga_debugger_node *node = PDE_DATA(inode); +#endif return single_open(file, node->info_ent->show, node); } @@ -836,6 +840,10 @@ static int rga_dump_image_to_file(struct rga_internal_buffer *dump_buffer, struct file *file; size_t size = 0; loff_t pos = 0; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0) + int ret; + struct iosys_map map; +#endif void *kvaddr = NULL; void *kvaddr_origin = NULL; @@ -848,7 +856,12 @@ static int rga_dump_image_to_file(struct rga_internal_buffer *dump_buffer, return -EINVAL; } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0) + ret = dma_buf_vmap(dump_buffer->dma_buffer->dma_buf, &map); + kvaddr = ret ? NULL : map.vaddr; +#else kvaddr = dma_buf_vmap(dump_buffer->dma_buffer->dma_buf); +#endif if (!kvaddr) { pr_err("can't vmap the dma buffer!\n"); return -EINVAL; @@ -918,7 +931,11 @@ static int rga_dump_image_to_file(struct rga_internal_buffer *dump_buffer, switch (dump_buffer->type) { case RGA_DMA_BUFFER: case RGA_DMA_BUFFER_PTR: +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0) + dma_buf_vunmap(dump_buffer->dma_buffer->dma_buf, &map); +#else dma_buf_vunmap(dump_buffer->dma_buffer->dma_buf, kvaddr_origin); +#endif break; case RGA_VIRTUAL_ADDRESS: vunmap(kvaddr_origin); diff --git a/drivers/video/rockchip/rga3/rga_dma_buf.c b/drivers/video/rockchip/rga3/rga_dma_buf.c index 718010088d5a..db34db5af86c 100644 --- a/drivers/video/rockchip/rga3/rga_dma_buf.c +++ b/drivers/video/rockchip/rga3/rga_dma_buf.c @@ -203,7 +203,7 @@ static dma_addr_t rga_iommu_dma_alloc_iova(struct iommu_domain *domain, size_t size, u64 dma_limit, struct device *dev) { - struct rga_iommu_dma_cookie *cookie = domain->iova_cookie; + struct rga_iommu_dma_cookie *cookie = (void *)domain->iova_cookie; struct iova_domain *iovad = &cookie->iovad; unsigned long shift, iova_len, iova = 0; @@ -246,7 +246,7 @@ static dma_addr_t rga_iommu_dma_alloc_iova(struct iommu_domain *domain, static void rga_iommu_dma_free_iova(struct iommu_domain *domain, dma_addr_t iova, size_t size) { - struct rga_iommu_dma_cookie *cookie = domain->iova_cookie; + struct rga_iommu_dma_cookie *cookie = (void *)domain->iova_cookie; struct iova_domain *iovad = &cookie->iovad; free_iova_fast(iovad, iova_pfn(iovad, iova), size >> iova_shift(iovad)); @@ -285,7 +285,7 @@ int rga_iommu_map_sgt(struct sg_table *sgt, size_t size, } domain = rga_iommu_get_dma_domain(rga_dev); - cookie = domain->iova_cookie; + cookie = (void *)domain->iova_cookie; iovad = &cookie->iovad; align_size = iova_align(iovad, size); @@ -330,7 +330,7 @@ int rga_iommu_map(phys_addr_t paddr, size_t size, } domain = rga_iommu_get_dma_domain(rga_dev); - cookie = domain->iova_cookie; + cookie = (void *)domain->iova_cookie; iovad = &cookie->iovad; align_size = iova_align(iovad, size); @@ -394,12 +394,20 @@ int rga_dma_memory_check(struct rga_dma_buffer *rga_dma_buffer, struct rga_img_i { int ret = 0; void *vaddr; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0) + struct iosys_map map; +#endif struct dma_buf *dma_buf; dma_buf = rga_dma_buffer->dma_buf; if (!IS_ERR_OR_NULL(dma_buf)) { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0) + ret = dma_buf_vmap(dma_buf, &map); + vaddr = ret ? NULL : map.vaddr; +#else vaddr = dma_buf_vmap(dma_buf); +#endif if (vaddr) { ret = rga_virtual_memory_check(vaddr, img->vir_w, img->vir_h, img->format, img->yrgb_addr); @@ -407,8 +415,11 @@ int rga_dma_memory_check(struct rga_dma_buffer *rga_dma_buffer, struct rga_img_i pr_err("can't vmap the dma buffer!\n"); return -EINVAL; } - +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0) + dma_buf_vunmap(dma_buf, &map); +#else dma_buf_vunmap(dma_buf, vaddr); +#endif } return ret; diff --git a/drivers/video/rockchip/rga3/rga_job.c b/drivers/video/rockchip/rga3/rga_job.c index 09e199779047..bbe6fa87e82f 100644 --- a/drivers/video/rockchip/rga3/rga_job.c +++ b/drivers/video/rockchip/rga3/rga_job.c @@ -537,7 +537,11 @@ static int rga_request_add_acquire_fence_callback(int acquire_fence_fd, return -EINVAL; } /* close acquire fence fd */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0) + close_fd(acquire_fence_fd); +#else ksys_close(acquire_fence_fd); +#endif ret = rga_dma_fence_get_status(acquire_fence); if (ret < 0) { From c3f038c2dcafc56b6516d6704e2d8d5988154ac8 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Fri, 16 Jun 2023 17:13:31 +0800 Subject: [PATCH 11/27] PCI: rockchip: dw_ep: Delaying the link training after hot reset Delaying the link training after hot reset, so that it's possible to read/write some register status through the DBI. The controller support delaying the Link Training by setting app_dly2_en/done register. Change-Id: Ic6d1b28ca42e3d355610db33f4e5086cf26d705c Signed-off-by: Jon Lin --- .../pci/controller/dwc/pcie-dw-ep-rockchip.c | 60 +++++++++++++++---- 1 file changed, 50 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c index 6655bed9a26c..6b9976bcd110 100644 --- a/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c @@ -81,6 +81,10 @@ #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 #define PCIE_CLIENT_LTSSM_STATUS 0x300 #define PCIE_CLIENT_INTR_MASK 0x24 +#define PCIE_LTSSM_APP_DLY1_EN BIT(0) +#define PCIE_LTSSM_APP_DLY2_EN BIT(1) +#define PCIE_LTSSM_APP_DLY1_DONE BIT(2) +#define PCIE_LTSSM_APP_DLY2_DONE BIT(3) #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) #define PCIE_CLIENT_MSI_GEN_CON 0x38 @@ -106,6 +110,7 @@ #define PCIE_EP_OBJ_INFO_DRV_VERSION 0x00000001 #define PCIE_BAR_MAX_NUM 6 +#define PCIE_HOTRESET_TMOUT_US 10000 struct rockchip_pcie { struct dw_pcie pci; @@ -130,6 +135,8 @@ struct rockchip_pcie { phys_addr_t dbi_base_physical; struct pcie_ep_obj_info *obj_info; enum pcie_ep_mmap_resource cur_mmap_res; + struct workqueue_struct *hot_rst_wq; + struct work_struct hot_rst_work; }; struct rockchip_pcie_misc_dev { @@ -586,7 +593,8 @@ static void rockchip_pcie_fast_link_setup(struct rockchip_pcie *rockchip) /* LTSSM EN ctrl mode */ val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_HOT_RESET_CTRL); - val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16); + val |= (PCIE_LTSSM_ENABLE_ENHANCE | PCIE_LTSSM_APP_DLY2_EN) | + ((PCIE_LTSSM_ENABLE_ENHANCE | PCIE_LTSSM_APP_DLY2_EN) << 16); rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); } @@ -642,7 +650,7 @@ static irqreturn_t rockchip_pcie_sys_irq_handler(int irq, void *arg) u32 chn; union int_status wr_status, rd_status; union int_clear clears; - u32 reg, val, mask; + u32 reg, mask; bool sigio = false; /* ELBI helper, only check the valid bits, and discard the rest interrupts */ @@ -713,14 +721,8 @@ out: } reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC); - if (reg & BIT(2)) { - /* Setup command register */ - val = dw_pcie_readl_dbi(pci, PCI_COMMAND); - val &= 0xffff0000; - val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_SERR; - dw_pcie_writel_dbi(pci, PCI_COMMAND, val); - } + if (reg & BIT(2)) + queue_work(rockchip->hot_rst_wq, &rockchip->hot_rst_work); rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC); @@ -870,6 +872,23 @@ static void rockchip_pcie_config_dma_dwc(struct dma_table *table) table->start.chnl = table->chn; } +static void rockchip_pcie_hot_rst_work(struct work_struct *work) +{ + struct rockchip_pcie *rockchip = container_of(work, struct rockchip_pcie, hot_rst_work); + u32 status; + int ret; + + if (rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_HOT_RESET_CTRL) & PCIE_LTSSM_APP_DLY2_EN) { + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_LTSSM_STATUS, + status, ((status & 0x3F) == 0), 100, PCIE_HOTRESET_TMOUT_US); + if (ret) + dev_err(rockchip->pci.dev, "wait for detect quiet failed!\n"); + + rockchip_pcie_writel_apb(rockchip, (PCIE_LTSSM_APP_DLY2_DONE) | ((PCIE_LTSSM_APP_DLY2_DONE) << 16), + PCIE_CLIENT_HOT_RESET_CTRL); + } +} + static int rockchip_pcie_get_dma_status(struct dma_trx_obj *obj, u8 chn, enum dma_dir dir) { struct rockchip_pcie *rockchip = dev_get_drvdata(obj->dev); @@ -1121,6 +1140,7 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) struct rockchip_pcie *rockchip; int ret; int retry, i; + u32 reg; rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL); if (!rockchip) @@ -1182,6 +1202,26 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) rockchip_pcie_start_link(&rockchip->pci); rockchip_pcie_devmode_update(rockchip, RKEP_MODE_KERNEL, RKEP_SMODE_LNKRDY); + rockchip->hot_rst_wq = create_singlethread_workqueue("rkep_hot_rst_wq"); + if (rockchip->hot_rst_wq) { + dev_err(dev, "failed to create hot_rst workqueue\n"); + ret = -ENOMEM; + goto deinit_phy; + } + INIT_WORK(&rockchip->hot_rst_work, rockchip_pcie_hot_rst_work); + + reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC); + if ((reg & BIT(2)) && + (rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_HOT_RESET_CTRL) & PCIE_LTSSM_APP_DLY2_EN)) { + rockchip_pcie_writel_apb(rockchip, PCIE_LTSSM_APP_DLY2_DONE | (PCIE_LTSSM_APP_DLY2_DONE << 16), + PCIE_CLIENT_HOT_RESET_CTRL); + dev_info(dev, "hot reset ever\n"); + } + rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC); + + /* Enable client reset or link down interrupt */ + rockchip_pcie_writel_apb(rockchip, 0x40000, PCIE_CLIENT_INTR_MASK); + for (retry = 0; retry < 10000; retry++) { if (dw_pcie_link_up(&rockchip->pci)) { /* From 3473270fe274c95302420776745e6311f35753d8 Mon Sep 17 00:00:00 2001 From: Yifeng Zhao Date: Wed, 21 Jun 2023 17:34:52 +0800 Subject: [PATCH 12/27] soc: rockchip: mtd_vendor_storage: force config spi nor erase size to 64KB Some projects config 4KB erase sizes for SPI NOR, which are incompatible with 64KB in u-boot, and may cause functional abnormalities or data loss. Signed-off-by: Yifeng Zhao Change-Id: I90a026a4cd8cc2550f1cdb84db4602c2e239e51c --- drivers/soc/rockchip/mtd_vendor_storage.c | 31 ++++++++++++++++------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/soc/rockchip/mtd_vendor_storage.c b/drivers/soc/rockchip/mtd_vendor_storage.c index 2f4e4f8038f9..1f32930d906c 100644 --- a/drivers/soc/rockchip/mtd_vendor_storage.c +++ b/drivers/soc/rockchip/mtd_vendor_storage.c @@ -20,6 +20,7 @@ #define MTD_VENDOR_PART_START 0 #define MTD_VENDOR_PART_SIZE FLASH_VENDOR_PART_SIZE +#define MTD_VENDOR_NOR_BLOCK_SIZE 128 #define MTD_VENDOR_PART_NUM 1 #define MTD_VENDOR_TAG VENDOR_HEAD_TAG @@ -43,6 +44,7 @@ static u8 *g_idb_buffer; static struct flash_vendor_info *g_vendor; static DEFINE_MUTEX(vendor_ops_mutex); static struct mtd_info *mtd; +static u32 mtd_erase_size; static const char *vendor_mtd_name = "vnvm"; static struct mtd_nand_info nand_info; static struct platform_device *g_pdev; @@ -54,8 +56,8 @@ static int mtd_vendor_nand_write(void) struct erase_info ei; re_write: - if (nand_info.page_offset >= mtd->erasesize) { - nand_info.blk_offset += mtd->erasesize; + if (nand_info.page_offset >= mtd_erase_size) { + nand_info.blk_offset += mtd_erase_size; if (nand_info.blk_offset >= mtd->size) nand_info.blk_offset = 0; if (mtd_block_isbad(mtd, nand_info.blk_offset)) @@ -63,7 +65,7 @@ re_write: memset(&ei, 0, sizeof(struct erase_info)); ei.addr = nand_info.blk_offset; - ei.len = mtd->erasesize; + ei.len = mtd_erase_size; if (mtd_erase(mtd, &ei)) goto re_write; @@ -100,7 +102,15 @@ static int mtd_vendor_storage_init(void) nand_info.ops_size = (sizeof(*g_vendor) + mtd->writesize - 1) / mtd->writesize; nand_info.ops_size *= mtd->writesize; - for (offset = 0; offset < mtd->size; offset += mtd->erasesize) { + /* + * The NOR FLASH erase size maybe config as 4KB, need to re-define + * and maintain consistency with uboot. + */ + mtd_erase_size = mtd->erasesize; + if (mtd_erase_size <= MTD_VENDOR_NOR_BLOCK_SIZE * 512) + mtd_erase_size = MTD_VENDOR_NOR_BLOCK_SIZE * 512; + + for (offset = 0; offset < mtd->size; offset += mtd_erase_size) { if (!mtd_block_isbad(mtd, offset)) { err = mtd_read(mtd, offset, sizeof(*g_vendor), &bytes_read, (u8 *)g_vendor); @@ -115,11 +125,11 @@ static int mtd_vendor_storage_init(void) } } } else if (nand_info.blk_offset == offset) - nand_info.blk_offset += mtd->erasesize; + nand_info.blk_offset += mtd_erase_size; } if (nand_info.version) { - for (offset = mtd->erasesize - nand_info.ops_size; + for (offset = mtd_erase_size - nand_info.ops_size; offset >= 0; offset -= nand_info.ops_size) { err = mtd_read(mtd, nand_info.blk_offset + offset, @@ -145,7 +155,10 @@ static int mtd_vendor_storage_init(void) if (bytes_read == sizeof(*g_vendor) && g_vendor->tag == MTD_VENDOR_TAG && g_vendor->version == g_vendor->version2) { - nand_info.version = g_vendor->version; + if (nand_info.version > g_vendor->version) + g_vendor->version = nand_info.version; + else + nand_info.version = g_vendor->version; break; } } @@ -155,11 +168,11 @@ static int mtd_vendor_storage_init(void) g_vendor->tag = MTD_VENDOR_TAG; g_vendor->free_size = sizeof(g_vendor->data); g_vendor->version2 = g_vendor->version; - for (offset = 0; offset < mtd->size; offset += mtd->erasesize) { + for (offset = 0; offset < mtd->size; offset += mtd_erase_size) { if (!mtd_block_isbad(mtd, offset)) { memset(&ei, 0, sizeof(struct erase_info)); ei.addr = nand_info.blk_offset + offset; - ei.len = mtd->erasesize; + ei.len = mtd_erase_size; mtd_erase(mtd, &ei); } } From 1dd504da414fd3837b1d0cf82e7bb969345c58a2 Mon Sep 17 00:00:00 2001 From: Chandler Chen Date: Wed, 14 Jun 2023 17:03:58 +0800 Subject: [PATCH 13/27] video: rockchip: mpp: fix crash issue when no iommu Signed-off-by: Chandler Chen Change-Id: Ic0a8523fecad460ec129836ab2693ceb0472f0f9 --- drivers/video/rockchip/mpp/mpp_rkvdec2_link.c | 3 ++- drivers/video/rockchip/mpp/mpp_rkvenc2.c | 9 ++++++--- drivers/video/rockchip/mpp/mpp_vepu2.c | 3 ++- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/video/rockchip/mpp/mpp_rkvdec2_link.c b/drivers/video/rockchip/mpp/mpp_rkvdec2_link.c index eb0e62097460..1176d2886b50 100644 --- a/drivers/video/rockchip/mpp/mpp_rkvdec2_link.c +++ b/drivers/video/rockchip/mpp/mpp_rkvdec2_link.c @@ -1356,7 +1356,8 @@ int rkvdec2_attach_ccu(struct device *dev, struct rkvdec2_dev *dec) /* set the ccu-domain for current device */ ccu_info = queue->cores[0]->iommu_info; cur_info = dec->mpp.iommu_info; - cur_info->domain = ccu_info->domain; + if (cur_info) + cur_info->domain = ccu_info->domain; mpp_iommu_attach(cur_info); } diff --git a/drivers/video/rockchip/mpp/mpp_rkvenc2.c b/drivers/video/rockchip/mpp/mpp_rkvenc2.c index 1168ef5be0db..20936053221a 100644 --- a/drivers/video/rockchip/mpp/mpp_rkvenc2.c +++ b/drivers/video/rockchip/mpp/mpp_rkvenc2.c @@ -2288,8 +2288,10 @@ static int rkvenc_attach_ccu(struct device *dev, struct rkvenc_dev *enc) ccu_info = ccu->main_core->iommu_info; cur_info = enc->mpp.iommu_info; - cur_info->domain = ccu_info->domain; - cur_info->rw_sem = ccu_info->rw_sem; + if (cur_info) { + cur_info->domain = ccu_info->domain; + cur_info->rw_sem = ccu_info->rw_sem; + } mpp_iommu_attach(cur_info); /* increase main core message capacity */ @@ -2467,7 +2469,8 @@ static int rkvenc_core_probe(struct platform_device *pdev) } mpp->session_max_buffers = RKVENC_SESSION_MAX_BUFFERS; enc->hw_info = to_rkvenc_info(mpp->var->hw_info); - mpp->iommu_info->hdl = rkvenc2_iommu_fault_handle; + if (mpp->iommu_info) + mpp->iommu_info->hdl = rkvenc2_iommu_fault_handle; rkvenc_procfs_init(mpp); rkvenc_procfs_ccu_init(mpp); diff --git a/drivers/video/rockchip/mpp/mpp_vepu2.c b/drivers/video/rockchip/mpp/mpp_vepu2.c index 12aef5ebe75b..522cebcafe01 100644 --- a/drivers/video/rockchip/mpp/mpp_vepu2.c +++ b/drivers/video/rockchip/mpp/mpp_vepu2.c @@ -1050,7 +1050,8 @@ static int vepu_attach_ccu(struct device *dev, struct vepu_dev *enc) ccu_info = ccu->main_core->iommu_info; cur_info = enc->mpp.iommu_info; - cur_info->domain = ccu_info->domain; + if (cur_info) + cur_info->domain = ccu_info->domain; mpp_iommu_attach(cur_info); } enc->ccu = ccu; From b20870d86912eb8020d86b893076785b2dadca22 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Mon, 26 Jun 2023 15:01:20 +0800 Subject: [PATCH 14/27] nvme-pci: add NVME_QUIRK_LIMIT_IOQD32 to fix Phison E15 NVMe controller Phison E15 NVMe controller is known to be broken when doing a high loading test. Limit io queue depth to 32 is suggested by vendor. Signed-off-by: Shawn Lin Change-Id: Ie2a89197311a6a7b59281ff12caf545ae0ab37bf --- drivers/nvme/host/nvme.h | 5 +++++ drivers/nvme/host/pci.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/drivers/nvme/host/nvme.h b/drivers/nvme/host/nvme.h index 86336496c65c..9324a38ac871 100644 --- a/drivers/nvme/host/nvme.h +++ b/drivers/nvme/host/nvme.h @@ -155,6 +155,11 @@ enum nvme_quirks { * Reports garbage in the namespace identifiers (eui64, nguid, uuid). */ NVME_QUIRK_BOGUS_NID = (1 << 18), + + /* + * Limit io queue depth to 32 + */ + NVME_QUIRK_LIMIT_IOQD32 = (1 << 31), }; /* diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index c222d7bf6ce1..0cefbe95ed88 100644 --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c @@ -2394,6 +2394,9 @@ static int nvme_pci_enable(struct nvme_dev *dev) dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); + if (dev->ctrl.quirks & NVME_QUIRK_LIMIT_IOQD32) + io_queue_depth = 32; + dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, io_queue_depth); dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ @@ -3236,6 +3239,8 @@ static const struct pci_device_id nvme_id_table[] = { .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | NVME_QUIRK_DISABLE_WRITE_ZEROES| NVME_QUIRK_IGNORE_DEV_SUBNQN, }, + { PCI_DEVICE(0x1987, 0x5013), /* Phison E13 */ + .driver_data = NVME_QUIRK_LIMIT_IOQD32}, { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | NVME_QUIRK_BOGUS_NID, }, From 053f5f2aa57b5ec6248f54925f453132d6359378 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Wed, 21 Jun 2023 10:21:52 +0800 Subject: [PATCH 15/27] arm64: dts: rockchip: rk3562-evb: enable logo display for rgb board Signed-off-by: Damon Ding Change-Id: I451968707f05a5e464cecf7146d15d274bf31d3a --- .../boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb-k350c4516t.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb-k350c4516t.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb-k350c4516t.dts index 93a2f564b592..faaf453266f4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb-k350c4516t.dts +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb-k350c4516t.dts @@ -19,6 +19,7 @@ #size-cells = <0x0>; pinctrl-names = "default"; pinctrl-0 = <&spi_gpio_pins>; + spi-delay-us = <10>; status = "okay"; sck-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; @@ -44,6 +45,7 @@ disable-delay-ms = <20>; width-mm = <217>; height-mm = <136>; + rockchip,cmd-type = "spi"; status = "okay"; // type:0 is cmd, 1 is data @@ -235,7 +237,7 @@ }; &route_rgb { - status = "disabled"; + status = "okay"; connect = <&vp0_out_rgb>; }; From e1e3340e25eb368052f7b369007142606cde7d34 Mon Sep 17 00:00:00 2001 From: Zou Dengming Date: Mon, 26 Jun 2023 20:00:26 +0800 Subject: [PATCH 16/27] arm64: dts: rockchip: rk3588 boards: btsco enable 16k pcm support In android 9,10,11,12,13, we have already support 16k wbs in hardware level code. So, enable 16k support in kernel dts default. Info: In future, to support BTSCO 16k, it only need to change the default setting of bluedroid's "DISABLE_WBS" setting. Change-Id: I31db010004b09723840c9674a093eaaa78822658 Signed-off-by: Zou Dengming --- arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi index f29a82044e47..14620a87b124 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi @@ -87,7 +87,7 @@ bt_sco: bt-sco { status = "disabled"; compatible = "delta,dfbmcs320"; - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; }; bt_sound: bt-sound { @@ -101,7 +101,7 @@ sound-dai = <&i2s2_2ch>; }; simple-audio-card,codec { - sound-dai = <&bt_sco>; + sound-dai = <&bt_sco 1>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi index dcdb93f2b725..008ff6fb4816 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi @@ -85,7 +85,7 @@ bt_sco: bt-sco { status = "disabled"; compatible = "delta,dfbmcs320"; - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; }; bt_sound: bt-sound { @@ -99,7 +99,7 @@ sound-dai = <&i2s2_2ch>; }; simple-audio-card,codec { - sound-dai = <&bt_sco>; + sound-dai = <&bt_sco 1>; }; }; From 2093b6351aca3ee59e6c501decd369d067106eed Mon Sep 17 00:00:00 2001 From: Zou Dengming Date: Mon, 26 Jun 2023 17:22:18 +0800 Subject: [PATCH 17/27] arm64: dts: rockchip: rk356x boards: btsco enable 16k pcm support In android 9,10,11,12,13, we have already support 16k wbs in hardware level code. So, enable 16k support in kernel dts default. Info: In future, to support BTSCO 16k, it only need to change the default setting of bluedroid's "DISABLE_WBS" setting. Change-Id: I382bfdb47a6e13c54c53e8e666aecbad6e135f41 Signed-off-by: Zou Dengming --- arch/arm64/boot/dts/rockchip/rk3566-box.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-box.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-box.dtsi index 73bba8bea79e..ae296857438e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-box.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-box.dtsi @@ -35,7 +35,7 @@ bt_sco: bt-sco { status = "disabled"; compatible = "delta,dfbmcs320"; - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; }; bt_sound: bt-sound { @@ -49,7 +49,7 @@ sound-dai = <&i2s2_2ch>; }; simple-audio-card,codec { - sound-dai = <&bt_sco>; + sound-dai = <&bt_sco 1>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi index a998a93266e0..63b8833f93df 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi @@ -144,7 +144,7 @@ bt_sco: bt-sco { status = "disabled"; compatible = "delta,dfbmcs320"; - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; }; bt_sound: bt-sound { @@ -158,7 +158,7 @@ sound-dai = <&i2s3_2ch>; }; simple-audio-card,codec { - sound-dai = <&bt_sco>; + sound-dai = <&bt_sco 1>; }; }; From ac3b62bb6392a08b4f6f3aeb26c5f2246142eb04 Mon Sep 17 00:00:00 2001 From: Zou Dengming Date: Tue, 27 Jun 2023 10:04:22 +0800 Subject: [PATCH 18/27] arm64: dts: rockchip: rk3528 boards: btsco enable 16k pcm support In android 9,10,11,12,13, we have already support 16k wbs in hardware level code. So, enable 16k support in kernel dts default. Info: In future, to support BTSCO 16k, it only need to change the default setting of bluedroid's "DISABLE_WBS" setting. Signed-off-by: Zou Dengming Change-Id: Ide2435eb0fb9e8e0ffb705d8ba4b43af95dd37ff --- arch/arm64/boot/dts/rockchip/rk3528-demo.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3528-evb.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3528-demo.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-demo.dtsi index d9310275cf5f..aebd9464dddd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-demo.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528-demo.dtsi @@ -43,7 +43,7 @@ bt_sco: bt-sco { status = "disabled"; compatible = "delta,dfbmcs320"; - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; }; bt_sound: bt-sound { @@ -57,7 +57,7 @@ sound-dai = <&sai0>; }; simple-audio-card,codec { - sound-dai = <&bt_sco>; + sound-dai = <&bt_sco 1>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-evb.dtsi index 915a42c20b09..b737c44c3877 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528-evb.dtsi @@ -42,7 +42,7 @@ bt_sco: bt-sco { status = "disabled"; compatible = "delta,dfbmcs320"; - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; }; bt_sound: bt-sound { @@ -56,7 +56,7 @@ sound-dai = <&sai0>; }; simple-audio-card,codec { - sound-dai = <&bt_sco>; + sound-dai = <&bt_sco 1>; }; }; From 1d2f80aa5eb58ed9a5a9613d3212ca701bc1d7ba Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Thu, 13 Oct 2022 17:09:02 +0800 Subject: [PATCH 19/27] video: rockchip: rga3: add mm_flag 'RGA_MEM_FORCE_FLUSH_CACHE' Use the RGA_MEM_FORCE_FLUSH_CACHE flag to force the flush cache for the current buffer, not by judging the memory type. Update driver version to 1.2.27 Signed-off-by: Yu Qiaowei Change-Id: Ife6d26faf59c1e33a2cddc389ded7c93b63a22a5 --- drivers/video/rockchip/rga3/include/rga_drv.h | 2 +- drivers/video/rockchip/rga3/include/rga_mm.h | 2 ++ drivers/video/rockchip/rga3/rga_mm.c | 20 ++++++++++--------- 3 files changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/video/rockchip/rga3/include/rga_drv.h b/drivers/video/rockchip/rga3/include/rga_drv.h index 29a64a6b5a89..68718d1a9300 100644 --- a/drivers/video/rockchip/rga3/include/rga_drv.h +++ b/drivers/video/rockchip/rga3/include/rga_drv.h @@ -87,7 +87,7 @@ #define DRIVER_MAJOR_VERISON 1 #define DRIVER_MINOR_VERSION 2 -#define DRIVER_REVISION_VERSION 26 +#define DRIVER_REVISION_VERSION 27 #define DRIVER_PATCH_VERSION #define DRIVER_VERSION (STR(DRIVER_MAJOR_VERISON) "." STR(DRIVER_MINOR_VERSION) \ diff --git a/drivers/video/rockchip/rga3/include/rga_mm.h b/drivers/video/rockchip/rga3/include/rga_mm.h index 3c2761507990..0bb8e926559a 100644 --- a/drivers/video/rockchip/rga3/include/rga_mm.h +++ b/drivers/video/rockchip/rga3/include/rga_mm.h @@ -18,6 +18,8 @@ enum rga_mm_flag { RGA_MEM_NEED_USE_IOMMU = 1 << 1, /* Flag this is a physical contiguous memory. */ RGA_MEM_PHYSICAL_CONTIGUOUS = 1 << 2, + /* need force flush cache */ + RGA_MEM_FORCE_FLUSH_CACHE = 1 << 3, }; struct rga_mm { diff --git a/drivers/video/rockchip/rga3/rga_mm.c b/drivers/video/rockchip/rga3/rga_mm.c index cd461b57ff7e..dec1e3ad5314 100644 --- a/drivers/video/rockchip/rga3/rga_mm.c +++ b/drivers/video/rockchip/rga3/rga_mm.c @@ -577,6 +577,13 @@ static int rga_mm_map_virt_addr(struct rga_external_buffer *external_buffer, mm_flag |= RGA_MEM_PHYSICAL_CONTIGUOUS; } + /* + * Some userspace virtual addresses do not have an + * interface for flushing the cache, so it is mandatory + * to flush the cache when the virtual address is used. + */ + mm_flag |= RGA_MEM_FORCE_FLUSH_CACHE; + if (!rga_mm_check_memory_limit(scheduler, mm_flag)) { pr_err("scheduler core[%d] unsupported mm_flag[0x%x]!\n", scheduler->core, mm_flag); @@ -1434,7 +1441,7 @@ static int rga_mm_get_buffer(struct rga_mm *mm, goto put_internal_buffer; } - if (internal_buffer->type == RGA_VIRTUAL_ADDRESS) { + if (internal_buffer->mm_flag & RGA_MEM_FORCE_FLUSH_CACHE) { /* * Some userspace virtual addresses do not have an * interface for flushing the cache, so it is mandatory @@ -1463,7 +1470,7 @@ static void rga_mm_put_buffer(struct rga_mm *mm, struct rga_internal_buffer *internal_buffer, enum dma_data_direction dir) { - if (internal_buffer->type == RGA_VIRTUAL_ADDRESS && dir != DMA_NONE) + if (internal_buffer->mm_flag & RGA_MEM_FORCE_FLUSH_CACHE && dir != DMA_NONE) if (rga_mm_sync_dma_sg_for_cpu(internal_buffer, job, dir)) pr_err("sync sgt for cpu error!\n"); @@ -1765,7 +1772,7 @@ static void rga_mm_unmap_channel_job_buffer(struct rga_job *job, struct rga_job_buffer *job_buffer, enum dma_data_direction dir) { - if (job_buffer->addr->type == RGA_VIRTUAL_ADDRESS && dir != DMA_NONE) + if (job_buffer->addr->mm_flag & RGA_MEM_FORCE_FLUSH_CACHE && dir != DMA_NONE) if (rga_mm_sync_dma_sg_for_cpu(job_buffer->addr, job, dir)) pr_err("sync sgt for cpu error!\n"); @@ -1802,12 +1809,7 @@ static int rga_mm_map_channel_job_buffer(struct rga_job *job, goto error_unmap_buffer; } - if (buffer->type == RGA_VIRTUAL_ADDRESS) { - /* - * Some userspace virtual addresses do not have an - * interface for flushing the cache, so it is mandatory - * to flush the cache when the virtual address is used. - */ + if (buffer->mm_flag & RGA_MEM_FORCE_FLUSH_CACHE) { ret = rga_mm_sync_dma_sg_for_device(buffer, job, dir); if (ret < 0) { pr_err("sync sgt for device error!\n"); From b114426b908b7e7603462c286b439bc783e197a9 Mon Sep 17 00:00:00 2001 From: Cai Wenzhong Date: Wed, 14 Jun 2023 11:47:06 +0800 Subject: [PATCH 20/27] media: i2c: max96722: version 1.00.00 Signed-off-by: Cai Wenzhong Change-Id: I59fafb4aa4bfa06b989b9d13ae9b88aa25dc65df --- drivers/media/i2c/max96722.c | 1589 +++++++++++++++++++++++++++------- 1 file changed, 1262 insertions(+), 327 deletions(-) diff --git a/drivers/media/i2c/max96722.c b/drivers/media/i2c/max96722.c index a5a054aef352..94c6204db85f 100644 --- a/drivers/media/i2c/max96722.c +++ b/drivers/media/i2c/max96722.c @@ -2,17 +2,21 @@ /* * max96722 GMSL2/GMSL1 to CSI-2 Deserializer driver * - * Copyright (C) 2022 Rockchip Electronics Co., Ltd. + * Copyright (C) 2023 Rockchip Electronics Co., Ltd. * * V0.0X01.0X00 first version. + * V1.0X00.0X00 Support New Driver Framework. * */ #include #include #include +#include #include +#include #include +#include #include #include #include @@ -21,59 +25,94 @@ #include #include #include +#include #include #include #include #include -#include +#include +#include +#include -#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00) +#define DRIVER_VERSION KERNEL_VERSION(1, 0x00, 0x00) #ifndef V4L2_CID_DIGITAL_GAIN #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN #endif -#define MAX96722_LINK_FREQ_400MHZ 400000000UL -/* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */ -#define MAX96722_PIXEL_RATE (MAX96722_LINK_FREQ_400MHZ * 2LL * 4LL / 24LL) -#define MAX96722_XVCLK_FREQ 24000000 +#define MAX96722_LINK_FREQ_MHZ(x) ((x) * 1000000UL) +#define MAX96722_XVCLK_FREQ 25000000 -#define CHIP_ID 0xA1 +#define MAX96722_CHIP_ID 0xA1 #define MAX96722_REG_CHIP_ID 0x0D -#define MAX96722_REG_CTRL_MODE 0x08a0 -#define MAX96722_MODE_SW_STANDBY 0x4 -#define MAX96722_MODE_STREAMING 0xa4 +#define MAX96715_CHIP_ID 0x45 +#define MAX96715_REG_CHIP_ID 0x1E + +#define MAX9295_CHIP_ID 0x91 +#define MAX9295_REG_CHIP_ID 0x0D + +#define MAX96717_CHIP_ID 0xBF +#define MAX96717_REG_CHIP_ID 0x0D #define MAX96722_REMOTE_CTRL 0x0003 #define MAX96722_REMOTE_DISABLE 0xFF -#define REG_NULL 0xFFFF +/* max96722->link mask: link type = bit[7:4], link mask = bit[3:0] */ +#define MAX96722_GMSL_TYPE_LINK_A BIT(4) +#define MAX96722_GMSL_TYPE_LINK_B BIT(5) +#define MAX96722_GMSL_TYPE_LINK_C BIT(6) +#define MAX96722_GMSL_TYPE_LINK_D BIT(7) +#define MAX96722_GMSL_TYPE_MASK 0xF0 /* bit[7:4], GMSL link type: 0 = GMSL1, 1 = GMSL2 */ -#define MAX96722_LANES 4 +#define MAX96722_LOCK_STATE_LINK_A BIT(0) +#define MAX96722_LOCK_STATE_LINK_B BIT(1) +#define MAX96722_LOCK_STATE_LINK_C BIT(2) +#define MAX96722_LOCK_STATE_LINK_D BIT(3) +#define MAX96722_LOCK_STATE_MASK 0x0F /* bit[3:0], GMSL link mask: 1 = disable, 1 = enable */ + +#define MAX96722_FORCE_ALL_CLOCK_EN 1 /* 1: enable, 0: disable */ + +#define REG_NULL 0xFFFF #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default" #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep" +#define MAX96722_NAME "max96722" + +/* register length: 8bit or 16bit */ +#define MAX96722_REG_LENGTH_08BIT 1 +#define MAX96722_REG_LENGTH_16BIT 2 + +/* register value: 8bit or 16bit or 24bit */ #define MAX96722_REG_VALUE_08BIT 1 #define MAX96722_REG_VALUE_16BIT 2 #define MAX96722_REG_VALUE_24BIT 3 -#define MAX96722_NAME "max96722" -#define MAX96722_MEDIA_BUS_FMT MEDIA_BUS_FMT_RGB888_1X24 +#define MAX96722_I2C_ADDR (0x29) +#define MAX9295_I2C_ADDR (0x40) +#define MAX96715_I2C_ADDR (0x40) +#define MAX96717_I2C_ADDR (0x40) +#define CAMERA_I2C_ADDR (0x36) -static const char * const max96722_supply_names[] = { - "avdd", /* Analog power */ - "dovdd", /* Digital I/O power */ - "dvdd", /* Digital core power */ +#define MAX96722_GET_BIT(x, bit) ((x & (1 << bit)) >> bit) +#define MAX96722_GET_BIT_M_TO_N(x, m, n) \ + ((unsigned int)(x << (31 - (n))) >> ((31 - (n)) + (m))) + +static const char *const max96722_supply_names[] = { + "avdd", /* Analog power */ + "dovdd", /* Digital I/O power */ + "dvdd", /* Digital core power */ }; -#define MAX96722_NUM_SUPPLIES ARRAY_SIZE(max96722_supply_names) +#define MAX96722_NUM_SUPPLIES ARRAY_SIZE(max96722_supply_names) struct regval { u16 i2c_addr; - u16 addr; + u16 reg_len; + u16 reg; u8 val; + u8 mask; u16 delay; }; @@ -85,227 +124,936 @@ struct max96722_mode { u32 vts_def; u32 exp_def; u32 link_freq_idx; + u32 bus_fmt; u32 bpp; const struct regval *reg_list; + u32 vc[PAD_MAX]; }; struct max96722 { - struct i2c_client *client; - struct clk *xvclk; - struct gpio_desc *power_gpio; - struct gpio_desc *reset_gpio; - struct gpio_desc *pwdn_gpio; + struct i2c_client *client; + struct clk *xvclk; + struct gpio_desc *power_gpio; + struct gpio_desc *reset_gpio; + struct gpio_desc *pwdn_gpio; + struct gpio_desc *pocen_gpio; + struct gpio_desc *lock_gpio; struct regulator_bulk_data supplies[MAX96722_NUM_SUPPLIES]; - struct pinctrl *pinctrl; - struct pinctrl_state *pins_default; - struct pinctrl_state *pins_sleep; + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_sleep; - struct v4l2_subdev subdev; - struct media_pad pad; + struct v4l2_subdev subdev; + struct media_pad pad; struct v4l2_ctrl_handler ctrl_handler; - struct v4l2_ctrl *exposure; - struct v4l2_ctrl *anal_gain; - struct v4l2_ctrl *digi_gain; - struct v4l2_ctrl *hblank; - struct v4l2_ctrl *vblank; - struct v4l2_ctrl *pixel_rate; - struct v4l2_ctrl *link_freq; - struct v4l2_ctrl *test_pattern; - struct mutex mutex; - bool streaming; - bool power_on; - bool hot_plug; - u8 is_reset; + struct v4l2_ctrl *exposure; + struct v4l2_ctrl *anal_gain; + struct v4l2_ctrl *digi_gain; + struct v4l2_ctrl *hblank; + struct v4l2_ctrl *vblank; + struct v4l2_ctrl *pixel_rate; + struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *test_pattern; + struct v4l2_fwnode_endpoint bus_cfg; + + struct mutex mutex; + bool streaming; + bool power_on; + bool hot_plug; + u8 is_reset; + int hot_plug_irq; + u32 link_mask; + const struct max96722_mode *supported_modes; const struct max96722_mode *cur_mode; - u32 module_index; - const char *module_facing; - const char *module_name; - const char *len_name; + u32 cfg_modes_num; + u32 module_index; + u32 auto_init_deskew_mask; + u32 frame_sync_period; + const char *module_facing; + const char *module_name; + const char *len_name; + struct regmap *regmap; }; -#define to_max96722(sd) container_of(sd, struct max96722, subdev) +static const struct regmap_config max96722_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .max_register = 0x1F17, +}; -static const struct regval max96722_mipi_init[] = { - {0x6b, 0x0006, 0xF0, 0x00}, - // Disable MIPI output - {0x6b, 0x040B, 0x00, 0x00}, - // RGB888 software override for all pipes since connected GMSL1 is under parallel mode - {0x6b, 0x040B, 0xC0, 0x00}, //0b11000-000, bpp0=0x18 - {0x6b, 0x040E, 0xA4, 0x00}, //0b10-100100, DT0=0x24 - {0x6b, 0x040F, 0x04, 0x00}, //0b0000-0100, DT1=0x24 - {0x6b, 0x0411, 0x18, 0x00}, //0b000-11000, bpp1=0x18 - //Video pipe sel - {0x6b, 0x00F0, 0x40, 0x00}, //LINKA-pipex=pipe0, LINKB-pipex=pipe1 - // Send RGB888, FS, and FE from Pipe 0 to Controller 1 - {0x6b, 0x090B, 0x07, 0x00}, // Enable 3 Mappings - {0x6b, 0x092D, 0x15, 0x00}, //Map Data to Port A - // For the following MSB 2 bits = VC, LSB 6 bits =DT - {0x6b, 0x090D, 0x24, 0x00}, // SRC DT = RGB888 - {0x6b, 0x090E, 0x24, 0x00}, // DEST DT = RGB888 - {0x6b, 0x090F, 0x00, 0x00}, // SRC DT = Frame Start - {0x6b, 0x0910, 0x00, 0x00}, // DEST DT = Frame Start - {0x6b, 0x0911, 0x01, 0x00}, // SRC DT = Frame End - {0x6b, 0x0912, 0x01, 0x00}, // DEST DT = Frame End - //Send RGB888, FS, and FE from Pipe 1 to Controller 2 - {0x6b, 0x094B, 0x07, 0x00}, - {0x6b, 0x096D, 0xAA, 0x00}, // map to MIPI Controller 2 - // For the following MSB 2 bits = VC, LSB 6 bits =DT - {0x6b, 0x094D, 0x24, 0x00}, - {0x6b, 0x094E, 0x24, 0x00}, // map to VC0 - {0x6b, 0x094F, 0x00, 0x00}, // frame start - {0x6b, 0x0950, 0x00, 0x00}, - {0x6b, 0x0951, 0x01, 0x00}, - {0x6b, 0x0952, 0x01, 0x00}, +static struct rkmodule_csi_dphy_param rk3588_dcphy_param = { + .vendor = PHY_VENDOR_SAMSUNG, + .lp_vol_ref = 3, + .lp_hys_sw = {3, 0, 0, 0}, + .lp_escclk_pol_sel = {1, 0, 0, 0}, + .skew_data_cal_clk = {0, 0, 0, 0}, + .clk_hs_term_sel = 2, + .data_hs_term_sel = {2, 2, 2, 2}, + .reserved = {0}, +}; + +/* Max96715 */ +static const struct regval max96722_mipi_4lane_1280x800_30fps[] = { + // Link A/B/C/D all use GMSL1, and disabled + { 0x29, 2, 0x0006, 0x00, 0x00, 0x00 }, // Link A/B/C/D: select GMSL1, Disabled + // Disable MIPI CSI output + { 0x29, 2, 0x040B, 0x00, 0x00, 0x00 }, // CSI_OUT_EN=0, CSI output disabled + // Increase CMU voltage + { 0x29, 2, 0x06C2, 0x10, 0x00, 0x0a }, // Increase CMU voltage to for wide temperature range + // VGAHiGain + { 0x29, 2, 0x14D1, 0x03, 0x00, 0x00 }, // VGAHiGain + { 0x29, 2, 0x15D1, 0x03, 0x00, 0x00 }, // VGAHiGain + { 0x29, 2, 0x16D1, 0x03, 0x00, 0x00 }, // VGAHiGain + { 0x29, 2, 0x17D1, 0x03, 0x00, 0x0a }, // VGAHiGain + // SSC Configuration + { 0x29, 2, 0x1445, 0x00, 0x00, 0x00 }, // Disable SSC + { 0x29, 2, 0x1545, 0x00, 0x00, 0x00 }, // Disable SSC + { 0x29, 2, 0x1645, 0x00, 0x00, 0x00 }, // Disable SSC + { 0x29, 2, 0x1745, 0x00, 0x00, 0x0a }, // Disable SSC + // GMSL1 configuration to match serializer + { 0x29, 2, 0x0B07, 0x84, 0x00, 0x00 }, // Enable HVEN and DBL (application specific) + { 0x29, 2, 0x0C07, 0x84, 0x00, 0x00 }, // Enable HVEN and DBL (application specific) + { 0x29, 2, 0x0D07, 0x84, 0x00, 0x00 }, // Enable HVEN and DBL (application specific) + { 0x29, 2, 0x0E07, 0x84, 0x00, 0x00 }, // Enable HVEN and DBL (application specific) + { 0x29, 2, 0x0B0F, 0x01, 0x00, 0x00 }, // Disable processing HS and DE signals(required when paring with GMSL1 parallel serializers) + { 0x29, 2, 0x0C0F, 0x01, 0x00, 0x00 }, // Disable processing HS and DE signals(required when paring with GMSL1 parallel serializers) + { 0x29, 2, 0x0D0F, 0x01, 0x00, 0x00 }, // Disable processing HS and DE signals(required when paring with GMSL1 parallel serializers) + { 0x29, 2, 0x0E0F, 0x01, 0x00, 0x00 }, // Disable processing HS and DE signals(required when paring with GMSL1 parallel serializers) + // Send YUV422, FS, and FE from Video Pipe 0 to Controller 1 + { 0x29, 2, 0x090B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings + { 0x29, 2, 0x092D, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + { 0x29, 2, 0x090D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit + { 0x29, 2, 0x090E, 0x1e, 0x00, 0x00 }, // DST0 VC = 0, DT = YUV422 8bit + { 0x29, 2, 0x090F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start + { 0x29, 2, 0x0910, 0x00, 0x00, 0x00 }, // DST1 VC = 0, DT = Frame Start + { 0x29, 2, 0x0911, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End + { 0x29, 2, 0x0912, 0x01, 0x00, 0x00 }, // DST2 VC = 0, DT = Frame End + // Send YUV422, FS, and FE from Video Pipe 1 to Controller 1 + { 0x29, 2, 0x094B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings + { 0x29, 2, 0x096D, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + { 0x29, 2, 0x094D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit + { 0x29, 2, 0x094E, 0x5e, 0x00, 0x00 }, // DST0 VC = 1, DT = YUV422 8bit + { 0x29, 2, 0x094F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start + { 0x29, 2, 0x0950, 0x40, 0x00, 0x00 }, // DST1 VC = 1, DT = Frame Start + { 0x29, 2, 0x0951, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End + { 0x29, 2, 0x0952, 0x41, 0x00, 0x00 }, // DST2 VC = 1, DT = Frame End + // Send YUV422, FS, and FE from Video Pipe 2 to Controller 1 + { 0x29, 2, 0x098B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings + { 0x29, 2, 0x09AD, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + { 0x29, 2, 0x098D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit + { 0x29, 2, 0x098E, 0x9e, 0x00, 0x00 }, // DST0 VC = 2, DT = YUV422 8bit + { 0x29, 2, 0x098F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start + { 0x29, 2, 0x0990, 0x80, 0x00, 0x00 }, // DST1 VC = 2, DT = Frame Start + { 0x29, 2, 0x0991, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End + { 0x29, 2, 0x0992, 0x81, 0x00, 0x00 }, // DST2 VC = 2, DT = Frame End + // Send YUV422, FS, and FE from Video Pipe 3 to Controller 1 + { 0x29, 2, 0x09CB, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings + { 0x29, 2, 0x09ED, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + { 0x29, 2, 0x09CD, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit + { 0x29, 2, 0x09CE, 0xde, 0x00, 0x00 }, // DST0 VC = 3, DT = YUV422 8bit + { 0x29, 2, 0x09CF, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start + { 0x29, 2, 0x09D0, 0xc0, 0x00, 0x00 }, // DST1 VC = 3, DT = Frame Start + { 0x29, 2, 0x09D1, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End + { 0x29, 2, 0x09D2, 0xc1, 0x00, 0x00 }, // DST2 VC = 3, DT = Frame End // MIPI PHY Setting - // Set Des in 2x4 mode - {0x6b, 0x08A0, 0x04, 0x00}, + { 0x29, 2, 0x08A0, 0x24, 0x00, 0x00 }, // DPHY0 enabled as clock, MIPI PHY Mode: 2x4 mode // Set Lane Mapping for 4-lane port A - {0x6b, 0x08A3, 0xE4, 0x00}, - {0x6b, 0x08A4, 0xE4, 0x00}, - // Set 4 lane D-PHY - {0x6b, 0x090A, 0xC0, 0x00}, - {0x6b, 0x094A, 0xC0, 0x00}, - {0x6b, 0x098A, 0xC0, 0x00}, - {0x6b, 0x09CA, 0xC0, 0x00}, + { 0x29, 2, 0x08A3, 0xe4, 0x00, 0x00 }, // PHY1 D1->D3, D0->D2; PHY0 D1->D1, D0->D0 + // Set 4 lane D-PHY, 2bit VC + { 0x29, 2, 0x090A, 0xc0, 0x00, 0x00 }, // MIPI PHY 0: 4 lanes, DPHY, 2bit VC + { 0x29, 2, 0x094A, 0xc0, 0x00, 0x00 }, // MIPI PHY 1: 4 lanes, DPHY, 2bit VC // Turn on MIPI PHYs - {0x6b, 0x08A2, 0xF0, 0x00}, - // Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate - {0x6b, 0x1C00, 0xF4, 0x00}, - {0x6b, 0x1D00, 0xF4, 0x00}, - {0x6b, 0x1E00, 0xF4, 0x00}, - {0x6b, 0x1F00, 0xF4, 0x00}, - // Set Data rate to be 800Mbps/lane for port A and enable software override - {0x6b, 0x0415, 0xE8, 0x00}, //override pipe0/1 - {0x6b, 0x0418, 0x28, 0x00}, - {0x6b, 0x041B, 0x28, 0x00}, - {0x6b, 0x041E, 0x28, 0x00}, - // Release reset to DPLL (config_soft_rst_n = 1) - {0x6b, 0x1C00, 0xF5, 0x00}, - {0x6b, 0x1D00, 0xF5, 0x00}, - {0x6b, 0x1E00, 0xF5, 0x00}, - {0x6b, 0x1F00, 0xF5, 0x00}, - {0x6b, 0x0003, 0xFF, 0x00}, - {0x6b, 0x0006, 0xF3, 0x0a}, - // {0x6b, 0x08A0, 0x84}, - {0x6b, REG_NULL, 0x00, 0x00}, + { 0x29, 2, 0x08A2, 0x34, 0x00, 0x00 }, // Enable MIPI PHY 0/1, t_lpx = 106.7ns + // Enable software override for all pipes since GMSL1 data is parallel mode, bpp=8, dt=0x1e(yuv-8) + { 0x29, 2, 0x040B, 0x40, 0x00, 0x00 }, // pipe 0 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + { 0x29, 2, 0x040C, 0x00, 0x00, 0x00 }, // pipe 0 and 1 VC software override: 0x00 + { 0x29, 2, 0x040D, 0x00, 0x00, 0x00 }, // pipe 2 and 3 VC software override: 0x00 + { 0x29, 2, 0x040E, 0x5e, 0x00, 0x00 }, // pipe 0 DT=0x1E: YUV422 8-bit + { 0x29, 2, 0x040F, 0x7e, 0x00, 0x00 }, // pipe 1 DT=0x1E: YUV422 8-bit + { 0x29, 2, 0x0410, 0x7a, 0x00, 0x00 }, // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit + { 0x29, 2, 0x0411, 0x48, 0x00, 0x00 }, // pipe 1 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + { 0x29, 2, 0x0412, 0x20, 0x00, 0x00 }, // pipe 2 bpp=0x08, pipe 3 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + { 0x29, 2, 0x0415, 0xc0, 0xc0, 0x00 }, // pipe 0/1 enable software overide + { 0x29, 2, 0x0418, 0xc0, 0xc0, 0x00 }, // pipe 2/3 enable software overide + { 0x29, 2, 0x041A, 0xf0, 0x00, 0x00 }, // pipe 0/1/2/3: Enable YUV8-/10-bit mux mode + // Enable all links and pipes + { 0x29, 2, 0x0003, 0xaa, 0x00, 0x00 }, // Enable Remote Control Channel Link A/B/C/D for Port 0 + { 0x29, 2, 0x0006, 0x0f, 0x00, 0x64 }, // Enable all links and pipes + // Serializer Setting + { 0x40, 1, 0x04, 0x47, 0x00, 0x05 }, // main_control: Enable CLINK + { 0x40, 1, 0x07, 0x84, 0x00, 0x00 }, // Config SerDes: DBL=1, BWS=0, HIBW=0, PXL_CRC=0, HVEN=1 + { 0x40, 1, 0x67, 0xc4, 0x00, 0x00 }, // Double Alignment Mode: Align at each rising edge of HS + { 0x40, 1, 0x0F, 0xbf, 0x00, 0x00 }, // Enable Set GPO, GPO Output High + { 0x40, 1, 0x3F, 0x08, 0x00, 0x00 }, // Crossbar HS: DIN8 + { 0x40, 1, 0x40, 0x2d, 0x00, 0x00 }, // Crossbar VS: DIN13, INVERT_MUX_VS + { 0x40, 1, 0x20, 0x10, 0x00, 0x00 }, + { 0x40, 1, 0x21, 0x11, 0x00, 0x00 }, + { 0x40, 1, 0x22, 0x12, 0x00, 0x00 }, + { 0x40, 1, 0x23, 0x13, 0x00, 0x00 }, + { 0x40, 1, 0x24, 0x14, 0x00, 0x00 }, + { 0x40, 1, 0x25, 0x15, 0x00, 0x00 }, + { 0x40, 1, 0x26, 0x16, 0x00, 0x00 }, + { 0x40, 1, 0x27, 0x17, 0x00, 0x00 }, + { 0x40, 1, 0x30, 0x00, 0x00, 0x00 }, + { 0x40, 1, 0x31, 0x01, 0x00, 0x00 }, + { 0x40, 1, 0x32, 0x02, 0x00, 0x00 }, + { 0x40, 1, 0x33, 0x03, 0x00, 0x00 }, + { 0x40, 1, 0x34, 0x04, 0x00, 0x00 }, + { 0x40, 1, 0x35, 0x05, 0x00, 0x00 }, + { 0x40, 1, 0x36, 0x06, 0x00, 0x00 }, + { 0x40, 1, 0x37, 0x07, 0x00, 0x00 }, + { 0x40, 1, 0x04, 0x87, 0x00, 0x05 }, // main_control: Enable Serialization + { 0x29, 2, REG_NULL, 0x00, 0x00, 0x00 }, }; -static const struct max96722_mode supported_modes[] = { +static const struct max96722_mode supported_modes_4lane[] = { { - .width = 1920, - .height = 1080, + .width = 1280, + .height = 800, .max_fps = { .numerator = 10000, .denominator = 300000, }, - .reg_list = max96722_mipi_init, - .link_freq_idx = 0, + .reg_list = max96722_mipi_4lane_1280x800_30fps, + .link_freq_idx = 20, + .bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8, + .bpp = 16, + .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0, + .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1, + .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2, + .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3, }, }; +/* link freq = index * MAX96722_LINK_FREQ_MHZ(50) */ static const s64 link_freq_items[] = { - MAX96722_LINK_FREQ_400MHZ, + MAX96722_LINK_FREQ_MHZ(0), + MAX96722_LINK_FREQ_MHZ(50), + MAX96722_LINK_FREQ_MHZ(100), + MAX96722_LINK_FREQ_MHZ(150), + MAX96722_LINK_FREQ_MHZ(200), + MAX96722_LINK_FREQ_MHZ(250), + MAX96722_LINK_FREQ_MHZ(300), + MAX96722_LINK_FREQ_MHZ(350), + MAX96722_LINK_FREQ_MHZ(400), + MAX96722_LINK_FREQ_MHZ(450), + MAX96722_LINK_FREQ_MHZ(500), + MAX96722_LINK_FREQ_MHZ(550), + MAX96722_LINK_FREQ_MHZ(600), + MAX96722_LINK_FREQ_MHZ(650), + MAX96722_LINK_FREQ_MHZ(700), + MAX96722_LINK_FREQ_MHZ(750), + MAX96722_LINK_FREQ_MHZ(800), + MAX96722_LINK_FREQ_MHZ(850), + MAX96722_LINK_FREQ_MHZ(900), + MAX96722_LINK_FREQ_MHZ(950), + MAX96722_LINK_FREQ_MHZ(1000), + MAX96722_LINK_FREQ_MHZ(1050), + MAX96722_LINK_FREQ_MHZ(1100), + MAX96722_LINK_FREQ_MHZ(1150), + MAX96722_LINK_FREQ_MHZ(1200), + MAX96722_LINK_FREQ_MHZ(1250), }; -/* Write registers up to 4 at a time */ -static int max96722_write_reg(struct i2c_client *client, u16 reg, - u32 len, u32 val) +static int max96722_write_reg(struct i2c_client *client, + u16 client_addr, u16 reg, u16 reg_len, u16 val_len, u32 val) { u32 buf_i, val_i; u8 buf[6]; u8 *val_p; __be32 val_be; - dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val); + dev_info(&client->dev, "addr(0x%02x) write reg(0x%04x, %d, 0x%02x)\n", + client_addr, reg, reg_len, val); - if (len > 4) + if (val_len > 4) return -EINVAL; - buf[0] = reg >> 8; - buf[1] = reg & 0xff; + if (reg_len == 2) { + buf[0] = reg >> 8; + buf[1] = reg & 0xff; + + buf_i = 2; + } else { + buf[0] = reg & 0xff; + + buf_i = 1; + } val_be = cpu_to_be32(val); val_p = (u8 *)&val_be; - buf_i = 2; - val_i = 4 - len; + val_i = 4 - val_len; while (val_i < 4) buf[buf_i++] = val_p[val_i++]; - if (i2c_master_send(client, buf, len + 2) != len + 2) { - dev_err(&client->dev, "%s: writing register 0x%x from 0x%x failed\n", - __func__, reg, client->addr); + client->addr = client_addr; + + if (i2c_master_send(client, buf, (val_len + reg_len)) != (val_len + reg_len)) { + dev_err(&client->dev, + "%s: writing register 0x%04x from 0x%02x failed\n", + __func__, reg, client->addr); return -EIO; } return 0; } -static int max96722_write_array(struct i2c_client *client, - const struct regval *regs) -{ - u32 i; - int ret = 0; - - for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) { - client->addr = regs[i].i2c_addr; - ret = max96722_write_reg(client, regs[i].addr, - MAX96722_REG_VALUE_08BIT, - regs[i].val); - msleep(regs[i].delay); - } - - return ret; -} - -/* Read registers up to 4 at a time */ -static int max96722_read_reg(struct i2c_client *client, u16 reg, - unsigned int len, u32 *val) +static int max96722_read_reg(struct i2c_client *client, + u16 client_addr, u16 reg, u16 reg_len, u16 val_len, u8 *val) { struct i2c_msg msgs[2]; u8 *data_be_p; __be32 data_be = 0; __be16 reg_addr_be = cpu_to_be16(reg); + u8 *reg_be_p; int ret; - if (len > 4 || !len) + if (val_len > 4 || !val_len) return -EINVAL; + client->addr = client_addr; data_be_p = (u8 *)&data_be; + reg_be_p = (u8 *)®_addr_be; + /* Write register address */ msgs[0].addr = client->addr; msgs[0].flags = 0; - msgs[0].len = 2; - msgs[0].buf = (u8 *)®_addr_be; + msgs[0].len = reg_len; + msgs[0].buf = ®_be_p[2 - reg_len]; /* Read data from register */ msgs[1].addr = client->addr; msgs[1].flags = I2C_M_RD; - msgs[1].len = len; - msgs[1].buf = &data_be_p[4 - len]; + msgs[1].len = val_len; + msgs[1].buf = &data_be_p[4 - val_len]; ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); if (ret != ARRAY_SIZE(msgs)) { - dev_err(&client->dev, "%s: reading register 0x%x from 0x%x failed\n", - __func__, reg, client->addr); + dev_err(&client->dev, + "%s: reading register 0x%x from 0x%x failed\n", + __func__, reg, client->addr); return -EIO; } *val = be32_to_cpu(data_be); +#if 0 + dev_info(&client->dev, "addr(0x%02x) read reg(0x%04x, %d, 0x%02x)\n", + client_addr, reg, reg_len, *val); +#endif + return 0; } +static int max96722_update_reg_bits(struct i2c_client *client, + u16 client_addr, u16 reg, u16 reg_len, u8 mask, u8 val) +{ + u8 value; + u32 val_len = MAX96722_REG_VALUE_08BIT; + int ret; + + ret = max96722_read_reg(client, client_addr, reg, reg_len, val_len, &value); + if (ret) + return ret; + + value &= ~mask; + value |= (val & mask); + ret = max96722_write_reg(client, client_addr, reg, reg_len, val_len, value); + if (ret) + return ret; + + return 0; +} + +static int max96722_write_array(struct i2c_client *client, + const struct regval *regs) +{ + u32 i; + int ret = 0; + + for (i = 0; ret == 0 && regs[i].reg != REG_NULL; i++) { + if (regs[i].mask != 0) + ret = max96722_update_reg_bits(client, regs[i].i2c_addr, + regs[i].reg, regs[i].reg_len, + regs[i].mask, regs[i].val); + else + ret = max96722_write_reg(client, regs[i].i2c_addr, + regs[i].reg, regs[i].reg_len, + MAX96722_REG_VALUE_08BIT, regs[i].val); + + if (regs[i].delay != 0) + msleep(regs[i].delay); + } + + return ret; +} + +static int max96722_check_local_chipid(struct max96722 *max96722) +{ + struct i2c_client *client = max96722->client; + struct device *dev = &max96722->client->dev; + int ret; + u8 id = 0; + + ret = max96722_read_reg(client, MAX96722_I2C_ADDR, + MAX96722_REG_CHIP_ID, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, &id); + if ((ret != 0) || (id != MAX96722_CHIP_ID)) { + dev_err(dev, "Unexpected MAX96722 chip id(%02x), ret(%d)\n", id, ret); + return -ENODEV; + } + + dev_info(dev, "Detected MAX96722 chipid: %02x\n", id); + + return 0; +} + +static int __maybe_unused max96722_check_remote_chipid(struct max96722 *max96722) +{ + struct device *dev = &max96722->client->dev; + int ret = 0; + u8 id; + + dev_info(dev, "Check remote chipid\n"); + + id = 0; +#if 0 + // max96717 + ret = max96722_read_reg(max96722->client, MAX96717_I2C_ADDR, + MAX96717_REG_CHIP_ID, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, &id); + if ((ret != 0) || (id != MAX96717_CHIP_ID)) { + dev_err(dev, "Unexpected MAX96717 chip id(%02x), ret(%d)\n", id, ret); + return -ENODEV; + } + dev_info(dev, "Detected MAX96717 chipid: 0x%02x\n", id); +#endif + +#if 0 + // max9295 + ret = max96722_read_reg(max96722->client, MAX9295_I2C_ADDR, + MAX9295_REG_CHIP_ID, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, &id); + if ((ret != 0) || (id != MAX9295_CHIP_ID)) { + dev_err(dev, "Unexpected MAX9295 chip id(%02x), ret(%d)\n", id, ret); + return -ENODEV; + } + dev_info(dev, "Detected MAX9295 chipid: 0x%02x\n", id); +#endif + +#if 0 + // max96715 + ret = max96722_read_reg(max96722->client, MAX96715_I2C_ADDR, + MAX96715_REG_CHIP_ID, MAX96722_REG_LENGTH_08BIT, + MAX96722_REG_VALUE_08BIT, &id); + if ((ret != 0) || (id != MAX96715_CHIP_ID)) { + dev_err(dev, "Unexpected MAX96715 chip id(%02x), ret(%d)\n", id, ret); + return -ENODEV; + } + dev_info(dev, "Detected MAX96715 chipid: 0x%02x\n", id); +#endif + + return ret; +} + +static u8 max96722_get_link_lock_state(struct max96722 *max96722, u8 link_mask) +{ + struct i2c_client *client = max96722->client; + struct device *dev = &max96722->client->dev; + u8 lock = 0, lock_state = 0; + u8 link_type = 0; + + link_type = max96722->link_mask & MAX96722_GMSL_TYPE_MASK; + + if (link_mask & MAX96722_LOCK_STATE_LINK_A) { + if (link_type & MAX96722_GMSL_TYPE_LINK_A) { + // GMSL2 LinkA + max96722_read_reg(client, MAX96722_I2C_ADDR, + 0x001a, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, &lock); + if (lock & BIT(3)) { + lock_state |= MAX96722_LOCK_STATE_LINK_A; + dev_info(dev, "GMSL2 LinkA locked\n"); + } + } else { + // GMSL1 LinkA + max96722_read_reg(client, MAX96722_I2C_ADDR, + 0x0bcb, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, &lock); + if (lock & BIT(0)) { + lock_state |= MAX96722_LOCK_STATE_LINK_A; + dev_info(dev, "GMSL1 LinkA locked\n"); + } + } + } + + if (link_mask & MAX96722_LOCK_STATE_LINK_B) { + if (link_type & MAX96722_GMSL_TYPE_LINK_B) { + // GMSL2 LinkB + max96722_read_reg(client, MAX96722_I2C_ADDR, + 0x000a, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, &lock); + if (lock & BIT(3)) { + lock_state |= MAX96722_LOCK_STATE_LINK_B; + dev_info(dev, "GMSL2 LinkB locked\n"); + } + } else { + // GMSL1 LinkB + max96722_read_reg(client, MAX96722_I2C_ADDR, + 0x0ccb, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, &lock); + if (lock & BIT(0)) { + lock_state |= MAX96722_LOCK_STATE_LINK_B; + dev_info(dev, "GMSL1 LinkB locked\n"); + } + } + } + + if (link_mask & MAX96722_LOCK_STATE_LINK_C) { + if (link_type & MAX96722_GMSL_TYPE_LINK_C) { + // GMSL2 LinkC + max96722_read_reg(client, MAX96722_I2C_ADDR, + 0x000b, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, &lock); + if (lock & BIT(3)) { + lock_state |= MAX96722_LOCK_STATE_LINK_C; + dev_info(dev, "GMSL2 LinkC locked\n"); + } + } else { + // GMSL1 LinkC + max96722_read_reg(client, MAX96722_I2C_ADDR, + 0x0dcb, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, &lock); + if (lock & BIT(0)) { + lock_state |= MAX96722_LOCK_STATE_LINK_C; + dev_info(dev, "GMSL1 LinkC locked\n"); + } + } + } + + if (link_mask & MAX96722_LOCK_STATE_LINK_D) { + if (link_type & MAX96722_GMSL_TYPE_LINK_D) { + // GMSL2 LinkD + max96722_read_reg(client, MAX96722_I2C_ADDR, + 0x000c, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, &lock); + if (lock & BIT(3)) { + lock_state |= MAX96722_LOCK_STATE_LINK_D; + dev_info(dev, "GMSL2 LinkD locked\n"); + } + } else { + // GMSL1 LinkD + max96722_read_reg(client, MAX96722_I2C_ADDR, + 0x0ecb, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, &lock); + if (lock & BIT(0)) { + lock_state |= MAX96722_LOCK_STATE_LINK_D; + dev_info(dev, "GMSL1 LinkD locked\n"); + } + } + } + + return lock_state; +} + +static int max96722_check_link_lock_state(struct max96722 *max96722) +{ + struct i2c_client *client = max96722->client; + struct device *dev = &max96722->client->dev; + u8 lock_state = 0, link_mask = 0, link_type = 0; + int ret, i, time_ms; + + ret = max96722_check_local_chipid(max96722); + if (ret) + return ret; + + /* IF VDD = 1.2V: Enable REG_ENABLE and REG_MNL + * CTRL0: Enable REG_ENABLE + * CTRL2: Enable REG_MNL + */ + max96722_update_reg_bits(client, MAX96722_I2C_ADDR, + 0x0017, MAX96722_REG_LENGTH_16BIT, BIT(2), BIT(2)); + max96722_update_reg_bits(client, MAX96722_I2C_ADDR, + 0x0019, MAX96722_REG_LENGTH_16BIT, BIT(4), BIT(4)); + + // CSI output disabled + max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x040B, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0x00); + + // All links select mode by link_type and disable at beginning. + link_type = max96722->link_mask & MAX96722_GMSL_TYPE_MASK; + max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x0006, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, link_type); + + // Link Rate + // Link A ~ Link D Transmitter Rate: 187.5Mbps, Receiver Rate: 3Gbps + max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x0010, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0x11); + max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x0011, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0x11); + + // GMSL1: Enable HIM on deserializer on Link A/B/C/D + if ((link_type & MAX96722_GMSL_TYPE_LINK_A) == 0) { + max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x0B06, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0xEF); + } + if ((link_type & MAX96722_GMSL_TYPE_LINK_B) == 0) { + max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x0C06, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0xEF); + } + if ((link_type & MAX96722_GMSL_TYPE_LINK_C) == 0) { + max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x0D06, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0xEF); + } + if ((link_type & MAX96722_GMSL_TYPE_LINK_D) == 0) { + max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x0E06, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0xEF); + } + + // Link A ~ Link D One-Shot Reset depend on link_mask + link_mask = max96722->link_mask & MAX96722_LOCK_STATE_MASK; + max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x0018, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, link_mask); + + // Link A ~ Link D enable depend on link_type and link_mask + max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x0006, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, link_type | link_mask); + + time_ms = 50; + msleep(time_ms); + + for (i = 0; i < 20; i++) { + if ((lock_state & MAX96722_LOCK_STATE_LINK_A) == 0) + if (max96722_get_link_lock_state(max96722, MAX96722_LOCK_STATE_LINK_A)) { + lock_state |= MAX96722_LOCK_STATE_LINK_A; + dev_info(dev, "LinkA locked time: %d ms\n", time_ms); + } + + if ((lock_state & MAX96722_LOCK_STATE_LINK_B) == 0) + if (max96722_get_link_lock_state(max96722, MAX96722_LOCK_STATE_LINK_B)) { + lock_state |= MAX96722_LOCK_STATE_LINK_B; + dev_info(dev, "LinkB locked time: %d ms\n", time_ms); + } + + if ((lock_state & MAX96722_LOCK_STATE_LINK_C) == 0) + if (max96722_get_link_lock_state(max96722, MAX96722_LOCK_STATE_LINK_C)) { + lock_state |= MAX96722_LOCK_STATE_LINK_C; + dev_info(dev, "LinkC locked time: %d ms\n", time_ms); + } + + if ((lock_state & MAX96722_LOCK_STATE_LINK_D) == 0) + if (max96722_get_link_lock_state(max96722, MAX96722_LOCK_STATE_LINK_D)) { + lock_state |= MAX96722_LOCK_STATE_LINK_D; + dev_info(dev, "LinkD locked time: %d ms\n", time_ms); + } + + if ((lock_state & link_mask) == link_mask) { + dev_info(dev, "All Links are locked: 0x%x, time_ms = %d\n", lock_state, time_ms); +#if 0 + max96722_check_remote_chipid(max96722); +#endif + return 0; + } + + msleep(10); + time_ms += 10; + } + + if ((lock_state & link_mask) != 0) { + dev_info(dev, "Partial links are locked: 0x%x, time_ms = %d\n", lock_state, time_ms); + return 0; + } else { + dev_err(dev, "Failed to detect camera link, time_ms = %d!\n", time_ms); + return -ENODEV; + } +} + +static irqreturn_t max96722_hot_plug_detect_irq_handler(int irq, void *dev_id) +{ + struct max96722 *max96722 = dev_id; + struct device *dev = &max96722->client->dev; + u8 lock_state = 0, link_mask = 0; + + link_mask = max96722->link_mask & MAX96722_LOCK_STATE_MASK; + if (max96722->streaming) { + lock_state = max96722_get_link_lock_state(max96722, link_mask); + if (lock_state == link_mask) { + dev_info(dev, "serializer plug in, lock_state = 0x%02x\n", lock_state); + } else { + dev_info(dev, "serializer plug out, lock_state = 0x%02x\n", lock_state); + } + } + + return IRQ_HANDLED; +} + +static int __maybe_unused max96722_dphy_dpll_predef_set(struct i2c_client *client, + u32 link_freq_mhz) +{ + int ret = 0; + u8 dpll_val = 0, dpll_lock = 0; + u8 mipi_tx_phy_enable = 0; + + ret = max96722_read_reg(client, MAX96722_I2C_ADDR, + 0x08A2, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, &mipi_tx_phy_enable); + if (ret) + return ret; + mipi_tx_phy_enable = (mipi_tx_phy_enable & 0xF0) >> 4; + + dev_info(&client->dev, "DPLL predef set: mipi_tx_phy_enable = 0x%02x, link_freq_mhz = %d\n", + mipi_tx_phy_enable, link_freq_mhz); + + // dphy max data rate is 2500MHz + if (link_freq_mhz > (2500 >> 1)) + link_freq_mhz = (2500 >> 1); + + dpll_val = DIV_ROUND_UP(link_freq_mhz * 2, 100) & 0x1F; + // Disable software override for frequency fine tuning + dpll_val |= BIT(5); + + // MIPI PHY0 + if (mipi_tx_phy_enable & BIT(0)) { + // Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x1C00, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, + 0xf4); + // Set data rate and enable software override + ret |= max96722_update_reg_bits(client, MAX96722_I2C_ADDR, + 0x0415, MAX96722_REG_LENGTH_16BIT, 0x3F, dpll_val); + // Release reset to DPLL (config_soft_rst_n = 1) + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x1C00, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0xf5); + } + + // MIPI PHY1 + if (mipi_tx_phy_enable & BIT(1)) { + // Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x1D00, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0xf4); + // Set data rate and enable software override + ret |= max96722_update_reg_bits(client, MAX96722_I2C_ADDR, + 0x0418, MAX96722_REG_LENGTH_16BIT, 0x3F, dpll_val); + // Release reset to DPLL (config_soft_rst_n = 1) + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x1D00, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0xf5); + } + + // MIPI PHY2 + if (mipi_tx_phy_enable & BIT(2)) { + // Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x1E00, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0xf4); + // Set data rate and enable software override + ret |= max96722_update_reg_bits(client, MAX96722_I2C_ADDR, + 0x041B, MAX96722_REG_LENGTH_16BIT, 0x3F, dpll_val); + // Release reset to DPLL (config_soft_rst_n = 1) + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x1E00, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0xf5); + } + + // MIPI PHY3 + if (mipi_tx_phy_enable & BIT(3)) { + // Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x1F00, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0xf4); + // Set data rate and enable software override + ret |= max96722_update_reg_bits(client, MAX96722_I2C_ADDR, + 0x041E, MAX96722_REG_LENGTH_16BIT, 0x3F, dpll_val); + // Release reset to DPLL (config_soft_rst_n = 1) + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x1F00, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0xf5); + } + + if (ret) { + dev_err(&client->dev, "DPLL predef set error!\n"); + return ret; + } + + ret = read_poll_timeout(max96722_read_reg, ret, + !(ret < 0) && (dpll_lock & 0xF0), + 1000, 10000, false, + client, MAX96722_I2C_ADDR, + 0x0400, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, &dpll_lock); + if (ret < 0) { + dev_err(&client->dev, "DPLL is not locked, dpll_lock = 0x%02x\n", dpll_lock); + return ret; + } else { + dev_err(&client->dev, "DPLL is locked, dpll_lock = 0x%02x\n", dpll_lock); + return 0; + } +} + +static int max96722_auto_init_deskew(struct i2c_client *client, u32 deskew_mask) +{ + int ret = 0; + + dev_info(&client->dev, "Auto initial deskew: deskew_mask = 0x%02x\n", deskew_mask); + + // D-PHY Deskew Initial Calibration Control + if (deskew_mask & BIT(0)) // MIPI PHY0 + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x0903, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0x80); + + if (deskew_mask & BIT(1)) // MIPI PHY1 + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x0943, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0x80); + + if (deskew_mask & BIT(2)) // MIPI PHY2 + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x0983, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0x80); + + if (deskew_mask & BIT(3)) // MIPI PHY3 + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x09C3, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0x80); + + return ret; +} + +static int max96722_frame_sync_period(struct i2c_client *client, u32 period) +{ + u32 pclk, fsync_peroid; + u8 fsync_peroid_h, fsync_peroid_m, fsync_peroid_l; + int ret = 0; + + if (period == 0) + return 0; + + dev_info(&client->dev, "Frame sync period = %d\n", period); + +#if 1 // TODO: Sensor + // sendor slave mode enable +#endif + + // Master link Video 0 for frame sync generation + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x04A2, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0x00); + // Disable Vsync-Fsync overlap window + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x04AA, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0x00); + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x04AB, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0x00); + + // Set FSYNC period to 25M/30 clock cycles. PCLK = 25MHz. Sync freq = 30Hz + pclk = 25 * 1000 * 1000; + fsync_peroid = DIV_ROUND_UP(pclk, period) - 1; + fsync_peroid_l = (fsync_peroid >> 0) & 0xFF; + fsync_peroid_m = (fsync_peroid >> 8) & 0xFF; + fsync_peroid_h = (fsync_peroid >> 16) & 0xFF; + dev_info(&client->dev, "Frame sync period: H = 0x%02x, M = 0x%02x, L = 0x%02x\n", + fsync_peroid_h, fsync_peroid_m, fsync_peroid_l); + // FSYNC_PERIOD_H + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x04A7, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, fsync_peroid_h); + // FSYNC_PERIOD_M + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x04A6, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, fsync_peroid_m); + // FSYNC_PERIOD_L + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x04A5, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, fsync_peroid_l); + + // FSYNC is GMSL2 type, use osc for fsync, include all links/pipes in fsync gen + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x04AF, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0xcf); + +#if 1 // TODO: FSYNC GPIO + // FSYNC_TX_ID: set 4 to match MFP4 on serializer side + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x04B1, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0x20); +#endif + +#if 1 // TODO: Serializer + // Enable GPIO_RX_EN on serializer MFP4 + ret |= max96722_write_reg(client, 0x40, + 0x02CA, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0x84); +#endif + + // MFP2, VS not gen internally, GPIO not used to gen fsync, manual mode + ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, + 0x04A0, MAX96722_REG_LENGTH_16BIT, + MAX96722_REG_VALUE_08BIT, 0x04); + + return ret; +} + +static int max96722_mipi_enable(struct i2c_client *client, bool enable) +{ + int ret = 0; + + if (enable) { +#if MAX96722_FORCE_ALL_CLOCK_EN + // Force all MIPI clocks running + ret |= max96722_update_reg_bits(client, + MAX96722_I2C_ADDR, + 0x08A0, MAX96722_REG_LENGTH_16BIT, BIT(7), BIT(7)); +#endif + // CSI output enabled + ret |= max96722_update_reg_bits(client, + MAX96722_I2C_ADDR, + 0x040B, MAX96722_REG_LENGTH_16BIT, BIT(1), BIT(1)); + } else { +#if MAX96722_FORCE_ALL_CLOCK_EN + // Normal mode + ret |= max96722_update_reg_bits(client, + MAX96722_I2C_ADDR, + 0x08A0, MAX96722_REG_LENGTH_16BIT, BIT(7), 0x00); +#endif + // CSI output disabled + ret |= max96722_update_reg_bits(client, + MAX96722_I2C_ADDR, + 0x040B, MAX96722_REG_LENGTH_16BIT, BIT(1), 0x00); + } + + return ret; +} + static int max96722_get_reso_dist(const struct max96722_mode *mode, - struct v4l2_mbus_framefmt *framefmt) + struct v4l2_mbus_framefmt *framefmt) { return abs(mode->width - framefmt->width) + - abs(mode->height - framefmt->height); + abs(mode->height - framefmt->height); } static const struct max96722_mode * -max96722_find_best_fit(struct v4l2_subdev_format *fmt) +max96722_find_best_fit(struct max96722 *max96722, struct v4l2_subdev_format *fmt) { struct v4l2_mbus_framefmt *framefmt = &fmt->format; int dist; @@ -313,28 +1061,32 @@ max96722_find_best_fit(struct v4l2_subdev_format *fmt) int cur_best_fit_dist = -1; unsigned int i; - for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { - dist = max96722_get_reso_dist(&supported_modes[i], framefmt); - if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) { + for (i = 0; i < max96722->cfg_modes_num; i++) { + dist = max96722_get_reso_dist(&max96722->supported_modes[i], framefmt); + if ((cur_best_fit_dist == -1 || dist < cur_best_fit_dist) + && (max96722->supported_modes[i].bus_fmt == framefmt->code)) { cur_best_fit_dist = dist; cur_best_fit = i; } } - return &supported_modes[cur_best_fit]; + return &max96722->supported_modes[cur_best_fit]; } static int max96722_set_fmt(struct v4l2_subdev *sd, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_format *fmt) + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) { - struct max96722 *max96722 = to_max96722(sd); + struct max96722 *max96722 = v4l2_get_subdevdata(sd); const struct max96722_mode *mode; + u64 pixel_rate = 0; + u8 data_lanes; mutex_lock(&max96722->mutex); - mode = max96722_find_best_fit(fmt); - fmt->format.code = MAX96722_MEDIA_BUS_FMT; + mode = max96722_find_best_fit(max96722, fmt); + + fmt->format.code = mode->bus_fmt; fmt->format.width = mode->width; fmt->format.height = mode->height; fmt->format.field = V4L2_FIELD_NONE; @@ -350,6 +1102,19 @@ static int max96722_set_fmt(struct v4l2_subdev *sd, mutex_unlock(&max96722->mutex); return -EBUSY; } + + max96722->cur_mode = mode; + + __v4l2_ctrl_s_ctrl(max96722->link_freq, mode->link_freq_idx); + /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */ + data_lanes = max96722->bus_cfg.bus.mipi_csi2.num_data_lanes; + pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * data_lanes; + __v4l2_ctrl_s_ctrl_int64(max96722->pixel_rate, pixel_rate); + + dev_info(&max96722->client->dev, "mipi_freq_idx = %d, mipi_link_freq = %lld\n", + mode->link_freq_idx, link_freq_items[mode->link_freq_idx]); + dev_info(&max96722->client->dev, "pixel_rate = %lld, bpp = %d\n", + pixel_rate, mode->bpp); } mutex_unlock(&max96722->mutex); @@ -358,10 +1123,10 @@ static int max96722_set_fmt(struct v4l2_subdev *sd, } static int max96722_get_fmt(struct v4l2_subdev *sd, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_format *fmt) + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) { - struct max96722 *max96722 = to_max96722(sd); + struct max96722 *max96722 = v4l2_get_subdevdata(sd); const struct max96722_mode *mode = max96722->cur_mode; mutex_lock(&max96722->mutex); @@ -375,8 +1140,12 @@ static int max96722_get_fmt(struct v4l2_subdev *sd, } else { fmt->format.width = mode->width; fmt->format.height = mode->height; - fmt->format.code = MAX96722_MEDIA_BUS_FMT; + fmt->format.code = mode->bus_fmt; fmt->format.field = V4L2_FIELD_NONE; + if (fmt->pad < PAD_MAX && fmt->pad >= PAD0) + fmt->reserved[0] = mode->vc[fmt->pad]; + else + fmt->reserved[0] = mode->vc[PAD0]; } mutex_unlock(&max96722->mutex); @@ -384,38 +1153,43 @@ static int max96722_get_fmt(struct v4l2_subdev *sd, } static int max96722_enum_mbus_code(struct v4l2_subdev *sd, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_mbus_code_enum *code) + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) { + struct max96722 *max96722 = v4l2_get_subdevdata(sd); + const struct max96722_mode *mode = max96722->cur_mode; + if (code->index != 0) return -EINVAL; - code->code = MAX96722_MEDIA_BUS_FMT; + code->code = mode->bus_fmt; return 0; } static int max96722_enum_frame_sizes(struct v4l2_subdev *sd, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_frame_size_enum *fse) + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) { - if (fse->index >= ARRAY_SIZE(supported_modes)) + struct max96722 *max96722 = v4l2_get_subdevdata(sd); + + if (fse->index >= max96722->cfg_modes_num) return -EINVAL; - if (fse->code != MAX96722_MEDIA_BUS_FMT) + if (fse->code != max96722->supported_modes[fse->index].bus_fmt) return -EINVAL; - fse->min_width = supported_modes[fse->index].width; - fse->max_width = supported_modes[fse->index].width; - fse->max_height = supported_modes[fse->index].height; - fse->min_height = supported_modes[fse->index].height; + fse->min_width = max96722->supported_modes[fse->index].width; + fse->max_width = max96722->supported_modes[fse->index].width; + fse->max_height = max96722->supported_modes[fse->index].height; + fse->min_height = max96722->supported_modes[fse->index].height; return 0; } static int max96722_g_frame_interval(struct v4l2_subdev *sd, - struct v4l2_subdev_frame_interval *fi) + struct v4l2_subdev_frame_interval *fi) { - struct max96722 *max96722 = to_max96722(sd); + struct max96722 *max96722 = v4l2_get_subdevdata(sd); const struct max96722_mode *mode = max96722->cur_mode; mutex_lock(&max96722->mutex); @@ -426,7 +1200,7 @@ static int max96722_g_frame_interval(struct v4l2_subdev *sd, } static void max96722_get_module_inf(struct max96722 *max96722, - struct rkmodule_inf *inf) + struct rkmodule_inf *inf) { memset(inf, 0, sizeof(*inf)); strscpy(inf->base.sensor, MAX96722_NAME, sizeof(inf->base.sensor)); @@ -435,26 +1209,30 @@ static void max96722_get_module_inf(struct max96722 *max96722, strscpy(inf->base.lens, max96722->len_name, sizeof(inf->base.lens)); } -static void max96722_get_vicap_rst_inf(struct max96722 *max96722, - struct rkmodule_vicap_reset_info *rst_info) +static void +max96722_get_vicap_rst_inf(struct max96722 *max96722, + struct rkmodule_vicap_reset_info *rst_info) { struct i2c_client *client = max96722->client; rst_info->is_reset = max96722->hot_plug; max96722->hot_plug = false; rst_info->src = RKCIF_RESET_SRC_ERR_HOTPLUG; - dev_info(&client->dev, "%s: rst_info->is_reset:%d.\n", __func__, rst_info->is_reset); + dev_info(&client->dev, "%s: rst_info->is_reset:%d.\n", __func__, + rst_info->is_reset); } -static void max96722_set_vicap_rst_inf(struct max96722 *max96722, - struct rkmodule_vicap_reset_info rst_info) +static void +max96722_set_vicap_rst_inf(struct max96722 *max96722, + struct rkmodule_vicap_reset_info rst_info) { max96722->is_reset = rst_info.is_reset; } static long max96722_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) { - struct max96722 *max96722 = to_max96722(sd); + struct max96722 *max96722 = v4l2_get_subdevdata(sd); + struct rkmodule_csi_dphy_param *dphy_param; long ret = 0; u32 stream = 0; @@ -463,30 +1241,34 @@ static long max96722_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) max96722_get_module_inf(max96722, (struct rkmodule_inf *)arg); break; case RKMODULE_SET_QUICK_STREAM: - stream = *((u32 *)arg); if (stream) - ret = max96722_write_reg(max96722->client, - MAX96722_REG_CTRL_MODE, - MAX96722_REG_VALUE_08BIT, - MAX96722_MODE_STREAMING); + ret = max96722_mipi_enable(max96722->client, true); else - ret = max96722_write_reg(max96722->client, - MAX96722_REG_CTRL_MODE, - MAX96722_REG_VALUE_08BIT, - MAX96722_MODE_SW_STANDBY); + ret = max96722_mipi_enable(max96722->client, false); break; case RKMODULE_GET_VICAP_RST_INFO: - max96722_get_vicap_rst_inf(max96722, - (struct rkmodule_vicap_reset_info *)arg); + max96722_get_vicap_rst_inf( + max96722, (struct rkmodule_vicap_reset_info *)arg); break; case RKMODULE_SET_VICAP_RST_INFO: - max96722_set_vicap_rst_inf(max96722, - *(struct rkmodule_vicap_reset_info *)arg); + max96722_set_vicap_rst_inf( + max96722, *(struct rkmodule_vicap_reset_info *)arg); break; - case RKMODULE_GET_CSI_DSI_INFO: - *(int *)arg = RKMODULE_CSI_INPUT; + case RKMODULE_GET_START_STREAM_SEQ: + break; + case RKMODULE_SET_CSI_DPHY_PARAM: + dphy_param = (struct rkmodule_csi_dphy_param *)arg; + if (dphy_param->vendor == rk3588_dcphy_param.vendor) + rk3588_dcphy_param = *dphy_param; + dev_dbg(&max96722->client->dev, "sensor set dphy param\n"); + break; + case RKMODULE_GET_CSI_DPHY_PARAM: + dphy_param = (struct rkmodule_csi_dphy_param *)arg; + if (dphy_param->vendor == rk3588_dcphy_param.vendor) + *dphy_param = rk3588_dcphy_param; + dev_dbg(&max96722->client->dev, "sensor get dphy param\n"); break; default: ret = -ENOIOCTLCMD; @@ -497,13 +1279,14 @@ static long max96722_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) } #ifdef CONFIG_COMPAT -static long max96722_compat_ioctl32(struct v4l2_subdev *sd, - unsigned int cmd, unsigned long arg) +static long max96722_compat_ioctl32(struct v4l2_subdev *sd, unsigned int cmd, + unsigned long arg) { void __user *up = compat_ptr(arg); struct rkmodule_inf *inf; struct rkmodule_awb_cfg *cfg; struct rkmodule_vicap_reset_info *vicap_rst_inf; + struct rkmodule_csi_dphy_param *dphy_param; long ret = 0; int *seq; u32 stream = 0; @@ -547,7 +1330,8 @@ static long max96722_compat_ioctl32(struct v4l2_subdev *sd, ret = max96722_ioctl(sd, cmd, vicap_rst_inf); if (!ret) { - ret = copy_to_user(up, vicap_rst_inf, sizeof(*vicap_rst_inf)); + ret = copy_to_user(up, vicap_rst_inf, + sizeof(*vicap_rst_inf)); if (ret) ret = -EFAULT; } @@ -589,20 +1373,34 @@ static long max96722_compat_ioctl32(struct v4l2_subdev *sd, else ret = -EFAULT; break; - case RKMODULE_GET_CSI_DSI_INFO: - seq = kzalloc(sizeof(*seq), GFP_KERNEL); - if (!seq) { + case RKMODULE_SET_CSI_DPHY_PARAM: + dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL); + if (!dphy_param) { ret = -ENOMEM; return ret; } - ret = max96722_ioctl(sd, cmd, seq); + ret = copy_from_user(dphy_param, up, sizeof(*dphy_param)); + if (!ret) + ret = max96722_ioctl(sd, cmd, dphy_param); + else + ret = -EFAULT; + kfree(dphy_param); + break; + case RKMODULE_GET_CSI_DPHY_PARAM: + dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL); + if (!dphy_param) { + ret = -ENOMEM; + return ret; + } + + ret = max96722_ioctl(sd, cmd, dphy_param); if (!ret) { - ret = copy_to_user(up, seq, sizeof(*seq)); + ret = copy_to_user(up, dphy_param, sizeof(*dphy_param)); if (ret) ret = -EFAULT; } - kfree(seq); + kfree(dphy_param); break; default: ret = -ENOIOCTLCMD; @@ -616,11 +1414,40 @@ static long max96722_compat_ioctl32(struct v4l2_subdev *sd, static int __max96722_start_stream(struct max96722 *max96722) { int ret; + u32 link_freq_mhz, link_freq_idx; - ret = max96722_write_array(max96722->client, max96722->cur_mode->reg_list); + ret = max96722_check_link_lock_state(max96722); if (ret) return ret; + if (max96722->hot_plug_irq > 0) + enable_irq(max96722->hot_plug_irq); + + ret = max96722_write_array(max96722->client, + max96722->cur_mode->reg_list); + if (ret) + return ret; + + link_freq_idx = max96722->cur_mode->link_freq_idx; + link_freq_mhz = (u32)div_s64(link_freq_items[link_freq_idx], 1000000L); + ret = max96722_dphy_dpll_predef_set(max96722->client, link_freq_mhz); + if (ret) + return ret; + + if (max96722->auto_init_deskew_mask != 0) { + ret = max96722_auto_init_deskew(max96722->client, + max96722->auto_init_deskew_mask); + if (ret) + return ret; + } + + if (max96722->frame_sync_period != 0) { + ret = max96722_frame_sync_period(max96722->client, + max96722->frame_sync_period); + if (ret) + return ret; + } + /* In case these controls are set before streaming */ mutex_unlock(&max96722->mutex); ret = v4l2_ctrl_handler_setup(&max96722->ctrl_handler); @@ -628,31 +1455,28 @@ static int __max96722_start_stream(struct max96722 *max96722) if (ret) return ret; - return max96722_write_reg(max96722->client, - MAX96722_REG_CTRL_MODE, - MAX96722_REG_VALUE_08BIT, - MAX96722_MODE_STREAMING); + return max96722_mipi_enable(max96722->client, true); + } static int __max96722_stop_stream(struct max96722 *max96722) { - return max96722_write_reg(max96722->client, - MAX96722_REG_CTRL_MODE, - MAX96722_REG_VALUE_08BIT, - MAX96722_MODE_SW_STANDBY); + if (max96722->hot_plug_irq > 0) + disable_irq(max96722->hot_plug_irq); + + return max96722_mipi_enable(max96722->client, false); } static int max96722_s_stream(struct v4l2_subdev *sd, int on) { - struct max96722 *max96722 = to_max96722(sd); + struct max96722 *max96722 = v4l2_get_subdevdata(sd); struct i2c_client *client = max96722->client; int ret = 0; dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on, - max96722->cur_mode->width, - max96722->cur_mode->height, + max96722->cur_mode->width, max96722->cur_mode->height, DIV_ROUND_CLOSEST(max96722->cur_mode->max_fps.denominator, - max96722->cur_mode->max_fps.numerator)); + max96722->cur_mode->max_fps.numerator)); mutex_lock(&max96722->mutex); on = !!on; @@ -687,7 +1511,7 @@ unlock_and_return: static int max96722_s_power(struct v4l2_subdev *sd, int on) { - struct max96722 *max96722 = to_max96722(sd); + struct max96722 *max96722 = v4l2_get_subdevdata(sd); struct i2c_client *client = max96722->client; int ret = 0; @@ -728,14 +1552,19 @@ static int __max96722_power_on(struct max96722 *max96722) u32 delay_us; struct device *dev = &max96722->client->dev; - if (!IS_ERR(max96722->power_gpio)) + if (!IS_ERR(max96722->power_gpio)) { gpiod_set_value_cansleep(max96722->power_gpio, 1); + usleep_range(5000, 10000); + } - usleep_range(1000, 2000); + if (!IS_ERR(max96722->pocen_gpio)) { + gpiod_set_value_cansleep(max96722->pocen_gpio, 1); + usleep_range(5000, 10000); + } if (!IS_ERR_OR_NULL(max96722->pins_default)) { ret = pinctrl_select_state(max96722->pinctrl, - max96722->pins_default); + max96722->pins_default); if (ret < 0) dev_err(dev, "could not set pins\n"); } @@ -748,11 +1577,11 @@ static int __max96722_power_on(struct max96722 *max96722) dev_err(dev, "Failed to enable regulators\n"); goto disable_clk; } - - if (!IS_ERR(max96722->reset_gpio)) + if (!IS_ERR(max96722->reset_gpio)) { gpiod_set_value_cansleep(max96722->reset_gpio, 1); + usleep_range(500, 1000); + } - usleep_range(500, 1000); if (!IS_ERR(max96722->pwdn_gpio)) gpiod_set_value_cansleep(max96722->pwdn_gpio, 1); @@ -776,6 +1605,7 @@ static void __max96722_power_off(struct max96722 *max96722) if (!IS_ERR(max96722->pwdn_gpio)) gpiod_set_value_cansleep(max96722->pwdn_gpio, 0); clk_disable_unprepare(max96722->xvclk); + if (!IS_ERR(max96722->reset_gpio)) gpiod_set_value_cansleep(max96722->reset_gpio, 0); @@ -785,17 +1615,21 @@ static void __max96722_power_off(struct max96722 *max96722) if (ret < 0) dev_dbg(dev, "could not set pins\n"); } - if (!IS_ERR(max96722->power_gpio)) - gpiod_set_value_cansleep(max96722->power_gpio, 0); regulator_bulk_disable(MAX96722_NUM_SUPPLIES, max96722->supplies); + + if (!IS_ERR(max96722->pocen_gpio)) + gpiod_set_value_cansleep(max96722->pocen_gpio, 0); + + if (!IS_ERR(max96722->power_gpio)) + gpiod_set_value_cansleep(max96722->power_gpio, 0); } static int max96722_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); - struct max96722 *max96722 = to_max96722(sd); + struct max96722 *max96722 = v4l2_get_subdevdata(sd); return __max96722_power_on(max96722); } @@ -804,7 +1638,7 @@ static int max96722_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); - struct max96722 *max96722 = to_max96722(sd); + struct max96722 *max96722 = v4l2_get_subdevdata(sd); __max96722_power_off(max96722); @@ -814,16 +1648,16 @@ static int max96722_runtime_suspend(struct device *dev) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API static int max96722_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) { - struct max96722 *max96722 = to_max96722(sd); + struct max96722 *max96722 = v4l2_get_subdevdata(sd); struct v4l2_mbus_framefmt *try_fmt = - v4l2_subdev_get_try_format(sd, fh->pad, 0); - const struct max96722_mode *def_mode = &supported_modes[0]; + v4l2_subdev_get_try_format(sd, fh->pad, 0); + const struct max96722_mode *def_mode = &max96722->supported_modes[0]; mutex_lock(&max96722->mutex); /* Initialize try_fmt */ try_fmt->width = def_mode->width; try_fmt->height = def_mode->height; - try_fmt->code = MAX96722_MEDIA_BUS_FMT; + try_fmt->code = def_mode->bus_fmt; try_fmt->field = V4L2_FIELD_NONE; mutex_unlock(&max96722->mutex); @@ -833,38 +1667,60 @@ static int max96722_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) } #endif -static int max96722_enum_frame_interval(struct v4l2_subdev *sd, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_frame_interval_enum *fie) +static int +max96722_enum_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum *fie) { - if (fie->index >= ARRAY_SIZE(supported_modes)) + struct max96722 *max96722 = v4l2_get_subdevdata(sd); + + if (fie->index >= max96722->cfg_modes_num) return -EINVAL; - fie->code = MAX96722_MEDIA_BUS_FMT; - - fie->width = supported_modes[fie->index].width; - fie->height = supported_modes[fie->index].height; - fie->interval = supported_modes[fie->index].max_fps; + fie->code = max96722->supported_modes[fie->index].bus_fmt; + fie->width = max96722->supported_modes[fie->index].width; + fie->height = max96722->supported_modes[fie->index].height; + fie->interval = max96722->supported_modes[fie->index].max_fps; return 0; } static int max96722_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad, - struct v4l2_mbus_config *config) + struct v4l2_mbus_config *config) { + struct max96722 *max96722 = v4l2_get_subdevdata(sd); + u32 val = 0; + u8 data_lanes = max96722->bus_cfg.bus.mipi_csi2.num_data_lanes; + + val |= V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; + val |= (1 << (data_lanes - 1)); + switch (data_lanes) { + case 4: + val |= V4L2_MBUS_CSI2_CHANNEL_3; + fallthrough; + case 3: + val |= V4L2_MBUS_CSI2_CHANNEL_2; + fallthrough; + case 2: + val |= V4L2_MBUS_CSI2_CHANNEL_1; + fallthrough; + case 1: + default: + val |= V4L2_MBUS_CSI2_CHANNEL_0; + break; + } + config->type = V4L2_MBUS_CSI2_DPHY; - config->flags = V4L2_MBUS_CSI2_4_LANE | - V4L2_MBUS_CSI2_CHANNEL_0 | - V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; + config->flags = val; return 0; } static int max96722_get_selection(struct v4l2_subdev *sd, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_selection *sel) + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_selection *sel) { - struct max96722 *max96722 = to_max96722(sd); + struct max96722 *max96722 = v4l2_get_subdevdata(sd); if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) { sel->r.left = 0; @@ -877,10 +1733,8 @@ static int max96722_get_selection(struct v4l2_subdev *sd, return -EINVAL; } -static const struct dev_pm_ops max96722_pm_ops = { - SET_RUNTIME_PM_OPS(max96722_runtime_suspend, - max96722_runtime_resume, NULL) -}; +static const struct dev_pm_ops max96722_pm_ops = { SET_RUNTIME_PM_OPS( + max96722_runtime_suspend, max96722_runtime_resume, NULL) }; #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API static const struct v4l2_subdev_internal_ops max96722_internal_ops = { @@ -912,15 +1766,17 @@ static const struct v4l2_subdev_pad_ops max96722_pad_ops = { }; static const struct v4l2_subdev_ops max96722_subdev_ops = { - .core = &max96722_core_ops, - .video = &max96722_video_ops, - .pad = &max96722_pad_ops, + .core = &max96722_core_ops, + .video = &max96722_video_ops, + .pad = &max96722_pad_ops, }; static int max96722_initialize_controls(struct max96722 *max96722) { const struct max96722_mode *mode; struct v4l2_ctrl_handler *handler; + u64 pixel_rate; + u8 data_lanes; int ret; handler = &max96722->ctrl_handler; @@ -932,21 +1788,25 @@ static int max96722_initialize_controls(struct max96722 *max96722) handler->lock = &max96722->mutex; max96722->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, - V4L2_CID_LINK_FREQ, - 1, 0, link_freq_items); + V4L2_CID_LINK_FREQ, + ARRAY_SIZE(link_freq_items) - 1, 0, + link_freq_items); + __v4l2_ctrl_s_ctrl(max96722->link_freq, mode->link_freq_idx); + dev_info(&max96722->client->dev, "mipi_freq_idx = %d, mipi_link_freq = %lld\n", + mode->link_freq_idx, link_freq_items[mode->link_freq_idx]); - max96722->pixel_rate = v4l2_ctrl_new_std(handler, NULL, - V4L2_CID_PIXEL_RATE, - 0, MAX96722_PIXEL_RATE, - 1, MAX96722_PIXEL_RATE); - - __v4l2_ctrl_s_ctrl(max96722->link_freq, - mode->link_freq_idx); + /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */ + data_lanes = max96722->bus_cfg.bus.mipi_csi2.num_data_lanes; + pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * data_lanes; + max96722->pixel_rate = + v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 0, + pixel_rate, 1, pixel_rate); + dev_info(&max96722->client->dev, "pixel_rate = %lld, bpp = %d\n", + pixel_rate, mode->bpp); if (handler->error) { ret = handler->error; - dev_err(&max96722->client->dev, - "Failed to init controls(%d)\n", ret); + dev_err(&max96722->client->dev, "Failed to init controls(%d)\n", ret); goto err_free_handler; } @@ -960,25 +1820,6 @@ err_free_handler: return ret; } -static int max96722_check_sensor_id(struct max96722 *max96722, - struct i2c_client *client) -{ - struct device *dev = &max96722->client->dev; - u32 id = 0; - int ret; - - ret = max96722_read_reg(client, MAX96722_REG_CHIP_ID, - MAX96722_REG_VALUE_08BIT, &id); - if (id != CHIP_ID) { - dev_err(dev, "Unexpected sensor id(%02x), ret(%d)\n", id, ret); - return -ENODEV; - } - - dev_info(dev, "Detected %02x sensor\n", id); - - return 0; -} - static int max96722_configure_regulators(struct max96722 *max96722) { unsigned int i; @@ -987,44 +1828,116 @@ static int max96722_configure_regulators(struct max96722 *max96722) max96722->supplies[i].supply = max96722_supply_names[i]; return devm_regulator_bulk_get(&max96722->client->dev, - MAX96722_NUM_SUPPLIES, - max96722->supplies); + MAX96722_NUM_SUPPLIES, + max96722->supplies); +} + +static int max96722_parse_dt(struct max96722 *max96722) +{ + struct device *dev = &max96722->client->dev; + struct device_node *node = dev->of_node; + u8 mipi_data_lanes = max96722->bus_cfg.bus.mipi_csi2.num_data_lanes; + int ret = 0; + + /* max96722 link mask: + * bit[3:0] = link enable mask: 0 = disable, 1 = enable: + * bit0 - LinkA, bit1 - LinkB, bit2 - LinkC, bit3 - LinkD + * bit[7:4] = link type, 0 = GMSL1, 1 = GMSL2: + * bit4 - LinkA, bit5 - LinkB, bit6 - LinkC, bit7 = LinkD + */ + ret = of_property_read_u32(node, "link-mask", &max96722->link_mask); + if (ret) { + /* default link mask */ + if (mipi_data_lanes == 4) + max96722->link_mask = 0xFF; /* Link A/B/C/D: GMSL2 and enable */ + else + max96722->link_mask = 0x33; /* Link A/B: GMSL2 and enable */ + } else { + dev_info(dev, "link-mask property: 0x%x\n", max96722->link_mask); + } + dev_info(dev, "serdes link mask: 0x%02x\n", max96722->link_mask); + + /* auto initial deskew mask */ + ret = of_property_read_u32(node, "auto-init-deskew-mask", + &max96722->auto_init_deskew_mask); + if (ret) + max96722->auto_init_deskew_mask = 0x0F; // 0x0F: default enable all + dev_info(dev, "auto init deskew mask: 0x%02x\n", max96722->auto_init_deskew_mask); + + /* FSYNC period config */ + ret = of_property_read_u32(node, "frame-sync-period", + &max96722->frame_sync_period); + if (ret) + max96722->frame_sync_period = 0; // 0: disable (default) + dev_info(dev, "frame sync period: %d\n", max96722->frame_sync_period); + + return 0; } static int max96722_probe(struct i2c_client *client, - const struct i2c_device_id *id) + const struct i2c_device_id *id) { struct device *dev = &client->dev; struct device_node *node = dev->of_node; struct max96722 *max96722; struct v4l2_subdev *sd; + struct device_node *endpoint; char facing[2]; + u8 mipi_data_lanes; int ret; - dev_info(dev, "driver version: %02x.%02x.%02x", - DRIVER_VERSION >> 16, - (DRIVER_VERSION & 0xff00) >> 8, - DRIVER_VERSION & 0x00ff); + dev_info(dev, "driver version: %02x.%02x.%02x", DRIVER_VERSION >> 16, + (DRIVER_VERSION & 0xff00) >> 8, DRIVER_VERSION & 0x00ff); max96722 = devm_kzalloc(dev, sizeof(*max96722), GFP_KERNEL); if (!max96722) return -ENOMEM; ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX, - &max96722->module_index); + &max96722->module_index); ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING, - &max96722->module_facing); + &max96722->module_facing); ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME, - &max96722->module_name); + &max96722->module_name); ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME, - &max96722->len_name); + &max96722->len_name); if (ret) { dev_err(dev, "could not get module information!\n"); return -EINVAL; } + max96722->regmap = devm_regmap_init_i2c(client, &max96722_regmap_config); + if (IS_ERR(max96722->regmap)) { + dev_err(dev, "Failed to regmap initialize I2C\n"); + return PTR_ERR(max96722->regmap); + } + max96722->client = client; - max96722->cur_mode = &supported_modes[0]; + i2c_set_clientdata(client, max96722); + + endpoint = of_graph_get_next_endpoint(dev->of_node, NULL); + if (!endpoint) { + dev_err(dev, "Failed to get endpoint\n"); + return -EINVAL; + } + + ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), + &max96722->bus_cfg); + if (ret) { + dev_err(dev, "Failed to get bus config\n"); + return -EINVAL; + } + mipi_data_lanes = max96722->bus_cfg.bus.mipi_csi2.num_data_lanes; + dev_info(dev, "mipi csi2 phy data lanes %d\n", mipi_data_lanes); + + if (mipi_data_lanes == 4) { + max96722->supported_modes = supported_modes_4lane; + max96722->cfg_modes_num = ARRAY_SIZE(supported_modes_4lane); + } else { + dev_err(dev, "Not support mipi data lane: %d\n", mipi_data_lanes); + return -EINVAL; + } + max96722->cur_mode = &max96722->supported_modes[0]; max96722->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW); if (IS_ERR(max96722->power_gpio)) @@ -1038,6 +1951,14 @@ static int max96722_probe(struct i2c_client *client, if (IS_ERR(max96722->pwdn_gpio)) dev_warn(dev, "Failed to get pwdn-gpios\n"); + max96722->pocen_gpio = devm_gpiod_get(dev, "pocen", GPIOD_OUT_LOW); + if (IS_ERR(max96722->pocen_gpio)) + dev_warn(dev, "Failed to get pocen-gpios\n"); + + max96722->lock_gpio = devm_gpiod_get(dev, "lock", GPIOD_IN); + if (IS_ERR(max96722->lock_gpio)) + dev_warn(dev, "Failed to get lock-gpios\n"); + ret = max96722_configure_regulators(max96722); if (ret) { dev_err(dev, "Failed to get power regulators\n"); @@ -1046,19 +1967,19 @@ static int max96722_probe(struct i2c_client *client, max96722->pinctrl = devm_pinctrl_get(dev); if (!IS_ERR(max96722->pinctrl)) { - max96722->pins_default = - pinctrl_lookup_state(max96722->pinctrl, - OF_CAMERA_PINCTRL_STATE_DEFAULT); + max96722->pins_default = pinctrl_lookup_state( + max96722->pinctrl, OF_CAMERA_PINCTRL_STATE_DEFAULT); if (IS_ERR(max96722->pins_default)) dev_err(dev, "could not get default pinstate\n"); - max96722->pins_sleep = - pinctrl_lookup_state(max96722->pinctrl, - OF_CAMERA_PINCTRL_STATE_SLEEP); + max96722->pins_sleep = pinctrl_lookup_state( + max96722->pinctrl, OF_CAMERA_PINCTRL_STATE_SLEEP); if (IS_ERR(max96722->pins_sleep)) dev_err(dev, "could not get sleep pinstate\n"); } + max96722_parse_dt(max96722); + mutex_init(&max96722->mutex); sd = &max96722->subdev; @@ -1071,16 +1992,7 @@ static int max96722_probe(struct i2c_client *client, if (ret) goto err_free_handler; - ret = max96722_write_reg(max96722->client, - MAX96722_REMOTE_CTRL, - MAX96722_REG_VALUE_08BIT, - MAX96722_REMOTE_DISABLE); - if (ret) { - dev_err(dev, "disable i2c remote control error\n"); - goto err_power_off; - } - - ret = max96722_check_sensor_id(max96722, client); + ret = max96722_check_link_lock_state(max96722); if (ret) goto err_power_off; @@ -1102,15 +2014,38 @@ static int max96722_probe(struct i2c_client *client, else facing[0] = 'f'; + v4l2_set_subdevdata(sd, max96722); + snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s", - max96722->module_index, facing, - MAX96722_NAME, dev_name(sd->dev)); + max96722->module_index, facing, MAX96722_NAME, + dev_name(sd->dev)); ret = v4l2_async_register_subdev_sensor_common(sd); if (ret) { dev_err(dev, "v4l2 async register subdev failed\n"); goto err_clean_entity; } + if (!IS_ERR(max96722->lock_gpio)) { + max96722->hot_plug_irq = gpiod_to_irq(max96722->lock_gpio); + if (max96722->hot_plug_irq < 0) { + dev_err(dev, "failed to get hot plug irq\n"); + } else { + ret = devm_request_threaded_irq(dev, + max96722->hot_plug_irq, + NULL, + max96722_hot_plug_detect_irq_handler, + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | IRQF_ONESHOT, + "max96722_hot_plug", + max96722); + if (ret) { + dev_err(dev, "failed to request hot plug irq (%d)\n", ret); + max96722->hot_plug_irq = -1; + } else { + disable_irq(max96722->hot_plug_irq); + } + } + } + pm_runtime_set_active(dev); pm_runtime_enable(dev); pm_runtime_idle(dev); @@ -1134,7 +2069,7 @@ err_destroy_mutex: static int max96722_remove(struct i2c_client *client) { struct v4l2_subdev *sd = i2c_get_clientdata(client); - struct max96722 *max96722 = to_max96722(sd); + struct max96722 *max96722 = v4l2_get_subdevdata(sd); v4l2_async_unregister_subdev(sd); #if defined(CONFIG_MEDIA_CONTROLLER) @@ -1185,7 +2120,7 @@ static void __exit sensor_mod_exit(void) i2c_del_driver(&max96722_i2c_driver); } -device_initcall_sync(sensor_mod_init); +module_init(sensor_mod_init); module_exit(sensor_mod_exit); MODULE_DESCRIPTION("Maxim max96722 deserializer driver"); From be4fe51d5bf7e69ec6c52af81a503186d7531599 Mon Sep 17 00:00:00 2001 From: Yingsong Ye Date: Fri, 24 Mar 2023 14:57:19 +0800 Subject: [PATCH 21/27] media: i2c: add ar0822 driver Change-Id: I8a860b248528cb6ad1e263ea5e10b89efd503bf9 Signed-off-by: Yingsong Ye --- drivers/media/i2c/Kconfig | 12 + drivers/media/i2c/Makefile | 1 + drivers/media/i2c/ar0822.c | 5484 ++++++++++++++++++++++++++++++++++++ 3 files changed, 5497 insertions(+) create mode 100644 drivers/media/i2c/ar0822.c diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 922de50521cf..77b48f60ce01 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -931,6 +931,18 @@ config VIDEO_AR0230 To compile this driver as a module, choose M here: the module will be called ar0230. +config VIDEO_AR0822 + tristate "Onsemi AR0822 sensor support" + depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API + depends on MEDIA_CAMERA_SUPPORT + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the Onsemi + AR0822 camera. + + To compile this driver as a module, choose M here: the + module will be called ar0822. + config VIDEO_GC02M2 tristate "GalaxyCore GC02M2 sensor support" depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index afef465f8dbb..fa2f8362c6ee 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -180,6 +180,7 @@ obj-$(CONFIG_VIDEO_TECHPOINT) += techpoint/ obj-$(CONFIG_VIDEO_THCV244) += thcv244.o obj-$(CONFIG_VIDEO_RK628) += rk628/ obj-$(CONFIG_VIDEO_AR0230) += ar0230.o +obj-$(CONFIG_VIDEO_AR0822) += ar0822.o obj-$(CONFIG_VIDEO_GC02M2) += gc02m2.o obj-$(CONFIG_VIDEO_GC08A3) += gc08a3.o obj-$(CONFIG_VIDEO_GC1084) += gc1084.o diff --git a/drivers/media/i2c/ar0822.c b/drivers/media/i2c/ar0822.c new file mode 100644 index 000000000000..a883f4ffdf85 --- /dev/null +++ b/drivers/media/i2c/ar0822.c @@ -0,0 +1,5484 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ar0822 driver + * + * Copyright (C) 2023 Rockchip Electronics Co., Ltd. + * + * V0.0X01.0X00 first version. + * V0.0X01.0X01 support conversion gain switch. + * V0.0X01.0X02 add debug interface for conversion gain switch. + * V0.0X01.0X03 support enum sensor fmt + * V0.0X01.0X04 add quick stream on/off + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../platform/rockchip/isp/rkisp_tb_helper.h" + +#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04) +#ifndef V4L2_CID_DIGITAL_GAIN +#define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN +#endif + +#define MIPI_FREQ_492M 492000000//500000000 +#define MIPI_FREQ_657M 657000000 +#define MIPI_FREQ_823M 823000000 +#define MIPI_FREQ_986M 986000000/*657M for 1.314Gbps,986M for 1.972Gbps */ + +#define PIXEL_RATE_MAX (MIPI_FREQ_986M / 12 *2 * 4) + +#define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode" + +#define AR0822_XVCLK_FREQ 27000000 /*MCLK* need to config if XCLK from SOC; open.k*/ + +#define CHIP_ID 0x0F56 +#define AR0822_REG_CHIP_ID 0x3000 + +#define AR0822_REG_CTRL_MODE 0x301A +#define AR0822_MODE_SW_STANDBY 0x0018 +#define AR0822_MODE_STREAMING 0x001C + +#define AR0822_EXPOSURE_MIN 2 /* 最小曝光时间 行 * need to config; open.k*/ +#define AR0822_EXPOSURE_STEP 1 +#define AR0822_VTS_MAX 0xffff /* Frame length line; open.k*/ + +#define AR0822_REG_EXP 0x3012 + +#define AR0822_REG_GAIN 0x5900 +#define AR0822_REG_GAIN2 0x5902 +#define AR0822_REG_GAIN3 0x5904 +#define AR0822_GAIN_MIN 0 +#define AR0822_GAIN_MAX 119 +#define AR0822_GAIN_STEP 1 +#define AR0822_GAIN_DEFAULT 0x20 + +#define AR0822_GROUP_UPDATE_ADDRESS 0x301A +#define AR0822_GROUP_UPDATE_START_DATA 0x801C +#define AR0822_GROUP_UPDATE_END_DATA 0x001C /* make sure exposure and gain take effect from N+2 frame; open.k*/ + +#define AR0822_SOFTWARE_RESET_REG 0x301A + +#define AR0822_REG_VTS 0x300A + +#define REG_NULL 0xFFFF /* Flag address for I2C array write,indicate this is the last row of I2C register table; open.k*/ +#define REG_DELAY 0xFFFE + +#define AR0822_REG_VALUE_08BIT 1 +#define AR0822_REG_VALUE_16BIT 2 +#define AR0822_REG_VALUE_24BIT 3 + +#define AR0822_LANES 4 +#define AR0822_BPP12 12 +#define AR0822_BPP14 14 + +#define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default" +#define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep" + +#define AR0822_NAME "ar0822" + +#define USED_SYS_DEBUG + + +/* sensor power on config, need check power, MCLK, GPIO etc,,, need go to .dts file to change the config; open.k */ +static const char * const ar0822_supply_names[] = { + "avdd", /* Analog power */ + "dovdd", /* Digital I/O power */ + "dvdd", /* Digital core power */ +}; + + +#define AR0822_NUM_SUPPLIES ARRAY_SIZE(ar0822_supply_names) + +#define AR0822_FLIP_REG 0x3040 +#define MIRROR_BIT_MASK BIT(14) +#define FLIP_BIT_MASK BIT(15) + +struct regval { + u16 addr; + u16 val; +}; + +/* Config resolution ,LLPCLK, FLL, exposure time,fps, MIPI channel config, HDR mode , open.k */ +struct ar0822_mode { + u32 bus_fmt; + u32 width; + u32 height; + struct v4l2_fract max_fps; + u32 hts_def; + u32 vts_def; + u32 exp_def; + const struct regval *reg_list; + u32 hdr_mode; + u32 mipi_freq; + u32 mipi_rate; + u32 vc[PAD_MAX]; +}; + +struct ar0822 { + struct i2c_client *client; + struct clk *xvclk; + struct gpio_desc *reset_gpio; + struct gpio_desc *pwdn_gpio; + struct regulator_bulk_data supplies[AR0822_NUM_SUPPLIES]; + + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_sleep; + + struct v4l2_subdev subdev; + struct media_pad pad; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *exposure; + struct v4l2_ctrl *anal_gain; + struct v4l2_ctrl *digi_gain; + struct v4l2_ctrl *hblank; + struct v4l2_ctrl *vblank; + struct v4l2_ctrl *test_pattern; + struct v4l2_ctrl *pixel_rate; + struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *h_flip; + struct v4l2_ctrl *v_flip; + struct mutex mutex; + bool streaming; + bool power_on; + const struct ar0822_mode *cur_mode; + u32 cfg_num; + u32 module_index; + const char *module_facing; + const char *module_name; + const char *len_name; + bool has_init_exp; + struct preisp_hdrae_exp_s init_hdrae_exp; + bool long_hcg; + bool middle_hcg; + bool short_hcg; + bool is_thunderboot; + bool is_thunderboot_ng; + bool is_first_streamoff; + u8 flip; +}; +#define to_ar0822(sd) container_of(sd, struct ar0822, subdev) + +/* + * Xclk 27Mhz + */ +static const struct regval ar0822_linear_global_regs[] = { + {REG_DELAY, 2000}, + {0x3030,0x0092},//PLL_MULTIPLIER + {0x302E,0x0002},//PRE_PLL_CLK_DIV + {0x302C,0x0002},//VT_SYS_CLK_DIV + {0x302A,0x0006},//VT_PIX_CLK_DIV + {0x3038,0x0004},//OP_SYS_CLK_DIV + {0x3036,0x0006},//OP_WORD_CLK_DIV + {0x31B0,0x0071},//FRAME_PREAMBLE + {0x31B2,0x004D},//LINE_PREAMBLE + {0x31B4,0x51C8},//MIPI_TIMING_0 + {0x31B6,0x5288},//MIPI_TIMING_1 + {0x31B8,0x70CA},//MIPI_TIMING_2 + {0x31BA,0x030B},//MIPI_TIMING_3 + {0x31BC,0x0C89},//MIPI_TIMING_4 + {0x3342,0x122C},//MIPI_F1_PDT_EDT + {0x2512,0xA000},//SEQ_CTRL_PORT + {0x2510,0x0720},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0x2122},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0x26FF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x0F8C},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0x8055},//SEQ_DATA_PORT + {0x2510,0xA0E1},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3088},//SEQ_DATA_PORT + {0x2510,0x3282},//SEQ_DATA_PORT + {0x2510,0xA681},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FE},//SEQ_DATA_PORT + {0x2510,0x9070},//SEQ_DATA_PORT + {0x2510,0x891D},//SEQ_DATA_PORT + {0x2510,0x867F},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FC},//SEQ_DATA_PORT + {0x2510,0x893F},//SEQ_DATA_PORT + {0x2510,0x0F92},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0x0F8F},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0x9770},//SEQ_DATA_PORT + {0x2510,0x20FC},//SEQ_DATA_PORT + {0x2510,0x8054},//SEQ_DATA_PORT + {0x2510,0x896C},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x9030},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x8040},//SEQ_DATA_PORT + {0x2510,0x8948},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x1597},//SEQ_DATA_PORT + {0x2510,0x8808},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x1F96},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0xA0C0},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x3044},//SEQ_DATA_PORT + {0x2510,0x3088},//SEQ_DATA_PORT + {0x2510,0x3282},//SEQ_DATA_PORT + {0x2510,0x2004},//SEQ_DATA_PORT + {0x2510,0x1FAA},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x3108},//SEQ_DATA_PORT + {0x2510,0x2400},//SEQ_DATA_PORT + {0x2510,0x3244},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x3108},//SEQ_DATA_PORT + {0x2510,0x2400},//SEQ_DATA_PORT + {0x2510,0x2702},//SEQ_DATA_PORT + {0x2510,0x3242},//SEQ_DATA_PORT + {0x2510,0x3108},//SEQ_DATA_PORT + {0x2510,0x2420},//SEQ_DATA_PORT + {0x2510,0x2703},//SEQ_DATA_PORT + {0x2510,0x3242},//SEQ_DATA_PORT + {0x2510,0x3108},//SEQ_DATA_PORT + {0x2510,0x2420},//SEQ_DATA_PORT + {0x2510,0x2704},//SEQ_DATA_PORT + {0x2510,0x3244},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x8801},//SEQ_DATA_PORT + {0x2510,0x000F},//SEQ_DATA_PORT + {0x2510,0x109C},//SEQ_DATA_PORT + {0x2510,0x8855},//SEQ_DATA_PORT + {0x2510,0x3101},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3102},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3181},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3188},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3282},//SEQ_DATA_PORT + {0x2510,0x3104},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0xB0E4},//SEQ_DATA_PORT + {0x2510,0xAD92},//SEQ_DATA_PORT + {0x2510,0xBC0C},//SEQ_DATA_PORT + {0x2510,0x1028},//SEQ_DATA_PORT + {0x2510,0x0022},//SEQ_DATA_PORT + {0x2510,0xC020},//SEQ_DATA_PORT + {0x2510,0x003E},//SEQ_DATA_PORT + {0x2510,0x0045},//SEQ_DATA_PORT + {0x2510,0x00B0},//SEQ_DATA_PORT + {0x2510,0x0028},//SEQ_DATA_PORT + {0x2510,0x30C1},//SEQ_DATA_PORT + {0x2510,0x8015},//SEQ_DATA_PORT + {0x2510,0xA038},//SEQ_DATA_PORT + {0x2510,0x100F},//SEQ_DATA_PORT + {0x2510,0x0507},//SEQ_DATA_PORT + {0x2510,0xA220},//SEQ_DATA_PORT + {0x2510,0x0010},//SEQ_DATA_PORT + {0x2510,0x10C2},//SEQ_DATA_PORT + {0x2510,0xB760},//SEQ_DATA_PORT + {0x2510,0x0033},//SEQ_DATA_PORT + {0x2510,0x1082},//SEQ_DATA_PORT + {0x2510,0x100B},//SEQ_DATA_PORT + {0x2510,0x1029},//SEQ_DATA_PORT + {0x2510,0xA85A},//SEQ_DATA_PORT + {0x2510,0x998D},//SEQ_DATA_PORT + {0x2510,0xC810},//SEQ_DATA_PORT + {0x2510,0x2004},//SEQ_DATA_PORT + {0x2510,0x0ECE},//SEQ_DATA_PORT + {0x2510,0x123B},//SEQ_DATA_PORT + {0x2510,0xC000},//SEQ_DATA_PORT + {0x2510,0x032F},//SEQ_DATA_PORT + {0x2510,0x11D5},//SEQ_DATA_PORT + {0x2510,0x162F},//SEQ_DATA_PORT + {0x2510,0x9000},//SEQ_DATA_PORT + {0x2510,0x2034},//SEQ_DATA_PORT + {0x2510,0x0015},//SEQ_DATA_PORT + {0x2510,0x04CB},//SEQ_DATA_PORT + {0x2510,0x1022},//SEQ_DATA_PORT + {0x2510,0x1031},//SEQ_DATA_PORT + {0x2510,0x002D},//SEQ_DATA_PORT + {0x2510,0x1015},//SEQ_DATA_PORT + {0x2510,0x80B9},//SEQ_DATA_PORT + {0x2510,0xA101},//SEQ_DATA_PORT + {0x2510,0x001C},//SEQ_DATA_PORT + {0x2510,0x008E},//SEQ_DATA_PORT + {0x2510,0x124B},//SEQ_DATA_PORT + {0x2510,0x01B5},//SEQ_DATA_PORT + {0x2510,0x0B92},//SEQ_DATA_PORT + {0x2510,0xA400},//SEQ_DATA_PORT + {0x2510,0x8091},//SEQ_DATA_PORT + {0x2510,0x0028},//SEQ_DATA_PORT + {0x2510,0x3002},//SEQ_DATA_PORT + {0x2510,0x2004},//SEQ_DATA_PORT + {0x2510,0x1012},//SEQ_DATA_PORT + {0x2510,0x100E},//SEQ_DATA_PORT + {0x2510,0x10A8},//SEQ_DATA_PORT + {0x2510,0x00A1},//SEQ_DATA_PORT + {0x2510,0x132D},//SEQ_DATA_PORT + {0x2510,0x09AF},//SEQ_DATA_PORT + {0x2510,0x0159},//SEQ_DATA_PORT + {0x2510,0x121D},//SEQ_DATA_PORT + {0x2510,0x1259},//SEQ_DATA_PORT + {0x2510,0x11AF},//SEQ_DATA_PORT + {0x2510,0x18B5},//SEQ_DATA_PORT + {0x2510,0x0395},//SEQ_DATA_PORT + {0x2510,0x054B},//SEQ_DATA_PORT + {0x2510,0x1021},//SEQ_DATA_PORT + {0x2510,0x0020},//SEQ_DATA_PORT + {0x2510,0x1015},//SEQ_DATA_PORT + {0x2510,0x1030},//SEQ_DATA_PORT + {0x2510,0x00CF},//SEQ_DATA_PORT + {0x2510,0xB146},//SEQ_DATA_PORT + {0x2510,0xC290},//SEQ_DATA_PORT + {0x2510,0x103C},//SEQ_DATA_PORT + {0x2510,0xA882},//SEQ_DATA_PORT + {0x2510,0x8055},//SEQ_DATA_PORT + {0x2510,0x00A9},//SEQ_DATA_PORT + {0x2510,0x8801},//SEQ_DATA_PORT + {0x2510,0xB700},//SEQ_DATA_PORT + {0x2510,0x0001},//SEQ_DATA_PORT + {0x2510,0x02A2},//SEQ_DATA_PORT + {0x2510,0x000A},//SEQ_DATA_PORT + {0x2510,0x98BB},//SEQ_DATA_PORT + {0x2510,0x203F},//SEQ_DATA_PORT + {0x2510,0x0036},//SEQ_DATA_PORT + {0x2510,0x1001},//SEQ_DATA_PORT + {0x2510,0x99BE},//SEQ_DATA_PORT + {0x2510,0x0139},//SEQ_DATA_PORT + {0x2510,0x100A},//SEQ_DATA_PORT + {0x2510,0x0040},//SEQ_DATA_PORT + {0x2510,0x1022},//SEQ_DATA_PORT + {0x2510,0x124C},//SEQ_DATA_PORT + {0x2510,0x109F},//SEQ_DATA_PORT + {0x2510,0x15A3},//SEQ_DATA_PORT + {0x2510,0x002A},//SEQ_DATA_PORT + {0x2510,0x3081},//SEQ_DATA_PORT + {0x2510,0x2001},//SEQ_DATA_PORT + {0x2510,0x3044},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x112A},//SEQ_DATA_PORT + {0x2510,0x101D},//SEQ_DATA_PORT + {0x2510,0x202B},//SEQ_DATA_PORT + {0x2510,0x02B8},//SEQ_DATA_PORT + {0x2510,0x10B8},//SEQ_DATA_PORT + {0x2510,0x1136},//SEQ_DATA_PORT + {0x2510,0x996B},//SEQ_DATA_PORT + {0x2510,0x004C},//SEQ_DATA_PORT + {0x2510,0x1039},//SEQ_DATA_PORT + {0x2510,0x1040},//SEQ_DATA_PORT + {0x2510,0x00B5},//SEQ_DATA_PORT + {0x2510,0x03C4},//SEQ_DATA_PORT + {0x2510,0x1144},//SEQ_DATA_PORT + {0x2510,0x1245},//SEQ_DATA_PORT + {0x2510,0x9A7B},//SEQ_DATA_PORT + {0x2510,0x002B},//SEQ_DATA_PORT + {0x2510,0x30D0},//SEQ_DATA_PORT + {0x2510,0x3141},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3142},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3110},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3120},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3144},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3148},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3182},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3184},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3190},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x31A0},//SEQ_DATA_PORT + {0x2510,0x3088},//SEQ_DATA_PORT + {0x2510,0x2201},//SEQ_DATA_PORT + {0x2510,0x807D},//SEQ_DATA_PORT + {0x2510,0x2206},//SEQ_DATA_PORT + {0x2510,0x8815},//SEQ_DATA_PORT + {0x2510,0x8877},//SEQ_DATA_PORT + {0x2510,0x0092},//SEQ_DATA_PORT + {0x2510,0x220E},//SEQ_DATA_PORT + {0x2510,0x2211},//SEQ_DATA_PORT + {0x2510,0x8055},//SEQ_DATA_PORT + {0x2510,0x3001},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x8A61},//SEQ_DATA_PORT + {0x2510,0x8801},//SEQ_DATA_PORT + {0x2510,0x1092},//SEQ_DATA_PORT + {0x2510,0x181F},//SEQ_DATA_PORT + {0x2510,0x0B1F},//SEQ_DATA_PORT + {0x2510,0x101F},//SEQ_DATA_PORT + {0x2510,0x00B6},//SEQ_DATA_PORT + {0x2510,0x0023},//SEQ_DATA_PORT + {0x2510,0x00B9},//SEQ_DATA_PORT + {0x2510,0x104C},//SEQ_DATA_PORT + {0x2510,0x996E},//SEQ_DATA_PORT + {0x2510,0x0140},//SEQ_DATA_PORT + {0x2510,0x0257},//SEQ_DATA_PORT + {0x2510,0x1035},//SEQ_DATA_PORT + {0x2510,0x9F26},//SEQ_DATA_PORT + {0x2510,0x1423},//SEQ_DATA_PORT + {0x2510,0x0048},//SEQ_DATA_PORT + {0x2510,0xC878},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x1548},//SEQ_DATA_PORT + {0x2510,0x0C49},//SEQ_DATA_PORT + {0x2510,0x1149},//SEQ_DATA_PORT + {0x2510,0x002A},//SEQ_DATA_PORT + {0x2510,0x1057},//SEQ_DATA_PORT + {0x2510,0x3281},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3044},//SEQ_DATA_PORT + {0x2510,0x2001},//SEQ_DATA_PORT + {0x2510,0xA020},//SEQ_DATA_PORT + {0x2510,0x000C},//SEQ_DATA_PORT + {0x2510,0x9825},//SEQ_DATA_PORT + {0x2510,0x1040},//SEQ_DATA_PORT + {0x2510,0x1054},//SEQ_DATA_PORT + {0x2510,0xB06D},//SEQ_DATA_PORT + {0x2510,0x0035},//SEQ_DATA_PORT + {0x2510,0x004D},//SEQ_DATA_PORT + {0x2510,0x9905},//SEQ_DATA_PORT + {0x2510,0xB064},//SEQ_DATA_PORT + {0x2510,0x99C5},//SEQ_DATA_PORT + {0x2510,0x0047},//SEQ_DATA_PORT + {0x2510,0xB920},//SEQ_DATA_PORT + {0x2510,0x1447},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x31F8,0x0008},//MIPI_CONFIG_2 + {0x3C70,0x6828},//CALIB_ROWS + {0x3092,0x0826},//ROW_NOISE_CONTROL + {0x3428,0x0209},//SEQUENCER_CONTROL + {0x3516,0xFF04},//DAC_LD_22_23 + {0x3526,0x6480},//DAC_LD_38_39 + {0x3504,0x8AAA},//DAC_LD_4_5 + {0x353C,0x220C},//DAC_LD_60_61 + {0x3536,0x4C6E},//DAC_LD_54_55 + {0x3D2A,0x0FFF},//T1_END_DEC_TH + {0x3364,0x00EC},//DCG_TRIM + {0x3512,0x8888},//DAC_LD_18_19 + {0x3514,0x888F},//DAC_LD_20_21 + {0x3520,0xFBF0},//DAC_LD_32_33 + {0x3524,0xB2A1},//DAC_LD_36_37 + {0x3528,0xCC84},//DAC_LD_40_41 + {0x3532,0x4C8E},//DAC_LD_50_51 + {0x3534,0x4E64},//DAC_LD_52_53 + {0x351E,0x5856},//DAC_LD_30_31 + {0x353E,0x98F2},//DAC_LD_62_63 + {0x352E,0x6A8A},//DAC_LD_46_47 + {0x3370,0x0211},//DBLC_CONTROL + {0x3372,0x700F},//DBLC_FS0_CONTROL + {0x3540,0x3597},//DAC_LD_64_65 + {0x58E2,0x0BE3},//COL_COUNT_VALUES1 + {0x58E4,0x18B4},//COL_COUNT_VALUES2 + {0x3522,0x7C97},//DAC_LD_34_35 + {0x30BA,0x0024},//DIGITAL_CTRL + {0x31D4,0x0042},//CLK_MEM_GATING_CTRL + {0x352A,0x6F8F},//DAC_LD_42_43 + {0x3530,0x4A08},//DAC_LD_48_49 + {0x351A,0x5FFF},//DAC_LD_26_27 + {0x350E,0x39D9},//DAC_LD_14_15 + {0x3510,0x9988},//DAC_LD_16_17 + {0x3380,0x1FFF},//DBLC_OFFSET1 + {0x337A,0x1000},//DBLC_SCALE1 + {0x3092,0x0800},//ROW_NOISE_CONTROL + {0x350A,0x0654},//DAC_LD_10_11 + {0x3364,0x00E0},//DCG_TRIM + {0x591E,0x61AE},//ANALOG_GAIN_WR_DATA + {0x591E,0x722C},//ANALOG_GAIN_WR_DATA + {0x591E,0x82B8},//ANALOG_GAIN_WR_DATA + {0x591E,0x92F6},//ANALOG_GAIN_WR_DATA + {0x591E,0xA447},//ANALOG_GAIN_WR_DATA + {0x591E,0xB66D},//ANALOG_GAIN_WR_DATA + {0x591E,0xC6EA},//ANALOG_GAIN_WR_DATA + {0x591E,0xDECD},//ANALOG_GAIN_WR_DATA + {0x3532,0x4C8A},//DAC_LD_50_51 + {0x3534,0x4E60},//DAC_LD_52_53 + {0x353E,0x90F2},//DAC_LD_62_63 + {0x351A,0x4FFF},//DAC_LD_26_27 + {0x591C,0x00D7},//DGR_AMP_GAIN + {0x3522,0x6097},//DAC_LD_34_35 + {0x5002,0x37C3},//T1_PIX_DEF_ID2 + {0x51CC,0x0149},//T1_NOISE_GAIN_THRESHOLD0 + {0x51D8,0x044D},//T1_NOISE_GAIN_THRESHOLD1 + {0x51CE,0x0700},//T1_NOISE_GAIN_THRESHOLD2 + {0x51D0,0x0001},//T1_NOISE_FLOOR0 + {0x51D2,0x0002},//T1_NOISE_FLOOR1 + {0x51D4,0x0003},//T1_NOISE_FLOOR2 + {0x51D6,0x0004},//T1_NOISE_FLOOR3 + {0x5202,0x37C3},//T2_PIX_DEF_ID2 + {0x51EA,0x0149},//T2_NOISE_GAIN_THRESHOLD0 + {0x51FC,0x044D},//T2_NOISE_GAIN_THRESHOLD1 + {0x51EC,0x0700},//T2_NOISE_GAIN_THRESHOLD2 + {0x51EE,0x0001},//T2_NOISE_FLOOR0 + {0x51F0,0x0002},//T2_NOISE_FLOOR1 + {0x51F2,0x0003},//T2_NOISE_FLOOR2 + {0x51F4,0x0004},//T2_NOISE_FLOOR3 + {0x5402,0x37C3},//T4_PIX_DEF_ID2 + {0x5560,0x0149},//T4_NOISE_GAIN_THRESHOLD0 + {0x556C,0x044D},//T4_NOISE_GAIN_THRESHOLD1 + {0x5562,0x0700},//T4_NOISE_GAIN_THRESHOLD2 + {0x5564,0x0001},//T4_NOISE_FLOOR0 + {0x5566,0x0002},//T4_NOISE_FLOOR1 + {0x5568,0x0003},//T4_NOISE_FLOOR2 + {0x556A,0x0004},//T4_NOISE_FLOOR3 + {0x31E0,0x0001},//PIX_DEF_ID + {0x5000,0x0080},//T1_PIX_DEF_ID + {0x5000,0x0180},//T1_PIX_DEF_ID + {0x5000,0x0180},//T1_PIX_DEF_ID + {0x5200,0x0080},//T2_PIX_DEF_ID + {0x5200,0x0180},//T2_PIX_DEF_ID + {0x5200,0x0180},//T2_PIX_DEF_ID + {0x5400,0x0080},//T4_PIX_DEF_ID + {0x5400,0x0180},//T4_PIX_DEF_ID + {0x5400,0x0180},//T4_PIX_DEF_ID + {0x5000,0x1180},//T1_PIX_DEF_ID + {0x50A2,0x2553},//BMT0 + {0x50A4,0xDFD4},//BMT1 + {0x50A6,0x030F},//SINGLEK_FACTOR0 + {0x50A6,0x0F0F},//SINGLEK_FACTOR0 + {0x50A8,0x030F},//SINGLEK_FACTOR1 + {0x50A8,0x0F0F},//SINGLEK_FACTOR1 + {0x50AA,0x030F},//SINGLEK_FACTOR2 + {0x50AA,0x050F},//SINGLEK_FACTOR2 + {0x50AC,0x0301},//CROSS_FACTOR0 + {0x50AC,0x0101},//CROSS_FACTOR0 + {0x50AE,0x0301},//CROSS_FACTOR1 + {0x50AE,0x0101},//CROSS_FACTOR1 + {0x50B0,0x0301},//CROSS_FACTOR2 + {0x50B0,0x0101},//CROSS_FACTOR2 + {0x50B2,0x03FF},//SINGLE_MAX_FACTOR + {0x50B4,0x030F},//COUPLE_FACTOR0 + {0x50B4,0x0F0F},//COUPLE_FACTOR0 + {0x50B6,0x030F},//COUPLE_FACTOR1 + {0x50B6,0x0F0F},//COUPLE_FACTOR1 + {0x50B8,0x030F},//COUPLE_FACTOR2 + {0x50B8,0x050F},//COUPLE_FACTOR2 + {0x31AE,0x0204},//SERIAL_FORMAT + {0x31AC,0x0C0C},//DATA_FORMAT_BITS + {0x3082,0x0001},//OPERATION_MODE_CTRL + {0x30BA,0x0024},//DIGITAL_CTRL + {0x31AE,0x0204},//SERIAL_FORMAT + {0x31AC,0x0C0C},//DATA_FORMAT_BITS + {0x300C,0x0866},//LINE_LENGTH_PCK_ + {0x300A,0x09F3},//FRAME_LENGTH_LINES_ + {0x3012,0x08F4},//COARSE_INTEGRATION_TIME_ + {0x5914,0x4012},//SENSOR_GAIN_TABLE_SEL + {REG_DELAY,100}, + {0x5914,0x4002},//SENSOR_GAIN_TABLE_SEL + {0x5910,0x608A},//SENSOR_GAIN_REG1 + {0x5910,0x7091},//SENSOR_GAIN_REG1 + {0x5910,0x689C},//SENSOR_GAIN_REG1 + {0x5910,0x8885},//SENSOR_GAIN_REG1 + {0x5910,0x98AD},//SENSOR_GAIN_REG1 + {0x5910,0xA8A9},//SENSOR_GAIN_REG1 + {0x5910,0xC894},//SENSOR_GAIN_REG1 + {0x5910,0xC8D1},//SENSOR_GAIN_REG1 + {0x5910,0xD88A},//SENSOR_GAIN_REG1 + {0x5910,0xD8C3},//SENSOR_GAIN_REG1 + {0x5910,0xD915},//SENSOR_GAIN_REG1 + {0x5910,0xD988},//SENSOR_GAIN_REG1 + {0x5910,0xDA2A},//SENSOR_GAIN_REG1 + {0x5910,0xDB0E},//SENSOR_GAIN_REG1 + {0x5910,0xDC53},//SENSOR_GAIN_REG1 + {0x5910,0x608A},//SENSOR_GAIN_REG1 + {0x5910,0xC919},//SENSOR_GAIN_REG1 + {0x5910,0xCA00},//SENSOR_GAIN_REG1 + {0x5910,0x0000},//SENSOR_GAIN_REG1 + {0x5910,0x0000},//SENSOR_GAIN_REG1 + {0x5910,0x0000},//SENSOR_GAIN_REG1 + {0x5910,0x0001},//SENSOR_GAIN_REG1 + {0x5910,0x0001},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0002},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x5A8B},//SENSOR_GAIN_REG1 + {0x5910,0xFF04},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xFF04},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0x0005},//SENSOR_GAIN_REG1 + {0x5910,0x0006},//SENSOR_GAIN_REG1 + {0x5910,0x0007},//SENSOR_GAIN_REG1 + {0x5910,0x9A8B},//SENSOR_GAIN_REG1 + {0x5910,0xFF04},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0x0015},//SENSOR_GAIN_REG1 + {0x5910,0x0016},//SENSOR_GAIN_REG1 + {0x5910,0x0017},//SENSOR_GAIN_REG1 + {0x5910,0xDA8B},//SENSOR_GAIN_REG1 + {0x5910,0xFF04},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0x0025},//SENSOR_GAIN_REG1 + {0x5910,0x0026},//SENSOR_GAIN_REG1 + {0x5910,0x0027},//SENSOR_GAIN_REG1 + {0x5910,0x59B9},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x0035},//SENSOR_GAIN_REG1 + {0x5910,0x0036},//SENSOR_GAIN_REG1 + {0x5910,0x0037},//SENSOR_GAIN_REG1 + {0x5910,0x99B9},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x0045},//SENSOR_GAIN_REG1 + {0x5910,0x0046},//SENSOR_GAIN_REG1 + {0x5910,0x0047},//SENSOR_GAIN_REG1 + {0x5910,0xD9B9},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x0055},//SENSOR_GAIN_REG1 + {0x5910,0x0056},//SENSOR_GAIN_REG1 + {0x5910,0x0057},//SENSOR_GAIN_REG1 + {0x5910,0x9A85},//SENSOR_GAIN_REG1 + {0x5910,0x0654},//SENSOR_GAIN_REG1 + {0x5910,0x0654},//SENSOR_GAIN_REG1 + {0x5910,0x0684},//SENSOR_GAIN_REG1 + {0x5910,0x0654},//SENSOR_GAIN_REG1 + {0x5910,0x0654},//SENSOR_GAIN_REG1 + {0x5910,0x0065},//SENSOR_GAIN_REG1 + {0x5910,0x0066},//SENSOR_GAIN_REG1 + {0x5910,0x0067},//SENSOR_GAIN_REG1 + {0x5910,0x59BD},//SENSOR_GAIN_REG1 + {0x5910,0x1000},//SENSOR_GAIN_REG1 + {0x5910,0x0C00},//SENSOR_GAIN_REG1 + {0x5910,0x0F00},//SENSOR_GAIN_REG1 + {0x5910,0x1000},//SENSOR_GAIN_REG1 + {0x5910,0x10F0},//SENSOR_GAIN_REG1 + {0x5910,0x0075},//SENSOR_GAIN_REG1 + {0x5910,0x0076},//SENSOR_GAIN_REG1 + {0x5910,0x0077},//SENSOR_GAIN_REG1 + {0x5912,0x608A},//SENSOR_GAIN_REG2 + {0x5912,0x7091},//SENSOR_GAIN_REG2 + {0x5912,0x689C},//SENSOR_GAIN_REG2 + {0x5912,0x8885},//SENSOR_GAIN_REG2 + {0x5912,0x98AD},//SENSOR_GAIN_REG2 + {0x5912,0xA8A9},//SENSOR_GAIN_REG2 + {0x5912,0xC894},//SENSOR_GAIN_REG2 + {0x5912,0xC8D1},//SENSOR_GAIN_REG2 + {0x5912,0xC927},//SENSOR_GAIN_REG2 + {0x5912,0xC9A0},//SENSOR_GAIN_REG2 + {0x5912,0xCA4C},//SENSOR_GAIN_REG2 + {0x5912,0xCB3F},//SENSOR_GAIN_REG2 + {0x5912,0xCC97},//SENSOR_GAIN_REG2 + {0x5912,0xCE7C},//SENSOR_GAIN_REG2 + {0x5912,0xCFFF},//SENSOR_GAIN_REG2 + {0x5912,0x608A},//SENSOR_GAIN_REG2 + {0x5912,0xC8F0},//SENSOR_GAIN_REG2 + {0x5912,0xCA00},//SENSOR_GAIN_REG2 + {0x5912,0x0000},//SENSOR_GAIN_REG2 + {0x5912,0x0000},//SENSOR_GAIN_REG2 + {0x5912,0x0000},//SENSOR_GAIN_REG2 + {0x5912,0x0001},//SENSOR_GAIN_REG2 + {0x5912,0x0001},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0002},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x5A8B},//SENSOR_GAIN_REG2 + {0x5912,0xFF04},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xFF04},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0x0005},//SENSOR_GAIN_REG2 + {0x5912,0x0006},//SENSOR_GAIN_REG2 + {0x5912,0x0007},//SENSOR_GAIN_REG2 + {0x5912,0x9A8B},//SENSOR_GAIN_REG2 + {0x5912,0xFF04},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0x0015},//SENSOR_GAIN_REG2 + {0x5912,0x0016},//SENSOR_GAIN_REG2 + {0x5912,0x0017},//SENSOR_GAIN_REG2 + {0x5912,0xDA8B},//SENSOR_GAIN_REG2 + {0x5912,0xFF04},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0x0025},//SENSOR_GAIN_REG2 + {0x5912,0x0026},//SENSOR_GAIN_REG2 + {0x5912,0x0027},//SENSOR_GAIN_REG2 + {0x5912,0x59B9},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x0035},//SENSOR_GAIN_REG2 + {0x5912,0x0036},//SENSOR_GAIN_REG2 + {0x5912,0x0037},//SENSOR_GAIN_REG2 + {0x5912,0x99B9},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x0045},//SENSOR_GAIN_REG2 + {0x5912,0x0046},//SENSOR_GAIN_REG2 + {0x5912,0x0047},//SENSOR_GAIN_REG2 + {0x5912,0xD9B9},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x0055},//SENSOR_GAIN_REG2 + {0x5912,0x0056},//SENSOR_GAIN_REG2 + {0x5912,0x0057},//SENSOR_GAIN_REG2 + {0x5912,0x9A85},//SENSOR_GAIN_REG2 + {0x5912,0x0654},//SENSOR_GAIN_REG2 + {0x5912,0x0654},//SENSOR_GAIN_REG2 + {0x5912,0x0684},//SENSOR_GAIN_REG2 + {0x5912,0x0654},//SENSOR_GAIN_REG2 + {0x5912,0x0654},//SENSOR_GAIN_REG2 + {0x5912,0x0065},//SENSOR_GAIN_REG2 + {0x5912,0x0066},//SENSOR_GAIN_REG2 + {0x5912,0x0067},//SENSOR_GAIN_REG2 + {0x5912,0x59BD},//SENSOR_GAIN_REG2 + {0x5912,0x1000},//SENSOR_GAIN_REG2 + {0x5912,0x0C00},//SENSOR_GAIN_REG2 + {0x5912,0x0F00},//SENSOR_GAIN_REG2 + {0x5912,0x1000},//SENSOR_GAIN_REG2 + {0x5912,0x10F0},//SENSOR_GAIN_REG2 + {0x5912,0x0075},//SENSOR_GAIN_REG2 + {0x5912,0x0076},//SENSOR_GAIN_REG2 + {0x5912,0x0077},//SENSOR_GAIN_REG2 + {0x5914,0x4002},//SENSOR_GAIN_TABLE_SEL + {0x5900,0x0000},//SENSOR_GAIN + {REG_NULL, 0x00}, +}; + +static const struct regval ar0822_hdr12bit_3840x2160_25fps_regs[] = { + {REG_DELAY, 2000}, + {0x3030,0x007A},//PLL_MULTIPLIER + {0x302E,0x0002},//PRE_PLL_CLK_DIV + {0x302C,0x0002},//VT_SYS_CLK_DIV + {0x302A,0x0005},//VT_PIX_CLK_DIV + {0x3038,0x0002},//OP_SYS_CLK_DIV + {0x3036,0x0006},//OP_WORD_CLK_DIV + {0x31B0,0x00A3},//FRAME_PREAMBLE + {0x31B2,0x006C},//LINE_PREAMBLE + {0x31B4,0x72CC},//MIPI_TIMING_0 + {0x31B6,0x73CE},//MIPI_TIMING_1 + {0x31B8,0xB0CD},//MIPI_TIMING_2 + {0x31BA,0x0411},//MIPI_TIMING_3 + {0x31BC,0x550E},//MIPI_TIMING_4 + {0x3342,0x122C},//MIPI_F1_PDT_EDT + {0x31BC,0x550E},//MIPI_TIMING_4 + {0x31DE,0x0004},//MIPI_HISPI_TRIM + {0x31C6,0xC000},//HISPI_CONTROL + {0x31C8,0x0B28},//MIPI_DESKEW_PAT_WIDTH + {0x2512,0xA000},//SEQ_CTRL_PORT + {0x2510,0x0720},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0x2122},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0x26FF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x0F8C},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0x8055},//SEQ_DATA_PORT + {0x2510,0xA0E1},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3088},//SEQ_DATA_PORT + {0x2510,0x3282},//SEQ_DATA_PORT + {0x2510,0xA681},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FE},//SEQ_DATA_PORT + {0x2510,0x9070},//SEQ_DATA_PORT + {0x2510,0x891D},//SEQ_DATA_PORT + {0x2510,0x867F},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FC},//SEQ_DATA_PORT + {0x2510,0x893F},//SEQ_DATA_PORT + {0x2510,0x0F92},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0x0F8F},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0x9770},//SEQ_DATA_PORT + {0x2510,0x20FC},//SEQ_DATA_PORT + {0x2510,0x8054},//SEQ_DATA_PORT + {0x2510,0x896C},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x9030},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x8040},//SEQ_DATA_PORT + {0x2510,0x8948},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x1597},//SEQ_DATA_PORT + {0x2510,0x8808},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x1F96},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0xA0C0},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x3044},//SEQ_DATA_PORT + {0x2510,0x3088},//SEQ_DATA_PORT + {0x2510,0x3282},//SEQ_DATA_PORT + {0x2510,0x2004},//SEQ_DATA_PORT + {0x2510,0x1FAA},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x3108},//SEQ_DATA_PORT + {0x2510,0x2400},//SEQ_DATA_PORT + {0x2510,0x3244},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x3108},//SEQ_DATA_PORT + {0x2510,0x2400},//SEQ_DATA_PORT + {0x2510,0x2702},//SEQ_DATA_PORT + {0x2510,0x3242},//SEQ_DATA_PORT + {0x2510,0x3108},//SEQ_DATA_PORT + {0x2510,0x2420},//SEQ_DATA_PORT + {0x2510,0x2703},//SEQ_DATA_PORT + {0x2510,0x3242},//SEQ_DATA_PORT + {0x2510,0x3108},//SEQ_DATA_PORT + {0x2510,0x2420},//SEQ_DATA_PORT + {0x2510,0x2704},//SEQ_DATA_PORT + {0x2510,0x3244},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x8801},//SEQ_DATA_PORT + {0x2510,0x000F},//SEQ_DATA_PORT + {0x2510,0x109C},//SEQ_DATA_PORT + {0x2510,0x8855},//SEQ_DATA_PORT + {0x2510,0x3101},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3102},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3181},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3188},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3282},//SEQ_DATA_PORT + {0x2510,0x3104},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0xB0E4},//SEQ_DATA_PORT + {0x2510,0xAD92},//SEQ_DATA_PORT + {0x2510,0xBC0C},//SEQ_DATA_PORT + {0x2510,0x1028},//SEQ_DATA_PORT + {0x2510,0x0022},//SEQ_DATA_PORT + {0x2510,0xC020},//SEQ_DATA_PORT + {0x2510,0x003E},//SEQ_DATA_PORT + {0x2510,0x0045},//SEQ_DATA_PORT + {0x2510,0x00B0},//SEQ_DATA_PORT + {0x2510,0x0028},//SEQ_DATA_PORT + {0x2510,0x30C1},//SEQ_DATA_PORT + {0x2510,0x8015},//SEQ_DATA_PORT + {0x2510,0xA038},//SEQ_DATA_PORT + {0x2510,0x100F},//SEQ_DATA_PORT + {0x2510,0x0507},//SEQ_DATA_PORT + {0x2510,0xA220},//SEQ_DATA_PORT + {0x2510,0x0010},//SEQ_DATA_PORT + {0x2510,0x10C2},//SEQ_DATA_PORT + {0x2510,0xB760},//SEQ_DATA_PORT + {0x2510,0x0033},//SEQ_DATA_PORT + {0x2510,0x1082},//SEQ_DATA_PORT + {0x2510,0x100B},//SEQ_DATA_PORT + {0x2510,0x1029},//SEQ_DATA_PORT + {0x2510,0xA85A},//SEQ_DATA_PORT + {0x2510,0x998D},//SEQ_DATA_PORT + {0x2510,0xC810},//SEQ_DATA_PORT + {0x2510,0x2004},//SEQ_DATA_PORT + {0x2510,0x0ECE},//SEQ_DATA_PORT + {0x2510,0x123B},//SEQ_DATA_PORT + {0x2510,0xC000},//SEQ_DATA_PORT + {0x2510,0x032F},//SEQ_DATA_PORT + {0x2510,0x11D5},//SEQ_DATA_PORT + {0x2510,0x162F},//SEQ_DATA_PORT + {0x2510,0x9000},//SEQ_DATA_PORT + {0x2510,0x2034},//SEQ_DATA_PORT + {0x2510,0x0015},//SEQ_DATA_PORT + {0x2510,0x04CB},//SEQ_DATA_PORT + {0x2510,0x1022},//SEQ_DATA_PORT + {0x2510,0x1031},//SEQ_DATA_PORT + {0x2510,0x002D},//SEQ_DATA_PORT + {0x2510,0x1015},//SEQ_DATA_PORT + {0x2510,0x80B9},//SEQ_DATA_PORT + {0x2510,0xA101},//SEQ_DATA_PORT + {0x2510,0x001C},//SEQ_DATA_PORT + {0x2510,0x008E},//SEQ_DATA_PORT + {0x2510,0x124B},//SEQ_DATA_PORT + {0x2510,0x01B5},//SEQ_DATA_PORT + {0x2510,0x0B92},//SEQ_DATA_PORT + {0x2510,0xA400},//SEQ_DATA_PORT + {0x2510,0x8091},//SEQ_DATA_PORT + {0x2510,0x0028},//SEQ_DATA_PORT + {0x2510,0x3002},//SEQ_DATA_PORT + {0x2510,0x2004},//SEQ_DATA_PORT + {0x2510,0x1012},//SEQ_DATA_PORT + {0x2510,0x100E},//SEQ_DATA_PORT + {0x2510,0x10A8},//SEQ_DATA_PORT + {0x2510,0x00A1},//SEQ_DATA_PORT + {0x2510,0x132D},//SEQ_DATA_PORT + {0x2510,0x09AF},//SEQ_DATA_PORT + {0x2510,0x0159},//SEQ_DATA_PORT + {0x2510,0x121D},//SEQ_DATA_PORT + {0x2510,0x1259},//SEQ_DATA_PORT + {0x2510,0x11AF},//SEQ_DATA_PORT + {0x2510,0x18B5},//SEQ_DATA_PORT + {0x2510,0x0395},//SEQ_DATA_PORT + {0x2510,0x054B},//SEQ_DATA_PORT + {0x2510,0x1021},//SEQ_DATA_PORT + {0x2510,0x0020},//SEQ_DATA_PORT + {0x2510,0x1015},//SEQ_DATA_PORT + {0x2510,0x1030},//SEQ_DATA_PORT + {0x2510,0x00CF},//SEQ_DATA_PORT + {0x2510,0xB146},//SEQ_DATA_PORT + {0x2510,0xC290},//SEQ_DATA_PORT + {0x2510,0x103C},//SEQ_DATA_PORT + {0x2510,0xA882},//SEQ_DATA_PORT + {0x2510,0x8055},//SEQ_DATA_PORT + {0x2510,0x00A9},//SEQ_DATA_PORT + {0x2510,0x8801},//SEQ_DATA_PORT + {0x2510,0xB700},//SEQ_DATA_PORT + {0x2510,0x0001},//SEQ_DATA_PORT + {0x2510,0x02A2},//SEQ_DATA_PORT + {0x2510,0x000A},//SEQ_DATA_PORT + {0x2510,0x98BB},//SEQ_DATA_PORT + {0x2510,0x203F},//SEQ_DATA_PORT + {0x2510,0x0036},//SEQ_DATA_PORT + {0x2510,0x1001},//SEQ_DATA_PORT + {0x2510,0x99BE},//SEQ_DATA_PORT + {0x2510,0x0139},//SEQ_DATA_PORT + {0x2510,0x100A},//SEQ_DATA_PORT + {0x2510,0x0040},//SEQ_DATA_PORT + {0x2510,0x1022},//SEQ_DATA_PORT + {0x2510,0x124C},//SEQ_DATA_PORT + {0x2510,0x109F},//SEQ_DATA_PORT + {0x2510,0x15A3},//SEQ_DATA_PORT + {0x2510,0x002A},//SEQ_DATA_PORT + {0x2510,0x3081},//SEQ_DATA_PORT + {0x2510,0x2001},//SEQ_DATA_PORT + {0x2510,0x3044},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x112A},//SEQ_DATA_PORT + {0x2510,0x101D},//SEQ_DATA_PORT + {0x2510,0x202B},//SEQ_DATA_PORT + {0x2510,0x02B8},//SEQ_DATA_PORT + {0x2510,0x10B8},//SEQ_DATA_PORT + {0x2510,0x1136},//SEQ_DATA_PORT + {0x2510,0x996B},//SEQ_DATA_PORT + {0x2510,0x004C},//SEQ_DATA_PORT + {0x2510,0x1039},//SEQ_DATA_PORT + {0x2510,0x1040},//SEQ_DATA_PORT + {0x2510,0x00B5},//SEQ_DATA_PORT + {0x2510,0x03C4},//SEQ_DATA_PORT + {0x2510,0x1144},//SEQ_DATA_PORT + {0x2510,0x1245},//SEQ_DATA_PORT + {0x2510,0x9A7B},//SEQ_DATA_PORT + {0x2510,0x002B},//SEQ_DATA_PORT + {0x2510,0x30D0},//SEQ_DATA_PORT + {0x2510,0x3141},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3142},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3110},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3120},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3144},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3148},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3182},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3184},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3190},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x31A0},//SEQ_DATA_PORT + {0x2510,0x3088},//SEQ_DATA_PORT + {0x2510,0x2201},//SEQ_DATA_PORT + {0x2510,0x807D},//SEQ_DATA_PORT + {0x2510,0x2206},//SEQ_DATA_PORT + {0x2510,0x8815},//SEQ_DATA_PORT + {0x2510,0x8877},//SEQ_DATA_PORT + {0x2510,0x0092},//SEQ_DATA_PORT + {0x2510,0x220E},//SEQ_DATA_PORT + {0x2510,0x2211},//SEQ_DATA_PORT + {0x2510,0x8055},//SEQ_DATA_PORT + {0x2510,0x3001},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x8A61},//SEQ_DATA_PORT + {0x2510,0x8801},//SEQ_DATA_PORT + {0x2510,0x1092},//SEQ_DATA_PORT + {0x2510,0x181F},//SEQ_DATA_PORT + {0x2510,0x0B1F},//SEQ_DATA_PORT + {0x2510,0x101F},//SEQ_DATA_PORT + {0x2510,0x00B6},//SEQ_DATA_PORT + {0x2510,0x0023},//SEQ_DATA_PORT + {0x2510,0x00B9},//SEQ_DATA_PORT + {0x2510,0x104C},//SEQ_DATA_PORT + {0x2510,0x996E},//SEQ_DATA_PORT + {0x2510,0x0140},//SEQ_DATA_PORT + {0x2510,0x0257},//SEQ_DATA_PORT + {0x2510,0x1035},//SEQ_DATA_PORT + {0x2510,0x9F26},//SEQ_DATA_PORT + {0x2510,0x1423},//SEQ_DATA_PORT + {0x2510,0x0048},//SEQ_DATA_PORT + {0x2510,0xC878},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x1548},//SEQ_DATA_PORT + {0x2510,0x0C49},//SEQ_DATA_PORT + {0x2510,0x1149},//SEQ_DATA_PORT + {0x2510,0x002A},//SEQ_DATA_PORT + {0x2510,0x1057},//SEQ_DATA_PORT + {0x2510,0x3281},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3044},//SEQ_DATA_PORT + {0x2510,0x2001},//SEQ_DATA_PORT + {0x2510,0xA020},//SEQ_DATA_PORT + {0x2510,0x000C},//SEQ_DATA_PORT + {0x2510,0x9825},//SEQ_DATA_PORT + {0x2510,0x1040},//SEQ_DATA_PORT + {0x2510,0x1054},//SEQ_DATA_PORT + {0x2510,0xB06D},//SEQ_DATA_PORT + {0x2510,0x0035},//SEQ_DATA_PORT + {0x2510,0x004D},//SEQ_DATA_PORT + {0x2510,0x9905},//SEQ_DATA_PORT + {0x2510,0xB064},//SEQ_DATA_PORT + {0x2510,0x99C5},//SEQ_DATA_PORT + {0x2510,0x0047},//SEQ_DATA_PORT + {0x2510,0xB920},//SEQ_DATA_PORT + {0x2510,0x1447},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x31F8,0x0008},//MIPI_CONFIG_2 + {0x3C70,0x6828},//CALIB_ROWS + {0x3092,0x0826},//ROW_NOISE_CONTROL + {0x3428,0x0209},//SEQUENCER_CONTROL + {0x3516,0xFF04},//DAC_LD_22_23 + {0x3526,0x6480},//DAC_LD_38_39 + {0x3504,0x8AAA},//DAC_LD_4_5 + {0x353C,0x220C},//DAC_LD_60_61 + {0x3536,0x4C6E},//DAC_LD_54_55 + {0x3D2A,0x0FFF},//T1_END_DEC_TH + {0x3364,0x00EC},//DCG_TRIM + {0x3512,0x8888},//DAC_LD_18_19 + {0x3514,0x888F},//DAC_LD_20_21 + {0x3520,0xFBF0},//DAC_LD_32_33 + {0x3524,0xB2A1},//DAC_LD_36_37 + {0x3528,0xCC84},//DAC_LD_40_41 + {0x3532,0x4C8E},//DAC_LD_50_51 + {0x3534,0x4E64},//DAC_LD_52_53 + {0x351E,0x5856},//DAC_LD_30_31 + {0x353E,0x98F2},//DAC_LD_62_63 + {0x352E,0x6A8A},//DAC_LD_46_47 + {0x3370,0x0211},//DBLC_CONTROL + {0x3372,0x700F},//DBLC_FS0_CONTROL + {0x3540,0x3597},//DAC_LD_64_65 + {0x58E2,0x0BE3},//COL_COUNT_VALUES1 + {0x58E4,0x18B4},//COL_COUNT_VALUES2 + {0x3522,0x7C97},//DAC_LD_34_35 + {0x30BA,0x0024},//DIGITAL_CTRL + {0x31D4,0x0042},//CLK_MEM_GATING_CTRL + {0x352A,0x6F8F},//DAC_LD_42_43 + {0x3530,0x4A08},//DAC_LD_48_49 + {0x351A,0x5FFF},//DAC_LD_26_27 + {0x350E,0x39D9},//DAC_LD_14_15 + {0x3510,0x9988},//DAC_LD_16_17 + {0x3380,0x1FFF},//DBLC_OFFSET1 + {0x337A,0x1000},//DBLC_SCALE1 + {0x3092,0x0800},//ROW_NOISE_CONTROL + {0x350A,0x0654},//DAC_LD_10_11 + {0x3364,0x00E0},//DCG_TRIM + {0x591E,0x61AE},//ANALOG_GAIN_WR_DATA + {0x591E,0x722C},//ANALOG_GAIN_WR_DATA + {0x591E,0x82B8},//ANALOG_GAIN_WR_DATA + {0x591E,0x92F6},//ANALOG_GAIN_WR_DATA + {0x591E,0xA447},//ANALOG_GAIN_WR_DATA + {0x591E,0xB66D},//ANALOG_GAIN_WR_DATA + {0x591E,0xC6EA},//ANALOG_GAIN_WR_DATA + {0x591E,0xDECD},//ANALOG_GAIN_WR_DATA + {0x3532,0x4C8A},//DAC_LD_50_51 + {0x3534,0x4E60},//DAC_LD_52_53 + {0x353E,0x90F2},//DAC_LD_62_63 + {0x351A,0x4FFF},//DAC_LD_26_27 + {0x591C,0x00D7},//DGR_AMP_GAIN + {0x3522,0x6097},//DAC_LD_34_35 + {0x5002,0x37C3},//T1_PIX_DEF_ID2 + {0x51CC,0x0149},//T1_NOISE_GAIN_THRESHOLD0 + {0x51D8,0x044D},//T1_NOISE_GAIN_THRESHOLD1 + {0x51CE,0x0700},//T1_NOISE_GAIN_THRESHOLD2 + {0x51D0,0x0001},//T1_NOISE_FLOOR0 + {0x51D2,0x0002},//T1_NOISE_FLOOR1 + {0x51D4,0x0003},//T1_NOISE_FLOOR2 + {0x51D6,0x0004},//T1_NOISE_FLOOR3 + {0x5202,0x37C3},//T2_PIX_DEF_ID2 + {0x51EA,0x0149},//T2_NOISE_GAIN_THRESHOLD0 + {0x51FC,0x044D},//T2_NOISE_GAIN_THRESHOLD1 + {0x51EC,0x0700},//T2_NOISE_GAIN_THRESHOLD2 + {0x51EE,0x0001},//T2_NOISE_FLOOR0 + {0x51F0,0x0002},//T2_NOISE_FLOOR1 + {0x51F2,0x0003},//T2_NOISE_FLOOR2 + {0x51F4,0x0004},//T2_NOISE_FLOOR3 + {0x5402,0x37C3},//T4_PIX_DEF_ID2 + {0x5560,0x0149},//T4_NOISE_GAIN_THRESHOLD0 + {0x556C,0x044D},//T4_NOISE_GAIN_THRESHOLD1 + {0x5562,0x0700},//T4_NOISE_GAIN_THRESHOLD2 + {0x5564,0x0001},//T4_NOISE_FLOOR0 + {0x5566,0x0002},//T4_NOISE_FLOOR1 + {0x5568,0x0003},//T4_NOISE_FLOOR2 + {0x556A,0x0004},//T4_NOISE_FLOOR3 + {0x31E0,0x0001},//PIX_DEF_ID + {0x5000,0x0080},//T1_PIX_DEF_ID + {0x5000,0x0180},//T1_PIX_DEF_ID + {0x5000,0x0180},//T1_PIX_DEF_ID + {0x5200,0x0080},//T2_PIX_DEF_ID + {0x5200,0x0180},//T2_PIX_DEF_ID + {0x5200,0x0180},//T2_PIX_DEF_ID + {0x5400,0x0080},//T4_PIX_DEF_ID + {0x5400,0x0180},//T4_PIX_DEF_ID + {0x5400,0x0180},//T4_PIX_DEF_ID + {0x5000,0x0180},//T1_PIX_DEF_ID + {0x5200,0x0180},//T2_PIX_DEF_ID + {0x5400,0x0180},//T4_PIX_DEF_ID + {0x50A2,0x3F2A},//BMT0 + {0x50A4,0x875A},//BMT1 + {0x50A6,0x030F},//SINGLEK_FACTOR0 + {0x50A6,0x0F0F},//SINGLEK_FACTOR0 + {0x50A8,0x030F},//SINGLEK_FACTOR1 + {0x50A8,0x0F0F},//SINGLEK_FACTOR1 + {0x50AA,0x030F},//SINGLEK_FACTOR2 + {0x50AA,0x050F},//SINGLEK_FACTOR2 + {0x50AC,0x0301},//CROSS_FACTOR0 + {0x50AC,0x0101},//CROSS_FACTOR0 + {0x50AE,0x0301},//CROSS_FACTOR1 + {0x50AE,0x0101},//CROSS_FACTOR1 + {0x50B0,0x0301},//CROSS_FACTOR2 + {0x50B0,0x0101},//CROSS_FACTOR2 + {0x50B2,0x03FF},//SINGLE_MAX_FACTOR + {0x50B4,0x030F},//COUPLE_FACTOR0 + {0x50B4,0x0F0F},//COUPLE_FACTOR0 + {0x50B6,0x030F},//COUPLE_FACTOR1 + {0x50B6,0x0F0F},//COUPLE_FACTOR1 + {0x50B8,0x030F},//COUPLE_FACTOR2 + {0x50B8,0x050F},//COUPLE_FACTOR2 + {0x3D2A,0x0FFF},//T1_END_DEC_TH + {0x3D34,0x9C40},//T2_STR_DEC_TH + {0x3D36,0xFFFF},//T2_END_DEC_TH + {0x3D02,0x5033},//MEC_CTRL2 + {0x3086,0x1A28},//PARK_ROW_ADDR + {0x33E4,0x0040},//VERT_SHADING_CONTROL + {0x3C70,0x6222},//CALIB_ROWS + {0x3110,0x0011},//HDR_CONTROL0 + {0x30B0,0x0820},//DIGITAL_TEST + {0x3280,0x0ED8},//T1_BARRIER_C0 + {0x3282,0x0ED8},//T1_BARRIER_C1 + {0x3284,0x0ED8},//T1_BARRIER_C2 + {0x3286,0x0ED8},//T1_BARRIER_C3 + {0x3288,0x0ED8},//T2_BARRIER_C0 + {0x328A,0x0ED8},//T2_BARRIER_C1 + {0x328C,0x0ED8},//T2_BARRIER_C2 + {0x328E,0x0ED8},//T2_BARRIER_C3 + {0x3290,0x0ED8},//T3_BARRIER_C0 + {0x3292,0x0ED8},//T3_BARRIER_C1 + {0x3294,0x0ED8},//T3_BARRIER_C2 + {0x3296,0x0ED8},//T3_BARRIER_C3 + {0x3100,0xC001},//DLO_CONTROL0 + {0x3102,0xBED8},//DLO_CONTROL1 + {0x3104,0xBED8},//DLO_CONTROL2 + {0x3106,0xBED8},//DLO_CONTROL3 + {0x3108,0x07D0},//DLO_CONTROL4 + {0x3116,0x2001},//HDR_CONTROL3 + {0x3124,0x006D},//HDR_MD_CONTROL0 + {0x3126,0x003C},//HDR_MD_CONTROL1 + {0x31AE,0x0204},//SERIAL_FORMAT + {0x31AC,0x0C0C},//DATA_FORMAT_BITS + {0x3082,0x0014},//OPERATION_MODE_CTRL + {0x30BA,0x0135},//DIGITAL_CTRL + {0x3238,0x0044},//EXPOSURE_RATIO + {0x3012,0x07A0},//COARSE_INTEGRATION_TIME_ + {0x3212,0x007A},//COARSE_INTEGRATION_TIME2 + {0x300C,0x0A8C},//LINE_LENGTH_PCK_ + {0x300A,0x0980},//FRAME_LENGTH_LINES_ + {0x5914,0x4012},//SENSOR_GAIN_TABLE_SEL + {REG_DELAY,100}, + {0x5914,0x4002},//SENSOR_GAIN_TABLE_SEL + {0x5910,0x608A},//SENSOR_GAIN_REG1 + {0x5910,0x7091},//SENSOR_GAIN_REG1 + {0x5910,0x689C},//SENSOR_GAIN_REG1 + {0x5910,0x8885},//SENSOR_GAIN_REG1 + {0x5910,0x98AD},//SENSOR_GAIN_REG1 + {0x5910,0xA8A9},//SENSOR_GAIN_REG1 + {0x5910,0xC894},//SENSOR_GAIN_REG1 + {0x5910,0xC8D1},//SENSOR_GAIN_REG1 + {0x5910,0xD88A},//SENSOR_GAIN_REG1 + {0x5910,0xD8C3},//SENSOR_GAIN_REG1 + {0x5910,0xD915},//SENSOR_GAIN_REG1 + {0x5910,0xD988},//SENSOR_GAIN_REG1 + {0x5910,0xDA2A},//SENSOR_GAIN_REG1 + {0x5910,0xDB0E},//SENSOR_GAIN_REG1 + {0x5910,0xDC53},//SENSOR_GAIN_REG1 + {0x5910,0x608A},//SENSOR_GAIN_REG1 + {0x5910,0xC919},//SENSOR_GAIN_REG1 + {0x5910,0xCA00},//SENSOR_GAIN_REG1 + {0x5910,0x0000},//SENSOR_GAIN_REG1 + {0x5910,0x0000},//SENSOR_GAIN_REG1 + {0x5910,0x0000},//SENSOR_GAIN_REG1 + {0x5910,0x0001},//SENSOR_GAIN_REG1 + {0x5910,0x0001},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0002},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x5A8B},//SENSOR_GAIN_REG1 + {0x5910,0xFF04},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xFF04},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0x0005},//SENSOR_GAIN_REG1 + {0x5910,0x0006},//SENSOR_GAIN_REG1 + {0x5910,0x0007},//SENSOR_GAIN_REG1 + {0x5910,0x9A8B},//SENSOR_GAIN_REG1 + {0x5910,0xFF04},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0x0015},//SENSOR_GAIN_REG1 + {0x5910,0x0016},//SENSOR_GAIN_REG1 + {0x5910,0x0017},//SENSOR_GAIN_REG1 + {0x5910,0xDA8B},//SENSOR_GAIN_REG1 + {0x5910,0xFF04},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0x0025},//SENSOR_GAIN_REG1 + {0x5910,0x0026},//SENSOR_GAIN_REG1 + {0x5910,0x0027},//SENSOR_GAIN_REG1 + {0x5910,0x59B9},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x0035},//SENSOR_GAIN_REG1 + {0x5910,0x0036},//SENSOR_GAIN_REG1 + {0x5910,0x0037},//SENSOR_GAIN_REG1 + {0x5910,0x99B9},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x0045},//SENSOR_GAIN_REG1 + {0x5910,0x0046},//SENSOR_GAIN_REG1 + {0x5910,0x0047},//SENSOR_GAIN_REG1 + {0x5910,0xD9B9},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x0055},//SENSOR_GAIN_REG1 + {0x5910,0x0056},//SENSOR_GAIN_REG1 + {0x5910,0x0057},//SENSOR_GAIN_REG1 + {0x5910,0x9A85},//SENSOR_GAIN_REG1 + {0x5910,0x0654},//SENSOR_GAIN_REG1 + {0x5910,0x0654},//SENSOR_GAIN_REG1 + {0x5910,0x0684},//SENSOR_GAIN_REG1 + {0x5910,0x0654},//SENSOR_GAIN_REG1 + {0x5910,0x0654},//SENSOR_GAIN_REG1 + {0x5910,0x0065},//SENSOR_GAIN_REG1 + {0x5910,0x0066},//SENSOR_GAIN_REG1 + {0x5910,0x0067},//SENSOR_GAIN_REG1 + {0x5910,0x59BD},//SENSOR_GAIN_REG1 + {0x5910,0x1000},//SENSOR_GAIN_REG1 + {0x5910,0x0C00},//SENSOR_GAIN_REG1 + {0x5910,0x0F00},//SENSOR_GAIN_REG1 + {0x5910,0x1000},//SENSOR_GAIN_REG1 + {0x5910,0x10F0},//SENSOR_GAIN_REG1 + {0x5910,0x0075},//SENSOR_GAIN_REG1 + {0x5910,0x0076},//SENSOR_GAIN_REG1 + {0x5910,0x0077},//SENSOR_GAIN_REG1 + {0x5912,0x608A},//SENSOR_GAIN_REG2 + {0x5912,0x7091},//SENSOR_GAIN_REG2 + {0x5912,0x689C},//SENSOR_GAIN_REG2 + {0x5912,0x8885},//SENSOR_GAIN_REG2 + {0x5912,0x98AD},//SENSOR_GAIN_REG2 + {0x5912,0xA8A9},//SENSOR_GAIN_REG2 + {0x5912,0xC894},//SENSOR_GAIN_REG2 + {0x5912,0xC8D1},//SENSOR_GAIN_REG2 + {0x5912,0xC927},//SENSOR_GAIN_REG2 + {0x5912,0xC9A0},//SENSOR_GAIN_REG2 + {0x5912,0xCA4C},//SENSOR_GAIN_REG2 + {0x5912,0xCB3F},//SENSOR_GAIN_REG2 + {0x5912,0xCC97},//SENSOR_GAIN_REG2 + {0x5912,0xCE7C},//SENSOR_GAIN_REG2 + {0x5912,0xCFFF},//SENSOR_GAIN_REG2 + {0x5912,0x608A},//SENSOR_GAIN_REG2 + {0x5912,0xC8F0},//SENSOR_GAIN_REG2 + {0x5912,0xCA00},//SENSOR_GAIN_REG2 + {0x5912,0x0000},//SENSOR_GAIN_REG2 + {0x5912,0x0000},//SENSOR_GAIN_REG2 + {0x5912,0x0000},//SENSOR_GAIN_REG2 + {0x5912,0x0001},//SENSOR_GAIN_REG2 + {0x5912,0x0001},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0002},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x5A8B},//SENSOR_GAIN_REG2 + {0x5912,0xFF04},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xFF04},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0x0005},//SENSOR_GAIN_REG2 + {0x5912,0x0006},//SENSOR_GAIN_REG2 + {0x5912,0x0007},//SENSOR_GAIN_REG2 + {0x5912,0x9A8B},//SENSOR_GAIN_REG2 + {0x5912,0xFF04},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0x0015},//SENSOR_GAIN_REG2 + {0x5912,0x0016},//SENSOR_GAIN_REG2 + {0x5912,0x0017},//SENSOR_GAIN_REG2 + {0x5912,0xDA8B},//SENSOR_GAIN_REG2 + {0x5912,0xFF04},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0x0025},//SENSOR_GAIN_REG2 + {0x5912,0x0026},//SENSOR_GAIN_REG2 + {0x5912,0x0027},//SENSOR_GAIN_REG2 + {0x5912,0x59B9},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x0035},//SENSOR_GAIN_REG2 + {0x5912,0x0036},//SENSOR_GAIN_REG2 + {0x5912,0x0037},//SENSOR_GAIN_REG2 + {0x5912,0x99B9},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x0045},//SENSOR_GAIN_REG2 + {0x5912,0x0046},//SENSOR_GAIN_REG2 + {0x5912,0x0047},//SENSOR_GAIN_REG2 + {0x5912,0xD9B9},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x0055},//SENSOR_GAIN_REG2 + {0x5912,0x0056},//SENSOR_GAIN_REG2 + {0x5912,0x0057},//SENSOR_GAIN_REG2 + {0x5912,0x9A85},//SENSOR_GAIN_REG2 + {0x5912,0x0654},//SENSOR_GAIN_REG2 + {0x5912,0x0654},//SENSOR_GAIN_REG2 + {0x5912,0x0684},//SENSOR_GAIN_REG2 + {0x5912,0x0654},//SENSOR_GAIN_REG2 + {0x5912,0x0654},//SENSOR_GAIN_REG2 + {0x5912,0x0065},//SENSOR_GAIN_REG2 + {0x5912,0x0066},//SENSOR_GAIN_REG2 + {0x5912,0x0067},//SENSOR_GAIN_REG2 + {0x5912,0x59BD},//SENSOR_GAIN_REG2 + {0x5912,0x1000},//SENSOR_GAIN_REG2 + {0x5912,0x0C00},//SENSOR_GAIN_REG2 + {0x5912,0x0F00},//SENSOR_GAIN_REG2 + {0x5912,0x1000},//SENSOR_GAIN_REG2 + {0x5912,0x10F0},//SENSOR_GAIN_REG2 + {0x5912,0x0075},//SENSOR_GAIN_REG2 + {0x5912,0x0076},//SENSOR_GAIN_REG2 + {0x5912,0x0077},//SENSOR_GAIN_REG2 + {0x5914,0x4006},//SENSOR_GAIN_TABLE_SEL + {0x5900,0x0020},//SENSOR_GAIN + {0x5902,0x0000},//SENSOR_GAIN_T2 + {0x3110,0x0001},//HDR_CONTROL0 + + {REG_NULL, 0x00}, +}; +static const struct regval ar0822_hdr12bit_3840x2160_20fps_regs[] = { + {REG_DELAY, 2000}, + {0x3030,0x0124},//PLL_MULTIPLIER + {0x302E,0x0006},//PRE_PLL_CLK_DIV + {0x302C,0x0002},//VT_SYS_CLK_DIV + {0x302A,0x0004},//VT_PIX_CLK_DIV + {0x3038,0x0002},//OP_SYS_CLK_DIV + {0x3036,0x0006},//OP_WORD_CLK_DIV + {0x31B0,0x0089},//FRAME_PREAMBLE + {0x31B2,0x005C},//LINE_PREAMBLE + {0x31B4,0x624A},//MIPI_TIMING_0 + {0x31B6,0x630B},//MIPI_TIMING_1 + {0x31B8,0x90CB},//MIPI_TIMING_2 + {0x31BA,0x038E},//MIPI_TIMING_3 + {0x31BC,0x508B},//MIPI_TIMING_4 + {0x3342,0x122C},//MIPI_F1_PDT_EDT + {0x2512,0xA000},//SEQ_CTRL_PORT + {0x2510,0x0720},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0x2122},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0x26FF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x0F8C},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0x8055},//SEQ_DATA_PORT + {0x2510,0xA0E1},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3088},//SEQ_DATA_PORT + {0x2510,0x3282},//SEQ_DATA_PORT + {0x2510,0xA681},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FE},//SEQ_DATA_PORT + {0x2510,0x9070},//SEQ_DATA_PORT + {0x2510,0x891D},//SEQ_DATA_PORT + {0x2510,0x867F},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FC},//SEQ_DATA_PORT + {0x2510,0x893F},//SEQ_DATA_PORT + {0x2510,0x0F92},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0x0F8F},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0x9770},//SEQ_DATA_PORT + {0x2510,0x20FC},//SEQ_DATA_PORT + {0x2510,0x8054},//SEQ_DATA_PORT + {0x2510,0x896C},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x9030},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x8040},//SEQ_DATA_PORT + {0x2510,0x8948},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x1597},//SEQ_DATA_PORT + {0x2510,0x8808},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x1F96},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0xA0C0},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x3044},//SEQ_DATA_PORT + {0x2510,0x3088},//SEQ_DATA_PORT + {0x2510,0x3282},//SEQ_DATA_PORT + {0x2510,0x2004},//SEQ_DATA_PORT + {0x2510,0x1FAA},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x3108},//SEQ_DATA_PORT + {0x2510,0x2400},//SEQ_DATA_PORT + {0x2510,0x3244},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x3108},//SEQ_DATA_PORT + {0x2510,0x2400},//SEQ_DATA_PORT + {0x2510,0x2702},//SEQ_DATA_PORT + {0x2510,0x3242},//SEQ_DATA_PORT + {0x2510,0x3108},//SEQ_DATA_PORT + {0x2510,0x2420},//SEQ_DATA_PORT + {0x2510,0x2703},//SEQ_DATA_PORT + {0x2510,0x3242},//SEQ_DATA_PORT + {0x2510,0x3108},//SEQ_DATA_PORT + {0x2510,0x2420},//SEQ_DATA_PORT + {0x2510,0x2704},//SEQ_DATA_PORT + {0x2510,0x3244},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x8801},//SEQ_DATA_PORT + {0x2510,0x000F},//SEQ_DATA_PORT + {0x2510,0x109C},//SEQ_DATA_PORT + {0x2510,0x8855},//SEQ_DATA_PORT + {0x2510,0x3101},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3102},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3181},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3188},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3282},//SEQ_DATA_PORT + {0x2510,0x3104},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0xB0E4},//SEQ_DATA_PORT + {0x2510,0xAD92},//SEQ_DATA_PORT + {0x2510,0xBC0C},//SEQ_DATA_PORT + {0x2510,0x1028},//SEQ_DATA_PORT + {0x2510,0x0022},//SEQ_DATA_PORT + {0x2510,0xC020},//SEQ_DATA_PORT + {0x2510,0x003E},//SEQ_DATA_PORT + {0x2510,0x0045},//SEQ_DATA_PORT + {0x2510,0x00B0},//SEQ_DATA_PORT + {0x2510,0x0028},//SEQ_DATA_PORT + {0x2510,0x30C1},//SEQ_DATA_PORT + {0x2510,0x8015},//SEQ_DATA_PORT + {0x2510,0xA038},//SEQ_DATA_PORT + {0x2510,0x100F},//SEQ_DATA_PORT + {0x2510,0x0507},//SEQ_DATA_PORT + {0x2510,0xA220},//SEQ_DATA_PORT + {0x2510,0x0010},//SEQ_DATA_PORT + {0x2510,0x10C2},//SEQ_DATA_PORT + {0x2510,0xB760},//SEQ_DATA_PORT + {0x2510,0x0033},//SEQ_DATA_PORT + {0x2510,0x1082},//SEQ_DATA_PORT + {0x2510,0x100B},//SEQ_DATA_PORT + {0x2510,0x1029},//SEQ_DATA_PORT + {0x2510,0xA85A},//SEQ_DATA_PORT + {0x2510,0x998D},//SEQ_DATA_PORT + {0x2510,0xC810},//SEQ_DATA_PORT + {0x2510,0x2004},//SEQ_DATA_PORT + {0x2510,0x0ECE},//SEQ_DATA_PORT + {0x2510,0x123B},//SEQ_DATA_PORT + {0x2510,0xC000},//SEQ_DATA_PORT + {0x2510,0x032F},//SEQ_DATA_PORT + {0x2510,0x11D5},//SEQ_DATA_PORT + {0x2510,0x162F},//SEQ_DATA_PORT + {0x2510,0x9000},//SEQ_DATA_PORT + {0x2510,0x2034},//SEQ_DATA_PORT + {0x2510,0x0015},//SEQ_DATA_PORT + {0x2510,0x04CB},//SEQ_DATA_PORT + {0x2510,0x1022},//SEQ_DATA_PORT + {0x2510,0x1031},//SEQ_DATA_PORT + {0x2510,0x002D},//SEQ_DATA_PORT + {0x2510,0x1015},//SEQ_DATA_PORT + {0x2510,0x80B9},//SEQ_DATA_PORT + {0x2510,0xA101},//SEQ_DATA_PORT + {0x2510,0x001C},//SEQ_DATA_PORT + {0x2510,0x008E},//SEQ_DATA_PORT + {0x2510,0x124B},//SEQ_DATA_PORT + {0x2510,0x01B5},//SEQ_DATA_PORT + {0x2510,0x0B92},//SEQ_DATA_PORT + {0x2510,0xA400},//SEQ_DATA_PORT + {0x2510,0x8091},//SEQ_DATA_PORT + {0x2510,0x0028},//SEQ_DATA_PORT + {0x2510,0x3002},//SEQ_DATA_PORT + {0x2510,0x2004},//SEQ_DATA_PORT + {0x2510,0x1012},//SEQ_DATA_PORT + {0x2510,0x100E},//SEQ_DATA_PORT + {0x2510,0x10A8},//SEQ_DATA_PORT + {0x2510,0x00A1},//SEQ_DATA_PORT + {0x2510,0x132D},//SEQ_DATA_PORT + {0x2510,0x09AF},//SEQ_DATA_PORT + {0x2510,0x0159},//SEQ_DATA_PORT + {0x2510,0x121D},//SEQ_DATA_PORT + {0x2510,0x1259},//SEQ_DATA_PORT + {0x2510,0x11AF},//SEQ_DATA_PORT + {0x2510,0x18B5},//SEQ_DATA_PORT + {0x2510,0x0395},//SEQ_DATA_PORT + {0x2510,0x054B},//SEQ_DATA_PORT + {0x2510,0x1021},//SEQ_DATA_PORT + {0x2510,0x0020},//SEQ_DATA_PORT + {0x2510,0x1015},//SEQ_DATA_PORT + {0x2510,0x1030},//SEQ_DATA_PORT + {0x2510,0x00CF},//SEQ_DATA_PORT + {0x2510,0xB146},//SEQ_DATA_PORT + {0x2510,0xC290},//SEQ_DATA_PORT + {0x2510,0x103C},//SEQ_DATA_PORT + {0x2510,0xA882},//SEQ_DATA_PORT + {0x2510,0x8055},//SEQ_DATA_PORT + {0x2510,0x00A9},//SEQ_DATA_PORT + {0x2510,0x8801},//SEQ_DATA_PORT + {0x2510,0xB700},//SEQ_DATA_PORT + {0x2510,0x0001},//SEQ_DATA_PORT + {0x2510,0x02A2},//SEQ_DATA_PORT + {0x2510,0x000A},//SEQ_DATA_PORT + {0x2510,0x98BB},//SEQ_DATA_PORT + {0x2510,0x203F},//SEQ_DATA_PORT + {0x2510,0x0036},//SEQ_DATA_PORT + {0x2510,0x1001},//SEQ_DATA_PORT + {0x2510,0x99BE},//SEQ_DATA_PORT + {0x2510,0x0139},//SEQ_DATA_PORT + {0x2510,0x100A},//SEQ_DATA_PORT + {0x2510,0x0040},//SEQ_DATA_PORT + {0x2510,0x1022},//SEQ_DATA_PORT + {0x2510,0x124C},//SEQ_DATA_PORT + {0x2510,0x109F},//SEQ_DATA_PORT + {0x2510,0x15A3},//SEQ_DATA_PORT + {0x2510,0x002A},//SEQ_DATA_PORT + {0x2510,0x3081},//SEQ_DATA_PORT + {0x2510,0x2001},//SEQ_DATA_PORT + {0x2510,0x3044},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x112A},//SEQ_DATA_PORT + {0x2510,0x101D},//SEQ_DATA_PORT + {0x2510,0x202B},//SEQ_DATA_PORT + {0x2510,0x02B8},//SEQ_DATA_PORT + {0x2510,0x10B8},//SEQ_DATA_PORT + {0x2510,0x1136},//SEQ_DATA_PORT + {0x2510,0x996B},//SEQ_DATA_PORT + {0x2510,0x004C},//SEQ_DATA_PORT + {0x2510,0x1039},//SEQ_DATA_PORT + {0x2510,0x1040},//SEQ_DATA_PORT + {0x2510,0x00B5},//SEQ_DATA_PORT + {0x2510,0x03C4},//SEQ_DATA_PORT + {0x2510,0x1144},//SEQ_DATA_PORT + {0x2510,0x1245},//SEQ_DATA_PORT + {0x2510,0x9A7B},//SEQ_DATA_PORT + {0x2510,0x002B},//SEQ_DATA_PORT + {0x2510,0x30D0},//SEQ_DATA_PORT + {0x2510,0x3141},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3142},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3110},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3120},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3144},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3148},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3182},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3184},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3190},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x31A0},//SEQ_DATA_PORT + {0x2510,0x3088},//SEQ_DATA_PORT + {0x2510,0x2201},//SEQ_DATA_PORT + {0x2510,0x807D},//SEQ_DATA_PORT + {0x2510,0x2206},//SEQ_DATA_PORT + {0x2510,0x8815},//SEQ_DATA_PORT + {0x2510,0x8877},//SEQ_DATA_PORT + {0x2510,0x0092},//SEQ_DATA_PORT + {0x2510,0x220E},//SEQ_DATA_PORT + {0x2510,0x2211},//SEQ_DATA_PORT + {0x2510,0x8055},//SEQ_DATA_PORT + {0x2510,0x3001},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x8A61},//SEQ_DATA_PORT + {0x2510,0x8801},//SEQ_DATA_PORT + {0x2510,0x1092},//SEQ_DATA_PORT + {0x2510,0x181F},//SEQ_DATA_PORT + {0x2510,0x0B1F},//SEQ_DATA_PORT + {0x2510,0x101F},//SEQ_DATA_PORT + {0x2510,0x00B6},//SEQ_DATA_PORT + {0x2510,0x0023},//SEQ_DATA_PORT + {0x2510,0x00B9},//SEQ_DATA_PORT + {0x2510,0x104C},//SEQ_DATA_PORT + {0x2510,0x996E},//SEQ_DATA_PORT + {0x2510,0x0140},//SEQ_DATA_PORT + {0x2510,0x0257},//SEQ_DATA_PORT + {0x2510,0x1035},//SEQ_DATA_PORT + {0x2510,0x9F26},//SEQ_DATA_PORT + {0x2510,0x1423},//SEQ_DATA_PORT + {0x2510,0x0048},//SEQ_DATA_PORT + {0x2510,0xC878},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x1548},//SEQ_DATA_PORT + {0x2510,0x0C49},//SEQ_DATA_PORT + {0x2510,0x1149},//SEQ_DATA_PORT + {0x2510,0x002A},//SEQ_DATA_PORT + {0x2510,0x1057},//SEQ_DATA_PORT + {0x2510,0x3281},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3044},//SEQ_DATA_PORT + {0x2510,0x2001},//SEQ_DATA_PORT + {0x2510,0xA020},//SEQ_DATA_PORT + {0x2510,0x000C},//SEQ_DATA_PORT + {0x2510,0x9825},//SEQ_DATA_PORT + {0x2510,0x1040},//SEQ_DATA_PORT + {0x2510,0x1054},//SEQ_DATA_PORT + {0x2510,0xB06D},//SEQ_DATA_PORT + {0x2510,0x0035},//SEQ_DATA_PORT + {0x2510,0x004D},//SEQ_DATA_PORT + {0x2510,0x9905},//SEQ_DATA_PORT + {0x2510,0xB064},//SEQ_DATA_PORT + {0x2510,0x99C5},//SEQ_DATA_PORT + {0x2510,0x0047},//SEQ_DATA_PORT + {0x2510,0xB920},//SEQ_DATA_PORT + {0x2510,0x1447},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x31F8,0x0008},//MIPI_CONFIG_2 + {0x3C70,0x6828},//CALIB_ROWS + {0x3092,0x0826},//ROW_NOISE_CONTROL + {0x3428,0x0209},//SEQUENCER_CONTROL + {0x3516,0xFF04},//DAC_LD_22_23 + {0x3526,0x6480},//DAC_LD_38_39 + {0x3504,0x8AAA},//DAC_LD_4_5 + {0x353C,0x220C},//DAC_LD_60_61 + {0x3536,0x4C6E},//DAC_LD_54_55 + {0x3D2A,0x0FFF},//T1_END_DEC_TH + {0x3364,0x00EC},//DCG_TRIM + {0x3512,0x8888},//DAC_LD_18_19 + {0x3514,0x888F},//DAC_LD_20_21 + {0x3520,0xFBF0},//DAC_LD_32_33 + {0x3524,0xB2A1},//DAC_LD_36_37 + {0x3528,0xCC84},//DAC_LD_40_41 + {0x3532,0x4C8E},//DAC_LD_50_51 + {0x3534,0x4E64},//DAC_LD_52_53 + {0x351E,0x5856},//DAC_LD_30_31 + {0x353E,0x98F2},//DAC_LD_62_63 + {0x352E,0x6A8A},//DAC_LD_46_47 + {0x3370,0x0211},//DBLC_CONTROL + {0x3372,0x700F},//DBLC_FS0_CONTROL + {0x3540,0x3597},//DAC_LD_64_65 + {0x58E2,0x0BE3},//COL_COUNT_VALUES1 + {0x58E4,0x18B4},//COL_COUNT_VALUES2 + {0x3522,0x7C97},//DAC_LD_34_35 + {0x30BA,0x0024},//DIGITAL_CTRL + {0x31D4,0x0042},//CLK_MEM_GATING_CTRL + {0x352A,0x6F8F},//DAC_LD_42_43 + {0x3530,0x4A08},//DAC_LD_48_49 + {0x351A,0x5FFF},//DAC_LD_26_27 + {0x350E,0x39D9},//DAC_LD_14_15 + {0x3510,0x9988},//DAC_LD_16_17 + {0x3380,0x1FFF},//DBLC_OFFSET1 + {0x337A,0x1000},//DBLC_SCALE1 + {0x3092,0x0800},//ROW_NOISE_CONTROL + {0x350A,0x0654},//DAC_LD_10_11 + {0x3364,0x00E0},//DCG_TRIM + {0x591E,0x61AE},//ANALOG_GAIN_WR_DATA + {0x591E,0x722C},//ANALOG_GAIN_WR_DATA + {0x591E,0x82B8},//ANALOG_GAIN_WR_DATA + {0x591E,0x92F6},//ANALOG_GAIN_WR_DATA + {0x591E,0xA447},//ANALOG_GAIN_WR_DATA + {0x591E,0xB66D},//ANALOG_GAIN_WR_DATA + {0x591E,0xC6EA},//ANALOG_GAIN_WR_DATA + {0x591E,0xDECD},//ANALOG_GAIN_WR_DATA + {0x3532,0x4C8A},//DAC_LD_50_51 + {0x3534,0x4E60},//DAC_LD_52_53 + {0x353E,0x90F2},//DAC_LD_62_63 + {0x351A,0x4FFF},//DAC_LD_26_27 + {0x591C,0x00D7},//DGR_AMP_GAIN + {0x3522,0x6097},//DAC_LD_34_35 + {0x5002,0x37C3},//T1_PIX_DEF_ID2 + {0x51CC,0x0149},//T1_NOISE_GAIN_THRESHOLD0 + {0x51D8,0x044D},//T1_NOISE_GAIN_THRESHOLD1 + {0x51CE,0x0700},//T1_NOISE_GAIN_THRESHOLD2 + {0x51D0,0x0001},//T1_NOISE_FLOOR0 + {0x51D2,0x0002},//T1_NOISE_FLOOR1 + {0x51D4,0x0003},//T1_NOISE_FLOOR2 + {0x51D6,0x0004},//T1_NOISE_FLOOR3 + {0x5202,0x37C3},//T2_PIX_DEF_ID2 + {0x51EA,0x0149},//T2_NOISE_GAIN_THRESHOLD0 + {0x51FC,0x044D},//T2_NOISE_GAIN_THRESHOLD1 + {0x51EC,0x0700},//T2_NOISE_GAIN_THRESHOLD2 + {0x51EE,0x0001},//T2_NOISE_FLOOR0 + {0x51F0,0x0002},//T2_NOISE_FLOOR1 + {0x51F2,0x0003},//T2_NOISE_FLOOR2 + {0x51F4,0x0004},//T2_NOISE_FLOOR3 + {0x5402,0x37C3},//T4_PIX_DEF_ID2 + {0x5560,0x0149},//T4_NOISE_GAIN_THRESHOLD0 + {0x556C,0x044D},//T4_NOISE_GAIN_THRESHOLD1 + {0x5562,0x0700},//T4_NOISE_GAIN_THRESHOLD2 + {0x5564,0x0001},//T4_NOISE_FLOOR0 + {0x5566,0x0002},//T4_NOISE_FLOOR1 + {0x5568,0x0003},//T4_NOISE_FLOOR2 + {0x556A,0x0004},//T4_NOISE_FLOOR3 + {0x31E0,0x0001},//PIX_DEF_ID + {0x5000,0x0080},//T1_PIX_DEF_ID + {0x5000,0x0180},//T1_PIX_DEF_ID + {0x5000,0x0180},//T1_PIX_DEF_ID + {0x5200,0x0080},//T2_PIX_DEF_ID + {0x5200,0x0180},//T2_PIX_DEF_ID + {0x5200,0x0180},//T2_PIX_DEF_ID + {0x5400,0x0080},//T4_PIX_DEF_ID + {0x5400,0x0180},//T4_PIX_DEF_ID + {0x5400,0x0180},//T4_PIX_DEF_ID + {0x5000,0x0180},//T1_PIX_DEF_ID + {0x5200,0x0180},//T2_PIX_DEF_ID + {0x5400,0x0180},//T4_PIX_DEF_ID + {0x50A2,0x3F2A},//BMT0 + {0x50A4,0x875A},//BMT1 + {0x50A6,0x030F},//SINGLEK_FACTOR0 + {0x50A6,0x0F0F},//SINGLEK_FACTOR0 + {0x50A8,0x030F},//SINGLEK_FACTOR1 + {0x50A8,0x0F0F},//SINGLEK_FACTOR1 + {0x50AA,0x030F},//SINGLEK_FACTOR2 + {0x50AA,0x050F},//SINGLEK_FACTOR2 + {0x50AC,0x0301},//CROSS_FACTOR0 + {0x50AC,0x0101},//CROSS_FACTOR0 + {0x50AE,0x0301},//CROSS_FACTOR1 + {0x50AE,0x0101},//CROSS_FACTOR1 + {0x50B0,0x0301},//CROSS_FACTOR2 + {0x50B0,0x0101},//CROSS_FACTOR2 + {0x50B2,0x03FF},//SINGLE_MAX_FACTOR + {0x50B4,0x030F},//COUPLE_FACTOR0 + {0x50B4,0x0F0F},//COUPLE_FACTOR0 + {0x50B6,0x030F},//COUPLE_FACTOR1 + {0x50B6,0x0F0F},//COUPLE_FACTOR1 + {0x50B8,0x030F},//COUPLE_FACTOR2 + {0x50B8,0x050F},//COUPLE_FACTOR2 + {0x3D2A,0x0FFF},//T1_END_DEC_TH + {0x3D34,0x9C40},//T2_STR_DEC_TH + {0x3D36,0xFFFF},//T2_END_DEC_TH + {0x3D02,0x5033},//MEC_CTRL2 + {0x3086,0x1A28},//PARK_ROW_ADDR + {0x33E4,0x0040},//VERT_SHADING_CONTROL + {0x3C70,0x6222},//CALIB_ROWS + {0x3110,0x0011},//HDR_CONTROL0 + {0x30B0,0x0820},//DIGITAL_TEST + {0x3280,0x0ED8},//T1_BARRIER_C0 + {0x3282,0x0ED8},//T1_BARRIER_C1 + {0x3284,0x0ED8},//T1_BARRIER_C2 + {0x3286,0x0ED8},//T1_BARRIER_C3 + {0x3288,0x0ED8},//T2_BARRIER_C0 + {0x328A,0x0ED8},//T2_BARRIER_C1 + {0x328C,0x0ED8},//T2_BARRIER_C2 + {0x328E,0x0ED8},//T2_BARRIER_C3 + {0x3290,0x0ED8},//T3_BARRIER_C0 + {0x3292,0x0ED8},//T3_BARRIER_C1 + {0x3294,0x0ED8},//T3_BARRIER_C2 + {0x3296,0x0ED8},//T3_BARRIER_C3 + {0x3100,0xC001},//DLO_CONTROL0 + {0x3102,0xBED8},//DLO_CONTROL1 + {0x3104,0xBED8},//DLO_CONTROL2 + {0x3106,0xBED8},//DLO_CONTROL3 + {0x3108,0x07D0},//DLO_CONTROL4 + {0x3116,0x2001},//HDR_CONTROL3 + {0x3124,0x006D},//HDR_MD_CONTROL0 + {0x3126,0x003C},//HDR_MD_CONTROL1 + {0x31AE,0x0204},//SERIAL_FORMAT + {0x31AC,0x0C0C},//DATA_FORMAT_BITS + {0x3082,0x0014},//OPERATION_MODE_CTRL + {0x30BA,0x0135},//DIGITAL_CTRL + {0x3238,0x0044},//EXPOSURE_RATIO + {0x3012,0x0900},//COARSE_INTEGRATION_TIME_ + {0x3212,0x0090},//COARSE_INTEGRATION_TIME2 + {0x300C,0x0CE2},//LINE_LENGTH_PCK_ + {0x300A,0x09B8},//FRAME_LENGTH_LINES_ + {0x5914,0x4012},//SENSOR_GAIN_TABLE_SEL + {REG_DELAY,100}, + {0x5914,0x4002},//SENSOR_GAIN_TABLE_SEL + {0x5910,0x608A},//SENSOR_GAIN_REG1 + {0x5910,0x7091},//SENSOR_GAIN_REG1 + {0x5910,0x689C},//SENSOR_GAIN_REG1 + {0x5910,0x8885},//SENSOR_GAIN_REG1 + {0x5910,0x98AD},//SENSOR_GAIN_REG1 + {0x5910,0xA8A9},//SENSOR_GAIN_REG1 + {0x5910,0xC894},//SENSOR_GAIN_REG1 + {0x5910,0xC8D1},//SENSOR_GAIN_REG1 + {0x5910,0xD88A},//SENSOR_GAIN_REG1 + {0x5910,0xD8C3},//SENSOR_GAIN_REG1 + {0x5910,0xD915},//SENSOR_GAIN_REG1 + {0x5910,0xD988},//SENSOR_GAIN_REG1 + {0x5910,0xDA2A},//SENSOR_GAIN_REG1 + {0x5910,0xDB0E},//SENSOR_GAIN_REG1 + {0x5910,0xDC53},//SENSOR_GAIN_REG1 + {0x5910,0x608A},//SENSOR_GAIN_REG1 + {0x5910,0xC919},//SENSOR_GAIN_REG1 + {0x5910,0xCA00},//SENSOR_GAIN_REG1 + {0x5910,0x0000},//SENSOR_GAIN_REG1 + {0x5910,0x0000},//SENSOR_GAIN_REG1 + {0x5910,0x0000},//SENSOR_GAIN_REG1 + {0x5910,0x0001},//SENSOR_GAIN_REG1 + {0x5910,0x0001},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0002},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x5A8B},//SENSOR_GAIN_REG1 + {0x5910,0xFF04},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xFF04},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0x0005},//SENSOR_GAIN_REG1 + {0x5910,0x0006},//SENSOR_GAIN_REG1 + {0x5910,0x0007},//SENSOR_GAIN_REG1 + {0x5910,0x9A8B},//SENSOR_GAIN_REG1 + {0x5910,0xFF04},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0x0015},//SENSOR_GAIN_REG1 + {0x5910,0x0016},//SENSOR_GAIN_REG1 + {0x5910,0x0017},//SENSOR_GAIN_REG1 + {0x5910,0xDA8B},//SENSOR_GAIN_REG1 + {0x5910,0xFF04},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0x0025},//SENSOR_GAIN_REG1 + {0x5910,0x0026},//SENSOR_GAIN_REG1 + {0x5910,0x0027},//SENSOR_GAIN_REG1 + {0x5910,0x59B9},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x0035},//SENSOR_GAIN_REG1 + {0x5910,0x0036},//SENSOR_GAIN_REG1 + {0x5910,0x0037},//SENSOR_GAIN_REG1 + {0x5910,0x99B9},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x0045},//SENSOR_GAIN_REG1 + {0x5910,0x0046},//SENSOR_GAIN_REG1 + {0x5910,0x0047},//SENSOR_GAIN_REG1 + {0x5910,0xD9B9},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x0055},//SENSOR_GAIN_REG1 + {0x5910,0x0056},//SENSOR_GAIN_REG1 + {0x5910,0x0057},//SENSOR_GAIN_REG1 + {0x5910,0x9A85},//SENSOR_GAIN_REG1 + {0x5910,0x0654},//SENSOR_GAIN_REG1 + {0x5910,0x0654},//SENSOR_GAIN_REG1 + {0x5910,0x0684},//SENSOR_GAIN_REG1 + {0x5910,0x0654},//SENSOR_GAIN_REG1 + {0x5910,0x0654},//SENSOR_GAIN_REG1 + {0x5910,0x0065},//SENSOR_GAIN_REG1 + {0x5910,0x0066},//SENSOR_GAIN_REG1 + {0x5910,0x0067},//SENSOR_GAIN_REG1 + {0x5910,0x59BD},//SENSOR_GAIN_REG1 + {0x5910,0x1000},//SENSOR_GAIN_REG1 + {0x5910,0x0C00},//SENSOR_GAIN_REG1 + {0x5910,0x0F00},//SENSOR_GAIN_REG1 + {0x5910,0x1000},//SENSOR_GAIN_REG1 + {0x5910,0x10F0},//SENSOR_GAIN_REG1 + {0x5910,0x0075},//SENSOR_GAIN_REG1 + {0x5910,0x0076},//SENSOR_GAIN_REG1 + {0x5910,0x0077},//SENSOR_GAIN_REG1 + {0x5912,0x608A},//SENSOR_GAIN_REG2 + {0x5912,0x7091},//SENSOR_GAIN_REG2 + {0x5912,0x689C},//SENSOR_GAIN_REG2 + {0x5912,0x8885},//SENSOR_GAIN_REG2 + {0x5912,0x98AD},//SENSOR_GAIN_REG2 + {0x5912,0xA8A9},//SENSOR_GAIN_REG2 + {0x5912,0xC894},//SENSOR_GAIN_REG2 + {0x5912,0xC8D1},//SENSOR_GAIN_REG2 + {0x5912,0xC927},//SENSOR_GAIN_REG2 + {0x5912,0xC9A0},//SENSOR_GAIN_REG2 + {0x5912,0xCA4C},//SENSOR_GAIN_REG2 + {0x5912,0xCB3F},//SENSOR_GAIN_REG2 + {0x5912,0xCC97},//SENSOR_GAIN_REG2 + {0x5912,0xCE7C},//SENSOR_GAIN_REG2 + {0x5912,0xCFFF},//SENSOR_GAIN_REG2 + {0x5912,0x608A},//SENSOR_GAIN_REG2 + {0x5912,0xC8F0},//SENSOR_GAIN_REG2 + {0x5912,0xCA00},//SENSOR_GAIN_REG2 + {0x5912,0x0000},//SENSOR_GAIN_REG2 + {0x5912,0x0000},//SENSOR_GAIN_REG2 + {0x5912,0x0000},//SENSOR_GAIN_REG2 + {0x5912,0x0001},//SENSOR_GAIN_REG2 + {0x5912,0x0001},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0002},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x5A8B},//SENSOR_GAIN_REG2 + {0x5912,0xFF04},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xFF04},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0x0005},//SENSOR_GAIN_REG2 + {0x5912,0x0006},//SENSOR_GAIN_REG2 + {0x5912,0x0007},//SENSOR_GAIN_REG2 + {0x5912,0x9A8B},//SENSOR_GAIN_REG2 + {0x5912,0xFF04},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0x0015},//SENSOR_GAIN_REG2 + {0x5912,0x0016},//SENSOR_GAIN_REG2 + {0x5912,0x0017},//SENSOR_GAIN_REG2 + {0x5912,0xDA8B},//SENSOR_GAIN_REG2 + {0x5912,0xFF04},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0x0025},//SENSOR_GAIN_REG2 + {0x5912,0x0026},//SENSOR_GAIN_REG2 + {0x5912,0x0027},//SENSOR_GAIN_REG2 + {0x5912,0x59B9},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x0035},//SENSOR_GAIN_REG2 + {0x5912,0x0036},//SENSOR_GAIN_REG2 + {0x5912,0x0037},//SENSOR_GAIN_REG2 + {0x5912,0x99B9},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x0045},//SENSOR_GAIN_REG2 + {0x5912,0x0046},//SENSOR_GAIN_REG2 + {0x5912,0x0047},//SENSOR_GAIN_REG2 + {0x5912,0xD9B9},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x0055},//SENSOR_GAIN_REG2 + {0x5912,0x0056},//SENSOR_GAIN_REG2 + {0x5912,0x0057},//SENSOR_GAIN_REG2 + {0x5912,0x9A85},//SENSOR_GAIN_REG2 + {0x5912,0x0654},//SENSOR_GAIN_REG2 + {0x5912,0x0654},//SENSOR_GAIN_REG2 + {0x5912,0x0684},//SENSOR_GAIN_REG2 + {0x5912,0x0654},//SENSOR_GAIN_REG2 + {0x5912,0x0654},//SENSOR_GAIN_REG2 + {0x5912,0x0065},//SENSOR_GAIN_REG2 + {0x5912,0x0066},//SENSOR_GAIN_REG2 + {0x5912,0x0067},//SENSOR_GAIN_REG2 + {0x5912,0x59BD},//SENSOR_GAIN_REG2 + {0x5912,0x1000},//SENSOR_GAIN_REG2 + {0x5912,0x0C00},//SENSOR_GAIN_REG2 + {0x5912,0x0F00},//SENSOR_GAIN_REG2 + {0x5912,0x1000},//SENSOR_GAIN_REG2 + {0x5912,0x10F0},//SENSOR_GAIN_REG2 + {0x5912,0x0075},//SENSOR_GAIN_REG2 + {0x5912,0x0076},//SENSOR_GAIN_REG2 + {0x5912,0x0077},//SENSOR_GAIN_REG2 + {0x5914,0x4006},//SENSOR_GAIN_TABLE_SEL + {0x5900,0x0020},//SENSOR_GAIN + {0x5902,0x0000},//SENSOR_GAIN_T2 + {0x3110,0x0001},//HDR_CONTROL0 + + {REG_NULL, 0x00}, +}; +static const struct regval ar0822_hdr12bit_3840x2160_30fps_regs[] = { + {REG_DELAY, 2000}, + {0x3030,0x0092},//PLL_MULTIPLIER + {0x302E,0x0002},//PRE_PLL_CLK_DIV + {0x302C,0x0002},//VT_SYS_CLK_DIV + {0x302A,0x0006},//VT_PIX_CLK_DIV + {0x3038,0x0002},//OP_SYS_CLK_DIV + {0x3036,0x0006},//OP_WORD_CLK_DIV + {0x31B0,0x00BF},//FRAME_PREAMBLE + {0x31B2,0x007D},//LINE_PREAMBLE + {0x31B4,0x834E},//MIPI_TIMING_0 + {0x31B6,0x8491},//MIPI_TIMING_1 + {0x31B8,0xD0CF},//MIPI_TIMING_2 + {0x31BA,0x0515},//MIPI_TIMING_3 + {0x31BC,0x1911},//MIPI_TIMING_4 + {0x3342,0x122C},//MIPI_F1_PDT_EDT + {0x2510,0x0720},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0x2122},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0x26FF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x0F8C},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0x8055},//SEQ_DATA_PORT + {0x2510,0xA0E1},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3088},//SEQ_DATA_PORT + {0x2510,0x3282},//SEQ_DATA_PORT + {0x2510,0xA681},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FE},//SEQ_DATA_PORT + {0x2510,0x9070},//SEQ_DATA_PORT + {0x2510,0x891D},//SEQ_DATA_PORT + {0x2510,0x867F},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FC},//SEQ_DATA_PORT + {0x2510,0x893F},//SEQ_DATA_PORT + {0x2510,0x0F92},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0x0F8F},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0x9770},//SEQ_DATA_PORT + {0x2510,0x20FC},//SEQ_DATA_PORT + {0x2510,0x8054},//SEQ_DATA_PORT + {0x2510,0x896C},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x9030},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x8040},//SEQ_DATA_PORT + {0x2510,0x8948},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x1597},//SEQ_DATA_PORT + {0x2510,0x8808},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x1F96},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0xA0C0},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x3044},//SEQ_DATA_PORT + {0x2510,0x3088},//SEQ_DATA_PORT + {0x2510,0x3282},//SEQ_DATA_PORT + {0x2510,0x2004},//SEQ_DATA_PORT + {0x2510,0x1FAA},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x3108},//SEQ_DATA_PORT + {0x2510,0x2400},//SEQ_DATA_PORT + {0x2510,0x3244},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x3108},//SEQ_DATA_PORT + {0x2510,0x2400},//SEQ_DATA_PORT + {0x2510,0x2702},//SEQ_DATA_PORT + {0x2510,0x3242},//SEQ_DATA_PORT + {0x2510,0x3108},//SEQ_DATA_PORT + {0x2510,0x2420},//SEQ_DATA_PORT + {0x2510,0x2703},//SEQ_DATA_PORT + {0x2510,0x3242},//SEQ_DATA_PORT + {0x2510,0x3108},//SEQ_DATA_PORT + {0x2510,0x2420},//SEQ_DATA_PORT + {0x2510,0x2704},//SEQ_DATA_PORT + {0x2510,0x3244},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x8801},//SEQ_DATA_PORT + {0x2510,0x010F},//SEQ_DATA_PORT + {0x2510,0x8855},//SEQ_DATA_PORT + {0x2510,0x3101},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3102},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3181},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3188},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3282},//SEQ_DATA_PORT + {0x2510,0x3104},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0xB0E4},//SEQ_DATA_PORT + {0x2510,0xAD92},//SEQ_DATA_PORT + {0x2510,0xBC0C},//SEQ_DATA_PORT + {0x2510,0x1028},//SEQ_DATA_PORT + {0x2510,0x0022},//SEQ_DATA_PORT + {0x2510,0xC020},//SEQ_DATA_PORT + {0x2510,0x003E},//SEQ_DATA_PORT + {0x2510,0x0045},//SEQ_DATA_PORT + {0x2510,0x00B0},//SEQ_DATA_PORT + {0x2510,0x0028},//SEQ_DATA_PORT + {0x2510,0x30C1},//SEQ_DATA_PORT + {0x2510,0x8015},//SEQ_DATA_PORT + {0x2510,0xA038},//SEQ_DATA_PORT + {0x2510,0x100F},//SEQ_DATA_PORT + {0x2510,0x0507},//SEQ_DATA_PORT + {0x2510,0xA220},//SEQ_DATA_PORT + {0x2510,0x0010},//SEQ_DATA_PORT + {0x2510,0x10C2},//SEQ_DATA_PORT + {0x2510,0xB760},//SEQ_DATA_PORT + {0x2510,0x0033},//SEQ_DATA_PORT + {0x2510,0x1082},//SEQ_DATA_PORT + {0x2510,0x100B},//SEQ_DATA_PORT + {0x2510,0x1029},//SEQ_DATA_PORT + {0x2510,0xA85A},//SEQ_DATA_PORT + {0x2510,0x998D},//SEQ_DATA_PORT + {0x2510,0xC810},//SEQ_DATA_PORT + {0x2510,0x2004},//SEQ_DATA_PORT + {0x2510,0x0CCE},//SEQ_DATA_PORT + {0x2510,0x113B},//SEQ_DATA_PORT + {0x2510,0x1055},//SEQ_DATA_PORT + {0x2510,0x101D},//SEQ_DATA_PORT + {0x2510,0xC000},//SEQ_DATA_PORT + {0x2510,0x052F},//SEQ_DATA_PORT + {0x2510,0x162F},//SEQ_DATA_PORT + {0x2510,0x9000},//SEQ_DATA_PORT + {0x2510,0x2034},//SEQ_DATA_PORT + {0x2510,0x0015},//SEQ_DATA_PORT + {0x2510,0x04CB},//SEQ_DATA_PORT + {0x2510,0x1022},//SEQ_DATA_PORT + {0x2510,0x1031},//SEQ_DATA_PORT + {0x2510,0x002D},//SEQ_DATA_PORT + {0x2510,0x1015},//SEQ_DATA_PORT + {0x2510,0x80B9},//SEQ_DATA_PORT + {0x2510,0xA301},//SEQ_DATA_PORT + {0x2510,0x008E},//SEQ_DATA_PORT + {0x2510,0x124B},//SEQ_DATA_PORT + {0x2510,0x01B5},//SEQ_DATA_PORT + {0x2510,0x0B92},//SEQ_DATA_PORT + {0x2510,0xA400},//SEQ_DATA_PORT + {0x2510,0x8091},//SEQ_DATA_PORT + {0x2510,0x0028},//SEQ_DATA_PORT + {0x2510,0x3002},//SEQ_DATA_PORT + {0x2510,0x2004},//SEQ_DATA_PORT + {0x2510,0x1012},//SEQ_DATA_PORT + {0x2510,0x100E},//SEQ_DATA_PORT + {0x2510,0x10A8},//SEQ_DATA_PORT + {0x2510,0x00A1},//SEQ_DATA_PORT + {0x2510,0x132D},//SEQ_DATA_PORT + {0x2510,0x09AF},//SEQ_DATA_PORT + {0x2510,0x03D9},//SEQ_DATA_PORT + {0x2510,0x1259},//SEQ_DATA_PORT + {0x2510,0x11AF},//SEQ_DATA_PORT + {0x2510,0x18B5},//SEQ_DATA_PORT + {0x2510,0x0395},//SEQ_DATA_PORT + {0x2510,0x05CB},//SEQ_DATA_PORT + {0x2510,0x1021},//SEQ_DATA_PORT + {0x2510,0x1015},//SEQ_DATA_PORT + {0x2510,0x1030},//SEQ_DATA_PORT + {0x2510,0x004F},//SEQ_DATA_PORT + {0x2510,0x001C},//SEQ_DATA_PORT + {0x2510,0xB146},//SEQ_DATA_PORT + {0x2510,0xC090},//SEQ_DATA_PORT + {0x2510,0x0020},//SEQ_DATA_PORT + {0x2510,0x103C},//SEQ_DATA_PORT + {0x2510,0xA882},//SEQ_DATA_PORT + {0x2510,0x8055},//SEQ_DATA_PORT + {0x2510,0x00A9},//SEQ_DATA_PORT + {0x2510,0x8801},//SEQ_DATA_PORT + {0x2510,0xB700},//SEQ_DATA_PORT + {0x2510,0x0001},//SEQ_DATA_PORT + {0x2510,0x00A2},//SEQ_DATA_PORT + {0x2510,0x11AE},//SEQ_DATA_PORT + {0x2510,0x000A},//SEQ_DATA_PORT + {0x2510,0x98BB},//SEQ_DATA_PORT + {0x2510,0x2047},//SEQ_DATA_PORT + {0x2510,0x0036},//SEQ_DATA_PORT + {0x2510,0x1001},//SEQ_DATA_PORT + {0x2510,0x9FBE},//SEQ_DATA_PORT + {0x2510,0x108A},//SEQ_DATA_PORT + {0x2510,0x1022},//SEQ_DATA_PORT + {0x2510,0x0039},//SEQ_DATA_PORT + {0x2510,0x01C0},//SEQ_DATA_PORT + {0x2510,0x109F},//SEQ_DATA_PORT + {0x2510,0x1023},//SEQ_DATA_PORT + {0x2510,0x052E},//SEQ_DATA_PORT + {0x2510,0x002A},//SEQ_DATA_PORT + {0x2510,0x3081},//SEQ_DATA_PORT + {0x2510,0x2001},//SEQ_DATA_PORT + {0x2510,0x3044},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x112A},//SEQ_DATA_PORT + {0x2510,0x101D},//SEQ_DATA_PORT + {0x2510,0x2020},//SEQ_DATA_PORT + {0x2510,0x02B8},//SEQ_DATA_PORT + {0x2510,0x10B8},//SEQ_DATA_PORT + {0x2510,0x1136},//SEQ_DATA_PORT + {0x2510,0x9B6B},//SEQ_DATA_PORT + {0x2510,0x1039},//SEQ_DATA_PORT + {0x2510,0x1040},//SEQ_DATA_PORT + {0x2510,0xAB80},//SEQ_DATA_PORT + {0x2510,0x03C4},//SEQ_DATA_PORT + {0x2510,0x10C4},//SEQ_DATA_PORT + {0x2510,0x1023},//SEQ_DATA_PORT + {0x2510,0x1245},//SEQ_DATA_PORT + {0x2510,0x009F},//SEQ_DATA_PORT + {0x2510,0x002B},//SEQ_DATA_PORT + {0x2510,0x30D0},//SEQ_DATA_PORT + {0x2510,0x3141},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3142},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3110},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3120},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3144},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3148},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3182},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3184},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3190},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x31A0},//SEQ_DATA_PORT + {0x2510,0x3088},//SEQ_DATA_PORT + {0x2510,0x2201},//SEQ_DATA_PORT + {0x2510,0x807D},//SEQ_DATA_PORT + {0x2510,0x2206},//SEQ_DATA_PORT + {0x2510,0x8815},//SEQ_DATA_PORT + {0x2510,0x8877},//SEQ_DATA_PORT + {0x2510,0x0092},//SEQ_DATA_PORT + {0x2510,0x220E},//SEQ_DATA_PORT + {0x2510,0x2211},//SEQ_DATA_PORT + {0x2510,0x8055},//SEQ_DATA_PORT + {0x2510,0x3001},//SEQ_DATA_PORT + {0x2510,0x2004},//SEQ_DATA_PORT + {0x2510,0x8C61},//SEQ_DATA_PORT + {0x2510,0x8801},//SEQ_DATA_PORT + {0x2510,0x1012},//SEQ_DATA_PORT + {0x2510,0x1D1F},//SEQ_DATA_PORT + {0x2510,0x0D9F},//SEQ_DATA_PORT + {0x2510,0x101F},//SEQ_DATA_PORT + {0x2510,0x0036},//SEQ_DATA_PORT + {0x2510,0x0040},//SEQ_DATA_PORT + {0x2510,0x0023},//SEQ_DATA_PORT + {0x2510,0x996E},//SEQ_DATA_PORT + {0x2510,0x0257},//SEQ_DATA_PORT + {0x2510,0x1035},//SEQ_DATA_PORT + {0x2510,0x9926},//SEQ_DATA_PORT + {0x2510,0x0039},//SEQ_DATA_PORT + {0x2510,0x00AE},//SEQ_DATA_PORT + {0x2510,0x11A3},//SEQ_DATA_PORT + {0x2510,0x0048},//SEQ_DATA_PORT + {0x2510,0xC878},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x1548},//SEQ_DATA_PORT + {0x2510,0x0C49},//SEQ_DATA_PORT + {0x2510,0x1149},//SEQ_DATA_PORT + {0x2510,0x002A},//SEQ_DATA_PORT + {0x2510,0x1057},//SEQ_DATA_PORT + {0x2510,0x3281},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3044},//SEQ_DATA_PORT + {0x2510,0x2001},//SEQ_DATA_PORT + {0x2510,0xA020},//SEQ_DATA_PORT + {0x2510,0x000C},//SEQ_DATA_PORT + {0x2510,0x9825},//SEQ_DATA_PORT + {0x2510,0x1040},//SEQ_DATA_PORT + {0x2510,0x1054},//SEQ_DATA_PORT + {0x2510,0xB06D},//SEQ_DATA_PORT + {0x2510,0x0035},//SEQ_DATA_PORT + {0x2510,0x004D},//SEQ_DATA_PORT + {0x2510,0x1020},//SEQ_DATA_PORT + {0x2510,0xB064},//SEQ_DATA_PORT + {0x2510,0x99C5},//SEQ_DATA_PORT + {0x2510,0x0047},//SEQ_DATA_PORT + {0x2510,0xB920},//SEQ_DATA_PORT + {0x2510,0x1447},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x31F8,0x0008},//MIPI_CONFIG_2 + {0x3C70,0x6828},//CALIB_ROWS + {0x3092,0x0826},//ROW_NOISE_CONTROL + {0x3428,0x0209},//SEQUENCER_CONTROL + {0x3516,0xFF04},//DAC_LD_22_23 + {0x3526,0x6480},//DAC_LD_38_39 + {0x3504,0x8AAA},//DAC_LD_4_5 + {0x353C,0x220C},//DAC_LD_60_61 + {0x3536,0x4C6E},//DAC_LD_54_55 + {0x3D2A,0x0FFF},//T1_END_DEC_TH + {0x3364,0x00EC},//DCG_TRIM + {0x3512,0x8888},//DAC_LD_18_19 + {0x3514,0x888F},//DAC_LD_20_21 + {0x3520,0xFBF0},//DAC_LD_32_33 + {0x3524,0xB2A1},//DAC_LD_36_37 + {0x3528,0xCC84},//DAC_LD_40_41 + {0x3532,0x4C8E},//DAC_LD_50_51 + {0x3534,0x4E64},//DAC_LD_52_53 + {0x351E,0x5856},//DAC_LD_30_31 + {0x353E,0x98F2},//DAC_LD_62_63 + {0x352E,0x6A8A},//DAC_LD_46_47 + {0x3370,0x0211},//DBLC_CONTROL + {0x3372,0x700F},//DBLC_FS0_CONTROL + {0x3540,0x3597},//DAC_LD_64_65 + {0x58E2,0x0BE3},//COL_COUNT_VALUES1 + {0x58E4,0x18B4},//COL_COUNT_VALUES2 + {0x3522,0x7C97},//DAC_LD_34_35 + {0x30BA,0x0024},//DIGITAL_CTRL + {0x31D4,0x0042},//CLK_MEM_GATING_CTRL + {0x352A,0x6F8F},//DAC_LD_42_43 + {0x3530,0x4A08},//DAC_LD_48_49 + {0x351A,0x5FFF},//DAC_LD_26_27 + {0x350E,0x39D9},//DAC_LD_14_15 + {0x3510,0x9988},//DAC_LD_16_17 + {0x3380,0x1FFF},//DBLC_OFFSET1 + {0x337A,0x1000},//DBLC_SCALE1 + {0x3092,0x0800},//ROW_NOISE_CONTROL + {0x350A,0x0654},//DAC_LD_10_11 + {0x3364,0x00E0},//DCG_TRIM + {0x591E,0x61AE},//ANALOG_GAIN_WR_DATA + {0x591E,0x722C},//ANALOG_GAIN_WR_DATA + {0x591E,0x82B8},//ANALOG_GAIN_WR_DATA + {0x591E,0x92F6},//ANALOG_GAIN_WR_DATA + {0x591E,0xA447},//ANALOG_GAIN_WR_DATA + {0x591E,0xB66D},//ANALOG_GAIN_WR_DATA + {0x591E,0xC6EA},//ANALOG_GAIN_WR_DATA + {0x591E,0xDECD},//ANALOG_GAIN_WR_DATA + {0x3532,0x4C8A},//DAC_LD_50_51 + {0x3534,0x4E60},//DAC_LD_52_53 + {0x353E,0x90F2},//DAC_LD_62_63 + {0x351A,0x4FFF},//DAC_LD_26_27 + {0x591C,0x00D7},//DGR_AMP_GAIN + {0x5002,0x37C3},//T1_PIX_DEF_ID2 + {0x51CC,0x0149},//T1_NOISE_GAIN_THRESHOLD0 + {0x51D8,0x044D},//T1_NOISE_GAIN_THRESHOLD1 + {0x51CE,0x0700},//T1_NOISE_GAIN_THRESHOLD2 + {0x51D0,0x0001},//T1_NOISE_FLOOR0 + {0x51D2,0x0002},//T1_NOISE_FLOOR1 + {0x51D4,0x0003},//T1_NOISE_FLOOR2 + {0x51D6,0x0004},//T1_NOISE_FLOOR3 + {0x5202,0x37C3},//T2_PIX_DEF_ID2 + {0x51EA,0x0149},//T2_NOISE_GAIN_THRESHOLD0 + {0x51FC,0x044D},//T2_NOISE_GAIN_THRESHOLD1 + {0x51EC,0x0700},//T2_NOISE_GAIN_THRESHOLD2 + {0x51EE,0x0001},//T2_NOISE_FLOOR0 + {0x51F0,0x0002},//T2_NOISE_FLOOR1 + {0x51F2,0x0003},//T2_NOISE_FLOOR2 + {0x51F4,0x0004},//T2_NOISE_FLOOR3 + {0x5402,0x37C3},//T4_PIX_DEF_ID2 + {0x5560,0x0149},//T4_NOISE_GAIN_THRESHOLD0 + {0x556C,0x044D},//T4_NOISE_GAIN_THRESHOLD1 + {0x5562,0x0700},//T4_NOISE_GAIN_THRESHOLD2 + {0x5564,0x0001},//T4_NOISE_FLOOR0 + {0x5566,0x0002},//T4_NOISE_FLOOR1 + {0x5568,0x0003},//T4_NOISE_FLOOR2 + {0x556A,0x0004},//T4_NOISE_FLOOR3 + {0x31E0,0x0001},//PIX_DEF_ID + {0x5000,0x0080},//T1_PIX_DEF_ID + {0x5000,0x0180},//T1_PIX_DEF_ID + {0x5000,0x0180},//T1_PIX_DEF_ID + {0x5200,0x0080},//T2_PIX_DEF_ID + {0x5200,0x0180},//T2_PIX_DEF_ID + {0x5200,0x0180},//T2_PIX_DEF_ID + {0x5400,0x0080},//T4_PIX_DEF_ID + {0x5400,0x0180},//T4_PIX_DEF_ID + {0x5400,0x0180},//T4_PIX_DEF_ID + {0x5000,0x0180},//T1_PIX_DEF_ID + {0x5200,0x0180},//T2_PIX_DEF_ID + {0x5400,0x0180},//T4_PIX_DEF_ID + {0x50A2,0x3F2A},//BMT0 + {0x50A4,0x875A},//BMT1 + {0x50A6,0x030F},//SINGLEK_FACTOR0 + {0x50A6,0x0F0F},//SINGLEK_FACTOR0 + {0x50A8,0x030F},//SINGLEK_FACTOR1 + {0x50A8,0x0F0F},//SINGLEK_FACTOR1 + {0x50AA,0x030F},//SINGLEK_FACTOR2 + {0x50AA,0x050F},//SINGLEK_FACTOR2 + {0x50AC,0x0301},//CROSS_FACTOR0 + {0x50AC,0x0101},//CROSS_FACTOR0 + {0x50AE,0x0301},//CROSS_FACTOR1 + {0x50AE,0x0101},//CROSS_FACTOR1 + {0x50B0,0x0301},//CROSS_FACTOR2 + {0x50B0,0x0101},//CROSS_FACTOR2 + {0x50B2,0x03FF},//SINGLE_MAX_FACTOR + {0x50B4,0x030F},//COUPLE_FACTOR0 + {0x50B4,0x0F0F},//COUPLE_FACTOR0 + {0x50B6,0x030F},//COUPLE_FACTOR1 + {0x50B6,0x0F0F},//COUPLE_FACTOR1 + {0x50B8,0x030F},//COUPLE_FACTOR2 + {0x50B8,0x050F},//COUPLE_FACTOR2 + {0x3D2A,0x0FFF},//T1_END_DEC_TH + {0x3D34,0x9C40},//T2_STR_DEC_TH + {0x3D36,0xFFFF},//T2_END_DEC_TH + {0x3D02,0x5033},//MEC_CTRL2 + {0x3D00,0x600F},//MEC_CTRL1 + {0x3086,0x1A28},//PARK_ROW_ADDR + {0x33E4,0x0040},//VERT_SHADING_CONTROL + {0x3C70,0x6222},//CALIB_ROWS + {0x3110,0x0011},//HDR_CONTROL0 + {0x30B0,0x0820},//DIGITAL_TEST + {0x3280,0x0ED8},//T1_BARRIER_C0 + {0x3282,0x0ED8},//T1_BARRIER_C1 + {0x3284,0x0ED8},//T1_BARRIER_C2 + {0x3286,0x0ED8},//T1_BARRIER_C3 + {0x3288,0x0ED8},//T2_BARRIER_C0 + {0x328A,0x0ED8},//T2_BARRIER_C1 + {0x328C,0x0ED8},//T2_BARRIER_C2 + {0x328E,0x0ED8},//T2_BARRIER_C3 + {0x3290,0x0ED8},//T3_BARRIER_C0 + {0x3292,0x0ED8},//T3_BARRIER_C1 + {0x3294,0x0ED8},//T3_BARRIER_C2 + {0x3296,0x0ED8},//T3_BARRIER_C3 + {0x3100,0xC001},//DLO_CONTROL0 + {0x3102,0xBED8},//DLO_CONTROL1 + {0x3104,0xBED8},//DLO_CONTROL2 + {0x3106,0xBED8},//DLO_CONTROL3 + {0x3108,0x07D0},//DLO_CONTROL4 + {0x3116,0x4001},//HDR_CONTROL3 + {0x3124,0x006D},//HDR_MD_CONTROL0 + {0x3126,0x003C},//HDR_MD_CONTROL1 + {0x31AE,0x0204},//SERIAL_FORMAT + {0x31AC,0x0C0C},//DATA_FORMAT_BITS + {0x3082,0x0014},//OPERATION_MODE_CTRL + {0x30BA,0x0135},//DIGITAL_CTRL + {0x3238,0x0044},//EXPOSURE_RATIO + {0x3012,0x0700},//COARSE_INTEGRATION_TIME_ + {0x3212,0x0070},//COARSE_INTEGRATION_TIME2 + {0x300C,0x10CC},//LINE_LENGTH_PCK_ + {0x300A,0x09F3},//FRAME_LENGTH_LINES_ + {0x5914,0x4002},//SENSOR_GAIN_TABLE_SEL + {0x5910,0x608A},//SENSOR_GAIN_REG1 + {0x5910,0x7091},//SENSOR_GAIN_REG1 + {0x5910,0x689C},//SENSOR_GAIN_REG1 + {0x5910,0x8885},//SENSOR_GAIN_REG1 + {0x5910,0x98AD},//SENSOR_GAIN_REG1 + {0x5910,0xA8A9},//SENSOR_GAIN_REG1 + {0x5910,0xC894},//SENSOR_GAIN_REG1 + {0x5910,0xC8D1},//SENSOR_GAIN_REG1 + {0x5910,0xD88A},//SENSOR_GAIN_REG1 + {0x5910,0xD8C3},//SENSOR_GAIN_REG1 + {0x5910,0xD915},//SENSOR_GAIN_REG1 + {0x5910,0xD988},//SENSOR_GAIN_REG1 + {0x5910,0xDA2A},//SENSOR_GAIN_REG1 + {0x5910,0xDB0E},//SENSOR_GAIN_REG1 + {0x5910,0xDC53},//SENSOR_GAIN_REG1 + {0x5910,0x608A},//SENSOR_GAIN_REG1 + {0x5910,0xC919},//SENSOR_GAIN_REG1 + {0x5910,0xCA00},//SENSOR_GAIN_REG1 + {0x5910,0x0000},//SENSOR_GAIN_REG1 + {0x5910,0x0000},//SENSOR_GAIN_REG1 + {0x5910,0x0000},//SENSOR_GAIN_REG1 + {0x5910,0x0001},//SENSOR_GAIN_REG1 + {0x5910,0x0001},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0002},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x5A8B},//SENSOR_GAIN_REG1 + {0x5910,0xFF04},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xFF04},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0x0005},//SENSOR_GAIN_REG1 + {0x5910,0x0006},//SENSOR_GAIN_REG1 + {0x5910,0x0007},//SENSOR_GAIN_REG1 + {0x5910,0x9A8B},//SENSOR_GAIN_REG1 + {0x5910,0xFF04},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0x0015},//SENSOR_GAIN_REG1 + {0x5910,0x0016},//SENSOR_GAIN_REG1 + {0x5910,0x0017},//SENSOR_GAIN_REG1 + {0x5910,0xDA8B},//SENSOR_GAIN_REG1 + {0x5910,0xFF04},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0x0025},//SENSOR_GAIN_REG1 + {0x5910,0x0026},//SENSOR_GAIN_REG1 + {0x5910,0x0027},//SENSOR_GAIN_REG1 + {0x5910,0x59B9},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x0035},//SENSOR_GAIN_REG1 + {0x5910,0x0036},//SENSOR_GAIN_REG1 + {0x5910,0x0037},//SENSOR_GAIN_REG1 + {0x5910,0x99B9},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x0045},//SENSOR_GAIN_REG1 + {0x5910,0x0046},//SENSOR_GAIN_REG1 + {0x5910,0x0047},//SENSOR_GAIN_REG1 + {0x5910,0xD9B9},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x0055},//SENSOR_GAIN_REG1 + {0x5910,0x0056},//SENSOR_GAIN_REG1 + {0x5910,0x0057},//SENSOR_GAIN_REG1 + {0x5910,0x9A85},//SENSOR_GAIN_REG1 + {0x5910,0x0654},//SENSOR_GAIN_REG1 + {0x5910,0x0654},//SENSOR_GAIN_REG1 + {0x5910,0x0684},//SENSOR_GAIN_REG1 + {0x5910,0x0654},//SENSOR_GAIN_REG1 + {0x5910,0x0654},//SENSOR_GAIN_REG1 + {0x5910,0x0065},//SENSOR_GAIN_REG1 + {0x5910,0x0066},//SENSOR_GAIN_REG1 + {0x5910,0x0067},//SENSOR_GAIN_REG1 + {0x5910,0x59BD},//SENSOR_GAIN_REG1 + {0x5910,0x1000},//SENSOR_GAIN_REG1 + {0x5910,0x0C00},//SENSOR_GAIN_REG1 + {0x5910,0x0F00},//SENSOR_GAIN_REG1 + {0x5910,0x1000},//SENSOR_GAIN_REG1 + {0x5910,0x10F0},//SENSOR_GAIN_REG1 + {0x5910,0x0075},//SENSOR_GAIN_REG1 + {0x5910,0x0076},//SENSOR_GAIN_REG1 + {0x5910,0x0077},//SENSOR_GAIN_REG1 + {0x5912,0x608A},//SENSOR_GAIN_REG2 + {0x5912,0x7091},//SENSOR_GAIN_REG2 + {0x5912,0x689C},//SENSOR_GAIN_REG2 + {0x5912,0x8885},//SENSOR_GAIN_REG2 + {0x5912,0x98AD},//SENSOR_GAIN_REG2 + {0x5912,0xA8A9},//SENSOR_GAIN_REG2 + {0x5912,0xC894},//SENSOR_GAIN_REG2 + {0x5912,0xC8D1},//SENSOR_GAIN_REG2 + {0x5912,0xC927},//SENSOR_GAIN_REG2 + {0x5912,0xC9A0},//SENSOR_GAIN_REG2 + {0x5912,0xCA4C},//SENSOR_GAIN_REG2 + {0x5912,0xCB3F},//SENSOR_GAIN_REG2 + {0x5912,0xCC97},//SENSOR_GAIN_REG2 + {0x5912,0xCE7C},//SENSOR_GAIN_REG2 + {0x5912,0xCFFF},//SENSOR_GAIN_REG2 + {0x5912,0x608A},//SENSOR_GAIN_REG2 + {0x5912,0xC919},//SENSOR_GAIN_REG2 + {0x5912,0xCA00},//SENSOR_GAIN_REG2 + {0x5912,0x0000},//SENSOR_GAIN_REG2 + {0x5912,0x0000},//SENSOR_GAIN_REG2 + {0x5912,0x0000},//SENSOR_GAIN_REG2 + {0x5912,0x0001},//SENSOR_GAIN_REG2 + {0x5912,0x0001},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0002},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x5A8B},//SENSOR_GAIN_REG2 + {0x5912,0xFF04},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xFF04},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0x0005},//SENSOR_GAIN_REG2 + {0x5912,0x0006},//SENSOR_GAIN_REG2 + {0x5912,0x0007},//SENSOR_GAIN_REG2 + {0x5912,0x9A8B},//SENSOR_GAIN_REG2 + {0x5912,0xFF04},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0x0015},//SENSOR_GAIN_REG2 + {0x5912,0x0016},//SENSOR_GAIN_REG2 + {0x5912,0x0017},//SENSOR_GAIN_REG2 + {0x5912,0xDA8B},//SENSOR_GAIN_REG2 + {0x5912,0xFF04},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0x0025},//SENSOR_GAIN_REG2 + {0x5912,0x0026},//SENSOR_GAIN_REG2 + {0x5912,0x0027},//SENSOR_GAIN_REG2 + {0x5912,0x59B9},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x0035},//SENSOR_GAIN_REG2 + {0x5912,0x0036},//SENSOR_GAIN_REG2 + {0x5912,0x0037},//SENSOR_GAIN_REG2 + {0x5912,0x99B9},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x0045},//SENSOR_GAIN_REG2 + {0x5912,0x0046},//SENSOR_GAIN_REG2 + {0x5912,0x0047},//SENSOR_GAIN_REG2 + {0x5912,0xD9B9},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x0055},//SENSOR_GAIN_REG2 + {0x5912,0x0056},//SENSOR_GAIN_REG2 + {0x5912,0x0057},//SENSOR_GAIN_REG2 + {0x5912,0x9A85},//SENSOR_GAIN_REG2 + {0x5912,0x0654},//SENSOR_GAIN_REG2 + {0x5912,0x0654},//SENSOR_GAIN_REG2 + {0x5912,0x0684},//SENSOR_GAIN_REG2 + {0x5912,0x0654},//SENSOR_GAIN_REG2 + {0x5912,0x0654},//SENSOR_GAIN_REG2 + {0x5912,0x0065},//SENSOR_GAIN_REG2 + {0x5912,0x0066},//SENSOR_GAIN_REG2 + {0x5912,0x0067},//SENSOR_GAIN_REG2 + {0x5912,0x59BD},//SENSOR_GAIN_REG2 + {0x5912,0x1000},//SENSOR_GAIN_REG2 + {0x5912,0x0C00},//SENSOR_GAIN_REG2 + {0x5912,0x0F00},//SENSOR_GAIN_REG2 + {0x5912,0x1000},//SENSOR_GAIN_REG2 + {0x5912,0x10F0},//SENSOR_GAIN_REG2 + {0x5912,0x0075},//SENSOR_GAIN_REG2 + {0x5912,0x0076},//SENSOR_GAIN_REG2 + {0x5912,0x0077},//SENSOR_GAIN_REG2 + {0x5914,0x4006},//SENSOR_GAIN_TABLE_SEL + {0x5900,0x0020},//SENSOR_GAIN + {0x5902,0x0000},//SENSOR_GAIN_T2 + {0x3110,0x0001},//HDR_CONTROL0 + + {REG_NULL, 0x00}, +}; + +static const struct regval ar0822_linear_60fps_regs[] = { + {REG_DELAY, 2000}, + {0x3030,0x0092},//PLL_MULTIPLIER + {0x302E,0x0002},//PRE_PLL_CLK_DIV + {0x302C,0x0002},//VT_SYS_CLK_DIV + {0x302A,0x0006},//VT_PIX_CLK_DIV + {0x3038,0x0002},//OP_SYS_CLK_DIV + {0x3036,0x0006},//OP_WORD_CLK_DIV + {0x31B0,0x00BF},//FRAME_PREAMBLE + {0x31B2,0x007D},//LINE_PREAMBLE + {0x31B4,0x834E},//MIPI_TIMING_0 + {0x31B6,0x8491},//MIPI_TIMING_1 + {0x31B8,0xD0CF},//MIPI_TIMING_2 + {0x31BA,0x0515},//MIPI_TIMING_3 + {0x31BC,0x1911},//MIPI_TIMING_4 + {0x3342,0x122C},//MIPI_F1_PDT_EDT + {0x31BC,0x5911},//MIPI_TIMING_4 + {0x31DE,0x0004},//MIPI_HISPI_TRIM + {0x31C6,0xC000},//HISPI_CONTROL + {0x31C8,0x0B28},//MIPI_DESKEW_PAT_WIDTH + {0x2512,0xA000},//SEQ_CTRL_PORT + {0x2510,0x0720},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0x2122},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0x26FF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0xFFFF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x0F8C},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0x8055},//SEQ_DATA_PORT + {0x2510,0xA0E1},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3088},//SEQ_DATA_PORT + {0x2510,0x3282},//SEQ_DATA_PORT + {0x2510,0xA681},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FE},//SEQ_DATA_PORT + {0x2510,0x9070},//SEQ_DATA_PORT + {0x2510,0x891D},//SEQ_DATA_PORT + {0x2510,0x867F},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FC},//SEQ_DATA_PORT + {0x2510,0x893F},//SEQ_DATA_PORT + {0x2510,0x0F92},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0x0F8F},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0x9770},//SEQ_DATA_PORT + {0x2510,0x20FC},//SEQ_DATA_PORT + {0x2510,0x8054},//SEQ_DATA_PORT + {0x2510,0x896C},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x9030},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x8040},//SEQ_DATA_PORT + {0x2510,0x8948},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x1597},//SEQ_DATA_PORT + {0x2510,0x8808},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x1F96},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0xA0C0},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x3044},//SEQ_DATA_PORT + {0x2510,0x3088},//SEQ_DATA_PORT + {0x2510,0x3282},//SEQ_DATA_PORT + {0x2510,0x2004},//SEQ_DATA_PORT + {0x2510,0x1FAA},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x20E0},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x20FF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x3108},//SEQ_DATA_PORT + {0x2510,0x2400},//SEQ_DATA_PORT + {0x2510,0x3244},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x3108},//SEQ_DATA_PORT + {0x2510,0x2400},//SEQ_DATA_PORT + {0x2510,0x2702},//SEQ_DATA_PORT + {0x2510,0x3242},//SEQ_DATA_PORT + {0x2510,0x3108},//SEQ_DATA_PORT + {0x2510,0x2420},//SEQ_DATA_PORT + {0x2510,0x2703},//SEQ_DATA_PORT + {0x2510,0x3242},//SEQ_DATA_PORT + {0x2510,0x3108},//SEQ_DATA_PORT + {0x2510,0x2420},//SEQ_DATA_PORT + {0x2510,0x2704},//SEQ_DATA_PORT + {0x2510,0x3244},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x8801},//SEQ_DATA_PORT + {0x2510,0x000F},//SEQ_DATA_PORT + {0x2510,0x109C},//SEQ_DATA_PORT + {0x2510,0x8855},//SEQ_DATA_PORT + {0x2510,0x3101},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3102},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3181},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3188},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3282},//SEQ_DATA_PORT + {0x2510,0x3104},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0xB0E4},//SEQ_DATA_PORT + {0x2510,0xAD92},//SEQ_DATA_PORT + {0x2510,0xBC0C},//SEQ_DATA_PORT + {0x2510,0x1028},//SEQ_DATA_PORT + {0x2510,0x0022},//SEQ_DATA_PORT + {0x2510,0xC020},//SEQ_DATA_PORT + {0x2510,0x003E},//SEQ_DATA_PORT + {0x2510,0x0045},//SEQ_DATA_PORT + {0x2510,0x00B0},//SEQ_DATA_PORT + {0x2510,0x0028},//SEQ_DATA_PORT + {0x2510,0x30C1},//SEQ_DATA_PORT + {0x2510,0x8015},//SEQ_DATA_PORT + {0x2510,0xA038},//SEQ_DATA_PORT + {0x2510,0x100F},//SEQ_DATA_PORT + {0x2510,0x0507},//SEQ_DATA_PORT + {0x2510,0xA220},//SEQ_DATA_PORT + {0x2510,0x0010},//SEQ_DATA_PORT + {0x2510,0x10C2},//SEQ_DATA_PORT + {0x2510,0xB760},//SEQ_DATA_PORT + {0x2510,0x0033},//SEQ_DATA_PORT + {0x2510,0x1082},//SEQ_DATA_PORT + {0x2510,0x100B},//SEQ_DATA_PORT + {0x2510,0x1029},//SEQ_DATA_PORT + {0x2510,0xA85A},//SEQ_DATA_PORT + {0x2510,0x998D},//SEQ_DATA_PORT + {0x2510,0xC810},//SEQ_DATA_PORT + {0x2510,0x2004},//SEQ_DATA_PORT + {0x2510,0x0ECE},//SEQ_DATA_PORT + {0x2510,0x123B},//SEQ_DATA_PORT + {0x2510,0xC000},//SEQ_DATA_PORT + {0x2510,0x032F},//SEQ_DATA_PORT + {0x2510,0x11D5},//SEQ_DATA_PORT + {0x2510,0x162F},//SEQ_DATA_PORT + {0x2510,0x9000},//SEQ_DATA_PORT + {0x2510,0x2034},//SEQ_DATA_PORT + {0x2510,0x0015},//SEQ_DATA_PORT + {0x2510,0x04CB},//SEQ_DATA_PORT + {0x2510,0x1022},//SEQ_DATA_PORT + {0x2510,0x1031},//SEQ_DATA_PORT + {0x2510,0x002D},//SEQ_DATA_PORT + {0x2510,0x1015},//SEQ_DATA_PORT + {0x2510,0x80B9},//SEQ_DATA_PORT + {0x2510,0xA101},//SEQ_DATA_PORT + {0x2510,0x001C},//SEQ_DATA_PORT + {0x2510,0x008E},//SEQ_DATA_PORT + {0x2510,0x124B},//SEQ_DATA_PORT + {0x2510,0x01B5},//SEQ_DATA_PORT + {0x2510,0x0B92},//SEQ_DATA_PORT + {0x2510,0xA400},//SEQ_DATA_PORT + {0x2510,0x8091},//SEQ_DATA_PORT + {0x2510,0x0028},//SEQ_DATA_PORT + {0x2510,0x3002},//SEQ_DATA_PORT + {0x2510,0x2004},//SEQ_DATA_PORT + {0x2510,0x1012},//SEQ_DATA_PORT + {0x2510,0x100E},//SEQ_DATA_PORT + {0x2510,0x10A8},//SEQ_DATA_PORT + {0x2510,0x00A1},//SEQ_DATA_PORT + {0x2510,0x132D},//SEQ_DATA_PORT + {0x2510,0x09AF},//SEQ_DATA_PORT + {0x2510,0x0159},//SEQ_DATA_PORT + {0x2510,0x121D},//SEQ_DATA_PORT + {0x2510,0x1259},//SEQ_DATA_PORT + {0x2510,0x11AF},//SEQ_DATA_PORT + {0x2510,0x18B5},//SEQ_DATA_PORT + {0x2510,0x0395},//SEQ_DATA_PORT + {0x2510,0x054B},//SEQ_DATA_PORT + {0x2510,0x1021},//SEQ_DATA_PORT + {0x2510,0x0020},//SEQ_DATA_PORT + {0x2510,0x1015},//SEQ_DATA_PORT + {0x2510,0x1030},//SEQ_DATA_PORT + {0x2510,0x00CF},//SEQ_DATA_PORT + {0x2510,0xB146},//SEQ_DATA_PORT + {0x2510,0xC290},//SEQ_DATA_PORT + {0x2510,0x103C},//SEQ_DATA_PORT + {0x2510,0xA882},//SEQ_DATA_PORT + {0x2510,0x8055},//SEQ_DATA_PORT + {0x2510,0x00A9},//SEQ_DATA_PORT + {0x2510,0x8801},//SEQ_DATA_PORT + {0x2510,0xB700},//SEQ_DATA_PORT + {0x2510,0x0001},//SEQ_DATA_PORT + {0x2510,0x02A2},//SEQ_DATA_PORT + {0x2510,0x000A},//SEQ_DATA_PORT + {0x2510,0x98BB},//SEQ_DATA_PORT + {0x2510,0x203F},//SEQ_DATA_PORT + {0x2510,0x0036},//SEQ_DATA_PORT + {0x2510,0x1001},//SEQ_DATA_PORT + {0x2510,0x99BE},//SEQ_DATA_PORT + {0x2510,0x0139},//SEQ_DATA_PORT + {0x2510,0x100A},//SEQ_DATA_PORT + {0x2510,0x0040},//SEQ_DATA_PORT + {0x2510,0x1022},//SEQ_DATA_PORT + {0x2510,0x124C},//SEQ_DATA_PORT + {0x2510,0x109F},//SEQ_DATA_PORT + {0x2510,0x15A3},//SEQ_DATA_PORT + {0x2510,0x002A},//SEQ_DATA_PORT + {0x2510,0x3081},//SEQ_DATA_PORT + {0x2510,0x2001},//SEQ_DATA_PORT + {0x2510,0x3044},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x112A},//SEQ_DATA_PORT + {0x2510,0x101D},//SEQ_DATA_PORT + {0x2510,0x202B},//SEQ_DATA_PORT + {0x2510,0x02B8},//SEQ_DATA_PORT + {0x2510,0x10B8},//SEQ_DATA_PORT + {0x2510,0x1136},//SEQ_DATA_PORT + {0x2510,0x996B},//SEQ_DATA_PORT + {0x2510,0x004C},//SEQ_DATA_PORT + {0x2510,0x1039},//SEQ_DATA_PORT + {0x2510,0x1040},//SEQ_DATA_PORT + {0x2510,0x00B5},//SEQ_DATA_PORT + {0x2510,0x03C4},//SEQ_DATA_PORT + {0x2510,0x1144},//SEQ_DATA_PORT + {0x2510,0x1245},//SEQ_DATA_PORT + {0x2510,0x9A7B},//SEQ_DATA_PORT + {0x2510,0x002B},//SEQ_DATA_PORT + {0x2510,0x30D0},//SEQ_DATA_PORT + {0x2510,0x3141},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3142},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3110},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3120},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3144},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3148},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3182},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3184},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3190},//SEQ_DATA_PORT + {0x2510,0x3041},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x31A0},//SEQ_DATA_PORT + {0x2510,0x3088},//SEQ_DATA_PORT + {0x2510,0x2201},//SEQ_DATA_PORT + {0x2510,0x807D},//SEQ_DATA_PORT + {0x2510,0x2206},//SEQ_DATA_PORT + {0x2510,0x8815},//SEQ_DATA_PORT + {0x2510,0x8877},//SEQ_DATA_PORT + {0x2510,0x0092},//SEQ_DATA_PORT + {0x2510,0x220E},//SEQ_DATA_PORT + {0x2510,0x2211},//SEQ_DATA_PORT + {0x2510,0x8055},//SEQ_DATA_PORT + {0x2510,0x3001},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x8A61},//SEQ_DATA_PORT + {0x2510,0x8801},//SEQ_DATA_PORT + {0x2510,0x1092},//SEQ_DATA_PORT + {0x2510,0x181F},//SEQ_DATA_PORT + {0x2510,0x0B1F},//SEQ_DATA_PORT + {0x2510,0x101F},//SEQ_DATA_PORT + {0x2510,0x00B6},//SEQ_DATA_PORT + {0x2510,0x0023},//SEQ_DATA_PORT + {0x2510,0x00B9},//SEQ_DATA_PORT + {0x2510,0x104C},//SEQ_DATA_PORT + {0x2510,0x996E},//SEQ_DATA_PORT + {0x2510,0x0140},//SEQ_DATA_PORT + {0x2510,0x0257},//SEQ_DATA_PORT + {0x2510,0x1035},//SEQ_DATA_PORT + {0x2510,0x9F26},//SEQ_DATA_PORT + {0x2510,0x1423},//SEQ_DATA_PORT + {0x2510,0x0048},//SEQ_DATA_PORT + {0x2510,0xC878},//SEQ_DATA_PORT + {0x2510,0x200A},//SEQ_DATA_PORT + {0x2510,0x1548},//SEQ_DATA_PORT + {0x2510,0x0C49},//SEQ_DATA_PORT + {0x2510,0x1149},//SEQ_DATA_PORT + {0x2510,0x002A},//SEQ_DATA_PORT + {0x2510,0x1057},//SEQ_DATA_PORT + {0x2510,0x3281},//SEQ_DATA_PORT + {0x2510,0x2000},//SEQ_DATA_PORT + {0x2510,0x3044},//SEQ_DATA_PORT + {0x2510,0x2001},//SEQ_DATA_PORT + {0x2510,0xA020},//SEQ_DATA_PORT + {0x2510,0x000C},//SEQ_DATA_PORT + {0x2510,0x9825},//SEQ_DATA_PORT + {0x2510,0x1040},//SEQ_DATA_PORT + {0x2510,0x1054},//SEQ_DATA_PORT + {0x2510,0xB06D},//SEQ_DATA_PORT + {0x2510,0x0035},//SEQ_DATA_PORT + {0x2510,0x004D},//SEQ_DATA_PORT + {0x2510,0x9905},//SEQ_DATA_PORT + {0x2510,0xB064},//SEQ_DATA_PORT + {0x2510,0x99C5},//SEQ_DATA_PORT + {0x2510,0x0047},//SEQ_DATA_PORT + {0x2510,0xB920},//SEQ_DATA_PORT + {0x2510,0x1447},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x2510,0x7FFF},//SEQ_DATA_PORT + {0x31F8,0x0008},//MIPI_CONFIG_2 + {0x3C70,0x6828},//CALIB_ROWS + {0x3092,0x0826},//ROW_NOISE_CONTROL + {0x3428,0x0209},//SEQUENCER_CONTROL + {0x3516,0xFF04},//DAC_LD_22_23 + {0x3526,0x6480},//DAC_LD_38_39 + {0x3504,0x8AAA},//DAC_LD_4_5 + {0x353C,0x220C},//DAC_LD_60_61 + {0x3536,0x4C6E},//DAC_LD_54_55 + {0x3D2A,0x0FFF},//T1_END_DEC_TH + {0x3364,0x00EC},//DCG_TRIM + {0x3512,0x8888},//DAC_LD_18_19 + {0x3514,0x888F},//DAC_LD_20_21 + {0x3520,0xFBF0},//DAC_LD_32_33 + {0x3524,0xB2A1},//DAC_LD_36_37 + {0x3528,0xCC84},//DAC_LD_40_41 + {0x3532,0x4C8E},//DAC_LD_50_51 + {0x3534,0x4E64},//DAC_LD_52_53 + {0x351E,0x5856},//DAC_LD_30_31 + {0x353E,0x98F2},//DAC_LD_62_63 + {0x352E,0x6A8A},//DAC_LD_46_47 + {0x3370,0x0211},//DBLC_CONTROL + {0x3372,0x700F},//DBLC_FS0_CONTROL + {0x3540,0x3597},//DAC_LD_64_65 + {0x58E2,0x0BE3},//COL_COUNT_VALUES1 + {0x58E4,0x18B4},//COL_COUNT_VALUES2 + {0x3522,0x7C97},//DAC_LD_34_35 + {0x30BA,0x0024},//DIGITAL_CTRL + {0x31D4,0x0042},//CLK_MEM_GATING_CTRL + {0x352A,0x6F8F},//DAC_LD_42_43 + {0x3530,0x4A08},//DAC_LD_48_49 + {0x351A,0x5FFF},//DAC_LD_26_27 + {0x350E,0x39D9},//DAC_LD_14_15 + {0x3510,0x9988},//DAC_LD_16_17 + {0x3380,0x1FFF},//DBLC_OFFSET1 + {0x337A,0x1000},//DBLC_SCALE1 + {0x3092,0x0800},//ROW_NOISE_CONTROL + {0x350A,0x0654},//DAC_LD_10_11 + {0x3364,0x00E0},//DCG_TRIM + {0x591E,0x61AE},//ANALOG_GAIN_WR_DATA + {0x591E,0x722C},//ANALOG_GAIN_WR_DATA + {0x591E,0x82B8},//ANALOG_GAIN_WR_DATA + {0x591E,0x92F6},//ANALOG_GAIN_WR_DATA + {0x591E,0xA447},//ANALOG_GAIN_WR_DATA + {0x591E,0xB66D},//ANALOG_GAIN_WR_DATA + {0x591E,0xC6EA},//ANALOG_GAIN_WR_DATA + {0x591E,0xDECD},//ANALOG_GAIN_WR_DATA + {0x3532,0x4C8A},//DAC_LD_50_51 + {0x3534,0x4E60},//DAC_LD_52_53 + {0x353E,0x90F2},//DAC_LD_62_63 + {0x351A,0x4FFF},//DAC_LD_26_27 + {0x591C,0x00D7},//DGR_AMP_GAIN + {0x3522,0x6097},//DAC_LD_34_35 + {0x5002,0x37C3},//T1_PIX_DEF_ID2 + {0x51CC,0x0149},//T1_NOISE_GAIN_THRESHOLD0 + {0x51D8,0x044D},//T1_NOISE_GAIN_THRESHOLD1 + {0x51CE,0x0700},//T1_NOISE_GAIN_THRESHOLD2 + {0x51D0,0x0001},//T1_NOISE_FLOOR0 + {0x51D2,0x0002},//T1_NOISE_FLOOR1 + {0x51D4,0x0003},//T1_NOISE_FLOOR2 + {0x51D6,0x0004},//T1_NOISE_FLOOR3 + {0x5202,0x37C3},//T2_PIX_DEF_ID2 + {0x51EA,0x0149},//T2_NOISE_GAIN_THRESHOLD0 + {0x51FC,0x044D},//T2_NOISE_GAIN_THRESHOLD1 + {0x51EC,0x0700},//T2_NOISE_GAIN_THRESHOLD2 + {0x51EE,0x0001},//T2_NOISE_FLOOR0 + {0x51F0,0x0002},//T2_NOISE_FLOOR1 + {0x51F2,0x0003},//T2_NOISE_FLOOR2 + {0x51F4,0x0004},//T2_NOISE_FLOOR3 + {0x5402,0x37C3},//T4_PIX_DEF_ID2 + {0x5560,0x0149},//T4_NOISE_GAIN_THRESHOLD0 + {0x556C,0x044D},//T4_NOISE_GAIN_THRESHOLD1 + {0x5562,0x0700},//T4_NOISE_GAIN_THRESHOLD2 + {0x5564,0x0001},//T4_NOISE_FLOOR0 + {0x5566,0x0002},//T4_NOISE_FLOOR1 + {0x5568,0x0003},//T4_NOISE_FLOOR2 + {0x556A,0x0004},//T4_NOISE_FLOOR3 + {0x31E0,0x0001},//PIX_DEF_ID + {0x5000,0x0080},//T1_PIX_DEF_ID + {0x5000,0x0180},//T1_PIX_DEF_ID + {0x5000,0x0180},//T1_PIX_DEF_ID + {0x5200,0x0080},//T2_PIX_DEF_ID + {0x5200,0x0180},//T2_PIX_DEF_ID + {0x5200,0x0180},//T2_PIX_DEF_ID + {0x5400,0x0080},//T4_PIX_DEF_ID + {0x5400,0x0180},//T4_PIX_DEF_ID + {0x5400,0x0180},//T4_PIX_DEF_ID + {0x5000,0x1180},//T1_PIX_DEF_ID + {0x50A2,0x2553},//BMT0 + {0x50A4,0xDFD4},//BMT1 + {0x50A6,0x030F},//SINGLEK_FACTOR0 + {0x50A6,0x0F0F},//SINGLEK_FACTOR0 + {0x50A8,0x030F},//SINGLEK_FACTOR1 + {0x50A8,0x0F0F},//SINGLEK_FACTOR1 + {0x50AA,0x030F},//SINGLEK_FACTOR2 + {0x50AA,0x050F},//SINGLEK_FACTOR2 + {0x50AC,0x0301},//CROSS_FACTOR0 + {0x50AC,0x0101},//CROSS_FACTOR0 + {0x50AE,0x0301},//CROSS_FACTOR1 + {0x50AE,0x0101},//CROSS_FACTOR1 + {0x50B0,0x0301},//CROSS_FACTOR2 + {0x50B0,0x0101},//CROSS_FACTOR2 + {0x50B2,0x03FF},//SINGLE_MAX_FACTOR + {0x50B4,0x030F},//COUPLE_FACTOR0 + {0x50B4,0x0F0F},//COUPLE_FACTOR0 + {0x50B6,0x030F},//COUPLE_FACTOR1 + {0x50B6,0x0F0F},//COUPLE_FACTOR1 + {0x50B8,0x030F},//COUPLE_FACTOR2 + {0x50B8,0x050F},//COUPLE_FACTOR2 + {0x31AE,0x0204},//SERIAL_FORMAT + {0x31AC,0x0C0C},//DATA_FORMAT_BITS + {0x3082,0x0001},//OPERATION_MODE_CTRL + {0x30BA,0x0024},//DIGITAL_CTRL + {0x31AE,0x0204},//SERIAL_FORMAT + {0x31AC,0x0C0C},//DATA_FORMAT_BITS + {0x300C,0x0482},//LINE_LENGTH_PCK_ + {0x300A,0x0944},//FRAME_LENGTH_LINES_ + {0x3012,0x093E},//COARSE_INTEGRATION_TIME_ + {0x5914,0x4012},//SENSOR_GAIN_TABLE_SEL + {REG_DELAY,100}, + {0x5914,0x4002},//SENSOR_GAIN_TABLE_SEL + {0x5910,0x608A},//SENSOR_GAIN_REG1 + {0x5910,0x7091},//SENSOR_GAIN_REG1 + {0x5910,0x689C},//SENSOR_GAIN_REG1 + {0x5910,0x8885},//SENSOR_GAIN_REG1 + {0x5910,0x98AD},//SENSOR_GAIN_REG1 + {0x5910,0xA8A9},//SENSOR_GAIN_REG1 + {0x5910,0xC894},//SENSOR_GAIN_REG1 + {0x5910,0xC8D1},//SENSOR_GAIN_REG1 + {0x5910,0xD88A},//SENSOR_GAIN_REG1 + {0x5910,0xD8C3},//SENSOR_GAIN_REG1 + {0x5910,0xD915},//SENSOR_GAIN_REG1 + {0x5910,0xD988},//SENSOR_GAIN_REG1 + {0x5910,0xDA2A},//SENSOR_GAIN_REG1 + {0x5910,0xDB0E},//SENSOR_GAIN_REG1 + {0x5910,0xDC53},//SENSOR_GAIN_REG1 + {0x5910,0x608A},//SENSOR_GAIN_REG1 + {0x5910,0xC919},//SENSOR_GAIN_REG1 + {0x5910,0xCA00},//SENSOR_GAIN_REG1 + {0x5910,0x0000},//SENSOR_GAIN_REG1 + {0x5910,0x0000},//SENSOR_GAIN_REG1 + {0x5910,0x0000},//SENSOR_GAIN_REG1 + {0x5910,0x0001},//SENSOR_GAIN_REG1 + {0x5910,0x0001},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0004},//SENSOR_GAIN_REG1 + {0x5910,0x0002},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x0003},//SENSOR_GAIN_REG1 + {0x5910,0x5A8B},//SENSOR_GAIN_REG1 + {0x5910,0xFF04},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xFF04},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0x0005},//SENSOR_GAIN_REG1 + {0x5910,0x0006},//SENSOR_GAIN_REG1 + {0x5910,0x0007},//SENSOR_GAIN_REG1 + {0x5910,0x9A8B},//SENSOR_GAIN_REG1 + {0x5910,0xFF04},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0x0015},//SENSOR_GAIN_REG1 + {0x5910,0x0016},//SENSOR_GAIN_REG1 + {0x5910,0x0017},//SENSOR_GAIN_REG1 + {0x5910,0xDA8B},//SENSOR_GAIN_REG1 + {0x5910,0xFF04},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0xF704},//SENSOR_GAIN_REG1 + {0x5910,0x0025},//SENSOR_GAIN_REG1 + {0x5910,0x0026},//SENSOR_GAIN_REG1 + {0x5910,0x0027},//SENSOR_GAIN_REG1 + {0x5910,0x59B9},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x0035},//SENSOR_GAIN_REG1 + {0x5910,0x0036},//SENSOR_GAIN_REG1 + {0x5910,0x0037},//SENSOR_GAIN_REG1 + {0x5910,0x99B9},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x0045},//SENSOR_GAIN_REG1 + {0x5910,0x0046},//SENSOR_GAIN_REG1 + {0x5910,0x0047},//SENSOR_GAIN_REG1 + {0x5910,0xD9B9},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x700F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x7F0F},//SENSOR_GAIN_REG1 + {0x5910,0x0055},//SENSOR_GAIN_REG1 + {0x5910,0x0056},//SENSOR_GAIN_REG1 + {0x5910,0x0057},//SENSOR_GAIN_REG1 + {0x5910,0x9A85},//SENSOR_GAIN_REG1 + {0x5910,0x0654},//SENSOR_GAIN_REG1 + {0x5910,0x0654},//SENSOR_GAIN_REG1 + {0x5910,0x0684},//SENSOR_GAIN_REG1 + {0x5910,0x0654},//SENSOR_GAIN_REG1 + {0x5910,0x0654},//SENSOR_GAIN_REG1 + {0x5910,0x0065},//SENSOR_GAIN_REG1 + {0x5910,0x0066},//SENSOR_GAIN_REG1 + {0x5910,0x0067},//SENSOR_GAIN_REG1 + {0x5910,0x59BD},//SENSOR_GAIN_REG1 + {0x5910,0x1000},//SENSOR_GAIN_REG1 + {0x5910,0x0C00},//SENSOR_GAIN_REG1 + {0x5910,0x0F00},//SENSOR_GAIN_REG1 + {0x5910,0x1000},//SENSOR_GAIN_REG1 + {0x5910,0x10F0},//SENSOR_GAIN_REG1 + {0x5910,0x0075},//SENSOR_GAIN_REG1 + {0x5910,0x0076},//SENSOR_GAIN_REG1 + {0x5910,0x0077},//SENSOR_GAIN_REG1 + {0x5912,0x608A},//SENSOR_GAIN_REG2 + {0x5912,0x7091},//SENSOR_GAIN_REG2 + {0x5912,0x689C},//SENSOR_GAIN_REG2 + {0x5912,0x8885},//SENSOR_GAIN_REG2 + {0x5912,0x98AD},//SENSOR_GAIN_REG2 + {0x5912,0xA8A9},//SENSOR_GAIN_REG2 + {0x5912,0xC894},//SENSOR_GAIN_REG2 + {0x5912,0xC8D1},//SENSOR_GAIN_REG2 + {0x5912,0xC927},//SENSOR_GAIN_REG2 + {0x5912,0xC9A0},//SENSOR_GAIN_REG2 + {0x5912,0xCA4C},//SENSOR_GAIN_REG2 + {0x5912,0xCB3F},//SENSOR_GAIN_REG2 + {0x5912,0xCC97},//SENSOR_GAIN_REG2 + {0x5912,0xCE7C},//SENSOR_GAIN_REG2 + {0x5912,0xCFFF},//SENSOR_GAIN_REG2 + {0x5912,0x608A},//SENSOR_GAIN_REG2 + {0x5912,0xC8F0},//SENSOR_GAIN_REG2 + {0x5912,0xCA00},//SENSOR_GAIN_REG2 + {0x5912,0x0000},//SENSOR_GAIN_REG2 + {0x5912,0x0000},//SENSOR_GAIN_REG2 + {0x5912,0x0000},//SENSOR_GAIN_REG2 + {0x5912,0x0001},//SENSOR_GAIN_REG2 + {0x5912,0x0001},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0004},//SENSOR_GAIN_REG2 + {0x5912,0x0002},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x0003},//SENSOR_GAIN_REG2 + {0x5912,0x5A8B},//SENSOR_GAIN_REG2 + {0x5912,0xFF04},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xFF04},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0x0005},//SENSOR_GAIN_REG2 + {0x5912,0x0006},//SENSOR_GAIN_REG2 + {0x5912,0x0007},//SENSOR_GAIN_REG2 + {0x5912,0x9A8B},//SENSOR_GAIN_REG2 + {0x5912,0xFF04},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0x0015},//SENSOR_GAIN_REG2 + {0x5912,0x0016},//SENSOR_GAIN_REG2 + {0x5912,0x0017},//SENSOR_GAIN_REG2 + {0x5912,0xDA8B},//SENSOR_GAIN_REG2 + {0x5912,0xFF04},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0xF704},//SENSOR_GAIN_REG2 + {0x5912,0x0025},//SENSOR_GAIN_REG2 + {0x5912,0x0026},//SENSOR_GAIN_REG2 + {0x5912,0x0027},//SENSOR_GAIN_REG2 + {0x5912,0x59B9},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x0035},//SENSOR_GAIN_REG2 + {0x5912,0x0036},//SENSOR_GAIN_REG2 + {0x5912,0x0037},//SENSOR_GAIN_REG2 + {0x5912,0x99B9},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x0045},//SENSOR_GAIN_REG2 + {0x5912,0x0046},//SENSOR_GAIN_REG2 + {0x5912,0x0047},//SENSOR_GAIN_REG2 + {0x5912,0xD9B9},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x700F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x7F0F},//SENSOR_GAIN_REG2 + {0x5912,0x0055},//SENSOR_GAIN_REG2 + {0x5912,0x0056},//SENSOR_GAIN_REG2 + {0x5912,0x0057},//SENSOR_GAIN_REG2 + {0x5912,0x9A85},//SENSOR_GAIN_REG2 + {0x5912,0x0654},//SENSOR_GAIN_REG2 + {0x5912,0x0654},//SENSOR_GAIN_REG2 + {0x5912,0x0684},//SENSOR_GAIN_REG2 + {0x5912,0x0654},//SENSOR_GAIN_REG2 + {0x5912,0x0654},//SENSOR_GAIN_REG2 + {0x5912,0x0065},//SENSOR_GAIN_REG2 + {0x5912,0x0066},//SENSOR_GAIN_REG2 + {0x5912,0x0067},//SENSOR_GAIN_REG2 + {0x5912,0x59BD},//SENSOR_GAIN_REG2 + {0x5912,0x1000},//SENSOR_GAIN_REG2 + {0x5912,0x0C00},//SENSOR_GAIN_REG2 + {0x5912,0x0F00},//SENSOR_GAIN_REG2 + {0x5912,0x1000},//SENSOR_GAIN_REG2 + {0x5912,0x10F0},//SENSOR_GAIN_REG2 + {0x5912,0x0075},//SENSOR_GAIN_REG2 + {0x5912,0x0076},//SENSOR_GAIN_REG2 + {0x5912,0x0077},//SENSOR_GAIN_REG2 + {0x5914,0x4002},//SENSOR_GAIN_TABLE_SEL + {0x5900,0x0000},//SENSOR_GAIN + + {REG_NULL, 0x00}, +}; +static const s64 link_freq_menu_items[] = { + MIPI_FREQ_492M, + MIPI_FREQ_657M, + MIPI_FREQ_823M, + MIPI_FREQ_986M, +}; +#define MIPI_FREQ_492M_INDEX 0 +#define MIPI_FREQ_657M_INDEX 1 +#define MIPI_FREQ_823M_INDEX 2 +#define MIPI_FREQ_986M_INDEX 3 +#define MIPI_FREQ_MAX_INDEX 4 +/* + * The width and height must be configured to be + * the same as the current output resolution of the sensor. + * The input width of the isp needs to be 16 aligned. + * The input height of the isp needs to be 8 aligned. + * If the width or height does not meet the alignment rules, + * you can configure the cropping parameters with the following function to + * crop out the appropriate resolution. + * struct v4l2_subdev_pad_ops { + * .get_selection + * } + */ + +/* Config resolution ,LLPCLK, FLL, exposure time,fps, MIPI channel config, HDR mode , open.k */ +static const struct ar0822_mode supported_modes[] = { +/* { + .bus_fmt = MEDIA_BUS_FMT_SGRBG12_1X12, + .width = 3840, + .height = 2160, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .exp_def = 0x0240, + .hts_def = 0x4330,//for linear mode, hblank is 4*LINE_LENGTH_PCK_-WIDTH,so hts is 4*LINE_LENGTH_PCK_. not used param by RK. + .vts_def = 0x0944,//used by AEC, should set correctly. + .reg_list = ar0822_linear_60fps_regs, + .hdr_mode = NO_HDR, + .mipi_freq = MIPI_FREQ_986M_INDEX, + .mipi_rate = MIPI_FREQ_986M/AR0822_BPP12*2*AR0822_LANES, + .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0, + },*/ + { + .bus_fmt = MEDIA_BUS_FMT_SGRBG12_1X12, + .width = 3840, + .height = 2160, + .max_fps = { + .numerator = 10000, + .denominator = 300000, + }, + .exp_def = 0x0240, + .hts_def = 0x4330,//for linear mode, hblank is 4*LINE_LENGTH_PCK_-WIDTH,so hts is 4*LINE_LENGTH_PCK_. not used param by RK. + .vts_def = 0x09F3,//used by AEC, should set correctly. + .reg_list = ar0822_linear_global_regs, + .hdr_mode = NO_HDR, + .mipi_freq = MIPI_FREQ_492M_INDEX, + .mipi_rate = MIPI_FREQ_492M / AR0822_BPP12 * 2 * AR0822_LANES, + .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0, + }, + + { + .bus_fmt = MEDIA_BUS_FMT_SGRBG12_1X12, + .width = 3840, + .height = 2160, + .max_fps = { + .numerator = 10000, + .denominator = 200000, + }, + .exp_def = 0x0240, + .hts_def = 0x0E7C*2,// + .vts_def = 0x9b8,//0x0888,// + .reg_list = ar0822_hdr12bit_3840x2160_20fps_regs, + .hdr_mode = HDR_X2, + .mipi_freq = MIPI_FREQ_657M_INDEX, + .mipi_rate = MIPI_FREQ_657M / AR0822_BPP12 * 2 *AR0822_LANES, + .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1, + .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0 + .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1, + .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2 + }, + + { + .bus_fmt = MEDIA_BUS_FMT_SGRBG12_1X12, + .width = 3840, + .height = 2160, + .max_fps = { + .numerator = 10000, + .denominator = 250000, + }, + .exp_def = 0x0080, + .hts_def = 0x0B98*4-3840,// + .vts_def = 0x0980,//0x0888,// + .reg_list = ar0822_hdr12bit_3840x2160_25fps_regs, + .hdr_mode = HDR_X2, + .mipi_freq = MIPI_FREQ_823M_INDEX, + .mipi_rate = MIPI_FREQ_823M / AR0822_BPP12 * 2 * AR0822_LANES, + .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1, + .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0, + .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0 + .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2 + }, + + { + .bus_fmt = MEDIA_BUS_FMT_SGRBG12_1X12, + .width = 3840, + .height = 2160, + .max_fps = { + .numerator = 10000, + .denominator = 300000, + }, + .exp_def = 0x0240, + .hts_def = 0x3430,//for HDR, hblank is 4*LINE_LENGTH_PCK_-WIDTH*2, so hts is 4*LINE_LENGTH_PCK_-WIDTH. param not used by RK. + .vts_def = 0x9F3,//should be set correctly, + .reg_list = ar0822_hdr12bit_3840x2160_30fps_regs, + .hdr_mode = HDR_X2, + .mipi_freq = MIPI_FREQ_986M_INDEX, + .mipi_rate = MIPI_FREQ_986M / AR0822_BPP12 * 2 * AR0822_LANES, + .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0, + .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0 + }, + + +}; + + +/* use ar0822_enable_test_pattern to config test pattern mode here, open.k */ +static const char * const ar0822_test_pattern_menu[] = { + "Disabled", + "Vertical Color Bar Type 1", + "Vertical Color Bar Type 2", + "Vertical Color Bar Type 3", + "Vertical Color Bar Type 4" +}; + +static int __ar0822_power_on(struct ar0822 *ar0822); + +/* Write registers up to 4 at a time */ +static int ar0822_write_reg(struct i2c_client *client, u16 reg, + u32 len, u32 val) +{ + u32 buf_i, val_i; + u8 buf[6]; + u8 *val_p; + __be32 val_be; + + if (len > 4) + return -EINVAL; + + buf[0] = reg >> 8; + buf[1] = reg & 0xff; + + val_be = cpu_to_be32(val); + val_p = (u8 *)&val_be; + buf_i = 2; + val_i = 4 - len; + + while (val_i < 4) + buf[buf_i++] = val_p[val_i++]; + + if (i2c_master_send(client, buf, len + 2) != len + 2) + return -EIO; + + return 0; +} + +static int ar0822_write_array(struct i2c_client *client, + const struct regval *regs) +{ + u32 i; + int ret = 0; + + for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) { + if (unlikely(regs[i].addr == REG_DELAY)) + usleep_range(regs[i].val, regs[i].val * 2); + else + ret |= ar0822_write_reg(client, regs[i].addr, + AR0822_REG_VALUE_16BIT, regs[i].val); + } + return ret; +} + +/* Read registers up to 4 at a time */ +static int ar0822_read_reg(struct i2c_client *client, + u16 reg, + unsigned int len, + u32 *val) +{ + struct i2c_msg msgs[2]; + u8 *data_be_p; + __be32 data_be = 0; + __be16 reg_addr_be = cpu_to_be16(reg); + int ret; + + if (len > 4 || !len) + return -EINVAL; + + data_be_p = (u8 *)&data_be; + /* Write register address */ + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = 2; + msgs[0].buf = (u8 *)®_addr_be; + + /* Read data from register */ + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = len; + msgs[1].buf = &data_be_p[4 - len]; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) + return -EIO; + + *val = be32_to_cpu(data_be); + + return 0; +} + +static int ar0822_get_reso_dist(const struct ar0822_mode *mode, + struct v4l2_mbus_framefmt *framefmt) +{ + return abs(mode->width - framefmt->width) + + abs(mode->height - framefmt->height); +} + +static const struct ar0822_mode * +ar0822_find_best_fit(struct ar0822 *ar0822, struct v4l2_subdev_format *fmt) +{ + struct v4l2_mbus_framefmt *framefmt = &fmt->format; + int dist; + int cur_best_fit = 0; + int cur_best_fit_dist = -1; + unsigned int i; + + for (i = 0; i < ar0822->cfg_num; i++) { + dist = ar0822_get_reso_dist(&supported_modes[i], framefmt); + if ((cur_best_fit_dist == -1 || dist < cur_best_fit_dist) && + (supported_modes[i].bus_fmt == framefmt->code)) { + cur_best_fit_dist = dist; + cur_best_fit = i; + } + } + + return &supported_modes[cur_best_fit]; +} +static int ar0822_set_rates(struct ar0822 *ar0822) +{ + const struct ar0822_mode *mode = ar0822->cur_mode; + s64 h_blank, vblank_def; + int ret = 0; + + h_blank = mode->hts_def - mode->width; + dev_err(&ar0822->client->dev, + "set format hblank is (%lld), mipi freq: %d, rate: %d\n", + h_blank, mode->mipi_freq,mode->mipi_rate); + __v4l2_ctrl_modify_range(ar0822->hblank, h_blank, + h_blank, 1, h_blank); + vblank_def = mode->vts_def - mode->height; + __v4l2_ctrl_modify_range(ar0822->vblank, vblank_def, + AR0822_VTS_MAX - mode->height, + 1, vblank_def); + + __v4l2_ctrl_s_ctrl_int64(ar0822->pixel_rate, + mode->mipi_rate); + __v4l2_ctrl_s_ctrl(ar0822->link_freq, + mode->mipi_freq); + + return ret; +} +/* setup sensor work format to determine the MIPI speed, open.k */ +static int ar0822_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct ar0822 *ar0822 = to_ar0822(sd); + const struct ar0822_mode *mode; + + mutex_lock(&ar0822->mutex); + + mode = ar0822_find_best_fit(ar0822, fmt); + fmt->format.code = mode->bus_fmt; + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.field = V4L2_FIELD_NONE; + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format; +#else + mutex_unlock(&ar0822->mutex); + return -ENOTTY; +#endif + } else { + ar0822->cur_mode = mode; + ar0822_set_rates(ar0822); + } + + mutex_unlock(&ar0822->mutex); + + return 0; +} + +static int ar0822_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct ar0822 *ar0822 = to_ar0822(sd); + const struct ar0822_mode *mode = ar0822->cur_mode; + + mutex_lock(&ar0822->mutex); + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad); +#else + mutex_unlock(&ar0822->mutex); + return -ENOTTY; +#endif + } else { + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.code = mode->bus_fmt; + fmt->format.field = V4L2_FIELD_NONE; + if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR) + fmt->reserved[0] = mode->vc[fmt->pad]; + else + fmt->reserved[0] = mode->vc[PAD0]; + } + mutex_unlock(&ar0822->mutex); + + return 0; +} + +static int ar0822_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct ar0822 *ar0822 = to_ar0822(sd); + + if (code->index >= ar0822->cfg_num) + return -EINVAL; + code->code = supported_modes[code->index].bus_fmt; + + return 0; +} + +static int ar0822_enum_frame_sizes(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct ar0822 *ar0822 = to_ar0822(sd); + + if (fse->index >= ar0822->cfg_num) + return -EINVAL; + + if (fse->code != supported_modes[fse->index].bus_fmt) + return -EINVAL; + + fse->min_width = supported_modes[fse->index].width; + fse->max_width = supported_modes[fse->index].width; + fse->max_height = supported_modes[fse->index].height; + fse->min_height = supported_modes[fse->index].height; + + return 0; +} +/* use ar0822_enable_test_pattern to config test pattern mode here, open.k */ +static int ar0822_enable_test_pattern(struct ar0822 *ar0822, u32 pattern) +{ + int ret = 0; + + return ret; +} + +static int ar0822_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *fi) +{ + struct ar0822 *ar0822 = to_ar0822(sd); + const struct ar0822_mode *mode = ar0822->cur_mode; + + mutex_lock(&ar0822->mutex); + fi->interval = mode->max_fps; + mutex_unlock(&ar0822->mutex); + + return 0; +} + +static int ar0822_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id, + struct v4l2_mbus_config *config) +{ + struct ar0822 *ar0822 = to_ar0822(sd); + const struct ar0822_mode *mode = ar0822->cur_mode; + u32 val = 0; + + val = 1 << (AR0822_LANES - 1) | + V4L2_MBUS_CSI2_CHANNEL_0 | + V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; + if (mode->hdr_mode != NO_HDR) + val |= V4L2_MBUS_CSI2_CHANNEL_1; + if (mode->hdr_mode == HDR_X3) + val |= V4L2_MBUS_CSI2_CHANNEL_2; + + config->type = V4L2_MBUS_CSI2_DPHY; + config->flags = val; + + return 0; +} + + +static void ar0822_get_module_inf(struct ar0822 *ar0822, + struct rkmodule_inf *inf) +{ + memset(inf, 0, sizeof(*inf)); + strlcpy(inf->base.sensor, AR0822_NAME, sizeof(inf->base.sensor)); + strlcpy(inf->base.module, ar0822->module_name, + sizeof(inf->base.module)); + strlcpy(inf->base.lens, ar0822->len_name, sizeof(inf->base.lens)); +} + +static int ar0822_set_hdrae(struct ar0822 *ar0822, + struct preisp_hdrae_exp_s *ae) +{ + u32 l_exp_time, m_exp_time, s_exp_time; + u32 l_a_gain, m_a_gain, s_a_gain; + int ret = 0; + u8 l_cg_mode = 0; + u8 m_cg_mode = 0; + u8 s_cg_mode = 0; + u32 gain_val = 0; + + if (!ar0822->has_init_exp && !ar0822->streaming) { + ar0822->init_hdrae_exp = *ae; + ar0822->has_init_exp = true; + dev_err(&ar0822->client->dev, "ar0822 don't stream, record exp for hdr!\n"); + return ret; + } + l_exp_time = ae->long_exp_reg; + m_exp_time = ae->middle_exp_reg; + s_exp_time = ae->short_exp_reg; + l_a_gain = ae->long_gain_reg; + m_a_gain = ae->middle_gain_reg; + s_a_gain = ae->short_gain_reg; + l_cg_mode = ae->long_cg_mode; + m_cg_mode = ae->middle_cg_mode; + s_cg_mode = ae->short_cg_mode; + dev_dbg(&ar0822->client->dev, + "Li-HDR irev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n", + l_exp_time, l_a_gain, + m_exp_time, m_a_gain, + s_exp_time, s_a_gain); + + if (ar0822->cur_mode->hdr_mode == HDR_X2) { + //2 stagger + l_a_gain = m_a_gain; + l_exp_time = m_exp_time; + l_cg_mode = m_cg_mode; + m_a_gain = s_a_gain; + m_exp_time = s_exp_time; + m_cg_mode = s_cg_mode; + } + + l_a_gain = (l_a_gain > AR0822_GAIN_MAX) ? AR0822_GAIN_MAX:l_a_gain; + m_a_gain = (m_a_gain > AR0822_GAIN_MAX) ? AR0822_GAIN_MAX:m_a_gain; + s_a_gain = (s_a_gain > AR0822_GAIN_MAX) ? AR0822_GAIN_MAX:s_a_gain; + l_a_gain = (l_a_gain < AR0822_GAIN_MIN) ? AR0822_GAIN_MIN:l_a_gain; + m_a_gain = (m_a_gain < AR0822_GAIN_MIN) ? AR0822_GAIN_MIN:m_a_gain; + s_a_gain = (s_a_gain < AR0822_GAIN_MIN) ? AR0822_GAIN_MIN:s_a_gain; + + gain_val = l_a_gain; + ret |= ar0822_write_reg(ar0822->client, + AR0822_GROUP_UPDATE_ADDRESS, + AR0822_REG_VALUE_16BIT, + AR0822_GROUP_UPDATE_START_DATA); + + ret |= ar0822_write_reg(ar0822->client, + AR0822_REG_GAIN, + AR0822_REG_VALUE_16BIT, gain_val); + + gain_val = m_a_gain; + ret |= ar0822_write_reg(ar0822->client, + AR0822_REG_GAIN2, + AR0822_REG_VALUE_16BIT, gain_val); + + if (ar0822->cur_mode->hdr_mode == HDR_X3) { + gain_val = s_a_gain; + ret |= ar0822_write_reg(ar0822->client, + AR0822_REG_GAIN3, + AR0822_REG_VALUE_16BIT, gain_val); + } + ret |= ar0822_write_reg(ar0822->client, + AR0822_REG_EXP, + AR0822_REG_VALUE_16BIT, + l_exp_time);//fixed ratio 1/16 is used here, T2 and T3 is from ratio* T1 or ratio^2* T1. + + ret |= ar0822_write_reg(ar0822->client, + AR0822_GROUP_UPDATE_ADDRESS, + AR0822_REG_VALUE_16BIT, + AR0822_GROUP_UPDATE_END_DATA); + + dev_dbg(&ar0822->client->dev, "ar0822_set_hdrae exp 0x%x\n",l_exp_time); + + return ret; +} + +static int ar0822_set_conversion_gain(struct ar0822 *ar0822, u32 *cg) +{ + int ret = 0; + return ret; +} + +#ifdef USED_SYS_DEBUG +//ag: echo 0 > /sys/devices/platform/ff510000.i2c/i2c-1/1-0036-1/cam_s_cg +static ssize_t set_conversion_gain_status(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ar0822 *ar0822 = to_ar0822(sd); + int status = 0; + int ret = 0; + + ret = kstrtoint(buf, 0, &status); + if (!ret && status >= 0 && status < 2) + ar0822_set_conversion_gain(ar0822, &status); + else + dev_err(dev, "input 0 for LCG, 1 for HCG, cur %d\n", status); + return count; +} + +static struct device_attribute attributes[] = { + __ATTR(cam_s_cg, S_IWUSR, NULL, set_conversion_gain_status), +}; + +static int add_sysfs_interfaces(struct device *dev) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(attributes); i++) + if (device_create_file(dev, attributes + i)) + goto undo; + return 0; +undo: + for (i--; i >= 0 ; i--) + device_remove_file(dev, attributes + i); + dev_err(dev, "%s: failed to create sysfs interface\n", __func__); + return -ENODEV; +} +#endif + +static int ar0822_get_channel_info(struct ar0822 *ar0822, struct rkmodule_channel_info *ch_info) +{ + if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX) + return -EINVAL; + ch_info->vc = ar0822->cur_mode->vc[ch_info->index]; + ch_info->width = ar0822->cur_mode->width; + ch_info->height = ar0822->cur_mode->height; + ch_info->bus_fmt = ar0822->cur_mode->bus_fmt; + return 0; +} + +static long ar0822_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct ar0822 *ar0822 = to_ar0822(sd); + struct rkmodule_hdr_cfg *hdr_cfg; + struct rkmodule_channel_info *ch_info; + long ret = 0; + u32 i, h, w; + u32 stream = 0; + + switch (cmd) { + case PREISP_CMD_SET_HDRAE_EXP: + ar0822_set_hdrae(ar0822, arg); + break; + case RKMODULE_SET_HDR_CFG: + hdr_cfg = (struct rkmodule_hdr_cfg *)arg; + w = ar0822->cur_mode->width; + h = ar0822->cur_mode->height; + for (i = 0; i < ar0822->cfg_num; i++) { + if (w == supported_modes[i].width && + h == supported_modes[i].height && + supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) { + ar0822->cur_mode = &supported_modes[i]; + break; + } + } + if (i == ar0822->cfg_num) { + dev_err(&ar0822->client->dev, + "not find hdr mode:%d %dx%d config\n", + hdr_cfg->hdr_mode, w, h); + ret = -EINVAL; + } else { + w = ar0822->cur_mode->hts_def - ar0822->cur_mode->width; + h = ar0822->cur_mode->vts_def - ar0822->cur_mode->height; + dev_info(&ar0822->client->dev, + "set hdr cfg, hblank is (%d)\n", w); + __v4l2_ctrl_modify_range(ar0822->hblank, w, w, 1, w); + __v4l2_ctrl_modify_range(ar0822->vblank, h, + AR0822_VTS_MAX - ar0822->cur_mode->height, + 1, h); + dev_info(&ar0822->client->dev, + "sensor mode: %d\n", + ar0822->cur_mode->hdr_mode); + } + ar0822_set_rates(ar0822); + break; + case RKMODULE_GET_MODULE_INFO: + ar0822_get_module_inf(ar0822, (struct rkmodule_inf *)arg); + break; + case RKMODULE_GET_HDR_CFG: + hdr_cfg = (struct rkmodule_hdr_cfg *)arg; + hdr_cfg->esp.mode = HDR_NORMAL_VC; + hdr_cfg->hdr_mode = ar0822->cur_mode->hdr_mode; + break; + case RKMODULE_SET_CONVERSION_GAIN: + ret = 0;//ar0822_set_conversion_gain(ar0822, (u32 *)arg); + break; + case RKMODULE_SET_QUICK_STREAM: + + stream = *((u32 *)arg); + + if (stream) + ret = ar0822_write_reg(ar0822->client, AR0822_REG_CTRL_MODE, + AR0822_REG_VALUE_16BIT, AR0822_MODE_STREAMING); + else + ret = ar0822_write_reg(ar0822->client, AR0822_REG_CTRL_MODE, + AR0822_REG_VALUE_16BIT, AR0822_MODE_SW_STANDBY); + break; + case RKMODULE_GET_CHANNEL_INFO: + ch_info = (struct rkmodule_channel_info *)arg; + ret = ar0822_get_channel_info(ar0822, ch_info); + break; + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} + +#ifdef CONFIG_COMPAT +static long ar0822_compat_ioctl32(struct v4l2_subdev *sd, + unsigned int cmd, unsigned long arg) +{ + void __user *up = compat_ptr(arg); + struct rkmodule_inf *inf; + struct rkmodule_awb_cfg *cfg; + struct rkmodule_hdr_cfg *hdr; + struct preisp_hdrae_exp_s *hdrae; + struct rkmodule_channel_info *ch_info; + long ret; + u32 cg = 0; + u32 stream = 0; + + switch (cmd) { + case RKMODULE_GET_MODULE_INFO: + inf = kzalloc(sizeof(*inf), GFP_KERNEL); + if (!inf) { + ret = -ENOMEM; + return ret; + } + + ret = ar0822_ioctl(sd, cmd, inf); + if (!ret) + ret = copy_to_user(up, inf, sizeof(*inf)); + kfree(inf); + break; + case RKMODULE_AWB_CFG: + cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); + if (!cfg) { + ret = -ENOMEM; + return ret; + } + + ret = copy_from_user(cfg, up, sizeof(*cfg)); + if (!ret) + ret = ar0822_ioctl(sd, cmd, cfg); + kfree(cfg); + break; + case RKMODULE_GET_HDR_CFG: + hdr = kzalloc(sizeof(*hdr), GFP_KERNEL); + if (!hdr) { + ret = -ENOMEM; + return ret; + } + + ret = ar0822_ioctl(sd, cmd, hdr); + if (!ret) + ret = copy_to_user(up, hdr, sizeof(*hdr)); + kfree(hdr); + break; + case RKMODULE_SET_HDR_CFG: + hdr = kzalloc(sizeof(*hdr), GFP_KERNEL); + if (!hdr) { + ret = -ENOMEM; + return ret; + } + + ret = copy_from_user(hdr, up, sizeof(*hdr)); + if (!ret) + ret = ar0822_ioctl(sd, cmd, hdr); + kfree(hdr); + break; + case PREISP_CMD_SET_HDRAE_EXP: + hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL); + if (!hdrae) { + ret = -ENOMEM; + return ret; + } + + ret = copy_from_user(hdrae, up, sizeof(*hdrae)); + if (!ret) + ret = ar0822_ioctl(sd, cmd, hdrae); + kfree(hdrae); + break; + case RKMODULE_SET_CONVERSION_GAIN: + ret = copy_from_user(&cg, up, sizeof(cg)); + if (!ret) + ret = ar0822_ioctl(sd, cmd, &cg); + break; + case RKMODULE_SET_QUICK_STREAM: + ret = copy_from_user(&stream, up, sizeof(u32)); + if (!ret) + ret = ar0822_ioctl(sd, cmd, &stream); + break; + case RKMODULE_GET_CHANNEL_INFO: + ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL); + if (!ch_info) { + ret = -ENOMEM; + return ret; + } + + ret = ar0822_ioctl(sd, cmd, ch_info); + if (!ret) { + ret = copy_to_user(up, ch_info, sizeof(*ch_info)); + if (ret) + ret = -EFAULT; + } + kfree(ch_info); + break; + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} +#endif + +static int __ar0822_start_stream(struct ar0822 *ar0822) +{ + int ret; + + if (!ar0822->is_thunderboot) { + ret = ar0822_write_reg(ar0822->client, + AR0822_SOFTWARE_RESET_REG, + AR0822_REG_VALUE_16BIT, + 0x0001); + usleep_range(100000, 200000); + ret = ar0822_write_array(ar0822->client, ar0822->cur_mode->reg_list); + if (ret) + return ret; + } + + /* In case these controls are set before streaming */ + ret = __v4l2_ctrl_handler_setup(&ar0822->ctrl_handler); + if (ret) + return ret; + if (ar0822->has_init_exp && ar0822->cur_mode->hdr_mode != NO_HDR) { + ret = ar0822_ioctl(&ar0822->subdev, PREISP_CMD_SET_HDRAE_EXP, &ar0822->init_hdrae_exp); + if (ret) { + dev_err(&ar0822->client->dev, + "init exp fail in hdr mode\n"); + return ret; + } + dev_err(&ar0822->client->dev, + "init exp success in hdr mode\n"); + } + return ar0822_write_reg(ar0822->client, AR0822_REG_CTRL_MODE, + AR0822_REG_VALUE_16BIT, AR0822_MODE_STREAMING); +} + +static int __ar0822_stop_stream(struct ar0822 *ar0822) +{ + ar0822->has_init_exp = false; + if (ar0822->is_thunderboot) + ar0822->is_first_streamoff = true; + return ar0822_write_reg(ar0822->client, AR0822_REG_CTRL_MODE, + AR0822_REG_VALUE_16BIT, AR0822_MODE_SW_STANDBY); +} + +static int ar0822_s_stream(struct v4l2_subdev *sd, int on) +{ + struct ar0822 *ar0822 = to_ar0822(sd); + struct i2c_client *client = ar0822->client; + int ret = 0; + + mutex_lock(&ar0822->mutex); + on = !!on; + if (on == ar0822->streaming) + goto unlock_and_return; + if (on) { + if (ar0822->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) { + ar0822->is_thunderboot = false; + __ar0822_power_on(ar0822); + } + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + + ret = __ar0822_start_stream(ar0822); + if (ret) { + v4l2_err(sd, "start stream failed while write regs\n"); + pm_runtime_put(&client->dev); + goto unlock_and_return; + } + } else { + __ar0822_stop_stream(ar0822); + pm_runtime_put(&client->dev); + } + ar0822->streaming = on; + + +unlock_and_return: + mutex_unlock(&ar0822->mutex); + + return ret; +} + +static int ar0822_s_power(struct v4l2_subdev *sd, int on) +{ + struct ar0822 *ar0822 = to_ar0822(sd); + struct i2c_client *client = ar0822->client; + int ret = 0; + + mutex_lock(&ar0822->mutex); + /* If the power state is not modified - no work to do. */ + if (ar0822->power_on == !!on) + goto unlock_and_return; + + if (on) { + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + + if (!ar0822->is_thunderboot) { + ret |= ar0822_write_reg(ar0822->client, + AR0822_SOFTWARE_RESET_REG, + AR0822_REG_VALUE_16BIT, + 0x0001); + usleep_range(100, 200); + } + + ar0822->power_on = true; + } else { + pm_runtime_put(&client->dev); + ar0822->power_on = false; + } + +unlock_and_return: + mutex_unlock(&ar0822->mutex); + + return ret; +} + +/* Calculate the delay in us by clock rate and clock cycles */ +static inline u32 ar0822_cal_delay(u32 cycles) +{ + return DIV_ROUND_UP(cycles, AR0822_XVCLK_FREQ / 1000 / 1000); +} + +static int __ar0822_power_on(struct ar0822 *ar0822) /* sensor power on config, need check power, MCLK, GPIO etc,,, need go to .dts file to change the config; open.k */ +{ + int ret; + u32 delay_us; + struct device *dev = &ar0822->client->dev; + + if (ar0822->is_thunderboot) + return 0; + + if (!IS_ERR_OR_NULL(ar0822->pins_default)) { + ret = pinctrl_select_state(ar0822->pinctrl, + ar0822->pins_default); + if (ret < 0) + dev_err(dev, "could not set pins\n"); + } + ret = clk_set_rate(ar0822->xvclk, AR0822_XVCLK_FREQ); + if (ret < 0) + dev_warn(dev, "Failed to set xvclk rate (24MHz)\n"); + if (clk_get_rate(ar0822->xvclk) != AR0822_XVCLK_FREQ) + dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n"); + ret = clk_prepare_enable(ar0822->xvclk); + if (ret < 0) { + dev_err(dev, "Failed to enable xvclk\n"); + return ret; + } + if (!IS_ERR(ar0822->reset_gpio)) + gpiod_direction_output(ar0822->reset_gpio, 1); + + ret = regulator_bulk_enable(AR0822_NUM_SUPPLIES, ar0822->supplies); + if (ret < 0) { + dev_err(dev, "Failed to enable regulators\n"); + goto disable_clk; + } + + if (!IS_ERR(ar0822->reset_gpio)) + gpiod_direction_output(ar0822->reset_gpio, 0); + + usleep_range(500, 1000); + if (!IS_ERR(ar0822->pwdn_gpio)) + gpiod_direction_output(ar0822->pwdn_gpio, 1); + /* + * There is no need to wait for the delay of RC circuit + * if the reset signal is directly controlled by GPIO. + */ + if (!IS_ERR(ar0822->reset_gpio)) + usleep_range(6000, 8000); + else + usleep_range(12000, 16000); + + /* 8192 cycles prior to first SCCB transaction */ + delay_us = ar0822_cal_delay(8192); + usleep_range(delay_us, delay_us * 2); + + return 0; + +disable_clk: + clk_disable_unprepare(ar0822->xvclk); + + return ret; +} + +static void __ar0822_power_off(struct ar0822 *ar0822) +{ + int ret; + struct device *dev = &ar0822->client->dev; + + if (ar0822->is_thunderboot) { + if (ar0822->is_first_streamoff) { + ar0822->is_thunderboot = false; + ar0822->is_first_streamoff = false; + } else { + return; + } + } + + if (!IS_ERR(ar0822->pwdn_gpio)) + gpiod_direction_output(ar0822->pwdn_gpio, 0); + + clk_disable_unprepare(ar0822->xvclk); + + if (!IS_ERR(ar0822->reset_gpio)) + gpiod_direction_output(ar0822->reset_gpio, 0); + if (!IS_ERR_OR_NULL(ar0822->pins_sleep)) { + ret = pinctrl_select_state(ar0822->pinctrl, + ar0822->pins_sleep); + if (ret < 0) + dev_dbg(dev, "could not set pins\n"); + } + + if (ar0822->is_thunderboot_ng) { + ar0822->is_thunderboot_ng = false; + regulator_bulk_disable(AR0822_NUM_SUPPLIES, ar0822->supplies); + } +} + +static int ar0822_runtime_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ar0822 *ar0822 = to_ar0822(sd); + + return __ar0822_power_on(ar0822); +} + +static int ar0822_runtime_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ar0822 *ar0822 = to_ar0822(sd); + + __ar0822_power_off(ar0822); + + return 0; +} + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API +static int ar0822_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct ar0822 *ar0822 = to_ar0822(sd); + struct v4l2_mbus_framefmt *try_fmt = + v4l2_subdev_get_try_format(sd, fh->pad, 0); + const struct ar0822_mode *def_mode = &supported_modes[0]; + mutex_lock(&ar0822->mutex); + /* Initialize try_fmt */ + try_fmt->width = def_mode->width; + try_fmt->height = def_mode->height; + try_fmt->code = def_mode->bus_fmt; + try_fmt->field = V4L2_FIELD_NONE; + + mutex_unlock(&ar0822->mutex); + /* No crop or compose */ + + return 0; +} +#endif + +static int ar0822_enum_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum *fie) +{ + struct ar0822 *ar0822 = to_ar0822(sd); + + if (fie->index >= ar0822->cfg_num) + return -EINVAL; + fie->code = supported_modes[fie->index].bus_fmt; + fie->width = supported_modes[fie->index].width; + fie->height = supported_modes[fie->index].height; + fie->interval = supported_modes[fie->index].max_fps; + fie->reserved[0] = supported_modes[fie->index].hdr_mode; + return 0; +} + +static const struct dev_pm_ops ar0822_pm_ops = { + SET_RUNTIME_PM_OPS(ar0822_runtime_suspend, + ar0822_runtime_resume, NULL) +}; + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API +static const struct v4l2_subdev_internal_ops ar0822_internal_ops = { + .open = ar0822_open, +}; +#endif + +static const struct v4l2_subdev_core_ops ar0822_core_ops = { + .s_power = ar0822_s_power, + .ioctl = ar0822_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = ar0822_compat_ioctl32, +#endif +}; + +static const struct v4l2_subdev_video_ops ar0822_video_ops = { + .s_stream = ar0822_s_stream, + .g_frame_interval = ar0822_g_frame_interval, +}; + +static const struct v4l2_subdev_pad_ops ar0822_pad_ops = { + .enum_mbus_code = ar0822_enum_mbus_code, + .enum_frame_size = ar0822_enum_frame_sizes, + .enum_frame_interval = ar0822_enum_frame_interval, + .get_fmt = ar0822_get_fmt, + .set_fmt = ar0822_set_fmt, + .get_mbus_config = ar0822_g_mbus_config, +}; + +static const struct v4l2_subdev_ops ar0822_subdev_ops = { + .core = &ar0822_core_ops, + .video = &ar0822_video_ops, + .pad = &ar0822_pad_ops, +}; + + +static int ar0822_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ar0822 *ar0822 = container_of(ctrl->handler, + struct ar0822, ctrl_handler); + struct i2c_client *client = ar0822->client; + s64 max; + int ret = 0; + u32 again = 0; + u32 val = 0; + + /* Propagate change of current control to all related controls */ + switch (ctrl->id) { + case V4L2_CID_VBLANK: + /* Update max exposure while meeting expected vblanking */ + max = ar0822->cur_mode->height + ctrl->val - 4; + __v4l2_ctrl_modify_range(ar0822->exposure, + ar0822->exposure->minimum, max, + ar0822->exposure->step, + ar0822->exposure->default_value); + break; + } + + if (!pm_runtime_get_if_in_use(&client->dev)) + return 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE: + if (ar0822->cur_mode->hdr_mode != NO_HDR) + goto ctrl_end; + ret = ar0822_write_reg(ar0822->client, + AR0822_REG_EXP, + AR0822_REG_VALUE_16BIT, + ctrl->val); + + dev_dbg(&client->dev, "set exposure 0x%x\n", + ctrl->val); + break; + case V4L2_CID_ANALOGUE_GAIN: + if (ar0822->cur_mode->hdr_mode != NO_HDR) + goto ctrl_end; + if (ctrl->val > AR0822_GAIN_MAX) { + again = AR0822_GAIN_MAX; + } else { + again = ctrl->val; + } + if (ctrl->val < AR0822_GAIN_MIN) { + again = AR0822_GAIN_MIN; + } else { + again = ctrl->val; + } + + val = again; + ret = ar0822_write_reg(ar0822->client, + AR0822_REG_GAIN, + AR0822_REG_VALUE_16BIT, + val); + + dev_dbg(&client->dev, "Corn set analog gain 0x%x\n", + ctrl->val); + break; + case V4L2_CID_VBLANK: + //ret = ar0822_write_reg(ar0822->client, AR0822_REG_VTS, + // AR0822_REG_VALUE_16BIT, + // ctrl->val + ar0822->cur_mode->height); + dev_dbg(&client->dev, "set vblank 0x%x\n", + ctrl->val); + break; + case V4L2_CID_TEST_PATTERN: + ret = ar0822_enable_test_pattern(ar0822, ctrl->val); + break; + case V4L2_CID_HFLIP: + ret = ar0822_read_reg(ar0822->client, AR0822_FLIP_REG, + AR0822_REG_VALUE_16BIT, + &val); + if (ctrl->val) + val |= MIRROR_BIT_MASK; + else + val &= ~MIRROR_BIT_MASK; + ret = ar0822_write_reg(ar0822->client, AR0822_FLIP_REG, + AR0822_REG_VALUE_16BIT, + val); + if (ret == 0) + ar0822->flip = val; + break; + case V4L2_CID_VFLIP: + ret = ar0822_read_reg(ar0822->client, AR0822_FLIP_REG, + AR0822_REG_VALUE_16BIT, + &val); + if (ctrl->val) + val |= FLIP_BIT_MASK; + else + val &= ~FLIP_BIT_MASK; + ret = ar0822_write_reg(ar0822->client, AR0822_FLIP_REG, + AR0822_REG_VALUE_16BIT, + val); + if (ret == 0) + ar0822->flip = val; + break; + default: + dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n", + __func__, ctrl->id, ctrl->val); + break; + } + + +ctrl_end: + pm_runtime_put(&client->dev); + + return ret; +} + +static const struct v4l2_ctrl_ops ar0822_ctrl_ops = { + .s_ctrl = ar0822_set_ctrl, +}; + +static int ar0822_initialize_controls(struct ar0822 *ar0822) +{ + const struct ar0822_mode *mode; + struct v4l2_ctrl_handler *handler; + s64 exposure_max, vblank_def; + u32 h_blank; + int ret; + u64 dst_link_freq = 0; + u64 dst_pixel_rate = 0; + + handler = &ar0822->ctrl_handler; + mode = ar0822->cur_mode; + ret = v4l2_ctrl_handler_init(handler, 9); + if (ret) + return ret; + handler->lock = &ar0822->mutex; + ar0822->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, + V4L2_CID_LINK_FREQ, + MIPI_FREQ_MAX_INDEX, 0, link_freq_menu_items); + + dst_link_freq = mode->mipi_freq; + dst_pixel_rate = mode->mipi_rate; + /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */ + ar0822->pixel_rate = v4l2_ctrl_new_std(handler, NULL, + V4L2_CID_PIXEL_RATE, + 0, PIXEL_RATE_MAX, + 1, dst_pixel_rate); + __v4l2_ctrl_s_ctrl(ar0822->link_freq, + dst_link_freq); + + h_blank = mode->hts_def - mode->width; + ar0822->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK, + h_blank, h_blank, 1, h_blank); + if (ar0822->hblank) + ar0822->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + vblank_def = mode->vts_def - mode->height; + ar0822->vblank = v4l2_ctrl_new_std(handler, &ar0822_ctrl_ops, + V4L2_CID_VBLANK, vblank_def, + AR0822_VTS_MAX - mode->height, + 1, vblank_def); + + exposure_max = mode->vts_def - 4; + ar0822->exposure = v4l2_ctrl_new_std(handler, &ar0822_ctrl_ops, + V4L2_CID_EXPOSURE, AR0822_EXPOSURE_MIN, + exposure_max, AR0822_EXPOSURE_STEP, + mode->exp_def); + + ar0822->anal_gain = v4l2_ctrl_new_std(handler, &ar0822_ctrl_ops, + V4L2_CID_ANALOGUE_GAIN, AR0822_GAIN_MIN, + AR0822_GAIN_MAX, AR0822_GAIN_STEP, + AR0822_GAIN_DEFAULT); + + ar0822->test_pattern = v4l2_ctrl_new_std_menu_items(handler, + &ar0822_ctrl_ops, V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(ar0822_test_pattern_menu) - 1, + 0, 0, ar0822_test_pattern_menu); + + ar0822->h_flip = v4l2_ctrl_new_std(handler, &ar0822_ctrl_ops, + V4L2_CID_HFLIP, 0, 1, 1, 0); + + ar0822->v_flip = v4l2_ctrl_new_std(handler, &ar0822_ctrl_ops, + V4L2_CID_VFLIP, 0, 1, 1, 0); + ar0822->flip = 0; + if (handler->error) { + ret = handler->error; + dev_err(&ar0822->client->dev, + "Failed to init controls(%d)\n", ret); + goto err_free_handler; + } + + ar0822->subdev.ctrl_handler = handler; + ar0822->has_init_exp = false; + ar0822->long_hcg = false; + ar0822->middle_hcg = false; + ar0822->short_hcg = false; + + return 0; + +err_free_handler: + v4l2_ctrl_handler_free(handler); + + return ret; +} + +static int ar0822_check_sensor_id(struct ar0822 *ar0822, + struct i2c_client *client) +{ + struct device *dev = &ar0822->client->dev; + u32 id = 0; + int ret; + + if (ar0822->is_thunderboot) { + dev_info(dev, "Enable thunderboot mode, skip sensor id check\n"); + return 0; + } + + ret = ar0822_read_reg(client, AR0822_REG_CHIP_ID, + AR0822_REG_VALUE_16BIT, &id); + if (id != CHIP_ID) { + dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret); + return -ENODEV; + } + + dev_info(dev, "Detected ar0822%04x sensor\n", CHIP_ID); + + return 0; +} + +static int ar0822_configure_regulators(struct ar0822 *ar0822) +{ + unsigned int i; + + for (i = 0; i < AR0822_NUM_SUPPLIES; i++) + ar0822->supplies[i].supply = ar0822_supply_names[i]; + + return devm_regulator_bulk_get(&ar0822->client->dev, + AR0822_NUM_SUPPLIES, + ar0822->supplies); +} + +static int ar0822_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct device_node *node = dev->of_node; + struct ar0822 *ar0822; + struct v4l2_subdev *sd; + char facing[2]; + int ret; + u32 i, hdr_mode = 0; + + dev_info(dev, "driver version: %02x.%02x.%02x", + DRIVER_VERSION >> 16, + (DRIVER_VERSION & 0xff00) >> 8, + DRIVER_VERSION & 0x00ff); + + ar0822 = devm_kzalloc(dev, sizeof(*ar0822), GFP_KERNEL); + if (!ar0822) + return -ENOMEM; + + ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX, + &ar0822->module_index); + ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING, + &ar0822->module_facing); + ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME, + &ar0822->module_name); + ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME, + &ar0822->len_name); + if (ret) { + dev_err(dev, "could not get module information!\n"); + return -EINVAL; + } + + ar0822->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP); + ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE, + &hdr_mode); + if (ret) { + hdr_mode = NO_HDR; + dev_warn(dev, " Get hdr mode failed! no hdr default\n"); + } + ar0822->cfg_num = ARRAY_SIZE(supported_modes); + if(ar0822->cfg_num == 0){ + dev_err(dev, "no any supported mode providec, force exit probe!\n"); + return -EINVAL; + } + ar0822->cur_mode = &supported_modes[0];//initialize. + for (i = 0; i < ar0822->cfg_num; i++) { + if (hdr_mode == supported_modes[i].hdr_mode) { + ar0822->cur_mode = &supported_modes[i]; + break; + } + } + ar0822->client = client; + + ar0822->xvclk = devm_clk_get(dev, "xvclk"); + if (IS_ERR(ar0822->xvclk)) { + dev_err(dev, "Failed to get xvclk\n"); + return -EINVAL; + } + + ar0822->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS); + if (IS_ERR(ar0822->reset_gpio)) + dev_warn(dev, "Failed to get reset-gpios\n"); + + ar0822->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS); + if (IS_ERR(ar0822->pwdn_gpio)) + dev_warn(dev, "Failed to get pwdn-gpios\n"); + + ar0822->pinctrl = devm_pinctrl_get(dev); + if (!IS_ERR(ar0822->pinctrl)) { + ar0822->pins_default = + pinctrl_lookup_state(ar0822->pinctrl, + OF_CAMERA_PINCTRL_STATE_DEFAULT); + if (IS_ERR(ar0822->pins_default)) + dev_err(dev, "could not get default pinstate\n"); + + ar0822->pins_sleep = + pinctrl_lookup_state(ar0822->pinctrl, + OF_CAMERA_PINCTRL_STATE_SLEEP); + if (IS_ERR(ar0822->pins_sleep)) + dev_err(dev, "could not get sleep pinstate\n"); + } else { + dev_err(dev, "no pinctrl\n"); + } + + ret = ar0822_configure_regulators(ar0822); + if (ret) { + dev_err(dev, "Failed to get power regulators\n"); + return ret; + } + + mutex_init(&ar0822->mutex); + + sd = &ar0822->subdev; + v4l2_i2c_subdev_init(sd, client, &ar0822_subdev_ops); + ret = ar0822_initialize_controls(ar0822); + if (ret) + goto err_destroy_mutex; + + ret = __ar0822_power_on(ar0822); + if (ret) + goto err_free_handler; + + ret = ar0822_check_sensor_id(ar0822, client); + if (ret) + goto err_power_off; + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + sd->internal_ops = &ar0822_internal_ops; + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; +#endif +#if defined(CONFIG_MEDIA_CONTROLLER) + ar0822->pad.flags = MEDIA_PAD_FL_SOURCE; + sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = media_entity_pads_init(&sd->entity, 1, &ar0822->pad); + if (ret < 0) + goto err_power_off; +#endif + + memset(facing, 0, sizeof(facing)); + if (strcmp(ar0822->module_facing, "back") == 0) + facing[0] = 'b'; + else + facing[0] = 'f'; + + snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s", + ar0822->module_index, facing, + AR0822_NAME, dev_name(sd->dev)); + ret = v4l2_async_register_subdev_sensor_common(sd); + if (ret) { + dev_err(dev, "v4l2 async register subdev failed\n"); + goto err_clean_entity; + } + + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + pm_runtime_idle(dev); +#ifdef USED_SYS_DEBUG + add_sysfs_interfaces(dev); +#endif + return 0; + +err_clean_entity: +#if defined(CONFIG_MEDIA_CONTROLLER) + media_entity_cleanup(&sd->entity); +#endif +err_power_off: + __ar0822_power_off(ar0822); +err_free_handler: + v4l2_ctrl_handler_free(&ar0822->ctrl_handler); +err_destroy_mutex: + mutex_destroy(&ar0822->mutex); + + return ret; +} + +static int ar0822_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ar0822 *ar0822 = to_ar0822(sd); + + v4l2_async_unregister_subdev(sd); +#if defined(CONFIG_MEDIA_CONTROLLER) + media_entity_cleanup(&sd->entity); +#endif + v4l2_ctrl_handler_free(&ar0822->ctrl_handler); + mutex_destroy(&ar0822->mutex); + + pm_runtime_disable(&client->dev); + if (!pm_runtime_status_suspended(&client->dev)) + __ar0822_power_off(ar0822); + pm_runtime_set_suspended(&client->dev); + + return 0; +} + +#if IS_ENABLED(CONFIG_OF) +static const struct of_device_id ar0822_of_match[] = { + { .compatible = "onsemi,ar0822" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ar0822_of_match); +#endif + +static const struct i2c_device_id ar0822_match_id[] = { + { "onsemi,ar0822", 0 }, + { }, +}; + +static struct i2c_driver ar0822_i2c_driver = { + .driver = { + .name = AR0822_NAME, + .pm = &ar0822_pm_ops, + .of_match_table = of_match_ptr(ar0822_of_match), + }, + .probe = &ar0822_probe, + .remove = &ar0822_remove, + .id_table = ar0822_match_id, +}; + +#ifdef CONFIG_ROCKCHIP_THUNDER_BOOT +module_i2c_driver(ar0822_i2c_driver); +#else +static int __init sensor_mod_init(void) +{ + return i2c_add_driver(&ar0822_i2c_driver); +} + +static void __exit sensor_mod_exit(void) +{ + i2c_del_driver(&ar0822_i2c_driver); +} + +device_initcall_sync(sensor_mod_init); +module_exit(sensor_mod_exit); +#endif + +MODULE_DESCRIPTION("Onsemi ar0822 sensor driver"); +MODULE_LICENSE("GPL"); From 3325b43a1abbfc6f2e467aed56dcdb69f146343c Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Sat, 17 Jun 2023 17:04:28 +0800 Subject: [PATCH 22/27] drm/rockchip: vop2: move cubic lut to rockchip drm driver move cubic lut support from drm croe to rockchip drm driver and remove depend on NO_GKI. Signed-off-by: Sandy Huang Change-Id: I8fb6ba4fc927bf9f7e1b38c180986b1e25393347 --- drivers/gpu/drm/rockchip/Kconfig | 7 --- drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 3 ++ drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 3 ++ drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 46 +++++++++++--------- 4 files changed, 32 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig index 8d5dda562c88..3154597de251 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -20,13 +20,6 @@ config DRM_ROCKCHIP if DRM_ROCKCHIP -config ROCKCHIP_DRM_CUBIC_LUT - bool "Support 3D cubic LUT" - depends on NO_GKI - help - This add properties to support provision of a 3D cubic - look up table, allowing for color specific adjustments. - config ROCKCHIP_DRM_DEBUG bool "Rockchip DRM debug" depends on DEBUG_FS diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c index d5b93d57fd89..a731b593980f 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c @@ -1337,6 +1337,9 @@ static int rockchip_drm_create_properties(struct drm_device *dev) private->aclk_prop = drm_property_create_range(dev, 0, "ACLK", 0, UINT_MAX); private->bg_prop = drm_property_create_range(dev, 0, "BACKGROUND", 0, UINT_MAX); private->line_flag_prop = drm_property_create_range(dev, 0, "LINE_FLAG1", 0, UINT_MAX); + private->cubic_lut_prop = drm_property_create(dev, DRM_MODE_PROP_BLOB, "CUBIC_LUT", 0); + private->cubic_lut_size_prop = drm_property_create_range(dev, DRM_MODE_PROP_IMMUTABLE, + "CUBIC_LUT_SIZE", 0, UINT_MAX); return drm_mode_create_tv_properties(dev, 0, NULL); } diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h index 4c36d9b08638..153ccd07de52 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h @@ -255,6 +255,7 @@ struct rockchip_crtc_state { struct drm_property_blob *hdr_ext_data; struct drm_property_blob *acm_lut_data; struct drm_property_blob *post_csc_data; + struct drm_property_blob *cubic_lut_data; int request_refresh_rate; int max_refresh_rate; @@ -452,6 +453,8 @@ struct rockchip_drm_private { struct drm_property *aclk_prop; struct drm_property *bg_prop; struct drm_property *line_flag_prop; + struct drm_property *cubic_lut_prop; + struct drm_property *cubic_lut_size_prop; /* private plane prop */ struct drm_property *eotf_prop; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index ed50bb2fee1f..ecaacd9f8052 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -3524,7 +3524,6 @@ static int vop2_crtc_atomic_gamma_set(struct drm_crtc *crtc, return 0; } -#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT) static int vop2_crtc_atomic_cubic_lut_set(struct drm_crtc *crtc, struct drm_crtc_state *old_state) { @@ -3597,18 +3596,12 @@ static int vop2_crtc_atomic_cubic_lut_set(struct drm_crtc *crtc, return 0; } -static void drm_crtc_enable_cubic_lut(struct drm_crtc *crtc, unsigned int cubic_lut_size) +static void vop2_attach_cubic_lut_prop(struct drm_crtc *crtc, unsigned int cubic_lut_size) { - struct drm_device *dev = crtc->dev; - struct drm_mode_config *config = &dev->mode_config; + struct rockchip_drm_private *private = crtc->dev->dev_private; - if (cubic_lut_size) { - drm_object_attach_property(&crtc->base, - config->cubic_lut_property, 0); - drm_object_attach_property(&crtc->base, - config->cubic_lut_size_property, - cubic_lut_size); - } + drm_object_attach_property(&crtc->base, private->cubic_lut_prop, 0); + drm_object_attach_property(&crtc->base, private->cubic_lut_size_prop, cubic_lut_size); } static void vop2_cubic_lut_init(struct vop2 *vop2) @@ -3628,12 +3621,9 @@ static void vop2_cubic_lut_init(struct vop2 *vop2) vp->cubic_lut_len = vp_data->cubic_lut_len; if (vp->cubic_lut_len) - drm_crtc_enable_cubic_lut(crtc, vp->cubic_lut_len); + vop2_attach_cubic_lut_prop(crtc, vp->cubic_lut_len); } } -#else -static void vop2_cubic_lut_init(struct vop2 *vop2) { } -#endif static int vop2_core_clks_prepare_enable(struct vop2 *vop2) { @@ -9755,13 +9745,11 @@ static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state vp->gamma_lut = crtc->state->gamma_lut->data; vop2_crtc_atomic_gamma_set(crtc, crtc->state); } -#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT) - if (crtc->state->cubic_lut || vp->cubic_lut) { - if (crtc->state->cubic_lut) - vp->cubic_lut = crtc->state->cubic_lut->data; + if (vcstate->cubic_lut_data || vp->cubic_lut) { + if (vcstate->cubic_lut_data) + vp->cubic_lut = vcstate->cubic_lut_data->data; vop2_crtc_atomic_cubic_lut_set(crtc, crtc->state); } -#endif } else { VOP_MODULE_SET(vop2, vp, cubic_lut_update_en, 0); } @@ -9874,6 +9862,8 @@ static struct drm_crtc_state *vop2_crtc_duplicate_state(struct drm_crtc *crtc) drm_property_blob_get(vcstate->acm_lut_data); if (vcstate->post_csc_data) drm_property_blob_get(vcstate->post_csc_data); + if (vcstate->cubic_lut_data) + drm_property_blob_get(vcstate->cubic_lut_data); __drm_atomic_helper_crtc_duplicate_state(crtc, &vcstate->base); return &vcstate->base; @@ -9888,6 +9878,7 @@ static void vop2_crtc_destroy_state(struct drm_crtc *crtc, drm_property_blob_put(vcstate->hdr_ext_data); drm_property_blob_put(vcstate->acm_lut_data); drm_property_blob_put(vcstate->post_csc_data); + drm_property_blob_put(vcstate->cubic_lut_data); kfree(vcstate); } @@ -10034,6 +10025,11 @@ static int vop2_crtc_atomic_get_property(struct drm_crtc *crtc, return 0; } + if (property == private->cubic_lut_prop) { + *val = (vcstate->cubic_lut_data) ? vcstate->cubic_lut_data->base.id : 0; + return 0; + } + DRM_ERROR("failed to get vop2 crtc property: %s\n", property->name); return -EINVAL; @@ -10159,6 +10155,16 @@ static int vop2_crtc_atomic_set_property(struct drm_crtc *crtc, return ret; } + if (property == private->cubic_lut_prop) { + ret = vop2_atomic_replace_property_blob_from_id(drm_dev, + &vcstate->cubic_lut_data, + val, + -1, sizeof(struct drm_color_lut), + &replaced); + state->color_mgmt_changed |= replaced; + return ret; + } + DRM_ERROR("failed to set vop2 crtc property %s\n", property->name); return -EINVAL; From 7f9e600004fd89f9f630a5faccfaa4d5a033e67a Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Sat, 17 Jun 2023 17:08:10 +0800 Subject: [PATCH 23/27] Revert "FROMLIST: drm: Extend color correction to support 3D-CLU" This reverts commit 4b81d4e5602a5b09ce084ef10656ac2e76b09987. Change-Id: I501bc346b574df3143a505abb509e331a5afc7b6 Signed-off-by: Sandy Huang --- drivers/gpu/drm/drm_atomic_helper.c | 3 -- drivers/gpu/drm/drm_atomic_state_helper.c | 7 ---- drivers/gpu/drm/drm_atomic_uapi.c | 14 -------- drivers/gpu/drm/drm_color_mgmt.c | 41 ++++------------------- drivers/gpu/drm/drm_mode_config.c | 16 --------- include/drm/drm_crtc.h | 11 +----- include/drm/drm_mode_config.h | 13 ------- 7 files changed, 8 insertions(+), 97 deletions(-) diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 33768ddfaacb..7fc8e7000046 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -3554,9 +3554,6 @@ int drm_atomic_helper_legacy_gamma_set(struct drm_crtc *crtc, replaced = drm_property_replace_blob(&crtc_state->degamma_lut, NULL); replaced |= drm_property_replace_blob(&crtc_state->ctm, NULL); replaced |= drm_property_replace_blob(&crtc_state->gamma_lut, blob); -#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT) - replaced |= drm_property_replace_blob(&crtc_state->cubic_lut, NULL); -#endif crtc_state->color_mgmt_changed |= replaced; ret = drm_atomic_commit(state); diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index c29183d2aa4e..9ad74045158e 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -141,10 +141,6 @@ void __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc, drm_property_blob_get(state->ctm); if (state->gamma_lut) drm_property_blob_get(state->gamma_lut); -#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT) - if (state->cubic_lut) - drm_property_blob_get(state->cubic_lut); -#endif state->mode_changed = false; state->active_changed = false; state->planes_changed = false; @@ -217,9 +213,6 @@ void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc_state *state) drm_property_blob_put(state->degamma_lut); drm_property_blob_put(state->ctm); drm_property_blob_put(state->gamma_lut); -#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT) - drm_property_blob_put(state->cubic_lut); -#endif } EXPORT_SYMBOL(__drm_atomic_helper_crtc_destroy_state); diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 975ece7e00a4..25c269bc4681 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -459,16 +459,6 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, &replaced); state->color_mgmt_changed |= replaced; return ret; -#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT) - } else if (property == config->cubic_lut_property) { - ret = drm_atomic_replace_property_blob_from_id(dev, - &state->cubic_lut, - val, - -1, sizeof(struct drm_color_lut), - &replaced); - state->color_mgmt_changed |= replaced; - return ret; -#endif } else if (property == config->prop_out_fence_ptr) { s32 __user *fence_ptr = u64_to_user_ptr(val); @@ -511,10 +501,6 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc, *val = (state->ctm) ? state->ctm->base.id : 0; else if (property == config->gamma_lut_property) *val = (state->gamma_lut) ? state->gamma_lut->base.id : 0; -#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT) - else if (property == config->cubic_lut_property) - *val = (state->cubic_lut) ? state->cubic_lut->base.id : 0; -#endif else if (property == config->prop_out_fence_ptr) *val = 0; else if (crtc->funcs->atomic_get_property) diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 7b270b68ade4..138ff34b31db 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -33,7 +33,7 @@ /** * DOC: overview * - * Color management or color space adjustments is supported through a set of 7 + * Color management or color space adjustments is supported through a set of 5 * properties on the &drm_crtc object. They are set up by calling * drm_crtc_enable_color_mgmt(). * @@ -60,7 +60,7 @@ * “CTM”: * Blob property to set the current transformation matrix (CTM) apply to * pixel data after the lookup through the degamma LUT and before the - * lookup through the cubic LUT. The data is interpreted as a struct + * lookup through the gamma LUT. The data is interpreted as a struct * &drm_color_ctm. * * Setting this to NULL (blob property value set to 0) means a @@ -68,40 +68,13 @@ * boot-up state too. Drivers can access the blob for the color conversion * matrix through &drm_crtc_state.ctm. * - * ”CUBIC_LUT”: - * Blob property to set the cubic (3D) lookup table performing color - * mapping after the transformation matrix and before the lookup through - * the gamma LUT. Unlike the degamma and gamma LUTs that map color - * components independently, the 3D LUT converts an input color to an - * output color by indexing into the 3D table using the color components - * as a 3D coordinate. The LUT is subsampled as 8-bit (or more) precision - * would require too much storage space in the hardware, so the precision - * of the color components is reduced before the look up, and the low - * order bits may be used to interpolate between the nearest points in 3D - * space. - * - * The data is interpreted as an array of &struct drm_color_lut elements. - * Hardware might choose not to use the full precision of the LUT - * elements. - * - * Setting this to NULL (blob property value set to 0) means the output - * color is identical to the input color. This is generally the driver - * boot-up state too. Drivers can access this blob through - * &drm_crtc_state.cubic_lut. - * - * ”CUBIC_LUT_SIZE”: - * Unsigned range property to give the size of the lookup table to be set - * on the CUBIC_LUT property (the size depends on the underlying hardware). - * If drivers support multiple LUT sizes then they should publish the - * largest size, and sub-sample smaller sized LUTs appropriately. - * * “GAMMA_LUT”: * Blob property to set the gamma lookup table (LUT) mapping pixel data - * after the cubic LUT to data sent to the connector. The data is - * interpreted as an array of &struct drm_color_lut elements. Hardware - * might choose not to use the full precision of the LUT elements nor use - * all the elements of the LUT (for example the hardware might choose to - * interpolate between LUT[0] and LUT[4]). + * after the transformation matrix to data sent to the connector. The + * data is interpreted as an array of &struct drm_color_lut elements. + * Hardware might choose not to use the full precision of the LUT elements + * nor use all the elements of the LUT (for example the hardware might + * choose to interpolate between LUT[0] and LUT[4]). * * Setting this to NULL (blob property value set to 0) means a * linear/pass-thru gamma table should be used. This is generally the diff --git a/drivers/gpu/drm/drm_mode_config.c b/drivers/gpu/drm/drm_mode_config.c index f7f21dfc4f47..f1affc1bb679 100644 --- a/drivers/gpu/drm/drm_mode_config.c +++ b/drivers/gpu/drm/drm_mode_config.c @@ -364,22 +364,6 @@ static int drm_mode_create_standard_properties(struct drm_device *dev) return -ENOMEM; dev->mode_config.gamma_lut_size_property = prop; -#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT) - prop = drm_property_create(dev, - DRM_MODE_PROP_BLOB, - "CUBIC_LUT", 0); - if (!prop) - return -ENOMEM; - dev->mode_config.cubic_lut_property = prop; - - prop = drm_property_create_range(dev, - DRM_MODE_PROP_IMMUTABLE, - "CUBIC_LUT_SIZE", 0, UINT_MAX); - if (!prop) - return -ENOMEM; - dev->mode_config.cubic_lut_size_property = prop; -#endif - prop = drm_property_create(dev, DRM_MODE_PROP_IMMUTABLE | DRM_MODE_PROP_BLOB, "IN_FORMATS", 0); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 3a3d9d887cad..59b51a09cae6 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -287,16 +287,7 @@ struct drm_crtc_state { * NULL) is an array of &struct drm_color_lut. */ struct drm_property_blob *gamma_lut; -#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT) - /** - * @cubic_lut: - * - * Cubic Lookup table for converting pixel data. See - * drm_crtc_enable_color_mgmt(). The blob (if not NULL) is a 3D array - * of &struct drm_color_lut. - */ - struct drm_property_blob *cubic_lut; -#endif + /** * @target_vblank: * diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h index 76d114569484..a18f73eb3cf6 100644 --- a/include/drm/drm_mode_config.h +++ b/include/drm/drm_mode_config.h @@ -794,19 +794,6 @@ struct drm_mode_config { */ struct drm_property *gamma_lut_size_property; -#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT) - /** - * @cubic_lut_property: Optional CRTC property to set the 3D LUT used to - * convert color spaces. - */ - struct drm_property *cubic_lut_property; - /** - * @cubic_lut_size_property: Optional CRTC property for the size of the - * 3D LUT as supported by the driver (read-only). - */ - struct drm_property *cubic_lut_size_property; -#endif - /** * @suggested_x_property: Optional connector property with a hint for * the position of the output on the host's screen. From 79f0bdb4fc7d3e5b4a73b806d3cf441de9a005ba Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Sat, 17 Jun 2023 17:35:43 +0800 Subject: [PATCH 24/27] Revert "arm64: rockchip_defconfig: enable CONFIG_ROCKCHIP_DRM_CUBIC_LUT" This reverts commit d7c77171a7477ef5f7eca65de82977b7f49f9434. Signed-off-by: Sandy Huang Change-Id: Ifff2f6bccc17c78fd6d449613da8b9c352293c70 --- arch/arm64/configs/rockchip_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/configs/rockchip_defconfig b/arch/arm64/configs/rockchip_defconfig index 835b0b66c925..7aae017d80a9 100644 --- a/arch/arm64/configs/rockchip_defconfig +++ b/arch/arm64/configs/rockchip_defconfig @@ -619,7 +619,6 @@ CONFIG_DRM_IGNORE_IOTCL_PERMIT=y CONFIG_DRM_DP_AUX_CHARDEV=y CONFIG_DRM_LOAD_EDID_FIRMWARE=y CONFIG_DRM_ROCKCHIP=y -CONFIG_ROCKCHIP_DRM_CUBIC_LUT=y CONFIG_ROCKCHIP_ANALOGIX_DP=y CONFIG_ROCKCHIP_CDN_DP=y CONFIG_ROCKCHIP_DRM_TVE=y From 4fa16359d69f30513a29231d38c4cd68aaa5e4bd Mon Sep 17 00:00:00 2001 From: Yifeng Zhao Date: Tue, 27 Jun 2023 11:14:19 +0800 Subject: [PATCH 25/27] mmc: sdhci-of-dwcmshc: support HS400ES for RK3568 Signed-off-by: Yifeng Zhao Change-Id: I0491bcb3def6e1f5975a94b8e8921027a9d6e271 --- drivers/mmc/host/sdhci-of-dwcmshc.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index 9db254ef6484..ae9a2a9c36bf 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -335,17 +335,19 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); txclk_tapnum = drv_data->hs200_tx_tap; - if ((drv_data->flags & RK_DLL_CMD_OUT) && - host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { + if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { txclk_tapnum = drv_data->hs400_tx_tap; - extra = DLL_CMDOUT_SRC_CLK_NEG | - DLL_CMDOUT_BOTH_CLK_EDGE | - DWCMSHC_EMMC_DLL_DLYENA | - drv_data->hs400_cmd_tap | - DLL_CMDOUT_TAPNUM_FROM_SW; - if (drv_data->flags & RK_TAP_VALUE_SEL) - extra |= DLL_TAP_VALUE_SEL | dll_lock_value << DLL_TAP_VALUE_OFFSET; - sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT); + + if (drv_data->flags & RK_DLL_CMD_OUT) { + extra = DLL_CMDOUT_SRC_CLK_NEG | + DLL_CMDOUT_BOTH_CLK_EDGE | + DWCMSHC_EMMC_DLL_DLYENA | + drv_data->hs400_cmd_tap | + DLL_CMDOUT_TAPNUM_FROM_SW; + if (drv_data->flags & RK_TAP_VALUE_SEL) + extra |= DLL_TAP_VALUE_SEL | dll_lock_value << DLL_TAP_VALUE_OFFSET; + sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT); + } } extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_TXCLK_TAPNUM_FROM_SW | From 96a4ade24fbd16171aec7e19cfd11b2d0893c233 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Sun, 25 Jun 2023 09:09:11 +0800 Subject: [PATCH 26/27] drm/rockchip: lvds: update MEDIA_BUS_FMT_RGB666_1X7X3_SPWG description Refer to the following information: https://www.kernel.org/doc/Documentation/devicetree/bindings/display/panel/panel-lvds.txt Signed-off-by: Sandy Huang Change-Id: I9ea389605940911d576e5ed0c0be20f892f41390 --- drivers/gpu/drm/rockchip/rockchip_lvds.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c index d4bd2fbfca0b..cd74e98e2f8c 100644 --- a/drivers/gpu/drm/rockchip/rockchip_lvds.c +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c @@ -83,8 +83,8 @@ enum lvds_format { LVDS_8BIT_MODE_FORMAT_1, LVDS_8BIT_MODE_FORMAT_2, - LVDS_8BIT_MODE_FORMAT_3, - LVDS_6BIT_MODE, + LVDS_6BIT_MODE_FORMAT_1, + LVDS_6BIT_MODE_FORMAT_2, LVDS_10BIT_MODE_FORMAT_1, LVDS_10BIT_MODE_FORMAT_2, }; @@ -190,8 +190,8 @@ rockchip_lvds_encoder_atomic_mode_set(struct drm_encoder *encoder, case MEDIA_BUS_FMT_RGB101010_1X7X5_JEIDA: /* jeida-30 */ lvds->format = LVDS_10BIT_MODE_FORMAT_2; break; - case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: /* vesa-18 */ - lvds->format = LVDS_8BIT_MODE_FORMAT_3; + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: /* jeida-18, compatible with the [JEIDA], [LDI] and [VESA] specifications */ + lvds->format = LVDS_6BIT_MODE_FORMAT_1; break; case MEDIA_BUS_FMT_RGB101010_1X7X5_SPWG: /* vesa-30 */ lvds->format = LVDS_10BIT_MODE_FORMAT_1; From ce5da098c4cd46deb075845111383d9fd34afa7a Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Fri, 16 Jun 2023 16:49:50 +0800 Subject: [PATCH 27/27] drm/rockchip: vop2: update rk3568 max height limit Signed-off-by: Sandy Huang Change-Id: Ic323e783452e1d97a0b4df955ad7d11ead8da17a --- drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index eb1433456af6..ae95fb5b3d3a 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -1256,7 +1256,7 @@ static const struct vop2_video_port_data rk3568_vop_video_ports[] = { VOP_FEATURE_HDR10 | VOP_FEATURE_OVERSCAN, .gamma_lut_len = 1024, .cubic_lut_len = 729, /* 9x9x9 */ - .max_output = { 4096, 2304 }, + .max_output = { 4096, 4096 }, .pre_scan_max_dly = { 69, 53, 53, 42 }, .intr = &rk3568_vp0_intr, .hdr_table = &rk3568_vop_hdr_table, @@ -1267,7 +1267,7 @@ static const struct vop2_video_port_data rk3568_vop_video_ports[] = { .soc_id = { 0x3568, 0x3566 }, .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN, .gamma_lut_len = 1024, - .max_output = { 2048, 1536 }, + .max_output = { 2048, 2048 }, .pre_scan_max_dly = { 40, 40, 40, 40 }, .intr = &rk3568_vp1_intr, .regs = &rk3568_vop_vp1_regs, @@ -1277,7 +1277,7 @@ static const struct vop2_video_port_data rk3568_vop_video_ports[] = { .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN, .soc_id = { 0x3568, 0x3566 }, .gamma_lut_len = 1024, - .max_output = { 1920, 1080 }, + .max_output = { 1920, 1920 }, .pre_scan_max_dly = { 40, 40, 40, 40 }, .intr = &rk3568_vp2_intr, .regs = &rk3568_vop_vp2_regs,