Commit Graph

5898 Commits

Author SHA1 Message Date
Giovanni Mascellani
7b36453b9d vkd3d-shader/ir: Check that PRIMID registers have dimension SCALAR. 2025-07-22 14:55:18 +02:00
Giovanni Mascellani
b3c1fb6740 vkd3d-shader/ir: Check that OUTPOINTID registers have dimension SCALAR. 2025-07-22 14:55:18 +02:00
Giovanni Mascellani
dfc18781cc vkd3d-shader/ir: Check that GSINSTID registers have dimension SCALAR. 2025-07-22 14:55:18 +02:00
Giovanni Mascellani
b02c3759be vkd3d-shader/ir: Check that SAMPLEMASK registers have dimension SCALAR.
Also fix the DXIL parser to emit them accordingly.
2025-07-22 14:55:18 +02:00
Giovanni Mascellani
226afa47c4 vkd3d-shader/ir: Check that THREADID registers have dimension VEC4. 2025-07-22 14:55:18 +02:00
Elizabeth Figura
f0906e9c5c vkd3d-shader/spirv: Use left-shifted writemasks for private variables for inputs.
One of the effects of I/O normalization, when it was introduced, was to shift
the writemask of all semantics to become 0-based—e.g., to convert .yz to .xy.
It did this by modifying the shader code, but did *not* modify the signature
masks.

The SPIR-V compiler, at the time, used both the write mask on the dcl_input
instruction and the signature masks. It also, due to the requirements of the
SPIR-V format, performed the same normalization, left-shifting each mask to
become zero-based. Despite this normalization now being performed earlier in
the aforementioned VSIR pass, the handling in the SPIR-V backend was never
removed.

When 66cb2815f0 was written, I either incorrectly
assumed that the signature mask was equal to the dcl_input write mask (at least,
in any well-formed shader), or (less likely) I noticed that the discrepancy
might exist but believed that the left-shifting normalization performed by the
spirv compiler covered all cases.

In either case it turns out there is one case where the difference was not
handled by the spirv compiler either. That is the case of a varying which has
a fixup function and therefore needs a private variable, which is currently true
for the SV_VertexID, SV_InstanceID, and SV_IsFrontFace varyings.

Thus, if one of those varyings has a signature mask other than .x, we currently
copy the SPIR-V builtin value to the relevant component of the private variable,
but subsequent code will load from the .x variable due to the normalization done
by shader_src_param_io_normalise().

This fixes a regression introduced by 66cb2815f0.

Wine-Bug: https://bugs.winehq.org/show_bug.cgi?id=57433
2025-07-22 14:51:09 +02:00
Giovanni Mascellani
decc155cca vkd3d-shader/ir: Split updating DCL_TEMPS instructions to a dedicated pass.
So that it can be used in other contexts as well. And so that
register allocation can be run also when there is no need to update
or create DCL_TEMPS instructions.
2025-07-21 12:31:08 +02:00
Giovanni Mascellani
079e989b8e vkd3d-shader/ir: Update the program TEMP count when allocating TEMP registers. 2025-07-21 12:26:10 +02:00
Giovanni Mascellani
f5cd0b4a15 vkd3d-shader/ir: Check that THREADGROUPID registers have dimension VEC4. 2025-07-21 12:23:34 +02:00
Giovanni Mascellani
59253a5e7f vkd3d-shader/ir: Check that LOCALTHREADID registers have dimension VEC4. 2025-07-21 12:23:34 +02:00
Giovanni Mascellani
834f762cb5 vkd3d-shader/ir: Check that DEPTHOUTLE registers have dimension SCALAR.
Also fix the DXIL parser to emit them accordingly.
2025-07-21 12:23:34 +02:00
Giovanni Mascellani
18ef9a4f9f vkd3d-shader/ir: Check that DEPTHOUTGE registers have dimension SCALAR.
Also fix the DXIL parser to emit them accordingly.
2025-07-21 12:23:34 +02:00
Giovanni Mascellani
9f453fbb66 vkd3d-shader/ir: Check that DEPTHOUT registers have dimension SCALAR.
Also fix the DXIL parser to emit them accordingly.
2025-07-21 12:23:32 +02:00
Giovanni Mascellani
3d23ef6bf8 vkd3d-shader/ir: Check that COVERAGE registers have dimension VEC4.
Also fix the HLSL compiler and DXIL parser to emit them accordingly.
2025-07-21 12:21:23 +02:00
Giovanni Mascellani
ee0447b973 vkd3d-shader/ir: Check that LOCALTHREADINDEX registers have dimension VEC4.
Also fix the HLSL compiler and DXIL parser to emit them accordingly.
2025-07-21 12:18:49 +02:00
Giovanni Mascellani
61c46f95da vkd3d-shader/ir: Validate MUL operations. 2025-07-21 12:16:16 +02:00
Giovanni Mascellani
87545dc4fd vkd3d-shader/ir: Validate MIN operations. 2025-07-21 12:16:16 +02:00
Giovanni Mascellani
366c899a00 vkd3d-shader/ir: Validate MAX operations. 2025-07-21 12:16:16 +02:00
Giovanni Mascellani
5dd226ffeb vkd3d-shader/ir: Validate MAD operations. 2025-07-21 12:16:16 +02:00
Giovanni Mascellani
2237e251fa vkd3d-shader/ir: Validate LTU operations. 2025-07-21 12:16:16 +02:00
Giovanni Mascellani
34cb8c63f4 vkd3d-shader/ir: Validate LTO operations. 2025-07-21 12:16:14 +02:00
Giovanni Mascellani
a8e8a9ee64 vkd3d-shader/ir: Validate LOG operations. 2025-07-21 12:14:22 +02:00
Henri Verbeet
db149cd8cf vkd3d-shader/ir: Rename VKD3D_DATA_DOUBLE to VSIR_DATA_F64. 2025-07-21 12:10:43 +02:00
Henri Verbeet
c5c1c03430 vkd3d-shader/ir: Rename VKD3D_DATA_FLOAT to VSIR_DATA_F32. 2025-07-21 12:10:43 +02:00
Henri Verbeet
d1dcbc26e5 vkd3d-shader/ir: Rename VKD3D_DATA_HALF to VSIR_DATA_F16. 2025-07-21 12:10:43 +02:00