Commit Graph

475 Commits

Author SHA1 Message Date
Elizabeth Figura
bfa655a01f vkd3d-shader/ir: Use the .w component of the existing swizzle when lowering texldb. 2025-05-14 15:07:46 +02:00
Elizabeth Figura
d40422592a vkd3d-shader/ir: Merge tess factor used masks together.
Encountered with the domain shader in
test_domain_shader_one_patch_constant_input().
2025-05-14 14:09:21 +02:00
Elizabeth Figura
315247bf02 vkd3d-shader: Normalize TEXKILL to use a source register. 2025-04-30 16:51:44 +02:00
Andrey Gusev
8882d324a6 vkd3d-shader/ir: Store the actual return value in shader_signature_map_patch_constant_index_ranges(). 2025-04-28 12:49:27 +02:00
Giovanni Mascellani
c764f71cf5 vkd3d-shader/ir: Validate that DEPTHOUTLE registers aren't used as sources. 2025-04-16 16:46:38 +02:00
Giovanni Mascellani
ee7895465c vkd3d-shader/ir: Validate that DEPTHOUTGE registers aren't used as sources. 2025-04-16 16:46:28 +02:00
Giovanni Mascellani
834017c198 vkd3d-shader/ir: Validate that DEPTHOUT registers aren't used as sources. 2025-04-16 16:46:05 +02:00
Giovanni Mascellani
922cb47a4b vkd3d-shader/ir: Validate descriptor counts in vsir programs. 2025-04-16 15:56:59 +02:00
Giovanni Mascellani
be94a37e23 vkd3d-shader/ir: Validate descriptor resource data types in vsir programs. 2025-04-16 15:52:46 +02:00
Giovanni Mascellani
01f47e00f2 vkd3d-shader/ir: Validate descriptor resource types in vsir programs. 2025-04-16 15:49:32 +02:00
Giovanni Mascellani
0da80c1f25 vkd3d-shader/ir: Validate descriptor types in vsir programs. 2025-04-16 15:46:20 +02:00
Elizabeth Figura
0c18736370 vkd3d-shader/ir: Validate SSA write masks. 2025-04-14 15:32:15 +02:00
Elizabeth Figura
d91d552a5e vkd3d-shader/ir: Introduce a vsir_dst_param_init_null() helper. 2025-04-14 15:32:12 +02:00
Francisco Casas
4b9c23272a vkd3d-shader/ir: Reset instruction pointers after shader_instruction_array_insert_at().
Every call to shader_instruction_array_insert_at() means a possible
reallocation of all vsir instructions in the program. This means that all
previous pointers are potentially no longer valid.

We are currently using these potentially invalid pointers in some cases,
usually in the form of "ins->location". This commit fixes these.

I moved all pointer changes to right after the call to
shader_instruction_array_insert_at() to make this more evident.
2025-04-02 19:25:12 +02:00
Giovanni Mascellani
875c5df519 vkd3d-shader/ir: Validate register id and index for CONSTBUFFER registers. 2025-04-02 19:24:10 +02:00
Giovanni Mascellani
c181f147ce vkd3d-shader/ir: Validate register id and index for SAMPLER registers. 2025-04-02 19:08:50 +02:00
Giovanni Mascellani
9b7256c0c8 vkd3d-shader/ir: Validate register id and index for UAV registers. 2025-04-02 19:08:00 +02:00
Giovanni Mascellani
10d8760134 vkd3d-shader/ir: Validate register id and index for RESOURCE registers. 2025-04-02 19:06:43 +02:00
Francisco Casas
f65e6265e0 vkd3d-shader/ir: Normalise MOVA and d3dbc indirect addressing. 2025-04-02 18:27:16 +02:00
Giovanni Mascellani
2377db33db vkd3d-shader: Represent descriptor information in the vsir program. 2025-03-18 15:38:01 +01:00
Giovanni Mascellani
674614cc7a vkd3d-shader/ir: Disallow IMMCONSTBUFFER registers in destination parameters. 2025-03-17 15:12:13 +01:00
Giovanni Mascellani
0761d73e9c vkd3d-shader/ir: Disallow CONSTBUFFER registers in destination parameters. 2025-03-17 15:12:13 +01:00
Giovanni Mascellani
0c9c29fb34 vkd3d-shader/ir: Validate CONSTBUFFER registers. 2025-03-17 15:11:52 +01:00
Henri Verbeet
fe4143ad19 vkd3d-shader/dxil: Generate I/O signatures with 16-bit component types for native 16-bit shaders.
Which incidentally matches the I/O signatures from the DXBC container.
2025-02-24 15:10:08 +01:00
Giovanni Mascellani
4b84fb486b vkd3d-shader/ir: Handle index ranges that do not touch a signature element for each register.
A good part of the I/O normaliser job is to merge together signature
elements that are spanned by DCL_INDEX_RANGE instructions. The
current algorithm assumes that each index range touches exactly
one signature element for each index spanned by the range. The
assumption is used in shader_signature_merge() in the form of
expecting that, if the index range is N registers long, then,
once you find the first signature element of an index range, the
other elements that will have to be merged with it are exactly the
following N-1 according to the order given by
signature_element_register_compare() or
signature_element_mask_compare(), depending on the signature type.

This doesn't necessarily happen. For example, The Falconeer has a
few hull shaders in which this happens:

    hs_fork_phase
    dcl_hs_fork_phase_instance_count 13
    dcl_input vForkInstanceId
    dcl_output o4.z
    dcl_output o5.z
    dcl_output o6.z
    dcl_output o7.z
    dcl_output o12.z
    dcl_output o13.z
    dcl_output o14.z
    dcl_output o15.z
    dcl_output o16.z
    dcl_output o17.z
    dcl_output o18.z
    dcl_output o19.z
    dcl_output o20.z
    dcl_temps 1
    dcl_index_range o4.z 17
    iadd r0.x, vForkInstanceId.x, l(4)
    ult r0.y, vForkInstanceId.x, l(4)
    movc r0.x, r0.y, vForkInstanceId.x, r0.x
    mov o[r0.x + 4].z, l(0)
    ret

Here the index range "skips" o8.z through o11.z, because those
registers only use mask .xy. The current algorithm fails on such
a shader.

Even depending on the signature element order doesn't look ideal.
I don't have a full counterexample for that, but it looks fragile,
especially given that the register allocation algorithm in FXC is
notoriously full of unexpected corner cases.

We solve both problems by slightly changing the architecture of
the normaliser: first we move computing the masks for the merge
signature element from signature_element_range_expand_mask(),
which is executed while merging signature, to
io_normaliser_add_index_range(), which is executed before merging
signatures. Then, while we are merging signatures, we can decide
for each single signature element whether it has to be retained
or not, and how it should be patched. The algorithm becomes
independent of the order, because each signature element can be
processed individually.
2025-02-19 17:30:00 +01:00