Shaun Ren
d5770cd347
vkd3d-shader/hlsl: Add support for the centroid interpolation mode in SM1.
2025-10-06 15:18:50 +02:00
Elizabeth Figura
322c91e3f8
vkd3d-shader/ir: Introduce a vsir DCE pass.
2025-10-06 14:38:32 +02:00
Francisco Casas
bdba25d028
vkd3d-shader: Store a vkd3d_result in struct vkd3d_shader_parser.
2025-10-02 23:40:51 +02:00
Henri Verbeet
89b05594f5
vkd3d-shader/d3dbc: Don't call vsir_update_dcl_temps().
2025-09-19 12:48:08 +02:00
Henri Verbeet
84d3a8d167
vkd3d-shader/hlsl: Use VKD3DSPR_COMBINED_SAMPLER destination operands in sm1_generate_vsir_sampler_dcls().
...
That's what the d3d-asm target expects in shader_print_dcl_usage(), and
what vkd3d_shader_scan() requires to create correct descriptor
information.
2025-09-11 16:09:46 +02:00
Henri Verbeet
3b41d99fa9
vkd3d-shader/tpf: Store a pointer to the vsir program in struct vkd3d_shader_sm4_parser.
2025-08-21 16:28:28 +02:00
Henri Verbeet
4039476c50
vkd3d-shader/d3dbc: Store a pointer to the vsir program in struct vkd3d_shader_sm1_parser.
2025-08-21 16:28:28 +02:00
Elizabeth Figura
a4f69d4ae6
vkd3d-shader/d3dbc: Move TEXLD lowering to d3dbc_parse().
2025-08-07 18:52:46 +02:00
Giovanni Mascellani
bb51b976df
vkd3d-shader/ir: Use size_t in the parameter allocator.
...
The idea is to, by default, use size_t for any quantity that is
a memory size or an array index.
2025-07-23 17:16:38 +02:00
Nikolay Sivov
83e54bdc0c
vkd3d-shader/hlsl: Handle HLSL_RESOURCE_SAMPLE_LOD in sm1_generate_vsir_instr_resource_load().
...
Wine-Bug: https://bugs.winehq.org/show_bug.cgi?id=58063
2025-07-23 17:06:21 +02:00
Giovanni Mascellani
14ee6b86e0
vkd3d-shader/d3dbc: Use iterators in d3dbc_write_program_instructions().
2025-07-22 17:11:19 +02:00
Giovanni Mascellani
4a1ca99cba
vkd3d-shader/d3dbc: Use vsir_program_append() in d3dbc_parse().
2025-07-22 17:11:19 +02:00
Henri Verbeet
742cce9a08
vkd3d-shader/ir: Rename VKD3D_DATA_UINT to VSIR_DATA_U32.
2025-07-22 14:57:26 +02:00
Henri Verbeet
a04e4e4010
vkd3d-shader/ir: Rename VKD3D_DATA_INT to VSIR_DATA_I32.
2025-07-22 14:57:26 +02:00
Giovanni Mascellani
decc155cca
vkd3d-shader/ir: Split updating DCL_TEMPS instructions to a dedicated pass.
...
So that it can be used in other contexts as well. And so that
register allocation can be run also when there is no need to update
or create DCL_TEMPS instructions.
2025-07-21 12:31:08 +02:00
Henri Verbeet
c5c1c03430
vkd3d-shader/ir: Rename VKD3D_DATA_FLOAT to VSIR_DATA_F32.
2025-07-21 12:10:43 +02:00
Henri Verbeet
0126beb3b2
vkd3d-shader/ir: Rename enum vkd3d_data_type to vsir_data_type.
2025-07-21 12:10:43 +02:00
Henri Verbeet
d219cccc99
vkd3d-shader/ir: Rename the VKD3DSIH_* enum elements to VSIR_OP_*.
2025-06-25 15:53:41 +02:00
Elizabeth Figura
ecb19b33ba
vkd3d-shader/hlsl: Output sm1 semantics with unique register_index values.
...
Match the register_index values from the d3dbc reader.
2025-06-25 15:43:15 +02:00
Henri Verbeet
be2c8041d0
vkd3d-shader/d3dbc: Use TAG_CTAB in d3dbc_compile().
2025-06-23 18:00:34 +02:00
Elizabeth Figura
5e4c61eba6
vkd3d-shader/ir: Introduce a stub SSA to temp allocation pass.
2025-06-23 17:32:59 +02:00
Nikolay Sivov
d08673bad1
vkd3d-shader/d3dbc: Use the actual instruction length in d3dbc_write_instruction().
...
The current calculation doesn't take indirect addressing into account.
This issue is easy to spot in disassembly, when we don't skip correctly
to the next instruction. On Windows the disassembler does not depend on
this it seems and skips naturally after processing all parameters that
may or may not use indirect addressing.
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com >
2025-06-16 17:35:37 +02:00
Henri Verbeet
66c0530a05
vkd3d-shader/d3dbc: Use vsir_opcode_get_name() in d3dbc_write_vsir_instruction().
2025-06-10 17:44:18 +02:00
Henri Verbeet
6a06929f6b
vkd3d-shader/d3dbc: Use vsir_opcode_get_name() in shader_sm1_get_opcode_info_from_vsir_instruction().
2025-06-10 17:44:18 +02:00
Elizabeth Figura
847c008b49
vkd3d-shader/ir: Split TEX into two separate vsir opcodes.
...
The two have the same d3dbc opcode, but have different names and different semantics.
2025-06-02 20:13:52 +02:00
