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7c0da1747a89a8cea27a42ace51b318e9d843a19
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331 Commits

Author SHA1 Message Date
Giovanni Mascellani
7c0da1747a vkd3d-shader/dxil: Allow constant zero values to be floating point. 
This fixes commit 59fb3a7893, where
the floating point alternative was mistakenly ignored.
 2025-06-16 17:41:20 +02:00
Giovanni Mascellani
94cbb333f8 vkd3d-shader/dxil: Emit 16-bit ICB values as minimum precision registers. 2025-06-11 18:20:23 +02:00
Giovanni Mascellani
0b5a96d963 vkd3d-shader/dxil: Emit 16-bit SSA values as minimum precision registers. 2025-06-11 18:20:23 +02:00
Giovanni Mascellani
73940cde73 vkd3d-shader/dxil: Emit 16-bit IDXTEMP values as minimum precision registers. 2025-06-11 18:20:23 +02:00
Giovanni Mascellani
5e86d5c21b vkd3d-shader/dxil: Emit 16-bit arrays as minimum precision types. 
The type is not explicitly annotated as minimum precision, because
no backend currently cares about that bit anyway. We're still
relying on the fact that in SM 6.0 16-bit types are always
understood as minimum precision.
 2025-06-11 18:20:20 +02:00
Giovanni Mascellani
1d780e1a6b vkd3d-shader/dxil: Emit 16-bit CONSTANT values as minimum precision registers. 2025-06-11 18:10:12 +02:00
Giovanni Mascellani
1b389f29c5 vkd3d-shader/dxil: Remove field "reg" from struct sm6_value. 
The VSIR register is now always generated dynamically and we
don't have to carry it around.
 2025-06-10 17:40:17 +02:00
Giovanni Mascellani
20d8ba7f8d vkd3d-shader/dxil: Introduce sm6_value_get_constant_float(). 
Similarly to sm6_value_get_constant_uint() and
sm6_value_get_constant_uint64().
 2025-06-10 17:40:17 +02:00
Giovanni Mascellani
873043226c vkd3d-shader/dxil: Rewrite sm6_parser_init_ssa_value() in terms of the SM6 value. 
Instead of using the VSIR register.
 2025-06-10 17:40:17 +02:00
Giovanni Mascellani
59fb3a7893 vkd3d-shader/dxil: Rewrite sm6_value_is_constant_zero() in terms of the SM6 value. 
Instead of using the VSIR register.
 2025-06-10 17:40:17 +02:00
Giovanni Mascellani
31e4cbba2e vkd3d-shader/dxil: Rewrite sm6_value_get_constant_uint64() in terms of the SM6 value. 
Instead of using the VSIR register.
 2025-06-10 17:40:17 +02:00
Giovanni Mascellani
2e3f99e61e vkd3d-shader/dxil: Rewrite sm6_value_get_constant_uint() in terms of the SM6 value. 
Instead of using the VSIR register.
 2025-06-10 17:40:17 +02:00
Giovanni Mascellani
f4f2617584 vkd3d-shader/dxil: Rewrite sm6_value_is_ssa() in terms of the value type. 2025-06-10 17:40:17 +02:00
Giovanni Mascellani
361ecd6cf5 vkd3d-shader/dxil: Rewrite sm6_value_is_undef() in terms of the value type. 2025-06-10 17:40:17 +02:00
Giovanni Mascellani
0ac20b3029 vkd3d-shader/dxil: Rewrite sm6_value_is_constant() in terms of the value type. 2025-06-10 17:40:17 +02:00
Giovanni Mascellani
7e134f85a4 vkd3d-shader/dxil: Do not set the value type in sm6_parser_function_init(). 
It is rewritten in all branches that produce a value.

VALUE_TYPE_REG is therefore never set and can be retired at last.
 2025-06-05 16:05:09 +02:00
Giovanni Mascellani
0e406cf0a8 vkd3d-shader/dxil: Do not set the value type in sm6_parser_declare_global(). 
It is rewritten in all branches.
 2025-06-05 16:05:09 +02:00
Giovanni Mascellani
00b3fb96d9 vkd3d-shader/dxil: Store a SM6 value in sm6_phi. 
Rather than a VSIR register.
 2025-06-05 16:05:09 +02:00
Giovanni Mascellani
a9a3100cca vkd3d-shader/dxil: Represent non uniformness in the SM6 value. 2025-06-05 16:05:09 +02:00
Giovanni Mascellani
af5e5fe31b vkd3d-shader/dxil: Generate specialized values in sm6_parser_emit_cast() for trivial casts. 
There is currently no need to make a special case for 16-bit
values, since the SPIR-V backend currently confuses them with
32-bit values. The generated VSIR code is not correct, but that
will have to be handled at a different level.
 2025-06-05 16:05:09 +02:00
Giovanni Mascellani
7f04060f33 vkd3d-shader/dxil: Handle 16-bit values uniformly in sm6_map_cast_op(). 
This makes the logic more transparent, and it eases handling
native 16-bit values once they will be supported.
 2025-06-04 13:03:57 +02:00
Giovanni Mascellani
b9ce828451 vkd3d-shader/dxil: Validate that floating-point extension casts increase bit width. 2025-06-04 13:01:51 +02:00
Giovanni Mascellani
a91fb0523a vkd3d-shader/dxil: Validate that integer extension casts increase bit width. 2025-06-04 13:01:51 +02:00
Giovanni Mascellani
a90b74baaa vkd3d-shader/dxil: Validate that floating-point truncation casts decrease bit width. 
Similarly to the integer case.
 2025-06-04 13:01:45 +02:00
Giovanni Mascellani
0e006715d8 vkd3d-shader/dxil: Do not use field "reg" in of sm6_value when writing bitcasts. 
It's going to be removed; the generated register data type is the
right thing to look at here.
 2025-06-04 12:34:21 +02:00