6989 Commits

Author SHA1 Message Date
Giovanni Mascellani
ed7a846e2e vkd3d: Only call d3d12_fence_garbage_collect_vk_semaphores_locked() when using binary semaphores.
The function is specific to binary semaphores, and will unconditionally
access the "u.binary" field of struct vkd3d_signaled_semaphore.
2025-01-21 13:45:27 +01:00
Shaun Ren
4fbfb44681 vkd3d-shader/spirv: Emit the tessellator domain for domain shaders.
Commit 1ed8d907b3998b847daa26154ca0261f55f0de23 inadvertently dropped
emitting the tessellator domain for domain shaders. Although Vulkan
environments allow us to write the tessellator domain from the hull
shader, the domain shader, or both, that's not generally true for OpenGL
environments.
2025-01-20 15:50:04 +01:00
Shaun Ren
802d7317cb vkd3d-shader/hlsl: Implement the InterlockedXor() intrinsic. 2025-01-20 15:42:45 +01:00
Shaun Ren
cbd504e888 vkd3d-shader/hlsl: Implement the InterlockedOr() intrinsic. 2025-01-20 15:42:45 +01:00
Shaun Ren
5b9634a7b7 vkd3d-shader/hlsl: Implement the InterlockedMin() intrinsic. 2025-01-20 15:42:43 +01:00
Shaun Ren
63fbe161f2 vkd3d-shader/hlsl: Implement the InterlockedMax() intrinsic. 2025-01-20 15:42:07 +01:00
Shaun Ren
b447fdce51 vkd3d-shader/hlsl: Implement the InterlockedExchange() intrinsic. 2025-01-20 15:41:07 +01:00
Shaun Ren
3fb47373a1 vkd3d-shader/hlsl: Implement the InterlockedCompareStore() intrinsic. 2025-01-20 15:41:07 +01:00
Shaun Ren
22ab08f4d8 vkd3d-shader/hlsl: Implement the InterlockedCompareExchange() intrinsic. 2025-01-20 15:41:07 +01:00
Shaun Ren
3b19a4aaf3 vkd3d-shader/hlsl: Implement the InterlockedAnd() intrinsic. 2025-01-20 15:41:07 +01:00
Shaun Ren
660a71ef22 vkd3d-shader/hlsl: Implement the InterlockedAdd() intrinsic. 2025-01-20 15:40:34 +01:00
Shaun Ren
5f943e9110 tests/hlsl: Add tests for valid destination types of atomic operations. 2025-01-20 15:30:54 +01:00
Shaun Ren
b3c13b443f tests/hlsl: Add tests to check the void return type of atomic ops. 2025-01-20 15:26:10 +01:00
Shaun Ren
728cf1dcfe tests/hlsl: Add tests to check the types of the value arguments of atomic ops. 2025-01-20 15:26:10 +01:00
Shaun Ren
c8b87f9bd9 tests/hlsl: Add a test for UAV InterlockedCompareExchange(). 2025-01-20 15:26:10 +01:00
Shaun Ren
24653b88f3 tests/shader_runner_gl: Bind buffer UAVs for compute shaders. 2025-01-20 15:25:56 +01:00
Shaun Ren
9fab6e4383 tests/shader_runner_gl: Add "opengl" tag. 2025-01-20 15:23:09 +01:00
Shaun Ren
31c3d46925 tests/shader_runner_vulkan: Check if create_shader_stage() fails in create_compute_pipeline(). 2025-01-20 14:59:12 +01:00
Conor McCarthy
10edcec030 vkd3d: Do not require the ALLOW_DEPTH_STENCIL flag for depth/stencil formats in GetCopyableFootprints(). 2025-01-20 14:37:13 +01:00
Conor McCarthy
e99906f05d vkd3d: Return correctly aligned depth/stencil sizes from GetCopyableFootprints(). 2025-01-20 13:59:46 +01:00
Conor McCarthy
1a4dedbc8d vkd3d: Return the correct depth/stencil plane format from GetCopyableFootprints(). 2025-01-20 13:45:16 +01:00
Giovanni Mascellani
17adde7f73 vkd3d: Describe DXGI_UNKNOWN as having one plane.
We're explicitly replacing zero with one in the only place where the
plane count being zero or one makes a difference. It also make sense:
UNKNOWN is used for buffers, which for all intents and purposes have one
plane.
2025-01-20 13:43:36 +01:00
Nikolay Sivov
a082daeb56 vkd3d-shader/hlsl: Implement the isinf() intrinsic.
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com>
2025-01-16 19:25:02 +01:00
Henri Verbeet
ce4f2728ba vkd3d-shader/msl: Get rid of a stray vkd3d_string_buffer_printf() in the VEC4 UINT immediate constant handling.
Uncovered by the ininf() test in the next commit. This is why we insist
on test coverage; unfortunately this one slipped through in
fd1beedc07becc7e5e49b64273f7bde7f9a8b2a0.
2025-01-16 19:18:08 +01:00
Francisco Casas
cf19b4da49 vkd3d-shader/hlsl: Specialize lowering SM1 casts to int for vertex shaders.
Vertex shaders do not have CMP, so we use SLT and MAD.

For example, this vertex shader:

    uniform float4 f;

    void main(inout float4 pos : position, out float4 t1 : TEXCOORD1)
    {
        t1 = (int4)f;
    }

results in:

    vs_2_0
    dcl_position v0
    slt r0, c0, -c0
    frc r1, c0
    add r2, -r1, c0
    slt r1, -r1, r1
    mad oT1, r0, r1, r2
    mov oPos, v0

while we have the lower_cmp() pass, each time it is applied many
instructions are generated, so this patch introduces a specialized
version of the cast-to-int lowering for efficiency.
2025-01-16 18:48:35 +01:00