Commit Graph

5066 Commits

Author SHA1 Message Date
Francisco Casas
d2feb33b47 vkd3d-shader/hlsl: Store SM4 texture declarations in the vsir program. 2024-12-09 16:09:16 +01:00
Francisco Casas
1d290bf5db vkd3d-shader/hlsl: Store SM4 sampler declarations in the vsir program.
Looking at the implementation of shader_sm4_read_dcl_sampler(), vsir
stores the resource index range both in

    vkd3d_shader_instruction.declaration.sampler.range

and in the

    vkd3d_shader_instruction.declaration.sampler.src.reg.idx[1-2]

indexes, so we do the same.

It is also worth noting that for shader models lower than 5.1, vsir
has a normalization on the ins->declaration src register indexes.
Refer to the following comment:

    /* SM5.1 places a symbol identifier in idx[0] and moves
     * other values up one slot. Normalize to SM5.1. */

on shader_sm4_read_param().

This normalization is also added to the generated vsir instructions.
2024-12-09 16:09:16 +01:00
Francisco Casas
37a61bf41a vkd3d-shader/hlsl: Store the global flags in the vsir program. 2024-12-09 16:09:16 +01:00
Francisco Casas
d3108de72a vkd3d-shader/hlsl: Store ROV feature requirement in the vsir_program. 2024-12-09 16:09:16 +01:00
Francisco Casas
d9c4a257c2 vkd3d-shader/dxbc: Parse the SFI0 ROV requirement. 2024-12-09 16:09:16 +01:00
Henri Verbeet
b484288a82 vkd3d-shader/spirv: Parse SPIR-V instructions. 2024-12-09 16:09:16 +01:00
Giovanni Mascellani
ac2901d2cb vkd3d-shader/spirv: Parse the SPIR-V instruction schema. 2024-12-09 16:09:16 +01:00
Giovanni Mascellani
9b4f5dab77 vkd3d-shader/spirv: Parse the SPIR-V id bound. 2024-12-09 16:09:16 +01:00
Giovanni Mascellani
3f548ccf9c vkd3d-shader/spirv: Parse the SPIR-V generator magic number. 2024-12-09 16:09:16 +01:00
Giovanni Mascellani
e218dae281 vkd3d-shader/spirv: Parse the SPIR-V version number. 2024-12-09 16:08:33 +01:00
Giovanni Mascellani
6cac18e395 vkd3d-shader/spirv: Parse the SPIR-V magic number. 2024-12-09 15:41:24 +01:00
Giovanni Mascellani
49fba97b0a vkd3d-shader/spirv: Introduce a SPIR-V parser. 2024-12-09 14:22:24 +01:00
Feifan He
9d4bcc951d vkd3d-shader/msl: Implement VKD3DSIH_USHR. 2024-12-05 21:26:03 +01:00
Feifan He
138e7caa03 vkd3d-shader/msl: Implement VKD3DSIH_ISHR. 2024-12-05 21:26:03 +01:00
Feifan He
5d6ed0fa30 vkd3d-shader/msl: Implement VKD3DSIH_ISHL. 2024-12-05 21:26:03 +01:00
Feifan He
a425c242a4 vkd3d-shader/msl: Implement VKD3DSIH_MAD. 2024-12-05 21:26:03 +01:00
Feifan He
8e0de82c74 vkd3d-shader/msl: Implement support for VKD3DSPDM_SATURATE modifiers. 2024-12-05 21:26:03 +01:00
Feifan He
ebf5828542 vkd3d-shader/msl: Implement VKD3DSIH_ELSE. 2024-12-05 21:25:35 +01:00
Feifan He
bbe10dcf17 vkd3d-shader/msl: Implement VKD3DSIH_NOT. 2024-12-05 21:13:29 +01:00
Giovanni Mascellani
74fa51d57c vkd3d-shader/ir: Check that DCL_INDEX_RANGE ranges do not overlap with unrelated signature elements. 2024-12-05 21:06:31 +01:00
Giovanni Mascellani
aae0a74d60 vkd3d-shader/ir: Validate the DCL_INDEX_RANGE instruction. 2024-12-05 21:06:31 +01:00
Giovanni Mascellani
38c53dca08 vkd3d-shader/ir: Introduce a helper function to determine the signature for a register type. 2024-12-05 21:05:50 +01:00
Giovanni Mascellani
b5e1c45827 vkd3d-shader/ir: Validate the register type for registers used as relative addresses. 2024-12-05 21:00:43 +01:00
Giovanni Mascellani
abf7a91834 vkd3d-shader/ir: Validate the array index when it is statically known. 2024-12-05 21:00:43 +01:00
Giovanni Mascellani
239c88e8d3 vkd3d: Do not use more than a few million descriptors in Vulkan heap set layouts.
Currently, when using Vulkan heaps, we create descriptor set
layouts with as many descriptors as allowed by the Vulkan
implementation limits. For some implementations this can mean
hundreds of millions of descriptors or more, which is wasteful,
given that even on the best resource binding tier Direct3D 12
applications should not expect to have more than a million usable
descriptors.

Recently this began being a problem, because since Mesa 24.2.7
the Intel driver advertises more than 200 million descriptors,
but pipeline compilation takes linear RAM in the number of
descriptors declared in the pipeline layout. This means that
compiling even a simple shader requires 10-20 GB of RAM.

In order to avoid using too much memory, with this commit we clamp
the number of descriptors declared in the set layouts to how many
we actually need to guarantee tier 3 resource binding support.
2024-12-05 21:00:03 +01:00