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vkd3d-shader/hlsl: Keep an hlsl_reg for each register set in hlsl_ir_var.

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This commit is contained in:
Francisco Casas 2022-11-24 17:03:54 -03:00 committed by Alexandre Julliard
parent 5272c5f86a
commit e0031d2a1f
Notes: Alexandre Julliard 2023-02-22 21:51:16 +01:00 
Approved-by: Giovanni Mascellani (@giomasce)
Approved-by: Zebediah Figura (@zfigura)
Approved-by: Francisco Casas (@fcasas)
Approved-by: Henri Verbeet (@hverbeet)
Approved-by: Alexandre Julliard (@julliard)
Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/66
4 changed files with 84 additions and 61 deletions
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16
libs/vkd3d-shader/hlsl.h
View File

@ -380,19 +380,13 @@ struct hlsl_ir_var
/* Offset where the variable's value is stored within its buffer in numeric register components.
* This in case the variable is uniform. */
unsigned int buffer_offset;
/* Register to which the variable is allocated during its lifetime.
* In case that the variable spans multiple registers, this is set to the start of the register
* range.
* The register type is inferred from the data type and the storage of the variable.
/* Register to which the variable is allocated during its lifetime, for each register set.
* In case that the variable spans multiple registers in one regset, this is set to the
* start of the register range.
* Builtin semantics don't use the field.
* In SM4, uniforms don't use the field because they are located using the buffer's hlsl_reg
* and the buffer_offset instead.
* If the variable is an input semantic copy, the register is 'v'.
* If the variable is an output semantic copy, the register is 'o'.
* Textures are stored on 's' registers in SM1, and 't' registers in SM4.
* Samplers are stored on 's' registers.
* UAVs are stored on 'u' registers. */
struct hlsl_reg reg;
* and the buffer_offset instead. */
struct hlsl_reg regs[HLSL_REGSET_LAST + 1];
uint32_t is_input_semantic : 1;
uint32_t is_output_semantic : 1;

47
libs/vkd3d-shader/hlsl_codegen.c
View File

@ -2520,13 +2520,13 @@ static void allocate_variable_temp_register(struct hlsl_ctx *ctx, struct hlsl_ir
if (var->is_input_semantic || var->is_output_semantic || var->is_uniform)
return;
if (!var->reg.allocated && var->last_read)
if (!var->regs[HLSL_REGSET_NUMERIC].allocated && var->last_read)
{
var->reg = allocate_numeric_registers_for_type(ctx, liveness, var->first_write, var->last_read,
var->data_type);
var->regs[HLSL_REGSET_NUMERIC] = allocate_numeric_registers_for_type(ctx, liveness,
var->first_write, var->last_read, var->data_type);
TRACE("Allocated %s to %s (liveness %u-%u).\n", var->name,
debug_register('r', var->reg, var->data_type), var->first_write, var->last_read);
TRACE("Allocated %s to %s (liveness %u-%u).\n", var->name, debug_register('r',
var->regs[HLSL_REGSET_NUMERIC], var->data_type), var->first_write, var->last_read);
}
}
@ -2693,11 +2693,15 @@ static void allocate_const_registers(struct hlsl_ctx *ctx, struct hlsl_ir_functi
{
if (var->is_uniform && var->last_read)
{
if (var->data_type->reg_size[HLSL_REGSET_NUMERIC] == 0)
unsigned int reg_size = var->data_type->reg_size[HLSL_REGSET_NUMERIC];
if (reg_size == 0)
continue;
var->reg = allocate_numeric_registers_for_type(ctx, &liveness, 1, UINT_MAX, var->data_type);
TRACE("Allocated %s to %s.\n", var->name, debug_register('c', var->reg, var->data_type));
var->regs[HLSL_REGSET_NUMERIC] = allocate_numeric_registers_for_type(ctx, &liveness,
1, UINT_MAX, var->data_type);
TRACE("Allocated %s to %s.\n", var->name,
debug_register('c', var->regs[HLSL_REGSET_NUMERIC], var->data_type));
}
}
}
@ -2771,10 +2775,11 @@ static void allocate_semantic_register(struct hlsl_ctx *ctx, struct hlsl_ir_var
}
else
{
var->reg.allocated = true;
var->reg.id = (*counter)++;
var->reg.writemask = (1 << var->data_type->dimx) - 1;
TRACE("Allocated %s to %s.\n", var->name, debug_register(output ? 'o' : 'v', var->reg, var->data_type));
var->regs[HLSL_REGSET_NUMERIC].allocated = true;
var->regs[HLSL_REGSET_NUMERIC].id = (*counter)++;
var->regs[HLSL_REGSET_NUMERIC].writemask = (1 << var->data_type->dimx) - 1;
TRACE("Allocated %s to %s.\n", var->name, debug_register(output ? 'o' : 'v',
var->regs[HLSL_REGSET_NUMERIC], var->data_type));
}
}
@ -2937,10 +2942,14 @@ static void allocate_objects(struct hlsl_ctx *ctx, enum hlsl_base_type type)
LIST_FOR_EACH_ENTRY(var, &ctx->extern_vars, struct hlsl_ir_var, extern_entry)
{
enum hlsl_regset regset;
if (!var->last_read || var->data_type->type != HLSL_CLASS_OBJECT
|| var->data_type->base_type != type)
continue;
regset = hlsl_type_get_regset(var->data_type);
if (var->reg_reservation.type == type_info->reg_name)
{
const struct hlsl_ir_var *reserved_object = get_reserved_object(ctx, type_info->reg_name,
@ -2962,8 +2971,8 @@ static void allocate_objects(struct hlsl_ctx *ctx, enum hlsl_base_type type)
type_info->reg_name, var->reg_reservation.index);
}
var->reg.id = var->reg_reservation.index;
var->reg.allocated = true;
var->regs[regset].id = var->reg_reservation.index;
var->regs[regset].allocated = true;
TRACE("Allocated reserved %s to %c%u.\n", var->name, type_info->reg_name, var->reg_reservation.index);
}
else if (!var->reg_reservation.type)
@ -2971,8 +2980,8 @@ static void allocate_objects(struct hlsl_ctx *ctx, enum hlsl_base_type type)
while (get_reserved_object(ctx, type_info->reg_name, index))
++index;
var->reg.id = index;
var->reg.allocated = true;
var->regs[regset].id = index;
var->regs[regset].allocated = true;
TRACE("Allocated object to %c%u.\n", type_info->reg_name, index);
++index;
}
@ -3111,7 +3120,7 @@ unsigned int hlsl_offset_from_deref_safe(struct hlsl_ctx *ctx, const struct hlsl
struct hlsl_reg hlsl_reg_from_deref(struct hlsl_ctx *ctx, const struct hlsl_deref *deref)
{
const struct hlsl_ir_var *var = deref->var;
struct hlsl_reg ret = var->reg;
struct hlsl_reg ret = var->regs[HLSL_REGSET_NUMERIC];
unsigned int offset = hlsl_offset_from_deref_safe(ctx, deref);
assert(deref->offset_regset == HLSL_REGSET_NUMERIC);
@ -3119,8 +3128,8 @@ struct hlsl_reg hlsl_reg_from_deref(struct hlsl_ctx *ctx, const struct hlsl_dere
ret.id += offset / 4;
ret.writemask = 0xf & (0xf << (offset % 4));
if (var->reg.writemask)
ret.writemask = hlsl_combine_writemasks(var->reg.writemask, ret.writemask);
if (var->regs[HLSL_REGSET_NUMERIC].writemask)
ret.writemask = hlsl_combine_writemasks(var->regs[HLSL_REGSET_NUMERIC].writemask, ret.writemask);
return ret;
}

22
libs/vkd3d-shader/hlsl_sm1.c
View File

@ -315,7 +315,9 @@ static void write_sm1_uniforms(struct hlsl_ctx *ctx, struct vkd3d_bytecode_buffe
LIST_FOR_EACH_ENTRY(var, &ctx->extern_vars, struct hlsl_ir_var, extern_entry)
{
if (!var->semantic.name && var->reg.allocated)
enum hlsl_regset regset = hlsl_type_get_regset(var->data_type);
if (!var->semantic.name && var->regs[regset].allocated)
{
++uniform_count;
@ -353,20 +355,24 @@ static void write_sm1_uniforms(struct hlsl_ctx *ctx, struct vkd3d_bytecode_buffe
LIST_FOR_EACH_ENTRY(var, &ctx->extern_vars, struct hlsl_ir_var, extern_entry)
{
if (!var->semantic.name && var->reg.allocated)
enum hlsl_regset regset = hlsl_type_get_regset(var->data_type);
if (!var->semantic.name && var->regs[regset].allocated)
{
put_u32(buffer, 0); /* name */
if (var->data_type->type == HLSL_CLASS_OBJECT
&& (var->data_type->base_type == HLSL_TYPE_SAMPLER
|| var->data_type->base_type == HLSL_TYPE_TEXTURE))
{
put_u32(buffer, vkd3d_make_u32(D3DXRS_SAMPLER, var->reg.id));
assert(regset == HLSL_REGSET_SAMPLERS);
put_u32(buffer, vkd3d_make_u32(D3DXRS_SAMPLER, var->regs[regset].id));
put_u32(buffer, 1);
}
else
{
put_u32(buffer, vkd3d_make_u32(D3DXRS_FLOAT4, var->reg.id));
put_u32(buffer, var->data_type->reg_size[HLSL_REGSET_NUMERIC] / 4);
assert(regset == HLSL_REGSET_NUMERIC);
put_u32(buffer, vkd3d_make_u32(D3DXRS_FLOAT4, var->regs[regset].id));
put_u32(buffer, var->data_type->reg_size[regset] / 4);
}
put_u32(buffer, 0); /* type */
put_u32(buffer, 0); /* FIXME: default value */
@ -377,7 +383,9 @@ static void write_sm1_uniforms(struct hlsl_ctx *ctx, struct vkd3d_bytecode_buffe
LIST_FOR_EACH_ENTRY(var, &ctx->extern_vars, struct hlsl_ir_var, extern_entry)
{
if (!var->semantic.name && var->reg.allocated)
enum hlsl_regset regset = hlsl_type_get_regset(var->data_type);
if (!var->semantic.name && var->regs[regset].allocated)
{
size_t var_offset = vars_start + (uniform_count * 5 * sizeof(uint32_t));
size_t name_offset;
@ -584,7 +592,7 @@ static void write_sm1_semantic_dcl(struct hlsl_ctx *ctx, struct vkd3d_bytecode_b
ret = hlsl_sm1_usage_from_semantic(&var->semantic, &usage, &usage_idx);
assert(ret);
reg.type = output ? D3DSPR_OUTPUT : D3DSPR_INPUT;
reg.reg = var->reg.id;
reg.reg = var->regs[HLSL_REGSET_NUMERIC].id;
}
token = D3DSIO_DCL;

46
libs/vkd3d-shader/hlsl_sm4.c
View File

@ -182,9 +182,9 @@ static void write_sm4_signature(struct hlsl_ctx *ctx, struct dxbc_writer *dxbc,
}
else
{
assert(var->reg.allocated);
assert(var->regs[HLSL_REGSET_NUMERIC].allocated);
type = VKD3D_SM4_RT_INPUT;
reg_idx = var->reg.id;
reg_idx = var->regs[HLSL_REGSET_NUMERIC].id;
}
use_mask = width; /* FIXME: accurately report use mask */
@ -484,23 +484,34 @@ static int sm4_compare_extern_resources(const void *a, const void *b)
{
const struct hlsl_ir_var *aa = *(const struct hlsl_ir_var **)a;
const struct hlsl_ir_var *bb = *(const struct hlsl_ir_var **)b;
enum hlsl_regset aa_regset, bb_regset;
if (aa->data_type->base_type != bb->data_type->base_type)
return aa->data_type->base_type - bb->data_type->base_type;
return aa->reg.id - bb->reg.id;
aa_regset = hlsl_type_get_regset(aa->data_type);
bb_regset = hlsl_type_get_regset(bb->data_type);
if (aa_regset != bb_regset)
return aa_regset - bb_regset;
return aa->regs[aa_regset].id - bb->regs[bb_regset].id;
}
static const struct hlsl_ir_var **sm4_get_extern_resources(struct hlsl_ctx *ctx, unsigned int *count)
{
const struct hlsl_ir_var **extern_resources = NULL;
const struct hlsl_ir_var *var;
enum hlsl_regset regset;
size_t capacity = 0;
*count = 0;
LIST_FOR_EACH_ENTRY(var, &ctx->extern_vars, struct hlsl_ir_var, extern_entry)
{
if (var->reg.allocated && var->data_type->type == HLSL_CLASS_OBJECT)
{
if (!hlsl_type_is_resource(var->data_type))
continue;
regset = hlsl_type_get_regset(var->data_type);
if (!var->regs[regset].allocated)
continue;
if (!(hlsl_array_reserve(ctx, (void **)&extern_resources, &capacity, *count + 1,
sizeof(*extern_resources))))
{
@ -511,7 +522,6 @@ static const struct hlsl_ir_var **sm4_get_extern_resources(struct hlsl_ctx *ctx,
extern_resources[*count] = var;
++*count;
}
}
qsort(extern_resources, *count, sizeof(*extern_resources), sm4_compare_extern_resources);
return extern_resources;
@ -578,16 +588,18 @@ static void write_sm4_rdef(struct hlsl_ctx *ctx, struct dxbc_writer *dxbc)
for (i = 0; i < extern_resources_count; ++i)
{
enum hlsl_regset regset;
uint32_t flags = 0;
var = extern_resources[i];
regset = hlsl_type_get_regset(var->data_type);
if (var->reg_reservation.type)
flags |= D3D_SIF_USERPACKED;
put_u32(&buffer, 0); /* name */
put_u32(&buffer, sm4_resource_type(var->data_type));
if (var->data_type->base_type == HLSL_TYPE_SAMPLER)
if (regset == HLSL_REGSET_SAMPLERS)
{
put_u32(&buffer, 0);
put_u32(&buffer, 0);
@ -600,7 +612,7 @@ static void write_sm4_rdef(struct hlsl_ctx *ctx, struct dxbc_writer *dxbc)
put_u32(&buffer, ~0u); /* FIXME: multisample count */
flags |= (var->data_type->e.resource_format->dimx - 1) << VKD3D_SM4_SIF_TEXTURE_COMPONENTS_SHIFT;
}
put_u32(&buffer, var->reg.id);
put_u32(&buffer, var->regs[regset].id);
put_u32(&buffer, 1); /* bind count */
put_u32(&buffer, flags);
}
@ -852,7 +864,7 @@ static void sm4_register_from_deref(struct hlsl_ctx *ctx, struct sm4_register *r
reg->dim = VKD3D_SM4_DIMENSION_VEC4;
if (swizzle_type)
*swizzle_type = VKD3D_SM4_SWIZZLE_VEC4;
reg->idx[0] = var->reg.id;
reg->idx[0] = var->regs[HLSL_REGSET_TEXTURES].id;
reg->idx_count = 1;
*writemask = VKD3DSP_WRITEMASK_ALL;
}
@ -862,7 +874,7 @@ static void sm4_register_from_deref(struct hlsl_ctx *ctx, struct sm4_register *r
reg->dim = VKD3D_SM4_DIMENSION_VEC4;
if (swizzle_type)
*swizzle_type = VKD3D_SM4_SWIZZLE_VEC4;
reg->idx[0] = var->reg.id;
reg->idx[0] = var->regs[HLSL_REGSET_UAVS].id;
reg->idx_count = 1;
*writemask = VKD3DSP_WRITEMASK_ALL;
}
@ -872,7 +884,7 @@ static void sm4_register_from_deref(struct hlsl_ctx *ctx, struct sm4_register *r
reg->dim = VKD3D_SM4_DIMENSION_NONE;
if (swizzle_type)
*swizzle_type = VKD3D_SM4_SWIZZLE_NONE;
reg->idx[0] = var->reg.id;
reg->idx[0] = var->regs[HLSL_REGSET_SAMPLERS].id;
reg->idx_count = 1;
*writemask = VKD3DSP_WRITEMASK_ALL;
}
@ -1142,7 +1154,7 @@ static void write_sm4_dcl_sampler(struct vkd3d_bytecode_buffer *buffer, const st
.opcode = VKD3D_SM4_OP_DCL_SAMPLER,
.dsts[0].reg.type = VKD3D_SM4_RT_SAMPLER,
.dsts[0].reg.idx = {var->reg.id},
.dsts[0].reg.idx = {var->regs[HLSL_REGSET_SAMPLERS].id},
.dsts[0].reg.idx_count = 1,
.dst_count = 1,
};
@ -1158,7 +1170,7 @@ static void write_sm4_dcl_texture(struct vkd3d_bytecode_buffer *buffer, const st
| (sm4_resource_dimension(var->data_type) << VKD3D_SM4_RESOURCE_TYPE_SHIFT),
.dsts[0].reg.type = uav ? VKD3D_SM5_RT_UAV : VKD3D_SM4_RT_RESOURCE,
.dsts[0].reg.idx = {var->reg.id},
.dsts[0].reg.idx = {uav ? var->regs[HLSL_REGSET_UAVS].id : var->regs[HLSL_REGSET_TEXTURES].id},
.dsts[0].reg.idx_count = 1,
.dst_count = 1,
@ -1197,9 +1209,9 @@ static void write_sm4_dcl_semantic(struct hlsl_ctx *ctx, struct vkd3d_bytecode_b
else
{
instr.dsts[0].reg.type = output ? VKD3D_SM4_RT_OUTPUT : VKD3D_SM4_RT_INPUT;
instr.dsts[0].reg.idx[0] = var->reg.id;
instr.dsts[0].reg.idx[0] = var->regs[HLSL_REGSET_NUMERIC].id;
instr.dsts[0].reg.idx_count = 1;
instr.dsts[0].writemask = var->reg.writemask;
instr.dsts[0].writemask = var->regs[HLSL_REGSET_NUMERIC].writemask;
}
if (instr.dsts[0].reg.type == VKD3D_SM4_RT_DEPTHOUT)