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vkd3d-shader/hlsl: Save per-component hlsl_ir_exprs in the vsir_program for SM1.

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This commit is contained in:
Francisco Casas 2024-05-31 02:20:36 -04:00 committed by Henri Verbeet
parent 82dec5db46
commit d70342d66d
Notes: Henri Verbeet 2024-09-11 15:33:53 +02:00 
Approved-by: Elizabeth Figura (@zfigura)
Approved-by: Henri Verbeet (@hverbeet)
Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/1041
3 changed files with 125 additions and 39 deletions
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75
libs/vkd3d-shader/d3dbc.c
View File

@ -2269,18 +2269,17 @@ static void d3dbc_write_vsir_dcl(struct d3dbc_compiler *d3dbc, const struct vkd3
}
}
static void d3dbc_write_vsir_simple_instruction(struct d3dbc_compiler *d3dbc,
const struct vkd3d_shader_instruction *ins)
static const struct vkd3d_sm1_opcode_info *shader_sm1_get_opcode_info_from_vsir_instruction(
struct d3dbc_compiler *d3dbc, const struct vkd3d_shader_instruction *ins)
{
const struct vkd3d_sm1_opcode_info *info;
struct sm1_instruction instr = {0};
if (!(info = shader_sm1_get_opcode_info_from_vsir(d3dbc, ins->opcode)))
{
vkd3d_shader_error(d3dbc->message_context, &ins->location, VKD3D_SHADER_ERROR_D3DBC_INVALID_OPCODE,
"Opcode %#x not supported for shader profile.", ins->opcode);
d3dbc->failed = true;
return;
return NULL;
}
if (ins->dst_count != info->dst_count)
@ -2289,7 +2288,7 @@ static void d3dbc_write_vsir_simple_instruction(struct d3dbc_compiler *d3dbc,
"Invalid destination count %u for vsir instruction %#x (expected %u).",
ins->dst_count, ins->opcode, info->dst_count);
d3dbc->failed = true;
return;
return NULL;
}
if (ins->src_count != info->src_count)
{
@ -2297,9 +2296,21 @@ static void d3dbc_write_vsir_simple_instruction(struct d3dbc_compiler *d3dbc,
"Invalid source count %u for vsir instruction %#x (expected %u).",
ins->src_count, ins->opcode, info->src_count);
d3dbc->failed = true;
return;
return NULL;
}
return info;
}
static void d3dbc_write_vsir_simple_instruction(struct d3dbc_compiler *d3dbc,
const struct vkd3d_shader_instruction *ins)
{
struct sm1_instruction instr = {0};
const struct vkd3d_sm1_opcode_info *info;
if (!(info = shader_sm1_get_opcode_info_from_vsir_instruction(d3dbc, ins)))
return;
instr.opcode = info->sm1_opcode;
instr.has_dst = info->dst_count;
instr.src_count = info->src_count;
@ -2314,6 +2325,8 @@ static void d3dbc_write_vsir_simple_instruction(struct d3dbc_compiler *d3dbc,
static void d3dbc_write_vsir_instruction(struct d3dbc_compiler *d3dbc, const struct vkd3d_shader_instruction *ins)
{
uint32_t writemask;
switch (ins->opcode)
{
case VKD3DSIH_DEF:
@ -2339,6 +2352,23 @@ static void d3dbc_write_vsir_instruction(struct d3dbc_compiler *d3dbc, const str
d3dbc_write_vsir_simple_instruction(d3dbc, ins);
break;
case VKD3DSIH_EXP:
case VKD3DSIH_LOG:
case VKD3DSIH_RCP:
case VKD3DSIH_RSQ:
writemask = ins->dst->write_mask;
if (writemask != VKD3DSP_WRITEMASK_0 && writemask != VKD3DSP_WRITEMASK_1
&& writemask != VKD3DSP_WRITEMASK_2 && writemask != VKD3DSP_WRITEMASK_3)
{
vkd3d_shader_error(d3dbc->message_context, &ins->location,
VKD3D_SHADER_ERROR_D3DBC_INVALID_WRITEMASK,
"writemask %#x for vsir instruction with opcode %#x is not single component.",
writemask, ins->opcode);
d3dbc->failed = true;
}
d3dbc_write_vsir_simple_instruction(d3dbc, ins);
break;
default:
vkd3d_shader_error(d3dbc->message_context, &ins->location, VKD3D_SHADER_ERROR_D3DBC_INVALID_OPCODE,
"vsir instruction with opcode %#x.", ins->opcode);
@ -2412,23 +2442,6 @@ static void d3dbc_write_semantic_dcls(struct d3dbc_compiler *d3dbc)
}
}
static void d3dbc_write_per_component_unary_op(struct d3dbc_compiler *d3dbc,
const struct hlsl_ir_node *instr, enum vkd3d_sm1_opcode opcode)
{
struct hlsl_ir_expr *expr = hlsl_ir_expr(instr);
struct hlsl_ir_node *arg1 = expr->operands[0].node;
unsigned int i;
for (i = 0; i < instr->data_type->dimx; ++i)
{
struct hlsl_reg src = arg1->reg, dst = instr->reg;
src.writemask = hlsl_combine_writemasks(src.writemask, 1u << i);
dst.writemask = hlsl_combine_writemasks(dst.writemask, 1u << i);
d3dbc_write_unary_op(d3dbc, opcode, &dst, &src, 0, 0);
}
}
static void d3dbc_write_sincos(struct d3dbc_compiler *d3dbc, enum hlsl_ir_expr_op op,
const struct hlsl_reg *dst, const struct hlsl_reg *src)
{
@ -2499,22 +2512,6 @@ static void d3dbc_write_expr(struct d3dbc_compiler *d3dbc, const struct hlsl_ir_
switch (expr->op)
{
case HLSL_OP1_EXP2:
d3dbc_write_per_component_unary_op(d3dbc, instr, VKD3D_SM1_OP_EXP);
break;
case HLSL_OP1_LOG2:
d3dbc_write_per_component_unary_op(d3dbc, instr, VKD3D_SM1_OP_LOG);
break;
case HLSL_OP1_RCP:
d3dbc_write_per_component_unary_op(d3dbc, instr, VKD3D_SM1_OP_RCP);
break;
case HLSL_OP1_RSQ:
d3dbc_write_per_component_unary_op(d3dbc, instr, VKD3D_SM1_OP_RSQ);
break;
case HLSL_OP1_COS_REDUCED:
case HLSL_OP1_SIN_REDUCED:
d3dbc_write_sincos(d3dbc, expr->op, &instr->reg, &arg1->reg);

88
libs/vkd3d-shader/hlsl_codegen.c
View File

@ -6558,6 +6558,78 @@ static void sm1_generate_vsir_instr_expr_single_instr_op(struct hlsl_ctx *ctx, s
hlsl_replace_node(instr, vsir_instr);
}
/* Translate ops that have 1 src and need one instruction for each component in
* the d3dbc backend. */
static void sm1_generate_vsir_instr_expr_per_component_instr_op(struct hlsl_ctx *ctx,
struct vsir_program *program, struct hlsl_ir_expr *expr, enum vkd3d_shader_opcode opcode)
{
struct vkd3d_shader_instruction_array *instructions = &program->instructions;
struct hlsl_ir_node *operand = expr->operands[0].node;
struct hlsl_ir_node *instr = &expr->node;
struct vkd3d_shader_dst_param *dst_param;
struct vkd3d_shader_src_param *src_param;
struct hlsl_ir_node *vsir_instr = NULL;
struct vkd3d_shader_instruction *ins;
uint32_t src_swizzle;
unsigned int i, c;
VKD3D_ASSERT(instr->reg.allocated);
VKD3D_ASSERT(operand);
src_swizzle = sm1_generate_vsir_get_src_swizzle(operand->reg.writemask, instr->reg.writemask);
for (i = 0; i < 4; ++i)
{
if (instr->reg.writemask & (1u << i))
{
if (!(ins = generate_vsir_add_program_instruction(ctx, program, &instr->loc, opcode, 1, 1)))
return;
dst_param = &ins->dst[0];
vsir_register_init(&dst_param->reg, VKD3DSPR_TEMP, VKD3D_DATA_FLOAT, 1);
dst_param->reg.idx[0].offset = instr->reg.id;
dst_param->write_mask = 1u << i;
src_param = &ins->src[0];
vsir_register_init(&src_param->reg, VKD3DSPR_TEMP, VKD3D_DATA_FLOAT, 1);
src_param->reg.idx[0].offset = operand->reg.id;
c = vsir_swizzle_get_component(src_swizzle, i);
src_param->swizzle = vsir_swizzle_from_writemask(1u << c);
if (!(vsir_instr = hlsl_new_vsir_instruction_ref(ctx, instructions->count - 1,
hlsl_get_scalar_type(ctx, instr->data_type->e.numeric.type),
&instr->reg, &instr->loc)))
{
ctx->result = VKD3D_ERROR_OUT_OF_MEMORY;
return;
}
list_add_before(&instr->entry, &vsir_instr->entry);
}
}
/* Replace expr with a no-op move. For the other instructions that reference it. */
if (!(ins = generate_vsir_add_program_instruction(ctx, program, &instr->loc, VKD3DSIH_MOV, 1, 1)))
return;
dst_param = &ins->dst[0];
vsir_register_init(&dst_param->reg, VKD3DSPR_TEMP, VKD3D_DATA_FLOAT, 1);
dst_param->reg.idx[0].offset = instr->reg.id;
dst_param->write_mask = instr->reg.writemask;
src_param = &ins->src[0];
vsir_register_init(&src_param->reg, VKD3DSPR_TEMP, VKD3D_DATA_FLOAT, 1);
src_param->reg.idx[0].offset = instr->reg.id;
src_param->swizzle = sm1_generate_vsir_get_src_swizzle(instr->reg.writemask, dst_param->write_mask);
if (!(vsir_instr = hlsl_new_vsir_instruction_ref(ctx, instructions->count - 1, instr->data_type,
&instr->reg, &instr->loc)))
{
ctx->result = VKD3D_ERROR_OUT_OF_MEMORY;
return;
}
list_add_before(&instr->entry, &vsir_instr->entry);
hlsl_replace_node(instr, vsir_instr);
}
static bool sm1_generate_vsir_instr_expr(struct hlsl_ctx *ctx, struct vsir_program *program,
struct hlsl_ir_expr *expr)
{
@ -6575,10 +6647,26 @@ static bool sm1_generate_vsir_instr_expr(struct hlsl_ctx *ctx, struct vsir_progr
sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_DSY, 0, 0);
break;
case HLSL_OP1_EXP2:
sm1_generate_vsir_instr_expr_per_component_instr_op(ctx, program, expr, VKD3DSIH_EXP);
break;
case HLSL_OP1_LOG2:
sm1_generate_vsir_instr_expr_per_component_instr_op(ctx, program, expr, VKD3DSIH_LOG);
break;
case HLSL_OP1_NEG:
sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MOV, VKD3DSPSM_NEG, 0);
break;
case HLSL_OP1_RCP:
sm1_generate_vsir_instr_expr_per_component_instr_op(ctx, program, expr, VKD3DSIH_RCP);
break;
case HLSL_OP1_RSQ:
sm1_generate_vsir_instr_expr_per_component_instr_op(ctx, program, expr, VKD3DSIH_RSQ);
break;
case HLSL_OP1_SAT:
sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MOV, 0, VKD3DSPDM_SATURATE);
break;

1
libs/vkd3d-shader/vkd3d_shader_private.h
View File

@ -179,6 +179,7 @@ enum vkd3d_shader_error
VKD3D_SHADER_ERROR_D3DBC_INVALID_REGISTER_COUNT = 7008,
VKD3D_SHADER_ERROR_D3DBC_NOT_IMPLEMENTED = 7009,
VKD3D_SHADER_ERROR_D3DBC_INVALID_PROFILE = 7010,
VKD3D_SHADER_ERROR_D3DBC_INVALID_WRITEMASK = 7011,
VKD3D_SHADER_WARNING_D3DBC_IGNORED_INSTRUCTION_FLAGS= 7300,