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vkd3d-shader/dxil: Emit switch instructions during parsing.
This commit is contained in:
committed by
Henri Verbeet
parent
8fdc156adb
commit
c9f660ec55
Notes:
Henri Verbeet
2025-11-20 18:36:32 +01:00
Approved-by: Giovanni Mascellani (@giomasce) Approved-by: Henri Verbeet (@hverbeet) Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/1133
@@ -767,19 +767,9 @@ enum sm6_block_terminator_type
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TERMINATOR_RET,
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};
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struct terminator_case
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{
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const struct sm6_block *block;
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uint64_t value;
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bool is_default;
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};
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struct sm6_block_terminator
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{
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struct vkd3d_shader_register conditional_reg;
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enum sm6_block_terminator_type type;
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struct terminator_case *cases;
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unsigned int case_count;
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};
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struct sm6_block
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@@ -7855,87 +7845,101 @@ static void sm6_parser_emit_store(struct sm6_parser *sm6, const struct dxil_reco
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dst_param->reg.idx_count = 1;
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}
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static void sm6_parser_emit_switch(struct sm6_parser *sm6, const struct dxil_record *record,
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static void sm6_parser_emit_switch(struct sm6_parser *dxil, const struct dxil_record *record,
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struct sm6_function *function, struct sm6_block *code_block, struct vkd3d_shader_instruction *ins)
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{
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struct sm6_block_terminator *terminator = &code_block->terminator;
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struct vkd3d_shader_src_param *src_params;
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const struct sm6_type *type;
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const struct sm6_value *src;
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unsigned int i = 1, j;
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uint64_t case_value;
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unsigned int i = 1;
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if (record->operand_count < 3 || !(record->operand_count & 1))
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{
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WARN("Invalid operand count %u.\n", record->operand_count);
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vkd3d_shader_parser_error(&sm6->p, VKD3D_SHADER_ERROR_DXIL_INVALID_OPERAND_COUNT,
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vkd3d_shader_parser_error(&dxil->p, VKD3D_SHADER_ERROR_DXIL_INVALID_OPERAND_COUNT,
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"Invalid operand count %u for a switch instruction.", record->operand_count);
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return;
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}
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if (!(type = sm6_parser_get_type(sm6, record->operands[0])))
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if (!(type = sm6_parser_get_type(dxil, record->operands[0])))
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return;
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if (!(src = sm6_parser_get_value_by_ref(sm6, record, type, &i))
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|| !sm6_value_validate_is_register(src, sm6))
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if (!(src = sm6_parser_get_value_by_ref(dxil, record, type, &i))
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|| !sm6_value_validate_is_register(src, dxil))
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return;
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VKD3D_ASSERT(i == 2);
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if (src->type != type)
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{
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WARN("Type mismatch.\n");
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vkd3d_shader_parser_warning(&sm6->p, VKD3D_SHADER_WARNING_DXIL_TYPE_MISMATCH,
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vkd3d_shader_parser_warning(&dxil->p, VKD3D_SHADER_WARNING_DXIL_TYPE_MISMATCH,
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"The type of a switch selector value does not match the selector type.");
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}
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if (!sm6_type_is_integer(type))
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{
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WARN("Selector is not scalar integer.\n");
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vkd3d_shader_parser_error(&sm6->p, VKD3D_SHADER_ERROR_DXIL_INVALID_OPERAND,
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vkd3d_shader_parser_error(&dxil->p, VKD3D_SHADER_ERROR_DXIL_INVALID_OPERAND,
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"Selector type class %u of a switch instruction is not scalar integer.", type->class);
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return;
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}
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vsir_register_from_dxil_value(&terminator->conditional_reg, src, 0, sm6);
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terminator->type = TERMINATOR_SWITCH;
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if (!sm6_function_validate_block_index(function, record->operands[2], dxil))
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return;
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terminator->case_count = record->operand_count / 2u;
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if (!(terminator->cases = vkd3d_calloc(terminator->case_count, sizeof(*terminator->cases))))
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vsir_instruction_init(ins, &dxil->p.location, VSIR_OP_SWITCH_MONOLITHIC);
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if (!(src_params = instruction_src_params_alloc(ins, record->operand_count, dxil)))
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{
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ERR("Failed to allocate case array.\n");
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vkd3d_shader_parser_error(&sm6->p, VKD3D_SHADER_ERROR_DXIL_OUT_OF_MEMORY,
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"Out of memory allocating a switch case array.");
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vkd3d_shader_instruction_make_nop(ins);
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return;
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}
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/* Executes 'operand_count / 2' times because operand_count is uneven. */
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for (; i < record->operand_count; i += 2)
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{
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j = i / 2u - 1;
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terminator->cases[j].block = sm6_function_get_block(function, record->operands[i], sm6);
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/* For structurisation it is convenient to store the default in the case array. */
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terminator->cases[j].is_default = !j;
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}
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src_param_init_from_value(&src_params[0], src, 0, dxil);
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/* Set the default block label id, 1-based. */
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vsir_src_param_init_label(&src_params[1], record->operands[2] + 1);
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/* Set a zero merge block label id as a placeholder until it is set during
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* the structurisation pass. */
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vsir_src_param_init_label(&src_params[2], 0);
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terminator->type = TERMINATOR_SWITCH;
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for (i = 3; i < record->operand_count; i += 2)
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{
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if (!(src = sm6_parser_get_value_safe(sm6, record->operands[i])))
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if (!(src = sm6_parser_get_value_safe(dxil, record->operands[i])))
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{
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vkd3d_shader_instruction_make_nop(ins);
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return;
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}
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if (src->type != type)
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{
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WARN("Type mismatch.\n");
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vkd3d_shader_parser_warning(&sm6->p, VKD3D_SHADER_WARNING_DXIL_TYPE_MISMATCH,
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vkd3d_shader_parser_warning(&dxil->p, VKD3D_SHADER_WARNING_DXIL_TYPE_MISMATCH,
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"The type of a switch case value does not match the selector type.");
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}
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if (!sm6_value_is_constant(src))
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{
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WARN("Case value is not a constant.\n");
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vkd3d_shader_parser_error(&sm6->p, VKD3D_SHADER_ERROR_DXIL_INVALID_OPERAND,
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vkd3d_shader_parser_error(&dxil->p, VKD3D_SHADER_ERROR_DXIL_INVALID_OPERAND,
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"A switch case value is not a constant.");
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case_value = sm6_value_get_constant_uint64(src, dxil);
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/* Set the case constant value. 64-bit values are supported. */
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if (src_params[0].reg.data_type == VSIR_DATA_U64)
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{
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vsir_src_param_init(&src_params[i], VKD3DSPR_IMMCONST64, VSIR_DATA_U64, 0);
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src_params[i].reg.u.immconst_u64[0] = case_value;
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}
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else
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{
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if (case_value > UINT_MAX)
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vkd3d_shader_parser_warning(&dxil->p, VKD3D_SHADER_WARNING_DXIL_TYPE_MISMATCH,
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"Truncating 64-bit switch case value %"PRIx64" to 32 bits.", case_value);
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vsir_src_param_init(&src_params[i], VKD3DSPR_IMMCONST, VSIR_DATA_U32, 0);
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src_params[i].reg.u.immconst_u32[0] = case_value;
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}
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terminator->cases[i / 2u].value = sm6_value_get_constant_uint64(src, sm6);
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if (!sm6_function_validate_block_index(function, record->operands[i + 1], dxil))
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{
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vkd3d_shader_instruction_make_nop(ins);
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return;
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}
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/* Set the case block label id, 1-based. */
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vsir_src_param_init_label(&src_params[i + 1], record->operands[i + 1] + 1);
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}
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ins->opcode = VSIR_OP_NOP;
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}
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static void sm6_parser_emit_vselect(struct sm6_parser *sm6, const struct dxil_record *record,
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@@ -8515,65 +8519,11 @@ static enum vkd3d_result sm6_parser_function_init(struct sm6_parser *sm6, const
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static void sm6_block_emit_terminator(const struct sm6_block *block, struct sm6_parser *sm6)
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{
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struct vkd3d_shader_src_param *src_params;
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struct vkd3d_shader_instruction *ins;
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unsigned int i, count;
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switch (block->terminator.type)
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{
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case TERMINATOR_BR:
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/* Emitted during parsing. */
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break;
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case TERMINATOR_SWITCH:
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if (!(ins = sm6_parser_add_instruction(sm6, VSIR_OP_SWITCH_MONOLITHIC)))
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return;
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if (!(src_params = instruction_src_params_alloc(ins, block->terminator.case_count * 2u + 1, sm6)))
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{
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vkd3d_shader_instruction_make_nop(ins);
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return;
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}
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src_param_init(&src_params[0]);
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src_params[0].reg = block->terminator.conditional_reg;
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/* TODO: emit the merge block id. */
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vsir_src_param_init_label(&src_params[2], 0);
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for (i = 0, count = 3; i < block->terminator.case_count; ++i)
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{
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const struct terminator_case *switch_case;
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const struct sm6_block *case_block;
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switch_case = &block->terminator.cases[i];
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if (!(case_block = switch_case->block))
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{
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VKD3D_ASSERT(sm6->p.status < 0);
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continue;
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}
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if (switch_case->is_default)
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{
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vsir_src_param_init_label(&src_params[1], case_block->id);
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continue;
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}
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if (src_params[0].reg.data_type == VSIR_DATA_U64)
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{
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vsir_src_param_init(&src_params[count], VKD3DSPR_IMMCONST64, VSIR_DATA_U64, 0);
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src_params[count++].reg.u.immconst_u64[0] = switch_case->value;
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}
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else
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{
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if (switch_case->value > UINT_MAX)
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{
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WARN("Truncating 64-bit constant %"PRIx64".\n", switch_case->value);
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vkd3d_shader_parser_warning(&sm6->p, VKD3D_SHADER_WARNING_DXIL_TYPE_MISMATCH,
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"Truncating 64-bit switch case value %"PRIx64" to 32 bits.", switch_case->value);
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}
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vsir_src_param_init(&src_params[count], VKD3DSPR_IMMCONST, VSIR_DATA_U32, 0);
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src_params[count++].reg.u.immconst_u32[0] = switch_case->value;
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}
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vsir_src_param_init_label(&src_params[count++], case_block->id);
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}
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/* Emitted during parsing. */
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break;
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case TERMINATOR_RET:
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@@ -10722,7 +10672,6 @@ static void sm6_block_destroy(struct sm6_block *block)
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for (i = 0; i < block->phi_count; ++i)
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sm6_phi_destroy(&block->phi[i]);
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vkd3d_free(block->phi);
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vkd3d_free(block->terminator.cases);
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vkd3d_free(block);
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}
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