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vkd3d-shader/dxil: Emit branch instructions during parsing.
This commit is contained in:
Conor McCarthy
committed by
Henri Verbeet
Henri Verbeet
parent
cfe9cd3794
commit
8fdc156adb
Notes:
Henri Verbeet
2025-11-20 18:36:32 +01:00
Approved-by: Giovanni Mascellani (@giomasce) Approved-by: Henri Verbeet (@hverbeet) Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/1133
@@ -762,8 +762,7 @@ struct sm6_phi
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enum sm6_block_terminator_type
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{
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TERMINATOR_UNCOND_BR,
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TERMINATOR_COND_BR,
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TERMINATOR_BR,
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TERMINATOR_SWITCH,
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TERMINATOR_RET,
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};
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@@ -779,8 +778,6 @@ struct sm6_block_terminator
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{
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struct vkd3d_shader_register conditional_reg;
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enum sm6_block_terminator_type type;
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const struct sm6_block *true_block;
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const struct sm6_block *false_block;
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struct terminator_case *cases;
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unsigned int case_count;
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};
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@@ -4741,59 +4738,86 @@ static void sm6_parser_emit_binop(struct sm6_parser *sm6, const struct dxil_reco
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instruction_dst_param_init_ssa_scalar(ins, type_flags, sm6);
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}
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static const struct sm6_block *sm6_function_get_block(const struct sm6_function *function, uint64_t index,
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struct sm6_parser *sm6)
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static bool sm6_function_validate_block_index(const struct sm6_function *function,
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uint64_t index, struct sm6_parser *dxil)
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{
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if (index >= function->block_count)
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{
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WARN("Invalid code block index %#"PRIx64".\n", index);
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vkd3d_shader_parser_error(&sm6->p, VKD3D_SHADER_ERROR_DXIL_INVALID_OPERAND_COUNT,
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vkd3d_shader_parser_error(&dxil->p, VKD3D_SHADER_ERROR_DXIL_INVALID_OPERAND_COUNT,
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"Invalid code block index %#"PRIx64" for a control flow instruction.", index);
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return NULL;
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return false;
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}
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return true;
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}
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static const struct sm6_block *sm6_function_get_block(const struct sm6_function *function,
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uint64_t index, struct sm6_parser *dxil)
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{
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if (!sm6_function_validate_block_index(function, index, dxil))
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return NULL;
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return function->blocks[index];
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}
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static void sm6_parser_emit_br(struct sm6_parser *sm6, const struct dxil_record *record,
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static void sm6_parser_emit_br(struct sm6_parser *dxil, const struct dxil_record *record,
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struct sm6_function *function, struct sm6_block *code_block, struct vkd3d_shader_instruction *ins)
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{
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struct vkd3d_shader_src_param *src_params;
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const struct sm6_value *value;
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unsigned int i = 2;
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if (record->operand_count != 1 && record->operand_count < 3)
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{
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WARN("Invalid operand count %u.\n", record->operand_count);
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vkd3d_shader_parser_error(&sm6->p, VKD3D_SHADER_ERROR_DXIL_INVALID_OPERAND_COUNT,
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vkd3d_shader_parser_error(&dxil->p, VKD3D_SHADER_ERROR_DXIL_INVALID_OPERAND_COUNT,
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"Invalid operand count %u for a branch instruction.", record->operand_count);
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return;
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}
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if (record->operand_count == 1)
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{
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code_block->terminator.type = TERMINATOR_UNCOND_BR;
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code_block->terminator.true_block = sm6_function_get_block(function, record->operands[0], sm6);
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if (!sm6_function_validate_block_index(function, record->operands[0], dxil))
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return;
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vsir_instruction_init(ins, &dxil->p.location, VSIR_OP_BRANCH);
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if (!(src_params = instruction_src_params_alloc(ins, 1, dxil)))
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{
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vkd3d_shader_instruction_make_nop(ins);
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return;
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}
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/* Label id is 1-based. */
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vsir_src_param_init_label(&src_params[0], record->operands[0] + 1);
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}
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else
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{
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if (!sm6->bool_type)
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if (!dxil->bool_type)
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{
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WARN("Bool type not found.\n");
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vkd3d_shader_parser_error(&sm6->p, VKD3D_SHADER_ERROR_DXIL_INVALID_MODULE,
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vkd3d_shader_parser_error(&dxil->p, VKD3D_SHADER_ERROR_DXIL_INVALID_MODULE,
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"Module does not define a boolean type for conditions.");
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return;
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}
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if (!(value = sm6_parser_get_value_by_ref(sm6, record, sm6->bool_type, &i))
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|| !sm6_value_validate_is_bool(value, sm6))
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if (!(value = sm6_parser_get_value_by_ref(dxil, record, dxil->bool_type, &i))
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|| !sm6_value_validate_is_bool(value, dxil))
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return;
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dxil_record_validate_operand_max_count(record, i, sm6);
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dxil_record_validate_operand_max_count(record, i, dxil);
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code_block->terminator.type = TERMINATOR_COND_BR;
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vsir_register_from_dxil_value(&code_block->terminator.conditional_reg, value, 0, sm6);
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code_block->terminator.true_block = sm6_function_get_block(function, record->operands[0], sm6);
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code_block->terminator.false_block = sm6_function_get_block(function, record->operands[1], sm6);
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if (!sm6_function_validate_block_index(function, record->operands[0], dxil)
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|| !sm6_function_validate_block_index(function, record->operands[1], dxil))
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return;
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vsir_instruction_init(ins, &dxil->p.location, VSIR_OP_BRANCH);
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if (!(src_params = instruction_src_params_alloc(ins, 3, dxil)))
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{
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vkd3d_shader_instruction_make_nop(ins);
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return;
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}
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src_param_init_from_value(&src_params[0], value, 0, dxil);
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/* Label id is 1-based. */
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vsir_src_param_init_label(&src_params[1], record->operands[0] + 1);
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vsir_src_param_init_label(&src_params[2], record->operands[1] + 1);
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}
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ins->opcode = VSIR_OP_NOP;
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code_block->terminator.type = TERMINATOR_BR;
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}
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static bool sm6_parser_emit_reg_composite_construct(struct sm6_parser *sm6,
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@@ -8458,13 +8482,17 @@ static enum vkd3d_result sm6_parser_function_init(struct sm6_parser *sm6, const
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if (record->code == FUNC_CODE_INST_PHI)
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code_block->phi[code_block->phi_count - 1].value = *dst;
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/* A vsir instruction can be emitted for a block terminator, so handle
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* a possible instruction count increment before moving to the next
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* code block. */
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if (code_block)
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code_block->instruction_count += ins->opcode != VSIR_OP_NOP;
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if (is_terminator)
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{
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++block_idx;
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code_block = (block_idx < function->block_count) ? function->blocks[block_idx] : NULL;
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}
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if (code_block)
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code_block->instruction_count += ins->opcode != VSIR_OP_NOP;
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if (dst->type && fwd_type && dst->type != fwd_type)
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{
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@@ -8493,33 +8521,8 @@ static void sm6_block_emit_terminator(const struct sm6_block *block, struct sm6_
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switch (block->terminator.type)
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{
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case TERMINATOR_UNCOND_BR:
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if (!block->terminator.true_block)
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return;
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if (!(ins = sm6_parser_add_instruction(sm6, VSIR_OP_BRANCH)))
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return;
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if (!(src_params = instruction_src_params_alloc(ins, 1, sm6)))
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{
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vkd3d_shader_instruction_make_nop(ins);
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return;
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}
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vsir_src_param_init_label(&src_params[0], block->terminator.true_block->id);
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break;
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case TERMINATOR_COND_BR:
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if (!block->terminator.true_block || !block->terminator.false_block)
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return;
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if (!(ins = sm6_parser_add_instruction(sm6, VSIR_OP_BRANCH)))
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return;
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if (!(src_params = instruction_src_params_alloc(ins, 3, sm6)))
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{
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vkd3d_shader_instruction_make_nop(ins);
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return;
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}
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src_param_init(&src_params[0]);
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src_params[0].reg = block->terminator.conditional_reg;
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vsir_src_param_init_label(&src_params[1], block->terminator.true_block->id);
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vsir_src_param_init_label(&src_params[2], block->terminator.false_block->id);
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case TERMINATOR_BR:
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/* Emitted during parsing. */
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break;
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case TERMINATOR_SWITCH:
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