wine/vkd3d
0
0
Fork 0
mirror of https://gitlab.winehq.org/wine/vkd3d.git synced 2025-12-15 08:03:30 -08:00
Code Issues Packages Projects Releases Wiki Activity

vkd3d-shader/ir: Repurpose IDIV to compute plain signed division.

Browse Source 
It doesn't compute signed remainder any more.
This commit is contained in:
Giovanni Mascellani
2025-06-10 19:32:54 +02:00
committed by Henri Verbeet
parent 823a8724de
commit ada09d003d
Notes: Henri Verbeet 2025-06-25 17:09:38 +02:00 
Approved-by: Henri Verbeet (@hverbeet)
Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/1603
3 changed files with 6 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
libs/vkd3d-shader/dxil.c
View File

@@ -4638,7 +4638,7 @@ static void sm6_parser_emit_binop(struct sm6_parser *sm6, const struct dxil_reco
dst->type = a->type;
if (handler_idx == VSIR_OP_UDIV || handler_idx == VSIR_OP_IDIV)
if (handler_idx == VSIR_OP_UDIV)
{
struct vkd3d_shader_dst_param *dst_params = instruction_dst_params_alloc(ins, 2, sm6);
unsigned int index = code != BINOP_UDIV && code != BINOP_SDIV;

1
libs/vkd3d-shader/ir.c
View File

@@ -8265,7 +8265,6 @@ static void liveness_track_dst(struct liveness_tracker *tracker, struct vkd3d_sh
/* All of these instructions have fixed destinations—they can
* in some cases be masked, but the destination cannot be
* reallocated to a different set of components. */
case VSIR_OP_IDIV:
case VSIR_OP_IMUL:
case VSIR_OP_SWAPC:
case VSIR_OP_UDIV:

12
libs/vkd3d-shader/spirv.c
View File

@@ -7534,6 +7534,7 @@ static SpvOp spirv_compiler_map_alu_instruction(const struct vkd3d_shader_instru
{VSIR_OP_FREM, SpvOpFRem},
{VSIR_OP_FTOD, SpvOpFConvert},
{VSIR_OP_IADD, SpvOpIAdd},
{VSIR_OP_IDIV, SpvOpSDiv},
{VSIR_OP_IMUL_LOW, SpvOpIMul},
{VSIR_OP_INEG, SpvOpSNegate},
{VSIR_OP_IREM, SpvOpSRem},
@@ -7670,6 +7671,7 @@ static enum vkd3d_result spirv_compiler_emit_alu_instruction(struct spirv_compil
* so we have an explicit check. */
switch (instruction->opcode)
{
case VSIR_OP_IDIV:
case VSIR_OP_IREM:
check_zero = true;
break;
@@ -8081,10 +8083,6 @@ static void spirv_compiler_emit_int_div(struct spirv_compiler *compiler,
const struct vkd3d_shader_dst_param *dst = instruction->dst;
const struct vkd3d_shader_src_param *src = instruction->src;
unsigned int component_count = 0;
SpvOp div_op, mod_op;
div_op = instruction->opcode == VSIR_OP_IDIV ? SpvOpSDiv : SpvOpUDiv;
mod_op = instruction->opcode == VSIR_OP_IDIV ? SpvOpSRem : SpvOpUMod;
if (dst[0].reg.type != VKD3DSPR_NULL)
{
@@ -8101,7 +8099,7 @@ static void spirv_compiler_emit_int_div(struct spirv_compiler *compiler,
else
uint_max_id = spirv_compiler_get_constant_uint_vector(compiler, 0xffffffff, component_count);
val_id = vkd3d_spirv_build_op_tr2(builder, &builder->function_stream, div_op, type_id, src0_id, src1_id);
val_id = vkd3d_spirv_build_op_tr2(builder, &builder->function_stream, SpvOpUDiv, type_id, src0_id, src1_id);
/* The SPIR-V spec says: "The resulting value is undefined if Operand 2 is 0." */
val_id = vkd3d_spirv_build_op_select(builder, type_id, condition_id, val_id, uint_max_id);
@@ -8126,7 +8124,7 @@ static void spirv_compiler_emit_int_div(struct spirv_compiler *compiler,
uint_max_id = spirv_compiler_get_constant_uint_vector(compiler, 0xffffffff, component_count);
}
val_id = vkd3d_spirv_build_op_tr2(builder, &builder->function_stream, mod_op, type_id, src0_id, src1_id);
val_id = vkd3d_spirv_build_op_tr2(builder, &builder->function_stream, SpvOpUMod, type_id, src0_id, src1_id);
/* The SPIR-V spec says: "The resulting value is undefined if Operand 2 is 0." */
val_id = vkd3d_spirv_build_op_select(builder, type_id, condition_id, val_id, uint_max_id);
@@ -10680,6 +10678,7 @@ static int spirv_compiler_handle_instruction(struct spirv_compiler *compiler,
case VSIR_OP_FREM:
case VSIR_OP_FTOD:
case VSIR_OP_IADD:
case VSIR_OP_IDIV:
case VSIR_OP_IMUL_LOW:
case VSIR_OP_INEG:
case VSIR_OP_IREM:
@@ -10749,7 +10748,6 @@ static int spirv_compiler_handle_instruction(struct spirv_compiler *compiler,
case VSIR_OP_IMAD:
spirv_compiler_emit_imad(compiler, instruction);
break;
case VSIR_OP_IDIV:
case VSIR_OP_UDIV:
spirv_compiler_emit_int_div(compiler, instruction);
break;