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vkd3d-shader/tpf: Write sysval semantic consistently.
Specifically we should write the sysval semantic as an instruction idx for the following instructions: VKD3D_SM4_OP_DCL_INPUT_SGV VKD3D_SM4_OP_DCL_INPUT_PS_SGV VKD3D_SM4_OP_DCL_INPUT_SIV VKD3D_SM4_OP_DCL_INPUT_PS_SIV VKD3D_SM4_OP_DCL_OUTPUT_SIV and not the following ones: VKD3D_SM4_OP_DCL_INPUT VKD3D_SM4_OP_DCL_PS_INPUT VKD3D_SM4_OP_DCL_OUTPUT Which is consistent with what we do when reading these instructions in the following functions: shader_sm4_read_declaration_register_semantic() shader_sm4_read_dcl_input_ps_siv() and shader_sm4_read_dcl_input_ps() shader_sm4_read_declaration_dst() for the non-SGV and non-SIV cases. Note that the non-SGV and non-SIV instructions don't need/use this extra information because they rely on the dst register type and index. I suggest to introduce this change because the here replaced check is brittle, and we might be omitting the sysval semantic in some cases.
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Notes:
Henri Verbeet
2024-10-15 17:04:18 +02:00
Approved-by: Elizabeth Figura (@zfigura) Approved-by: Henri Verbeet (@hverbeet) Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/1174
@ -4877,20 +4877,20 @@ static void write_sm4_dcl_semantic(const struct tpf_writer *tpf, const struct hl
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instr.opcode = VKD3D_SM4_OP_DCL_OUTPUT_SIV;
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}
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switch (semantic)
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if (instr.opcode == VKD3D_SM4_OP_DCL_OUTPUT)
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{
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case VKD3D_SHADER_SV_COVERAGE:
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case VKD3D_SHADER_SV_DEPTH:
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case VKD3D_SHADER_SV_DEPTH_GREATER_EQUAL:
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case VKD3D_SHADER_SV_DEPTH_LESS_EQUAL:
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case VKD3D_SHADER_SV_TARGET:
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case VKD3D_SHADER_SV_NONE:
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break;
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default:
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VKD3D_ASSERT(semantic == VKD3D_SHADER_SV_NONE || semantic == VKD3D_SHADER_SV_TARGET
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|| instr.dsts[0].reg.type != VKD3DSPR_OUTPUT);
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}
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else if (instr.opcode == VKD3D_SM4_OP_DCL_INPUT || instr.opcode == VKD3D_SM4_OP_DCL_INPUT_PS)
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{
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VKD3D_ASSERT(semantic == VKD3D_SHADER_SV_NONE);
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}
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else
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{
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VKD3D_ASSERT(semantic != VKD3D_SHADER_SV_NONE);
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instr.idx_count = 1;
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instr.idx[0] = semantic;
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break;
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}
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write_sm4_instruction(tpf, &instr);
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