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vkd3d-shader/dxil: Allocate instructions directly in sm6_parser_emit_dx_compute_builtin().
This commit is contained in:
committed by
Henri Verbeet
parent
f409b595b2
commit
9fae991877
Notes:
Henri Verbeet
2025-12-10 16:12:08 +01:00
Approved-by: Henri Verbeet (@hverbeet) Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/1864
@@ -5877,12 +5877,12 @@ static void sm6_parser_emit_dx_fabs(struct sm6_parser *dxil, enum dx_intrinsic_o
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vkd3d_shader_instruction_make_nop(ins);
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vkd3d_shader_instruction_make_nop(ins);
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}
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}
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static void sm6_parser_emit_dx_compute_builtin(struct sm6_parser *sm6, enum dx_intrinsic_opcode op,
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static void sm6_parser_emit_dx_compute_builtin(struct sm6_parser *dxil, enum dx_intrinsic_opcode op,
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const struct sm6_value **operands, struct function_emission_state *state)
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const struct sm6_value **operands, struct function_emission_state *state)
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{
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{
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unsigned int component_count = 3, component_idx = 0;
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unsigned int component_count = 3, component_idx = 0;
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struct vkd3d_shader_instruction *ins = state->ins;
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enum vkd3d_shader_register_type reg_type;
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enum vkd3d_shader_register_type reg_type;
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struct vkd3d_shader_instruction *ins;
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struct vsir_src_operand *src_param;
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struct vsir_src_operand *src_param;
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switch (op)
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switch (op)
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@@ -5904,17 +5904,29 @@ static void sm6_parser_emit_dx_compute_builtin(struct sm6_parser *sm6, enum dx_i
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vkd3d_unreachable();
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vkd3d_unreachable();
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}
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}
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sm6_parser_dcl_register_builtin(sm6, VSIR_OP_DCL_INPUT, reg_type, VSIR_DATA_U32, component_count);
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sm6_parser_dcl_register_builtin(dxil, VSIR_OP_DCL_INPUT, reg_type, VSIR_DATA_U32, component_count);
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vsir_instruction_init(ins, &sm6->p.location, VSIR_OP_MOV);
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if (!(src_param = instruction_src_params_alloc(ins, 1, sm6)))
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if (!(ins = sm6_parser_add_function_instruction(dxil, state)))
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return;
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return;
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state->pushed_instruction = true;
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vsir_instruction_init(ins, &dxil->p.location, VSIR_OP_MOV);
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if (!(src_param = instruction_src_params_alloc(ins, 1, dxil)))
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{
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vkd3d_shader_instruction_make_nop(ins);
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return;
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}
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vsir_register_init(&src_param->reg, reg_type, VSIR_DATA_U32, 0);
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vsir_register_init(&src_param->reg, reg_type, VSIR_DATA_U32, 0);
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src_param->reg.dimension = VSIR_DIMENSION_VEC4;
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src_param->reg.dimension = VSIR_DIMENSION_VEC4;
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if (component_count > 1)
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if (component_count > 1)
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component_idx = sm6_value_get_constant_uint(operands[0], sm6);
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component_idx = sm6_value_get_constant_uint(operands[0], dxil);
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src_param_init_scalar(src_param, component_idx);
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src_param_init_scalar(src_param, component_idx);
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instruction_dst_param_init_ssa_scalar(ins, 0, sm6);
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if (!instruction_dst_param_init_ssa_scalar(ins, 0, dxil))
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vkd3d_shader_instruction_make_nop(ins);
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}
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}
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static enum vkd3d_shader_opcode sm6_dx_map_ma_op(enum dx_intrinsic_opcode op, const struct sm6_type *type)
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static enum vkd3d_shader_opcode sm6_dx_map_ma_op(enum dx_intrinsic_opcode op, const struct sm6_type *type)
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