vkd3d: Validate the base descriptor handle in d3d12_command_list_set_descriptor_table().

The availability of allocation info makes it possible to check that
the descriptor belongs to a heap of the correct type. This will be
more important when Vulkan-backed descriptor heaps are added.

Signed-off-by: Conor McCarthy <cmccarthy@codeweavers.com>
Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
This commit is contained in:
Conor McCarthy 2022-01-05 14:54:51 +10:00 committed by Alexandre Julliard
parent 67ee837f2b
commit 711378ea31
3 changed files with 39 additions and 1 deletions

View File

@ -4178,11 +4178,24 @@ static void d3d12_command_list_set_descriptor_table(struct d3d12_command_list *l
{
struct vkd3d_pipeline_bindings *bindings = &list->pipeline_bindings[bind_point];
const struct d3d12_root_signature *root_signature = bindings->root_signature;
struct d3d12_desc *desc;
assert(root_signature_get_descriptor_table(root_signature, index));
assert(index < ARRAY_SIZE(bindings->descriptor_tables));
bindings->descriptor_tables[index] = d3d12_desc_from_gpu_handle(base_descriptor);
desc = d3d12_desc_from_gpu_handle(base_descriptor);
if (desc && !vkd3d_gpu_descriptor_allocator_heap_from_descriptor(&list->device->gpu_descriptor_allocator,
desc))
{
/* Failure to find a heap means the descriptor handle is from
* the wrong heap type or not a handle at all. */
ERR("Invalid heap for base descriptor %"PRIx64".\n", base_descriptor.ptr);
/* TODO: Mark list as invalid? */
return;
}
bindings->descriptor_tables[index] = desc;
bindings->descriptor_table_dirty_mask |= (uint64_t)1 << index;
bindings->descriptor_table_active_mask |= (uint64_t)1 << index;
}

View File

@ -2305,6 +2305,29 @@ size_t vkd3d_gpu_descriptor_allocator_range_size_from_descriptor(
return remaining;
}
struct d3d12_descriptor_heap *vkd3d_gpu_descriptor_allocator_heap_from_descriptor(
struct vkd3d_gpu_descriptor_allocator *allocator, const struct d3d12_desc *desc)
{
const struct vkd3d_gpu_descriptor_allocation *allocation;
int rc;
if (!allocator->allocation_count)
return NULL;
if ((rc = pthread_mutex_lock(&allocator->mutex)))
{
ERR("Failed to lock mutex, error %d.\n", rc);
return NULL;
}
allocation = vkd3d_gpu_descriptor_allocator_allocation_from_descriptor(allocator, desc);
pthread_mutex_unlock(&allocator->mutex);
return allocation ? CONTAINING_RECORD(allocation->base, struct d3d12_descriptor_heap, descriptors)
: NULL;
}
static bool vkd3d_gpu_descriptor_allocator_init(struct vkd3d_gpu_descriptor_allocator *allocator)
{
int rc;

View File

@ -260,6 +260,8 @@ bool vkd3d_gpu_descriptor_allocator_register_range(struct vkd3d_gpu_descriptor_a
const struct d3d12_desc *base, size_t count);
bool vkd3d_gpu_descriptor_allocator_unregister_range(
struct vkd3d_gpu_descriptor_allocator *allocator, const struct d3d12_desc *base);
struct d3d12_descriptor_heap *vkd3d_gpu_descriptor_allocator_heap_from_descriptor(
struct vkd3d_gpu_descriptor_allocator *allocator, const struct d3d12_desc *desc);
struct vkd3d_render_pass_key
{