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vkd3d-shader/hlsl: Save hlsl_ir_if in the vsir_program for SM1.
This commit is contained in:
parent
6b0baeb6c2
commit
6bd0390498
Notes:
Henri Verbeet
2024-09-14 16:54:03 +02:00
Approved-by: Elizabeth Figura (@zfigura) Approved-by: Henri Verbeet (@hverbeet) Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/1072
@ -2162,6 +2162,7 @@ static void d3dbc_write_vsir_simple_instruction(struct d3dbc_compiler *d3dbc,
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return;
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instr.opcode = info->sm1_opcode;
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instr.flags = ins->flags;
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instr.has_dst = info->dst_count;
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instr.src_count = info->src_count;
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@ -2195,7 +2196,10 @@ static void d3dbc_write_vsir_instruction(struct d3dbc_compiler *d3dbc, const str
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case VKD3DSIH_DP4:
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case VKD3DSIH_DSX:
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case VKD3DSIH_DSY:
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case VKD3DSIH_ELSE:
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case VKD3DSIH_ENDIF:
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case VKD3DSIH_FRC:
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case VKD3DSIH_IFC:
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case VKD3DSIH_MAD:
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case VKD3DSIH_MAX:
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case VKD3DSIH_MIN:
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@ -2299,48 +2303,6 @@ static void d3dbc_write_semantic_dcls(struct d3dbc_compiler *d3dbc)
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}
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}
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static void d3dbc_write_block(struct d3dbc_compiler *d3dbc, const struct hlsl_block *block);
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static void d3dbc_write_if(struct d3dbc_compiler *d3dbc, const struct hlsl_ir_node *instr)
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{
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const struct hlsl_ir_if *iff = hlsl_ir_if(instr);
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const struct hlsl_ir_node *condition;
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struct sm1_instruction sm1_ifc, sm1_else, sm1_endif;
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condition = iff->condition.node;
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VKD3D_ASSERT(condition->data_type->dimx == 1 && condition->data_type->dimy == 1);
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sm1_ifc = (struct sm1_instruction)
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{
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.opcode = VKD3D_SM1_OP_IFC,
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.flags = VKD3D_SHADER_REL_OP_NE, /* Make it a "if_ne" instruction. */
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.srcs[0].type = VKD3DSPR_TEMP,
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.srcs[0].swizzle = hlsl_swizzle_from_writemask(condition->reg.writemask),
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.srcs[0].reg = condition->reg.id,
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.srcs[0].mod = 0,
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.srcs[1].type = VKD3DSPR_TEMP,
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.srcs[1].swizzle = hlsl_swizzle_from_writemask(condition->reg.writemask),
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.srcs[1].reg = condition->reg.id,
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.srcs[1].mod = VKD3DSPSM_NEG,
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.src_count = 2,
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};
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d3dbc_write_instruction(d3dbc, &sm1_ifc);
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d3dbc_write_block(d3dbc, &iff->then_block);
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if (!list_empty(&iff->else_block.instrs))
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{
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sm1_else = (struct sm1_instruction){.opcode = VKD3D_SM1_OP_ELSE};
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d3dbc_write_instruction(d3dbc, &sm1_else);
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d3dbc_write_block(d3dbc, &iff->else_block);
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}
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sm1_endif = (struct sm1_instruction){.opcode = VKD3D_SM1_OP_ENDIF};
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d3dbc_write_instruction(d3dbc, &sm1_endif);
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}
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static void d3dbc_write_block(struct d3dbc_compiler *d3dbc, const struct hlsl_block *block)
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{
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struct vkd3d_shader_instruction *vsir_instr;
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@ -2364,13 +2326,6 @@ static void d3dbc_write_block(struct d3dbc_compiler *d3dbc, const struct hlsl_bl
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case HLSL_IR_CALL:
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vkd3d_unreachable();
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case HLSL_IR_IF:
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if (hlsl_version_ge(ctx, 2, 1))
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d3dbc_write_if(d3dbc, instr);
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else
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hlsl_fixme(ctx, &instr->loc, "Flatten \"if\" conditionals branches.");
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break;
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case HLSL_IR_VSIR_INSTRUCTION_REF:
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vsir_instr_idx = hlsl_ir_vsir_instruction_ref(instr)->vsir_instr_idx;
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vsir_instr = &d3dbc->program->instructions.elements[vsir_instr_idx];
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@ -7241,44 +7241,127 @@ static void sm1_generate_vsir_instr_jump(struct hlsl_ctx *ctx,
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}
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}
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static bool sm1_generate_vsir_instr(struct hlsl_ctx *ctx, struct hlsl_ir_node *instr, void *context)
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static void sm1_generate_vsir_block(struct hlsl_ctx *ctx, struct hlsl_block *block, struct vsir_program *program);
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static void sm1_generate_vsir_instr_if(struct hlsl_ctx *ctx, struct vsir_program *program, struct hlsl_ir_if *iff)
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{
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struct vsir_program *program = context;
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struct hlsl_ir_node *condition = iff->condition.node;
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struct vkd3d_shader_src_param *src_param;
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struct hlsl_ir_node *instr = &iff->node;
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struct vkd3d_shader_instruction *ins;
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struct hlsl_ir_node *vsir_instr;
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struct hlsl_block block;
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uint32_t swizzle;
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switch (instr->type)
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if (hlsl_version_lt(ctx, 2, 1))
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{
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case HLSL_IR_CONSTANT:
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sm1_generate_vsir_instr_constant(ctx, program, hlsl_ir_constant(instr));
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return true;
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case HLSL_IR_EXPR:
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return sm1_generate_vsir_instr_expr(ctx, program, hlsl_ir_expr(instr));
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case HLSL_IR_JUMP:
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sm1_generate_vsir_instr_jump(ctx, program, hlsl_ir_jump(instr));
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return true;
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case HLSL_IR_LOAD:
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sm1_generate_vsir_instr_load(ctx, program, hlsl_ir_load(instr));
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return true;
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case HLSL_IR_RESOURCE_LOAD:
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sm1_generate_vsir_instr_resource_load(ctx, program, hlsl_ir_resource_load(instr));
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return true;
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case HLSL_IR_STORE:
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sm1_generate_vsir_instr_store(ctx, program, hlsl_ir_store(instr));
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return true;
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case HLSL_IR_SWIZZLE:
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sm1_generate_vsir_instr_swizzle(ctx, program, hlsl_ir_swizzle(instr));
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return true;
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default:
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break;
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hlsl_fixme(ctx, &instr->loc, "Flatten \"if\" conditionals branches.");
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return;
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}
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VKD3D_ASSERT(condition->data_type->dimx == 1 && condition->data_type->dimy == 1);
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return false;
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hlsl_block_init(&block);
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if (!(ins = generate_vsir_add_program_instruction(ctx, program, &instr->loc, VKD3DSIH_IFC, 0, 2)))
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return;
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ins->flags = VKD3D_SHADER_REL_OP_NE;
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swizzle = hlsl_swizzle_from_writemask(condition->reg.writemask);
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swizzle = vsir_swizzle_from_hlsl(swizzle);
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src_param = &ins->src[0];
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vsir_register_init(&src_param->reg, VKD3DSPR_TEMP, VKD3D_DATA_FLOAT, 1);
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src_param->reg.idx[0].offset = condition->reg.id;
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src_param->swizzle = swizzle;
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src_param->modifiers = 0;
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src_param = &ins->src[1];
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vsir_register_init(&src_param->reg, VKD3DSPR_TEMP, VKD3D_DATA_FLOAT, 1);
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src_param->reg.idx[0].offset = condition->reg.id;
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src_param->swizzle = swizzle;
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src_param->modifiers = VKD3DSPSM_NEG;
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if (!(vsir_instr = hlsl_new_vsir_instruction_ref(ctx, program->instructions.count - 1, NULL, NULL, &instr->loc)))
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{
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ctx->result = VKD3D_ERROR_OUT_OF_MEMORY;
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return;
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}
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hlsl_block_add_instr(&block, vsir_instr);
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sm1_generate_vsir_block(ctx, &iff->then_block, program);
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hlsl_block_add_block(&block, &iff->then_block);
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if (!(ins = generate_vsir_add_program_instruction(ctx, program, &instr->loc, VKD3DSIH_ELSE, 0, 0)))
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return;
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if (!(vsir_instr = hlsl_new_vsir_instruction_ref(ctx, program->instructions.count - 1, NULL, NULL, &instr->loc)))
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{
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ctx->result = VKD3D_ERROR_OUT_OF_MEMORY;
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return;
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}
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hlsl_block_add_instr(&block, vsir_instr);
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sm1_generate_vsir_block(ctx, &iff->else_block, program);
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hlsl_block_add_block(&block, &iff->else_block);
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if (!(ins = generate_vsir_add_program_instruction(ctx, program, &instr->loc, VKD3DSIH_ENDIF, 0, 0)))
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return;
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if (!(vsir_instr = hlsl_new_vsir_instruction_ref(ctx, program->instructions.count - 1, NULL, NULL, &instr->loc)))
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{
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ctx->result = VKD3D_ERROR_OUT_OF_MEMORY;
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return;
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}
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hlsl_block_add_instr(&block, vsir_instr);
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list_move_after(&instr->entry, &block.instrs);
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hlsl_block_cleanup(&block);
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list_remove(&instr->entry);
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hlsl_free_instr(instr);
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}
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static void sm1_generate_vsir_block(struct hlsl_ctx *ctx, struct hlsl_block *block, struct vsir_program *program)
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{
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struct hlsl_ir_node *instr, *next;
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LIST_FOR_EACH_ENTRY_SAFE(instr, next, &block->instrs, struct hlsl_ir_node, entry)
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{
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switch (instr->type)
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{
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case HLSL_IR_CONSTANT:
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sm1_generate_vsir_instr_constant(ctx, program, hlsl_ir_constant(instr));
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break;
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case HLSL_IR_EXPR:
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sm1_generate_vsir_instr_expr(ctx, program, hlsl_ir_expr(instr));
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break;
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case HLSL_IR_IF:
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sm1_generate_vsir_instr_if(ctx, program, hlsl_ir_if(instr));
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break;
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case HLSL_IR_JUMP:
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sm1_generate_vsir_instr_jump(ctx, program, hlsl_ir_jump(instr));
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break;
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case HLSL_IR_LOAD:
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sm1_generate_vsir_instr_load(ctx, program, hlsl_ir_load(instr));
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break;
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case HLSL_IR_RESOURCE_LOAD:
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sm1_generate_vsir_instr_resource_load(ctx, program, hlsl_ir_resource_load(instr));
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break;
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case HLSL_IR_STORE:
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sm1_generate_vsir_instr_store(ctx, program, hlsl_ir_store(instr));
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break;
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case HLSL_IR_SWIZZLE:
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sm1_generate_vsir_instr_swizzle(ctx, program, hlsl_ir_swizzle(instr));
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break;
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default:
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break;
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}
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}
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}
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/* OBJECTIVE: Translate all the information from ctx and entry_func to the
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@ -7317,7 +7400,7 @@ static void sm1_generate_vsir(struct hlsl_ctx *ctx, struct hlsl_ir_function_decl
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sm1_generate_vsir_sampler_dcls(ctx, program, &block);
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list_move_head(&entry_func->body.instrs, &block.instrs);
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hlsl_transform_ir(ctx, sm1_generate_vsir_instr, &entry_func->body, program);
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sm1_generate_vsir_block(ctx, &entry_func->body, program);
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}
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static struct hlsl_ir_jump *loop_unrolling_find_jump(struct hlsl_block *block, struct hlsl_ir_node *stop_point,
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