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vkd3d: Implement RasterizedStream.
Signed-off-by: Józef Kucia <jkucia@codeweavers.com> Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com> Signed-off-by: Alexandre Julliard <julliard@winehq.org>
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@ -940,6 +940,7 @@ static HRESULT vkd3d_init_device_caps(struct d3d12_device *device,
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vulkan_info->device_limits = device_properties2.properties.limits;
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vulkan_info->sparse_properties = device_properties2.properties.sparseProperties;
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vulkan_info->rasterization_stream = xfb_properties.transformFeedbackRasterizationStreamSelect;
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vulkan_info->max_vertex_attrib_divisor = max(vertex_divisor_properties.maxVertexAttribDivisor, 1);
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device->feature_options.DoublePrecisionFloatShaderOps = features->shaderFloat64;
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@ -1614,6 +1614,27 @@ static void rs_desc_from_d3d12(struct VkPipelineRasterizationStateCreateInfo *vk
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FIXME("Ignoring ConservativeRaster %#x.\n", d3d12_desc->ConservativeRaster);
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}
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static void rs_stream_desc_from_d3d12(VkPipelineRasterizationStateStreamCreateInfoEXT *vk_desc,
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VkPipelineRasterizationStateCreateInfo *vk_rs_desc, const D3D12_STREAM_OUTPUT_DESC *so_desc,
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const struct vkd3d_vulkan_info *vk_info)
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{
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if (!so_desc->RasterizedStream || so_desc->RasterizedStream == D3D12_SO_NO_RASTERIZED_STREAM)
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return;
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if (!vk_info->rasterization_stream)
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{
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FIXME("Rasterization stream select is not supported by Vulkan implementation.\n");
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return;
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}
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vk_desc->sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_STREAM_CREATE_INFO_EXT;
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vk_desc->pNext = NULL;
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vk_desc->flags = 0;
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vk_desc->rasterizationStream = so_desc->RasterizedStream;
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vk_rs_desc->pNext = vk_desc;
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}
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static enum VkStencilOp vk_stencil_op_from_d3d12(D3D12_STENCIL_OP op)
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{
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switch (op)
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@ -1916,6 +1937,7 @@ static HRESULT d3d12_pipeline_state_init_graphics(struct d3d12_pipeline_state *s
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unsigned int ps_output_swizzle[D3D12_SIMULTANEOUS_RENDER_TARGET_COUNT];
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struct d3d12_graphics_pipeline_state *graphics = &state->u.graphics;
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const struct vkd3d_vk_device_procs *vk_procs = &device->vk_procs;
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const D3D12_STREAM_OUTPUT_DESC *so_desc = &desc->StreamOutput;
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VkVertexInputBindingDivisorDescriptionEXT *binding_divisor;
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const struct vkd3d_vulkan_info *vk_info = &device->vk_info;
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const struct vkd3d_shader_compile_arguments *compile_args;
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@ -2350,9 +2372,12 @@ static HRESULT d3d12_pipeline_state_init_graphics(struct d3d12_pipeline_state *s
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}
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rs_desc_from_d3d12(&graphics->rs_desc, &desc->RasterizerState);
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if (!graphics->attachment_count && !(desc->PS.pShaderBytecode && desc->PS.BytecodeLength))
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if ((!graphics->attachment_count && !(desc->PS.pShaderBytecode && desc->PS.BytecodeLength))
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|| so_desc->RasterizedStream == D3D12_SO_NO_RASTERIZED_STREAM)
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graphics->rs_desc.rasterizerDiscardEnable = VK_TRUE;
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rs_stream_desc_from_d3d12(&graphics->rs_stream_desc, &graphics->rs_desc, so_desc, vk_info);
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if (desc->SampleMask != ~0u)
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FIXME("Ignoring sample mask %#x.\n", desc->SampleMask);
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@ -90,6 +90,8 @@ struct vkd3d_vulkan_info
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bool EXT_transform_feedback;
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bool EXT_vertex_attribute_divisor;
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bool rasterization_stream;
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bool vertex_attrib_zero_divisor;
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unsigned int max_vertex_attrib_divisor;
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@ -559,7 +561,7 @@ struct d3d12_root_signature
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VkDescriptorSetLayout vk_push_set_layout;
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VkDescriptorSetLayout vk_set_layout;
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struct VkDescriptorPoolSize *pool_sizes;
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VkDescriptorPoolSize *pool_sizes;
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size_t pool_size_count;
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struct d3d12_root_parameter *parameters;
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@ -593,25 +595,27 @@ struct d3d12_root_signature *unsafe_impl_from_ID3D12RootSignature(ID3D12RootSign
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struct d3d12_graphics_pipeline_state
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{
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struct VkPipelineShaderStageCreateInfo stages[VKD3D_MAX_SHADER_STAGES];
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VkPipelineShaderStageCreateInfo stages[VKD3D_MAX_SHADER_STAGES];
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size_t stage_count;
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struct VkVertexInputAttributeDescription attributes[D3D12_VS_INPUT_REGISTER_COUNT];
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enum VkVertexInputRate input_rates[D3D12_IA_VERTEX_INPUT_RESOURCE_SLOT_COUNT];
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VkVertexInputAttributeDescription attributes[D3D12_VS_INPUT_REGISTER_COUNT];
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VkVertexInputRate input_rates[D3D12_IA_VERTEX_INPUT_RESOURCE_SLOT_COUNT];
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VkVertexInputBindingDivisorDescriptionEXT instance_divisors[D3D12_IA_VERTEX_INPUT_RESOURCE_SLOT_COUNT];
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size_t instance_divisor_count;
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size_t attribute_count;
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struct VkAttachmentDescription attachments[D3D12_SIMULTANEOUS_RENDER_TARGET_COUNT + 1];
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struct VkAttachmentReference attachment_references[D3D12_SIMULTANEOUS_RENDER_TARGET_COUNT + 1];
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struct VkPipelineColorBlendAttachmentState blend_attachments[D3D12_SIMULTANEOUS_RENDER_TARGET_COUNT];
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VkAttachmentDescription attachments[D3D12_SIMULTANEOUS_RENDER_TARGET_COUNT + 1];
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VkAttachmentReference attachment_references[D3D12_SIMULTANEOUS_RENDER_TARGET_COUNT + 1];
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VkPipelineColorBlendAttachmentState blend_attachments[D3D12_SIMULTANEOUS_RENDER_TARGET_COUNT];
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size_t attachment_count, rt_idx;
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VkRenderPass render_pass;
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D3D12_INDEX_BUFFER_STRIP_CUT_VALUE index_buffer_strip_cut_value;
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struct VkPipelineRasterizationStateCreateInfo rs_desc;
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struct VkPipelineMultisampleStateCreateInfo ms_desc;
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struct VkPipelineDepthStencilStateCreateInfo ds_desc;
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VkPipelineRasterizationStateCreateInfo rs_desc;
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VkPipelineMultisampleStateCreateInfo ms_desc;
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VkPipelineDepthStencilStateCreateInfo ds_desc;
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VkPipelineRasterizationStateStreamCreateInfoEXT rs_stream_desc;
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const struct d3d12_root_signature *root_signature;
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@ -961,7 +965,7 @@ static inline unsigned int d3d12_resource_desc_get_sub_resource_count(const D3D1
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return d3d12_resource_desc_get_layer_count(desc) * desc->MipLevels;
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}
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enum VkCompareOp vk_compare_op_from_d3d12(D3D12_COMPARISON_FUNC op) DECLSPEC_HIDDEN;
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VkCompareOp vk_compare_op_from_d3d12(D3D12_COMPARISON_FUNC op) DECLSPEC_HIDDEN;
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VkSampleCountFlagBits vk_samples_from_dxgi_sample_desc(const DXGI_SAMPLE_DESC *desc) DECLSPEC_HIDDEN;
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bool is_valid_feature_level(D3D_FEATURE_LEVEL feature_level) DECLSPEC_HIDDEN;
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