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https://gitlab.winehq.org/wine/vkd3d.git
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vkd3d-shader/hlsl: Store SM4 HLSL_RESOURCE_LOADs in the vsir program.
This commit is contained in:
parent
fd1beedc07
commit
52b81f42eb
Notes:
Henri Verbeet
2024-11-24 00:11:40 +01:00
Approved-by: Elizabeth Figura (@zfigura) Approved-by: Henri Verbeet (@hverbeet) Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/1276
@ -8898,6 +8898,145 @@ static bool sm4_generate_vsir_instr_resource_store(struct hlsl_ctx *ctx,
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return true;
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}
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static bool sm4_generate_vsir_validate_texel_offset_aoffimmi(const struct hlsl_ir_node *texel_offset)
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{
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struct hlsl_ir_constant *offset;
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VKD3D_ASSERT(texel_offset);
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if (texel_offset->type != HLSL_IR_CONSTANT)
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return false;
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offset = hlsl_ir_constant(texel_offset);
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if (offset->value.u[0].i < -8 || offset->value.u[0].i > 7)
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return false;
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if (offset->node.data_type->dimx > 1 && (offset->value.u[1].i < -8 || offset->value.u[1].i > 7))
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return false;
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if (offset->node.data_type->dimx > 2 && (offset->value.u[2].i < -8 || offset->value.u[2].i > 7))
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return false;
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return true;
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}
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static void sm4_generate_vsir_encode_texel_offset_as_aoffimmi(
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struct vkd3d_shader_instruction *ins, const struct hlsl_ir_node *texel_offset)
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{
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struct hlsl_ir_constant *offset;
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if (!texel_offset)
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return;
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offset = hlsl_ir_constant(texel_offset);
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ins->texel_offset.u = offset->value.u[0].i;
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ins->texel_offset.v = 0;
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ins->texel_offset.w = 0;
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if (offset->node.data_type->dimx > 1)
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ins->texel_offset.v = offset->value.u[1].i;
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if (offset->node.data_type->dimx > 2)
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ins->texel_offset.w = offset->value.u[2].i;
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}
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static bool sm4_generate_vsir_instr_ld(struct hlsl_ctx *ctx,
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struct vsir_program *program, const struct hlsl_ir_resource_load *load)
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{
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const struct hlsl_type *resource_type = hlsl_deref_get_type(ctx, &load->resource);
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bool uav = (hlsl_deref_get_regset(ctx, &load->resource) == HLSL_REGSET_UAVS);
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const struct vkd3d_shader_version *version = &program->shader_version;
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bool raw = resource_type->sampler_dim == HLSL_SAMPLER_DIM_RAW_BUFFER;
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const struct hlsl_ir_node *sample_index = load->sample_index.node;
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const struct hlsl_ir_node *texel_offset = load->texel_offset.node;
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const struct hlsl_ir_node *coords = load->coords.node;
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unsigned int coords_writemask = VKD3DSP_WRITEMASK_ALL;
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const struct hlsl_deref *resource = &load->resource;
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const struct hlsl_ir_node *instr = &load->node;
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enum hlsl_sampler_dim dim = load->sampling_dim;
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struct vkd3d_shader_instruction *ins;
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enum vkd3d_shader_opcode opcode;
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bool multisampled;
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VKD3D_ASSERT(load->load_type == HLSL_RESOURCE_LOAD);
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multisampled = resource_type->class == HLSL_CLASS_TEXTURE
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&& (resource_type->sampler_dim == HLSL_SAMPLER_DIM_2DMS
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|| resource_type->sampler_dim == HLSL_SAMPLER_DIM_2DMSARRAY);
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if (uav)
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opcode = VKD3DSIH_LD_UAV_TYPED;
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else if (raw)
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opcode = VKD3DSIH_LD_RAW;
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else
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opcode = multisampled ? VKD3DSIH_LD2DMS : VKD3DSIH_LD;
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if (!(ins = generate_vsir_add_program_instruction(ctx, program, &instr->loc, opcode, 1, 2 + multisampled)))
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return false;
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if (texel_offset && !sm4_generate_vsir_validate_texel_offset_aoffimmi(texel_offset))
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{
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hlsl_error(ctx, &texel_offset->loc, VKD3D_SHADER_ERROR_HLSL_INVALID_TEXEL_OFFSET,
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"Offset must resolve to integer literal in the range -8 to 7.");
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return false;
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}
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sm4_generate_vsir_encode_texel_offset_as_aoffimmi(ins, texel_offset);
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vsir_dst_from_hlsl_node(&ins->dst[0], ctx, instr);
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if (!uav)
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{
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/* Mipmap level is in the last component in the IR, but needs to be in
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* the W component in the instruction. */
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unsigned int dim_count = hlsl_sampler_dim_count(dim);
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if (dim_count == 1)
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coords_writemask = VKD3DSP_WRITEMASK_0 | VKD3DSP_WRITEMASK_3;
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if (dim_count == 2)
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coords_writemask = VKD3DSP_WRITEMASK_0 | VKD3DSP_WRITEMASK_1 | VKD3DSP_WRITEMASK_3;
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}
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vsir_src_from_hlsl_node(&ins->src[0], ctx, coords, coords_writemask);
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if (!sm4_generate_vsir_init_src_param_from_deref(ctx, program,
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&ins->src[1], resource, ins->dst[0].write_mask, &instr->loc))
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return false;
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if (multisampled)
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{
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if (sample_index->type == HLSL_IR_CONSTANT)
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vsir_src_from_hlsl_constant_value(&ins->src[2], ctx,
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&hlsl_ir_constant(sample_index)->value, VKD3D_DATA_INT, 1, 0);
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else if (version->major == 4 && version->minor == 0)
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hlsl_error(ctx, &sample_index->loc, VKD3D_SHADER_ERROR_HLSL_INVALID_TYPE, "Expected literal sample index.");
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else
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vsir_src_from_hlsl_node(&ins->src[2], ctx, sample_index, VKD3DSP_WRITEMASK_ALL);
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}
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return true;
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}
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static bool sm4_generate_vsir_instr_resource_load(struct hlsl_ctx *ctx,
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struct vsir_program *program, const struct hlsl_ir_resource_load *load)
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{
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if (load->sampler.var && !load->sampler.var->is_uniform)
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{
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hlsl_fixme(ctx, &load->node.loc, "Sample using non-uniform sampler variable.");
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return false;
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}
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if (!load->resource.var->is_uniform)
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{
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hlsl_fixme(ctx, &load->node.loc, "Load from non-uniform resource variable.");
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return false;
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}
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switch (load->load_type)
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{
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case HLSL_RESOURCE_LOAD:
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return sm4_generate_vsir_instr_ld(ctx, program, load);
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case HLSL_RESOURCE_SAMPLE_PROJ:
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vkd3d_unreachable();
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default:
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return false;
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}
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}
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static void sm4_generate_vsir_block(struct hlsl_ctx *ctx, struct hlsl_block *block, struct vsir_program *program)
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{
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struct vkd3d_string_buffer *dst_type_string;
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@ -8948,6 +9087,11 @@ static void sm4_generate_vsir_block(struct hlsl_ctx *ctx, struct hlsl_block *blo
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sm4_generate_vsir_block(ctx, &hlsl_ir_loop(instr)->body, program);
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break;
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case HLSL_IR_RESOURCE_LOAD:
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if (sm4_generate_vsir_instr_resource_load(ctx, program, hlsl_ir_resource_load(instr)))
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replace_instr_with_last_vsir_instr(ctx, program, instr);
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break;
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case HLSL_IR_RESOURCE_STORE:
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if (sm4_generate_vsir_instr_resource_store(ctx, program, hlsl_ir_resource_store(instr)))
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replace_instr_with_last_vsir_instr(ctx, program, instr);
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@ -5034,88 +5034,6 @@ static void write_sm4_ret(const struct tpf_compiler *tpf)
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write_sm4_instruction(tpf, &instr);
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}
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static void write_sm4_ld(const struct tpf_compiler *tpf, const struct hlsl_ir_node *dst,
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const struct hlsl_deref *resource, const struct hlsl_ir_node *coords,
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const struct hlsl_ir_node *sample_index, const struct hlsl_ir_node *texel_offset,
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enum hlsl_sampler_dim dim)
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{
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const struct hlsl_type *resource_type = hlsl_deref_get_type(tpf->ctx, resource);
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bool multisampled = resource_type->class == HLSL_CLASS_TEXTURE
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&& (resource_type->sampler_dim == HLSL_SAMPLER_DIM_2DMS || resource_type->sampler_dim == HLSL_SAMPLER_DIM_2DMSARRAY);
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bool uav = (hlsl_deref_get_regset(tpf->ctx, resource) == HLSL_REGSET_UAVS);
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const struct vkd3d_shader_version *version = &tpf->program->shader_version;
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bool raw = resource_type->sampler_dim == HLSL_SAMPLER_DIM_RAW_BUFFER;
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unsigned int coords_writemask = VKD3DSP_WRITEMASK_ALL;
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struct sm4_instruction instr;
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memset(&instr, 0, sizeof(instr));
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if (uav)
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instr.opcode = VKD3D_SM5_OP_LD_UAV_TYPED;
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else if (raw)
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instr.opcode = VKD3D_SM5_OP_LD_RAW;
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else
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instr.opcode = multisampled ? VKD3D_SM4_OP_LD2DMS : VKD3D_SM4_OP_LD;
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if (texel_offset)
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{
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if (!encode_texel_offset_as_aoffimmi(&instr, texel_offset))
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{
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hlsl_error(tpf->ctx, &texel_offset->loc, VKD3D_SHADER_ERROR_HLSL_INVALID_TEXEL_OFFSET,
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"Offset must resolve to integer literal in the range -8 to 7.");
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return;
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}
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}
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sm4_dst_from_node(&instr.dsts[0], dst);
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instr.dst_count = 1;
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if (!uav)
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{
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/* Mipmap level is in the last component in the IR, but needs to be in the W
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* component in the instruction. */
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unsigned int dim_count = hlsl_sampler_dim_count(dim);
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if (dim_count == 1)
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coords_writemask = VKD3DSP_WRITEMASK_0 | VKD3DSP_WRITEMASK_3;
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if (dim_count == 2)
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coords_writemask = VKD3DSP_WRITEMASK_0 | VKD3DSP_WRITEMASK_1 | VKD3DSP_WRITEMASK_3;
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}
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sm4_src_from_node(tpf, &instr.srcs[0], coords, coords_writemask);
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sm4_src_from_deref(tpf, &instr.srcs[1], resource, instr.dsts[0].write_mask, &instr);
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instr.src_count = 2;
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if (multisampled)
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{
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if (sample_index->type == HLSL_IR_CONSTANT)
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{
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struct vkd3d_shader_register *reg = &instr.srcs[2].reg;
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struct hlsl_ir_constant *index;
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index = hlsl_ir_constant(sample_index);
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memset(&instr.srcs[2], 0, sizeof(instr.srcs[2]));
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reg->type = VKD3DSPR_IMMCONST;
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reg->dimension = VSIR_DIMENSION_SCALAR;
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reg->u.immconst_u32[0] = index->value.u[0].u;
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}
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else if (version->major == 4 && version->minor == 0)
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{
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hlsl_error(tpf->ctx, &sample_index->loc, VKD3D_SHADER_ERROR_HLSL_INVALID_TYPE, "Expected literal sample index.");
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}
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else
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{
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sm4_src_from_node(tpf, &instr.srcs[2], sample_index, 0);
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}
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++instr.src_count;
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}
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write_sm4_instruction(tpf, &instr);
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}
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static void write_sm4_sample(const struct tpf_compiler *tpf, const struct hlsl_ir_resource_load *load)
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{
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const struct hlsl_ir_node *texel_offset = load->texel_offset.node;
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@ -5374,7 +5292,6 @@ static void write_sm4_gather(const struct tpf_compiler *tpf, const struct hlsl_i
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static void write_sm4_resource_load(const struct tpf_compiler *tpf, const struct hlsl_ir_resource_load *load)
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{
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const struct hlsl_ir_node *texel_offset = load->texel_offset.node;
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const struct hlsl_ir_node *sample_index = load->sample_index.node;
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const struct hlsl_ir_node *coords = load->coords.node;
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if (load->sampler.var && !load->sampler.var->is_uniform)
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@ -5391,11 +5308,6 @@ static void write_sm4_resource_load(const struct tpf_compiler *tpf, const struct
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switch (load->load_type)
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{
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case HLSL_RESOURCE_LOAD:
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write_sm4_ld(tpf, &load->node, &load->resource,
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coords, sample_index, texel_offset, load->sampling_dim);
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break;
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case HLSL_RESOURCE_SAMPLE:
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case HLSL_RESOURCE_SAMPLE_CMP:
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case HLSL_RESOURCE_SAMPLE_CMP_LZ:
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@ -5435,6 +5347,7 @@ static void write_sm4_resource_load(const struct tpf_compiler *tpf, const struct
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write_sm4_resinfo(tpf, load);
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break;
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case HLSL_RESOURCE_LOAD:
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case HLSL_RESOURCE_SAMPLE_PROJ:
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vkd3d_unreachable();
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}
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@ -5482,6 +5395,7 @@ static void write_sm4_switch(struct tpf_compiler *tpf, const struct hlsl_ir_swit
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static void tpf_simple_instruction(struct tpf_compiler *tpf, const struct vkd3d_shader_instruction *ins)
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{
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struct sm4_instruction_modifier *modifier;
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const struct vkd3d_sm4_opcode_info *info;
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struct sm4_instruction instr = {0};
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unsigned int dst_count, src_count;
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@ -5527,6 +5441,16 @@ static void tpf_simple_instruction(struct tpf_compiler *tpf, const struct vkd3d_
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for (unsigned int i = 0; i < ins->src_count; ++i)
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instr.srcs[i] = ins->src[i];
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if (ins->texel_offset.u || ins->texel_offset.v || ins->texel_offset.w)
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{
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VKD3D_ASSERT(instr.modifier_count < ARRAY_SIZE(instr.modifiers));
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modifier = &instr.modifiers[instr.modifier_count++];
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modifier->type = VKD3D_SM4_MODIFIER_AOFFIMMI;
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modifier->u.aoffimmi.u = ins->texel_offset.u;
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modifier->u.aoffimmi.v = ins->texel_offset.v;
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modifier->u.aoffimmi.w = ins->texel_offset.w;
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}
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write_sm4_instruction(tpf, &instr);
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}
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@ -5607,6 +5531,10 @@ static void tpf_handle_instruction(struct tpf_compiler *tpf, const struct vkd3d_
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case VKD3DSIH_ISHL:
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case VKD3DSIH_ISHR:
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case VKD3DSIH_ITOF:
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case VKD3DSIH_LD:
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case VKD3DSIH_LD2DMS:
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case VKD3DSIH_LD_RAW:
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case VKD3DSIH_LD_UAV_TYPED:
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case VKD3DSIH_LOG:
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case VKD3DSIH_LTO:
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case VKD3DSIH_MAD:
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