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libs/vkd3d-shader: Recognize more shader registers.
Signed-off-by: Józef Kucia <jkucia@codeweavers.com> Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com> Signed-off-by: Alexandre Julliard <julliard@winehq.org>
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@ -295,6 +295,7 @@ enum vkd3d_sm4_opcode
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VKD3D_SM5_OP_IMM_ATOMIC_UMAX = 0xbc,
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VKD3D_SM5_OP_IMM_ATOMIC_UMIN = 0xbd,
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VKD3D_SM5_OP_SYNC = 0xbe,
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VKD3D_SM5_OP_EVAL_SAMPLE_INDEX = 0xcc,
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VKD3D_SM5_OP_DCL_GS_INSTANCES = 0xce,
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};
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@ -312,6 +313,7 @@ enum vkd3d_sm4_register_type
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VKD3D_SM4_RT_PRIMID = 0x0b,
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VKD3D_SM4_RT_DEPTHOUT = 0x0c,
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VKD3D_SM4_RT_NULL = 0x0d,
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VKD3D_SM4_RT_RASTERIZER = 0x0e,
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VKD3D_SM4_RT_OMASK = 0x0f,
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VKD3D_SM5_RT_STREAM = 0x10,
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VKD3D_SM5_RT_FUNCTION_BODY = 0x11,
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@ -331,6 +333,8 @@ enum vkd3d_sm4_register_type
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VKD3D_SM5_RT_COVERAGE = 0x23,
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VKD3D_SM5_RT_LOCAL_THREAD_INDEX = 0x24,
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VKD3D_SM5_RT_GS_INSTANCE_ID = 0x25,
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VKD3D_SM5_RT_DEPTHOUT_GREATER_EQUAL = 0x26,
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VKD3D_SM5_RT_DEPTHOUT_LESS_EQUAL = 0x27,
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};
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enum vkd3d_sm4_output_primitive_type
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@ -1103,6 +1107,7 @@ static const struct vkd3d_sm4_opcode_info opcode_table[] =
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{VKD3D_SM5_OP_IMM_ATOMIC_UMIN, VKD3DSIH_IMM_ATOMIC_UMIN, "uU", "iu"},
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{VKD3D_SM5_OP_SYNC, VKD3DSIH_SYNC, "", "",
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shader_sm5_read_sync},
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{VKD3D_SM5_OP_EVAL_SAMPLE_INDEX, VKD3DSIH_EVAL_SAMPLE_INDEX, "f", "fi"},
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{VKD3D_SM5_OP_DCL_GS_INSTANCES, VKD3DSIH_DCL_GS_INSTANCES, "", "",
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shader_sm4_read_declaration_count},
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};
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@ -1123,7 +1128,7 @@ static const enum vkd3d_shader_register_type register_type_table[] =
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/* VKD3D_SM4_RT_PRIMID */ VKD3DSPR_PRIMID,
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/* VKD3D_SM4_RT_DEPTHOUT */ VKD3DSPR_DEPTHOUT,
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/* VKD3D_SM4_RT_NULL */ VKD3DSPR_NULL,
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/* UNKNOWN */ ~0u,
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/* VKD3D_SM4_RT_RASTERIZER */ VKD3DSPR_RASTERIZER,
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/* VKD3D_SM4_RT_OMASK */ VKD3DSPR_SAMPLEMASK,
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/* VKD3D_SM5_RT_STREAM */ VKD3DSPR_STREAM,
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/* VKD3D_SM5_RT_FUNCTION_BODY */ VKD3DSPR_FUNCTIONBODY,
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@ -1147,6 +1152,8 @@ static const enum vkd3d_shader_register_type register_type_table[] =
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/* VKD3D_SM5_RT_COVERAGE */ VKD3DSPR_COVERAGE,
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/* VKD3D_SM5_RT_LOCAL_THREAD_INDEX */ VKD3DSPR_LOCALTHREADINDEX,
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/* VKD3D_SM5_RT_GS_INSTANCE_ID */ VKD3DSPR_GSINSTID,
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/* VKD3D_SM5_RT_DEPTHOUT_GREATER_EQUAL */ VKD3DSPR_DEPTHOUTGE,
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/* VKD3D_SM5_RT_DEPTHOUT_LESS_EQUAL */ VKD3DSPR_DEPTHOUTLE,
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};
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static const struct vkd3d_sm4_opcode_info *get_opcode_info(enum vkd3d_sm4_opcode opcode)
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@ -156,6 +156,7 @@ enum VKD3D_SHADER_INSTRUCTION_HANDLER
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VKD3DSIH_ENDREP,
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VKD3DSIH_ENDSWITCH,
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VKD3DSIH_EQ,
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VKD3DSIH_EVAL_SAMPLE_INDEX,
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VKD3DSIH_EXP,
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VKD3DSIH_EXPP,
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VKD3DSIH_F16TOF32,
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@ -352,6 +353,9 @@ enum vkd3d_shader_register_type
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VKD3DSPR_COVERAGE,
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VKD3DSPR_SAMPLEMASK,
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VKD3DSPR_GSINSTID,
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VKD3DSPR_DEPTHOUTGE,
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VKD3DSPR_DEPTHOUTLE,
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VKD3DSPR_RASTERIZER,
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VKD3DSPR_INVALID = ~0u,
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};
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@ -436,6 +440,7 @@ enum vkd3d_shader_interpolation_mode
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enum vkd3d_shader_global_flags
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{
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VKD3DSGF_REFACTORING_ALLOWED = 0x1,
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VKD3DSGF_FORCE_EARLY_DEPTH_STENCIL = 0x4,
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VKD3DSGF_ENABLE_RAW_AND_STRUCTURED_BUFFERS = 0x8,
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};
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