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vkd3d-shader/ir: Rename the "handler_idx" field of struct vkd3d_shader_instruction to "opcode".
This commit is contained in:
Henri Verbeet
committed by
Alexandre Julliard
Alexandre Julliard
parent
5265fbb789
commit
1fe7a6581b
Notes:
Alexandre Julliard
2024-05-30 23:27:39 +02:00
Approved-by: Giovanni Mascellani (@giomasce) Approved-by: Henri Verbeet (@hverbeet) Approved-by: Alexandre Julliard (@julliard) Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/898
@@ -6831,7 +6831,7 @@ static void spirv_compiler_enter_shader_phase(struct spirv_compiler *compiler,
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uint32_t function_id, void_id, function_type_id;
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struct vkd3d_shader_phase *phase;
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assert(compiler->phase != instruction->handler_idx);
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assert(compiler->phase != instruction->opcode);
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if (!is_in_default_phase(compiler))
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spirv_compiler_leave_shader_phase(compiler);
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@@ -6843,16 +6843,16 @@ static void spirv_compiler_enter_shader_phase(struct spirv_compiler *compiler,
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vkd3d_spirv_build_op_function(builder, void_id, function_id,
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SpvFunctionControlMaskNone, function_type_id);
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compiler->phase = instruction->handler_idx;
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compiler->phase = instruction->opcode;
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spirv_compiler_emit_shader_phase_name(compiler, function_id, NULL);
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phase = (instruction->handler_idx == VKD3DSIH_HS_CONTROL_POINT_PHASE)
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phase = (instruction->opcode == VKD3DSIH_HS_CONTROL_POINT_PHASE)
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? &compiler->control_point_phase : &compiler->patch_constant_phase;
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phase->function_id = function_id;
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/* The insertion location must be set after the label is emitted. */
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phase->function_location = 0;
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if (instruction->handler_idx == VKD3DSIH_HS_CONTROL_POINT_PHASE)
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if (instruction->opcode == VKD3DSIH_HS_CONTROL_POINT_PHASE)
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compiler->emit_default_control_point_phase = instruction->flags;
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}
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@@ -7016,7 +7016,7 @@ static SpvOp spirv_compiler_map_alu_instruction(const struct vkd3d_shader_instru
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{
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static const struct
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{
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enum vkd3d_shader_opcode handler_idx;
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enum vkd3d_shader_opcode opcode;
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SpvOp spirv_op;
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}
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alu_ops[] =
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@@ -7056,7 +7056,7 @@ static SpvOp spirv_compiler_map_alu_instruction(const struct vkd3d_shader_instru
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for (i = 0; i < ARRAY_SIZE(alu_ops); ++i)
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{
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if (alu_ops[i].handler_idx == instruction->handler_idx)
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if (alu_ops[i].opcode == instruction->opcode)
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return alu_ops[i].spirv_op;
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}
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@@ -7065,7 +7065,7 @@ static SpvOp spirv_compiler_map_alu_instruction(const struct vkd3d_shader_instru
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static SpvOp spirv_compiler_map_logical_instruction(const struct vkd3d_shader_instruction *instruction)
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{
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switch (instruction->handler_idx)
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switch (instruction->opcode)
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{
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case VKD3DSIH_AND:
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return SpvOpLogicalAnd;
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@@ -7090,20 +7090,20 @@ static void spirv_compiler_emit_bool_cast(struct spirv_compiler *compiler,
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val_id = spirv_compiler_emit_load_src(compiler, src, dst->write_mask);
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if (dst->reg.data_type == VKD3D_DATA_HALF || dst->reg.data_type == VKD3D_DATA_FLOAT)
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{
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val_id = spirv_compiler_emit_bool_to_float(compiler, 1, val_id, instruction->handler_idx == VKD3DSIH_ITOF);
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val_id = spirv_compiler_emit_bool_to_float(compiler, 1, val_id, instruction->opcode == VKD3DSIH_ITOF);
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}
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else if (dst->reg.data_type == VKD3D_DATA_DOUBLE)
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{
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/* ITOD is not supported. Frontends which emit bool casts must use ITOF for double. */
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val_id = spirv_compiler_emit_bool_to_double(compiler, 1, val_id, instruction->handler_idx == VKD3DSIH_ITOF);
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val_id = spirv_compiler_emit_bool_to_double(compiler, 1, val_id, instruction->opcode == VKD3DSIH_ITOF);
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}
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else if (dst->reg.data_type == VKD3D_DATA_UINT16 || dst->reg.data_type == VKD3D_DATA_UINT)
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{
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val_id = spirv_compiler_emit_bool_to_int(compiler, 1, val_id, instruction->handler_idx == VKD3DSIH_ITOI);
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val_id = spirv_compiler_emit_bool_to_int(compiler, 1, val_id, instruction->opcode == VKD3DSIH_ITOI);
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}
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else if (dst->reg.data_type == VKD3D_DATA_UINT64)
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{
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val_id = spirv_compiler_emit_bool_to_int64(compiler, 1, val_id, instruction->handler_idx == VKD3DSIH_ITOI);
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val_id = spirv_compiler_emit_bool_to_int64(compiler, 1, val_id, instruction->opcode == VKD3DSIH_ITOI);
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}
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else
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{
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@@ -7126,7 +7126,7 @@ static enum vkd3d_result spirv_compiler_emit_alu_instruction(struct spirv_compil
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SpvOp op = SpvOpMax;
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unsigned int i;
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if (src->reg.data_type == VKD3D_DATA_UINT64 && instruction->handler_idx == VKD3DSIH_COUNTBITS)
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if (src->reg.data_type == VKD3D_DATA_UINT64 && instruction->opcode == VKD3DSIH_COUNTBITS)
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{
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/* At least some drivers support this anyway, but if validation is enabled it will fail. */
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FIXME("Unsupported 64-bit source for bit count.\n");
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@@ -7142,8 +7142,8 @@ static enum vkd3d_result spirv_compiler_emit_alu_instruction(struct spirv_compil
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/* VSIR supports logic ops AND/OR/XOR on bool values. */
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op = spirv_compiler_map_logical_instruction(instruction);
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}
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else if (instruction->handler_idx == VKD3DSIH_ITOF || instruction->handler_idx == VKD3DSIH_UTOF
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|| instruction->handler_idx == VKD3DSIH_ITOI || instruction->handler_idx == VKD3DSIH_UTOU)
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else if (instruction->opcode == VKD3DSIH_ITOF || instruction->opcode == VKD3DSIH_UTOF
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|| instruction->opcode == VKD3DSIH_ITOI || instruction->opcode == VKD3DSIH_UTOU)
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{
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/* VSIR supports cast from bool to signed/unsigned integer types and floating point types,
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* where bool is treated as a 1-bit integer and a signed 'true' value converts to -1. */
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@@ -7158,9 +7158,9 @@ static enum vkd3d_result spirv_compiler_emit_alu_instruction(struct spirv_compil
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if (op == SpvOpMax)
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{
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ERR("Unexpected instruction %#x.\n", instruction->handler_idx);
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ERR("Unexpected instruction %#x.\n", instruction->opcode);
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spirv_compiler_error(compiler, VKD3D_SHADER_ERROR_SPV_INVALID_HANDLER,
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"Encountered invalid/unhandled instruction handler %#x.", instruction->handler_idx);
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"Encountered invalid/unhandled instruction handler %#x.", instruction->opcode);
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return VKD3D_ERROR_INVALID_SHADER;
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}
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@@ -7179,8 +7179,8 @@ static enum vkd3d_result spirv_compiler_emit_alu_instruction(struct spirv_compil
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* Microsoft fxc will compile immediate constants larger than 5 bits.
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* Fixing up the constants would be more elegant, but the simplest way is
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* to let this handle constants too. */
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if (!(instruction->flags & VKD3DSI_SHIFT_UNMASKED) && (instruction->handler_idx == VKD3DSIH_ISHL
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|| instruction->handler_idx == VKD3DSIH_ISHR || instruction->handler_idx == VKD3DSIH_USHR))
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if (!(instruction->flags & VKD3DSI_SHIFT_UNMASKED) && (instruction->opcode == VKD3DSIH_ISHL
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|| instruction->opcode == VKD3DSIH_ISHR || instruction->opcode == VKD3DSIH_USHR))
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{
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uint32_t mask_id = spirv_compiler_get_constant_vector(compiler,
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VKD3D_SHADER_COMPONENT_UINT, vsir_write_mask_component_count(dst->write_mask), 0x1f);
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@@ -7218,7 +7218,7 @@ static enum GLSLstd450 spirv_compiler_map_ext_glsl_instruction(
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{
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static const struct
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{
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enum vkd3d_shader_opcode handler_idx;
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enum vkd3d_shader_opcode opcode;
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enum GLSLstd450 glsl_inst;
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}
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glsl_insts[] =
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@@ -7258,7 +7258,7 @@ static enum GLSLstd450 spirv_compiler_map_ext_glsl_instruction(
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for (i = 0; i < ARRAY_SIZE(glsl_insts); ++i)
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{
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if (glsl_insts[i].handler_idx == instruction->handler_idx)
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if (glsl_insts[i].opcode == instruction->opcode)
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return glsl_insts[i].glsl_inst;
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}
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@@ -7276,20 +7276,20 @@ static void spirv_compiler_emit_ext_glsl_instruction(struct spirv_compiler *comp
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unsigned int i, component_count;
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enum GLSLstd450 glsl_inst;
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if (src[0].reg.data_type == VKD3D_DATA_UINT64 && (instruction->handler_idx == VKD3DSIH_FIRSTBIT_HI
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|| instruction->handler_idx == VKD3DSIH_FIRSTBIT_LO || instruction->handler_idx == VKD3DSIH_FIRSTBIT_SHI))
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if (src[0].reg.data_type == VKD3D_DATA_UINT64 && (instruction->opcode == VKD3DSIH_FIRSTBIT_HI
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|| instruction->opcode == VKD3DSIH_FIRSTBIT_LO || instruction->opcode == VKD3DSIH_FIRSTBIT_SHI))
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{
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/* At least some drivers support this anyway, but if validation is enabled it will fail. */
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FIXME("Unsupported 64-bit source for handler %#x.\n", instruction->handler_idx);
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FIXME("Unsupported 64-bit source for handler %#x.\n", instruction->opcode);
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spirv_compiler_error(compiler, VKD3D_SHADER_ERROR_SPV_NOT_IMPLEMENTED,
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"64-bit source for handler %#x is not supported.", instruction->handler_idx);
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"64-bit source for handler %#x is not supported.", instruction->opcode);
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return;
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}
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glsl_inst = spirv_compiler_map_ext_glsl_instruction(instruction);
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if (glsl_inst == GLSLstd450Bad)
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{
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ERR("Unexpected instruction %#x.\n", instruction->handler_idx);
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ERR("Unexpected instruction %#x.\n", instruction->opcode);
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return;
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}
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@@ -7306,8 +7306,8 @@ static void spirv_compiler_emit_ext_glsl_instruction(struct spirv_compiler *comp
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val_id = vkd3d_spirv_build_op_ext_inst(builder, type_id,
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instr_set_id, glsl_inst, src_id, instruction->src_count);
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if (instruction->handler_idx == VKD3DSIH_FIRSTBIT_HI
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|| instruction->handler_idx == VKD3DSIH_FIRSTBIT_SHI)
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if (instruction->opcode == VKD3DSIH_FIRSTBIT_HI
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|| instruction->opcode == VKD3DSIH_FIRSTBIT_SHI)
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{
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/* In D3D bits are numbered from the most significant bit. */
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component_count = vsir_write_mask_component_count(dst->write_mask);
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@@ -7415,7 +7415,7 @@ static void spirv_compiler_emit_movc(struct spirv_compiler *compiler,
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if (src[0].reg.data_type != VKD3D_DATA_BOOL)
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{
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if (instruction->handler_idx == VKD3DSIH_CMP)
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if (instruction->opcode == VKD3DSIH_CMP)
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condition_id = vkd3d_spirv_build_op_tr2(builder, &builder->function_stream, SpvOpFOrdGreaterThanEqual,
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vkd3d_spirv_get_type_id(builder, VKD3D_SHADER_COMPONENT_BOOL, component_count), condition_id,
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spirv_compiler_get_constant_float_vector(compiler, 0.0f, component_count));
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@@ -7469,9 +7469,9 @@ static void spirv_compiler_emit_dot(struct spirv_compiler *compiler,
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component_count = vsir_write_mask_component_count(dst->write_mask);
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component_type = vkd3d_component_type_from_data_type(dst->reg.data_type);
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if (instruction->handler_idx == VKD3DSIH_DP4)
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if (instruction->opcode == VKD3DSIH_DP4)
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write_mask = VKD3DSP_WRITEMASK_ALL;
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else if (instruction->handler_idx == VKD3DSIH_DP3)
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else if (instruction->opcode == VKD3DSIH_DP3)
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write_mask = VKD3DSP_WRITEMASK_0 | VKD3DSP_WRITEMASK_1 | VKD3DSP_WRITEMASK_2;
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else
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write_mask = VKD3DSP_WRITEMASK_0 | VKD3DSP_WRITEMASK_1;
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@@ -7606,8 +7606,8 @@ static void spirv_compiler_emit_int_div(struct spirv_compiler *compiler,
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unsigned int component_count = 0;
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SpvOp div_op, mod_op;
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div_op = instruction->handler_idx == VKD3DSIH_IDIV ? SpvOpSDiv : SpvOpUDiv;
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mod_op = instruction->handler_idx == VKD3DSIH_IDIV ? SpvOpSRem : SpvOpUMod;
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div_op = instruction->opcode == VKD3DSIH_IDIV ? SpvOpSDiv : SpvOpUDiv;
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mod_op = instruction->opcode == VKD3DSIH_IDIV ? SpvOpSRem : SpvOpUMod;
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if (dst[0].reg.type != VKD3DSPR_NULL)
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{
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@@ -7778,13 +7778,13 @@ static void spirv_compiler_emit_bitfield_instruction(struct spirv_compiler *comp
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mask_id = spirv_compiler_get_constant_uint(compiler, size - 1);
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size_id = spirv_compiler_get_constant_uint(compiler, size);
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switch (instruction->handler_idx)
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switch (instruction->opcode)
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{
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case VKD3DSIH_BFI: op = SpvOpBitFieldInsert; break;
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case VKD3DSIH_IBFE: op = SpvOpBitFieldSExtract; break;
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case VKD3DSIH_UBFE: op = SpvOpBitFieldUExtract; break;
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default:
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ERR("Unexpected instruction %#x.\n", instruction->handler_idx);
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ERR("Unexpected instruction %#x.\n", instruction->opcode);
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return;
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}
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@@ -7895,7 +7895,7 @@ static void spirv_compiler_emit_comparison_instruction(struct spirv_compiler *co
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unsigned int component_count;
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SpvOp op;
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switch (instruction->handler_idx)
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switch (instruction->opcode)
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{
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case VKD3DSIH_DEQO:
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case VKD3DSIH_EQO: op = SpvOpFOrdEqual; break;
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@@ -7916,7 +7916,7 @@ static void spirv_compiler_emit_comparison_instruction(struct spirv_compiler *co
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case VKD3DSIH_UGE: op = SpvOpUGreaterThanEqual; break;
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case VKD3DSIH_ULT: op = SpvOpULessThan; break;
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default:
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ERR("Unexpected instruction %#x.\n", instruction->handler_idx);
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ERR("Unexpected instruction %#x.\n", instruction->opcode);
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return;
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}
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@@ -7949,7 +7949,7 @@ static void spirv_compiler_emit_orderedness_instruction(struct spirv_compiler *c
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src0_id = vkd3d_spirv_build_op_is_nan(builder, type_id, src0_id);
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src1_id = vkd3d_spirv_build_op_is_nan(builder, type_id, src1_id);
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val_id = vkd3d_spirv_build_op_logical_or(builder, type_id, src0_id, src1_id);
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if (instruction->handler_idx == VKD3DSIH_ORD)
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if (instruction->opcode == VKD3DSIH_ORD)
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val_id = vkd3d_spirv_build_op_logical_not(builder, type_id, val_id);
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spirv_compiler_emit_store_dst(compiler, dst, val_id);
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}
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@@ -7964,7 +7964,7 @@ static void spirv_compiler_emit_float_comparison_instruction(struct spirv_compil
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unsigned int component_count;
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SpvOp op;
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switch (instruction->handler_idx)
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switch (instruction->opcode)
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{
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case VKD3DSIH_SLT: op = SpvOpFOrdLessThan; break;
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case VKD3DSIH_SGE: op = SpvOpFOrdGreaterThanEqual; break;
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@@ -8262,7 +8262,7 @@ static void spirv_compiler_emit_deriv_instruction(struct spirv_compiler *compile
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static const struct instruction_info
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{
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enum vkd3d_shader_opcode handler_idx;
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enum vkd3d_shader_opcode opcode;
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SpvOp op;
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bool needs_derivative_control;
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}
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@@ -8279,7 +8279,7 @@ static void spirv_compiler_emit_deriv_instruction(struct spirv_compiler *compile
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info = NULL;
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for (i = 0; i < ARRAY_SIZE(deriv_instructions); ++i)
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{
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if (deriv_instructions[i].handler_idx == instruction->handler_idx)
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if (deriv_instructions[i].opcode == instruction->opcode)
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{
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info = &deriv_instructions[i];
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break;
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@@ -8287,7 +8287,7 @@ static void spirv_compiler_emit_deriv_instruction(struct spirv_compiler *compile
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}
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if (!info)
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{
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ERR("Unexpected instruction %#x.\n", instruction->handler_idx);
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ERR("Unexpected instruction %#x.\n", instruction->opcode);
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return;
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}
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@@ -8497,7 +8497,7 @@ static void spirv_compiler_emit_ld(struct spirv_compiler *compiler,
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uint32_t coordinate_mask;
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bool multisample;
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multisample = instruction->handler_idx == VKD3DSIH_LD2DMS;
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multisample = instruction->opcode == VKD3DSIH_LD2DMS;
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spirv_compiler_prepare_image(compiler, &image, &src[1].reg, NULL, VKD3D_IMAGE_FLAG_NONE);
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@@ -8576,7 +8576,7 @@ static void spirv_compiler_emit_sample(struct spirv_compiler *compiler,
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spirv_compiler_prepare_image(compiler, &image,
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&resource->reg, &sampler->reg, VKD3D_IMAGE_FLAG_SAMPLED);
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switch (instruction->handler_idx)
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switch (instruction->opcode)
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{
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case VKD3DSIH_SAMPLE:
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op = SpvOpImageSampleImplicitLod;
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@@ -8603,7 +8603,7 @@ static void spirv_compiler_emit_sample(struct spirv_compiler *compiler,
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&src[3], VKD3DSP_WRITEMASK_0);
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break;
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default:
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ERR("Unexpected instruction %#x.\n", instruction->handler_idx);
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ERR("Unexpected instruction %#x.\n", instruction->opcode);
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return;
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}
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@@ -8637,7 +8637,7 @@ static void spirv_compiler_emit_sample_c(struct spirv_compiler *compiler,
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uint32_t image_operands[2];
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SpvOp op;
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if (instruction->handler_idx == VKD3DSIH_SAMPLE_C_LZ)
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if (instruction->opcode == VKD3DSIH_SAMPLE_C_LZ)
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{
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op = SpvOpImageSampleDrefExplicitLod;
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operands_mask |= SpvImageOperandsLodMask;
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@@ -8687,12 +8687,12 @@ static void spirv_compiler_emit_gather4(struct spirv_compiler *compiler,
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uint32_t coordinate_mask;
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bool extended_offset;
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if (instruction->handler_idx == VKD3DSIH_GATHER4_C
|
||||
|| instruction->handler_idx == VKD3DSIH_GATHER4_PO_C)
|
||||
if (instruction->opcode == VKD3DSIH_GATHER4_C
|
||||
|| instruction->opcode == VKD3DSIH_GATHER4_PO_C)
|
||||
image_flags |= VKD3D_IMAGE_FLAG_DEPTH;
|
||||
|
||||
extended_offset = instruction->handler_idx == VKD3DSIH_GATHER4_PO
|
||||
|| instruction->handler_idx == VKD3DSIH_GATHER4_PO_C;
|
||||
extended_offset = instruction->opcode == VKD3DSIH_GATHER4_PO
|
||||
|| instruction->opcode == VKD3DSIH_GATHER4_PO_C;
|
||||
|
||||
addr = &src[0];
|
||||
offset = extended_offset ? &src[1] : NULL;
|
||||
@@ -8963,7 +8963,6 @@ static void spirv_compiler_emit_store_uav_raw_structured(struct spirv_compiler *
|
||||
{
|
||||
type_id = vkd3d_spirv_get_type_id(builder, VKD3D_SHADER_COMPONENT_UINT, 1);
|
||||
spirv_compiler_prepare_image(compiler, &image, &dst->reg, NULL, VKD3D_IMAGE_FLAG_NONE);
|
||||
assert((instruction->handler_idx == VKD3DSIH_STORE_STRUCTURED) != !image.structure_stride);
|
||||
base_coordinate_id = spirv_compiler_emit_raw_structured_addressing(compiler,
|
||||
type_id, image.structure_stride, &src[0], VKD3DSP_WRITEMASK_0, &src[1], VKD3DSP_WRITEMASK_0);
|
||||
|
||||
@@ -9007,7 +9006,6 @@ static void spirv_compiler_emit_store_tgsm(struct spirv_compiler *compiler,
|
||||
|
||||
type_id = vkd3d_spirv_get_type_id(builder, VKD3D_SHADER_COMPONENT_UINT, 1);
|
||||
ptr_type_id = vkd3d_spirv_get_op_type_pointer(builder, reg_info.storage_class, type_id);
|
||||
assert((instruction->handler_idx == VKD3DSIH_STORE_STRUCTURED) != !reg_info.structure_stride);
|
||||
base_coordinate_id = spirv_compiler_emit_raw_structured_addressing(compiler,
|
||||
type_id, reg_info.structure_stride, &src[0], VKD3DSP_WRITEMASK_0, &src[1], VKD3DSP_WRITEMASK_0);
|
||||
|
||||
@@ -9145,7 +9143,7 @@ static void spirv_compiler_emit_uav_counter_instruction(struct spirv_compiler *c
|
||||
uint32_t operands[3];
|
||||
SpvOp op;
|
||||
|
||||
op = instruction->handler_idx == VKD3DSIH_IMM_ATOMIC_ALLOC
|
||||
op = instruction->opcode == VKD3DSIH_IMM_ATOMIC_ALLOC
|
||||
? SpvOpAtomicIIncrement : SpvOpAtomicIDecrement;
|
||||
|
||||
resource_symbol = spirv_compiler_find_resource(compiler, &src->reg);
|
||||
@@ -9211,7 +9209,7 @@ static SpvOp spirv_compiler_map_atomic_instruction(const struct vkd3d_shader_ins
|
||||
{
|
||||
static const struct
|
||||
{
|
||||
enum vkd3d_shader_opcode handler_idx;
|
||||
enum vkd3d_shader_opcode opcode;
|
||||
SpvOp spirv_op;
|
||||
}
|
||||
atomic_ops[] =
|
||||
@@ -9240,16 +9238,16 @@ static SpvOp spirv_compiler_map_atomic_instruction(const struct vkd3d_shader_ins
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(atomic_ops); ++i)
|
||||
{
|
||||
if (atomic_ops[i].handler_idx == instruction->handler_idx)
|
||||
if (atomic_ops[i].opcode == instruction->opcode)
|
||||
return atomic_ops[i].spirv_op;
|
||||
}
|
||||
|
||||
return SpvOpMax;
|
||||
}
|
||||
|
||||
static bool is_imm_atomic_instruction(enum vkd3d_shader_opcode handler_idx)
|
||||
static bool is_imm_atomic_instruction(enum vkd3d_shader_opcode opcode)
|
||||
{
|
||||
return VKD3DSIH_IMM_ATOMIC_ALLOC <= handler_idx && handler_idx <= VKD3DSIH_IMM_ATOMIC_XOR;
|
||||
return VKD3DSIH_IMM_ATOMIC_ALLOC <= opcode && opcode <= VKD3DSIH_IMM_ATOMIC_XOR;
|
||||
}
|
||||
|
||||
static void spirv_compiler_emit_atomic_instruction(struct spirv_compiler *compiler,
|
||||
@@ -9274,12 +9272,12 @@ static void spirv_compiler_emit_atomic_instruction(struct spirv_compiler *compil
|
||||
bool raw;
|
||||
SpvOp op;
|
||||
|
||||
resource = is_imm_atomic_instruction(instruction->handler_idx) ? &dst[1] : &dst[0];
|
||||
resource = is_imm_atomic_instruction(instruction->opcode) ? &dst[1] : &dst[0];
|
||||
|
||||
op = spirv_compiler_map_atomic_instruction(instruction);
|
||||
if (op == SpvOpMax)
|
||||
{
|
||||
ERR("Unexpected instruction %#x.\n", instruction->handler_idx);
|
||||
ERR("Unexpected instruction %#x.\n", instruction->opcode);
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -9360,7 +9358,7 @@ static void spirv_compiler_emit_atomic_instruction(struct spirv_compiler *compil
|
||||
{
|
||||
WARN("Ignoring 'volatile' attribute.\n");
|
||||
spirv_compiler_warning(compiler, VKD3D_SHADER_WARNING_SPV_IGNORING_FLAG,
|
||||
"Ignoring the 'volatile' attribute flag for atomic instruction %#x.", instruction->handler_idx);
|
||||
"Ignoring the 'volatile' attribute flag for atomic instruction %#x.", instruction->opcode);
|
||||
}
|
||||
|
||||
memory_semantic = (instruction->flags & VKD3DARF_SEQ_CST)
|
||||
@@ -9379,7 +9377,7 @@ static void spirv_compiler_emit_atomic_instruction(struct spirv_compiler *compil
|
||||
result_id = vkd3d_spirv_build_op_trv(builder, &builder->function_stream,
|
||||
op, type_id, operands, i);
|
||||
|
||||
if (is_imm_atomic_instruction(instruction->handler_idx))
|
||||
if (is_imm_atomic_instruction(instruction->opcode))
|
||||
spirv_compiler_emit_store_dst(compiler, dst, result_id);
|
||||
}
|
||||
|
||||
@@ -9684,13 +9682,13 @@ static void spirv_compiler_emit_eval_attrib(struct spirv_compiler *compiler,
|
||||
|
||||
src_ids[src_count++] = register_info.id;
|
||||
|
||||
if (instruction->handler_idx == VKD3DSIH_EVAL_CENTROID)
|
||||
if (instruction->opcode == VKD3DSIH_EVAL_CENTROID)
|
||||
{
|
||||
op = GLSLstd450InterpolateAtCentroid;
|
||||
}
|
||||
else
|
||||
{
|
||||
assert(instruction->handler_idx == VKD3DSIH_EVAL_SAMPLE_INDEX);
|
||||
assert(instruction->opcode == VKD3DSIH_EVAL_SAMPLE_INDEX);
|
||||
op = GLSLstd450InterpolateAtSample;
|
||||
src_ids[src_count++] = spirv_compiler_emit_load_src(compiler, &src[1], VKD3DSP_WRITEMASK_0);
|
||||
}
|
||||
@@ -9772,7 +9770,7 @@ static void spirv_compiler_emit_emit_stream(struct spirv_compiler *compiler,
|
||||
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
|
||||
unsigned int stream_idx;
|
||||
|
||||
if (instruction->handler_idx == VKD3DSIH_EMIT_STREAM)
|
||||
if (instruction->opcode == VKD3DSIH_EMIT_STREAM)
|
||||
stream_idx = instruction->src[0].reg.idx[0].offset;
|
||||
else
|
||||
stream_idx = 0;
|
||||
@@ -9793,7 +9791,7 @@ static void spirv_compiler_emit_cut_stream(struct spirv_compiler *compiler,
|
||||
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
|
||||
unsigned int stream_idx;
|
||||
|
||||
if (instruction->handler_idx == VKD3DSIH_CUT_STREAM)
|
||||
if (instruction->opcode == VKD3DSIH_CUT_STREAM)
|
||||
stream_idx = instruction->src[0].reg.idx[0].offset;
|
||||
else
|
||||
stream_idx = 0;
|
||||
@@ -9807,9 +9805,9 @@ static void spirv_compiler_emit_cut_stream(struct spirv_compiler *compiler,
|
||||
vkd3d_spirv_build_op_end_primitive(builder);
|
||||
}
|
||||
|
||||
static SpvOp map_wave_bool_op(enum vkd3d_shader_opcode handler_idx)
|
||||
static SpvOp map_wave_bool_op(enum vkd3d_shader_opcode opcode)
|
||||
{
|
||||
switch (handler_idx)
|
||||
switch (opcode)
|
||||
{
|
||||
case VKD3DSIH_WAVE_ACTIVE_ALL_EQUAL:
|
||||
return SpvOpGroupNonUniformAllEqual;
|
||||
@@ -9833,7 +9831,7 @@ static void spirv_compiler_emit_wave_bool_op(struct spirv_compiler *compiler,
|
||||
|
||||
vkd3d_spirv_enable_capability(builder, SpvCapabilityGroupNonUniformVote);
|
||||
|
||||
op = map_wave_bool_op(instruction->handler_idx);
|
||||
op = map_wave_bool_op(instruction->opcode);
|
||||
type_id = vkd3d_spirv_get_op_type_bool(builder);
|
||||
val_id = spirv_compiler_emit_load_src(compiler, src, dst->write_mask);
|
||||
val_id = vkd3d_spirv_build_op_tr2(builder, &builder->function_stream, op,
|
||||
@@ -9865,9 +9863,9 @@ static void spirv_compiler_emit_wave_active_ballot(struct spirv_compiler *compil
|
||||
spirv_compiler_emit_store_dst(compiler, dst, val_id);
|
||||
}
|
||||
|
||||
static SpvOp map_wave_alu_op(enum vkd3d_shader_opcode handler_idx, bool is_float)
|
||||
static SpvOp map_wave_alu_op(enum vkd3d_shader_opcode opcode, bool is_float)
|
||||
{
|
||||
switch (handler_idx)
|
||||
switch (opcode)
|
||||
{
|
||||
case VKD3DSIH_WAVE_ACTIVE_BIT_AND:
|
||||
return SpvOpGroupNonUniformBitwiseAnd;
|
||||
@@ -9905,7 +9903,7 @@ static void spirv_compiler_emit_wave_alu_op(struct spirv_compiler *compiler,
|
||||
uint32_t type_id, val_id;
|
||||
SpvOp op;
|
||||
|
||||
op = map_wave_alu_op(instruction->handler_idx, data_type_is_floating_point(src->reg.data_type));
|
||||
op = map_wave_alu_op(instruction->opcode, data_type_is_floating_point(src->reg.data_type));
|
||||
|
||||
type_id = vkd3d_spirv_get_type_id_for_data_type(builder, dst->reg.data_type,
|
||||
vsir_write_mask_component_count(dst->write_mask));
|
||||
@@ -9928,7 +9926,7 @@ static void spirv_compiler_emit_wave_bit_count(struct spirv_compiler *compiler,
|
||||
SpvGroupOperation group_op;
|
||||
uint32_t type_id, val_id;
|
||||
|
||||
group_op = (instruction->handler_idx == VKD3DSIH_WAVE_PREFIX_BIT_COUNT) ? SpvGroupOperationExclusiveScan
|
||||
group_op = (instruction->opcode == VKD3DSIH_WAVE_PREFIX_BIT_COUNT) ? SpvGroupOperationExclusiveScan
|
||||
: SpvGroupOperationReduce;
|
||||
|
||||
val_id = spirv_compiler_emit_group_nonuniform_ballot(compiler, instruction->src);
|
||||
@@ -10014,7 +10012,7 @@ static int spirv_compiler_handle_instruction(struct spirv_compiler *compiler,
|
||||
|
||||
compiler->location = instruction->location;
|
||||
|
||||
switch (instruction->handler_idx)
|
||||
switch (instruction->opcode)
|
||||
{
|
||||
case VKD3DSIH_DCL_GLOBAL_FLAGS:
|
||||
spirv_compiler_emit_dcl_global_flags(compiler, instruction);
|
||||
@@ -10390,9 +10388,9 @@ static int spirv_compiler_handle_instruction(struct spirv_compiler *compiler,
|
||||
/* nothing to do */
|
||||
break;
|
||||
default:
|
||||
FIXME("Unhandled instruction %#x.\n", instruction->handler_idx);
|
||||
FIXME("Unhandled instruction %#x.\n", instruction->opcode);
|
||||
spirv_compiler_error(compiler, VKD3D_SHADER_ERROR_SPV_INVALID_HANDLER,
|
||||
"Encountered invalid/unhandled instruction handler %#x.", instruction->handler_idx);
|
||||
"Encountered invalid/unhandled instruction handler %#x.", instruction->opcode);
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user