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Backed out changeset a8832e8df0c8 (bug 811349) because of busted b2g debug builds

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This commit is contained in:
Ehsan Akhgari 2012-11-17 10:59:39 -05:00
parent 9c6f4bfb88
commit 400a738411
12 changed files with 742 additions and 544 deletions
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205
js/src/assembler/assembler/ARMAssembler.h
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@ -41,7 +41,24 @@
#include "AssemblerBufferWithConstantPool.h"
#include "assembler/wtf/Assertions.h"
// TODO: We don't print the condition code in our spew lines. Doing this
#include "methodjit/Logging.h"
#define IPFX " %s"
#define ISPFX " "
#ifdef JS_METHODJIT_SPEW
# define MAYBE_PAD (isOOLPath ? "> " : "")
# define FIXME_INSN_PRINTING \
do { \
js::JaegerSpew(js::JSpew_Insns, \
IPFX "FIXME insn printing %s:%d\n", \
MAYBE_PAD, \
__FILE__, __LINE__); \
} while (0)
#else
# define MAYBE_PAD ""
# define FIXME_INSN_PRINTING ((void) 0)
#endif
// TODO: We don't print the condition code in our JaegerSpew lines. Doing this
// is awkward whilst maintaining a consistent field width.
namespace js {
namespace ion {
@ -126,9 +143,16 @@ namespace JSC {
return (FPRegisterID)(d / 2);
}
} // namespace ARMRegisters
class ARMAssembler : public GenericAssembler {
class ARMAssembler {
public:
#ifdef JS_METHODJIT_SPEW
bool isOOLPath;
// Assign a default value to keep Valgrind quiet.
ARMAssembler() : isOOLPath(false) { }
#else
ARMAssembler() { }
#endif
typedef ARMRegisters::RegisterID RegisterID;
typedef ARMRegisters::FPRegisterID FPRegisterID;
typedef AssemblerBufferWithConstantPool<2048, 4, 4, ARMAssembler> ARMBuffer;
@ -469,14 +493,16 @@ namespace JSC {
void movw_r(int rd, ARMWord op2, Condition cc = AL)
{
ASSERT((op2 | 0xf0fff) == 0xf0fff);
spew("%-15s %s, 0x%04x", "movw", nameGpReg(rd), (op2 & 0xfff) | ((op2 >> 4) & 0xf000));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, 0x%04x\n", MAYBE_PAD, "movw", nameGpReg(rd), (op2 & 0xfff) | ((op2 >> 4) & 0xf000));
m_buffer.putInt(static_cast<ARMWord>(cc) | MOVW | RD(rd) | op2);
}
void movt_r(int rd, ARMWord op2, Condition cc = AL)
{
ASSERT((op2 | 0xf0fff) == 0xf0fff);
spew("%-15s %s, 0x%04x", "movt", nameGpReg(rd), (op2 & 0xfff) | ((op2 >> 4) & 0xf000));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, 0x%04x\n", MAYBE_PAD, "movt", nameGpReg(rd), (op2 & 0xfff) | ((op2 >> 4) & 0xf000));
m_buffer.putInt(static_cast<ARMWord>(cc) | MOVT | RD(rd) | op2);
}
#endif
@ -525,7 +551,8 @@ namespace JSC {
void mull_r(int rdhi, int rdlo, int rn, int rm, Condition cc = AL)
{
spew("%-15s %s, %s, %s, %s", "mull", nameGpReg(rdlo), nameGpReg(rdhi), nameGpReg(rn), nameGpReg(rm));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, %s, %s, %s\n", MAYBE_PAD, "mull", nameGpReg(rdlo), nameGpReg(rdhi), nameGpReg(rn), nameGpReg(rm));
m_buffer.putInt(static_cast<ARMWord>(cc) | MULL | RN(rdhi) | RD(rdlo) | RS(rn) | RM(rm));
}
@ -534,7 +561,8 @@ namespace JSC {
{
char mnemonic[16];
snprintf(mnemonic, 16, "ldr%s", nameCC(cc));
spew("%-15s %s, =0x%x @ (%d) (reusable pool entry)", mnemonic, nameGpReg(rd), imm, static_cast<int32_t>(imm));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, =0x%x @ (%d) (reusable pool entry)\n", MAYBE_PAD, mnemonic, nameGpReg(rd), imm, static_cast<int32_t>(imm));
m_buffer.putIntWithConstantInt(static_cast<ARMWord>(cc) | DTR | DT_LOAD | DT_UP | RN(ARMRegisters::pc) | RD(rd), imm, true);
}
@ -542,7 +570,8 @@ namespace JSC {
{
char mnemonic[16];
snprintf(mnemonic, 16, "ldr%s", nameCC(cc));
spew("%-15s %s, =0x%x @ (%d)", mnemonic, nameGpReg(rd), imm, static_cast<int32_t>(imm));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, =0x%x @ (%d)\n", MAYBE_PAD, mnemonic, nameGpReg(rd), imm, static_cast<int32_t>(imm));
m_buffer.putIntWithConstantInt(static_cast<ARMWord>(cc) | DTR | DT_LOAD | DT_UP | RN(ARMRegisters::pc) | RD(rd), imm);
}
@ -566,8 +595,9 @@ namespace JSC {
break;
}
char const * off_sign = (posOffset) ? ("+") : ("-");
spew("%sr%s%s %s, [%s, #%s%u]",
mnemonic_act, mnemonic_sign, mnemonic_size,
js::JaegerSpew(js::JSpew_Insns,
IPFX "%sr%s%s %s, [%s, #%s%u]\n",
MAYBE_PAD, mnemonic_act, mnemonic_sign, mnemonic_size,
nameGpReg(rd), nameGpReg(rb), off_sign, offset);
if (size == 32 || (size == 8 && !isSigned)) {
/* All (the one) 32 bit ops and the unsigned 8 bit ops use the original encoding.*/
@ -603,7 +633,8 @@ namespace JSC {
break;
}
char const * off_sign = (posOffset) ? ("+") : ("-");
spew("%sr%s%s %s, [%s, #%s%s]", mnemonic_act, mnemonic_sign, mnemonic_size,
js::JaegerSpew(js::JSpew_Insns,
IPFX "%sr%s%s %s, [%s, #%s%s]\n", MAYBE_PAD, mnemonic_act, mnemonic_sign, mnemonic_size,
nameGpReg(rd), nameGpReg(rb), off_sign, nameGpReg(rm));
if (size == 32 || (size == 8 && !isSigned)) {
/* All (the one) 32 bit ops and the signed 8 bit ops use the original encoding.*/
@ -628,8 +659,8 @@ namespace JSC {
void dtr_u(bool isLoad, int rd, int rb, ARMWord offset, Condition cc = AL)
{
char const * mnemonic = (isLoad) ? ("ldr") : ("str");
spew("%-15s %s, [%s, #+%u]",
mnemonic, nameGpReg(rd), nameGpReg(rb), offset);
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, [%s, #+%u]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), offset);
emitInst(static_cast<ARMWord>(cc) | DTR | (isLoad ? DT_LOAD : 0) | DT_UP, rd, rb, offset);
}
@ -639,8 +670,8 @@ namespace JSC {
void dtr_ur(bool isLoad, int rd, int rb, int rm, Condition cc = AL)
{
char const * mnemonic = (isLoad) ? ("ldr") : ("str");
spew("%-15s %s, [%s, +%s]",
mnemonic, nameGpReg(rd), nameGpReg(rb), nameGpReg(rm));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, [%s, +%s]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), nameGpReg(rm));
emitInst(static_cast<ARMWord>(cc) | DTR | (isLoad ? DT_LOAD : 0) | DT_UP | OP2_OFSREG, rd, rb, rm);
}
@ -650,8 +681,8 @@ namespace JSC {
void dtr_d(bool isLoad, int rd, int rb, ARMWord offset, Condition cc = AL)
{
char const * mnemonic = (isLoad) ? ("ldr") : ("str");
spew("%-15s %s, [%s, #-%u]",
mnemonic, nameGpReg(rd), nameGpReg(rb), offset);
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, [%s, #-%u]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), offset);
emitInst(static_cast<ARMWord>(cc) | DTR | (isLoad ? DT_LOAD : 0), rd, rb, offset);
}
@ -661,8 +692,8 @@ namespace JSC {
void dtr_dr(bool isLoad, int rd, int rb, int rm, Condition cc = AL)
{
char const * mnemonic = (isLoad) ? ("ldr") : ("str");
spew("%-15s %s, [%s, -%s]",
mnemonic, nameGpReg(rd), nameGpReg(rb), nameGpReg(rm));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, [%s, -%s]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), nameGpReg(rm));
emitInst(static_cast<ARMWord>(cc) | DTR | (isLoad ? DT_LOAD : 0) | OP2_OFSREG, rd, rb, rm);
}
@ -672,8 +703,8 @@ namespace JSC {
void dtrb_u(bool isLoad, int rd, int rb, ARMWord offset, Condition cc = AL)
{
char const * mnemonic = (isLoad) ? ("ldrb") : ("strb");
spew("%-15s %s, [%s, #+%u]",
mnemonic, nameGpReg(rd), nameGpReg(rb), offset);
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, [%s, #+%u]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), offset);
emitInst(static_cast<ARMWord>(cc) | DTR | DT_BYTE | (isLoad ? DT_LOAD : 0) | DT_UP, rd, rb, offset);
}
@ -683,8 +714,8 @@ namespace JSC {
void dtrsb_u(bool isLoad, int rd, int rb, ARMWord offset, Condition cc = AL)
{
char const * mnemonic = (isLoad) ? ("ldrsb") : ("strb");
spew("%-15s %s, [%s, #+%u]",
mnemonic, nameGpReg(rd), nameGpReg(rb), offset);
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, [%s, #+%u]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), offset);
emitInst(static_cast<ARMWord>(cc) | DTRH | HDT_S | (isLoad ? DT_LOAD : 0) | DT_UP, rd, rb, offset);
}
@ -694,8 +725,8 @@ namespace JSC {
void dtrb_ur(bool isLoad, int rd, int rb, int rm, Condition cc = AL)
{
char const * mnemonic = (isLoad) ? ("ldrb") : ("strb");
spew("%-15s %s, [%s, +%s]",
mnemonic, nameGpReg(rd), nameGpReg(rb), nameGpReg(rm));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, [%s, +%s]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), nameGpReg(rm));
emitInst(static_cast<ARMWord>(cc) | DTR | DT_BYTE | (isLoad ? DT_LOAD : 0) | DT_UP | OP2_OFSREG, rd, rb, rm);
}
@ -705,8 +736,8 @@ namespace JSC {
void dtrb_d(bool isLoad, int rd, int rb, ARMWord offset, Condition cc = AL)
{
char const * mnemonic = (isLoad) ? ("ldrb") : ("strb");
spew("%-15s %s, [%s, #-%u]",
mnemonic, nameGpReg(rd), nameGpReg(rb), offset);
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, [%s, #-%u]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), offset);
emitInst(static_cast<ARMWord>(cc) | DTR | DT_BYTE | (isLoad ? DT_LOAD : 0), rd, rb, offset);
}
@ -717,8 +748,8 @@ namespace JSC {
{
ASSERT(isLoad); /*can only do signed byte loads, not stores*/
char const * mnemonic = (isLoad) ? ("ldrsb") : ("strb");
spew("%-15s %s, [%s, #-%u]",
mnemonic, nameGpReg(rd), nameGpReg(rb), offset);
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, [%s, #-%u]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), offset);
emitInst(static_cast<ARMWord>(cc) | DTRH | HDT_S | (isLoad ? DT_LOAD : 0), rd, rb, offset);
}
@ -728,65 +759,65 @@ namespace JSC {
void dtrb_dr(bool isLoad, int rd, int rb, int rm, Condition cc = AL)
{
char const * mnemonic = (isLoad) ? ("ldrb") : ("strb");
spew("%-15s %s, [%s, -%s]",
mnemonic, nameGpReg(rd), nameGpReg(rb), nameGpReg(rm));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, [%s, -%s]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), nameGpReg(rm));
emitInst(static_cast<ARMWord>(cc) | DTR | DT_BYTE | (isLoad ? DT_LOAD : 0) | OP2_OFSREG, rd, rb, rm);
}
void ldrh_r(int rd, int rb, int rm, Condition cc = AL)
{
spew("%-15s %s, [%s, +%s]",
"ldrh", nameGpReg(rd), nameGpReg(rb), nameGpReg(rm));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, [%s, +%s]\n", MAYBE_PAD, "ldrh", nameGpReg(rd), nameGpReg(rb), nameGpReg(rm));
emitInst(static_cast<ARMWord>(cc) | LDRH | HDT_UH | DT_UP | DT_PRE, rd, rb, rm);
}
void ldrh_d(int rd, int rb, ARMWord offset, Condition cc = AL)
{
spew("%-15s %s, [%s, #-%u]",
"ldrh", nameGpReg(rd), nameGpReg(rb), offset);
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, [%s, #-%u]\n", MAYBE_PAD, "ldrh", nameGpReg(rd), nameGpReg(rb), offset);
emitInst(static_cast<ARMWord>(cc) | LDRH | HDT_UH | DT_PRE, rd, rb, offset);
}
void ldrh_u(int rd, int rb, ARMWord offset, Condition cc = AL)
{
spew("%-15s %s, [%s, #+%u]",
"ldrh", nameGpReg(rd), nameGpReg(rb), offset);
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, [%s, #+%u]\n", MAYBE_PAD, "ldrh", nameGpReg(rd), nameGpReg(rb), offset);
emitInst(static_cast<ARMWord>(cc) | LDRH | HDT_UH | DT_UP | DT_PRE, rd, rb, offset);
}
void ldrsh_d(int rd, int rb, ARMWord offset, Condition cc = AL)
{
spew("%-15s %s, [%s, #-%u]",
"ldrsh", nameGpReg(rd), nameGpReg(rb), offset);
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, [%s, #-%u]\n", MAYBE_PAD, "ldrsh", nameGpReg(rd), nameGpReg(rb), offset);
emitInst(static_cast<ARMWord>(cc) | LDRH | HDT_UH | HDT_S | DT_PRE, rd, rb, offset);
}
void ldrsh_u(int rd, int rb, ARMWord offset, Condition cc = AL)
{
spew("%-15s %s, [%s, #+%u]",
"ldrsh", nameGpReg(rd), nameGpReg(rb), offset);
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, [%s, #+%u]\n", MAYBE_PAD, "ldrsh", nameGpReg(rd), nameGpReg(rb), offset);
emitInst(static_cast<ARMWord>(cc) | LDRH | HDT_UH | HDT_S | DT_UP | DT_PRE, rd, rb, offset);
}
void strh_r(int rb, int rm, int rd, Condition cc = AL)
{
spew("%-15s %s, [%s, +%s]",
"strh", nameGpReg(rd), nameGpReg(rb), nameGpReg(rm));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, [%s, +%s]\n", MAYBE_PAD, "strh", nameGpReg(rd), nameGpReg(rb), nameGpReg(rm));
emitInst(static_cast<ARMWord>(cc) | STRH | HDT_UH | DT_UP | DT_PRE, rd, rb, rm);
}
void push_r(int reg, Condition cc = AL)
{
spew("%-15s {%s}",
"push", nameGpReg(reg));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s {%s}\n", MAYBE_PAD, "push", nameGpReg(reg));
ASSERT(ARMWord(reg) <= 0xf);
m_buffer.putInt(cc | DTR | DT_WB | RN(ARMRegisters::sp) | RD(reg) | 0x4);
}
void pop_r(int reg, Condition cc = AL)
{
spew("%-15s {%s}",
"pop", nameGpReg(reg));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s {%s}\n", MAYBE_PAD, "pop", nameGpReg(reg));
ASSERT(ARMWord(reg) <= 0xf);
m_buffer.putInt(cc | (DTR ^ DT_PRE) | DT_LOAD | DT_UP | RN(ARMRegisters::sp) | RD(reg) | 0x4);
}
@ -814,7 +845,8 @@ namespace JSC {
void bkpt(ARMWord value)
{
#if WTF_ARM_ARCH_VERSION >= 5
spew("%-15s #0x%04x", "bkpt", value);
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s #0x%04x\n", MAYBE_PAD, "bkpt", value);
m_buffer.putInt(BKPT | ((value & 0xfff0) << 4) | (value & 0xf));
#else
// Cannot access to Zero memory address
@ -825,7 +857,9 @@ namespace JSC {
void bx(int rm, Condition cc = AL)
{
#if WTF_ARM_ARCH_VERSION >= 5 || defined(__ARM_ARCH_4T__)
spew("bx%-13s %s", nameCC(cc), nameGpReg(rm));
js::JaegerSpew(
js::JSpew_Insns,
IPFX "bx%-13s %s\n", MAYBE_PAD, nameCC(cc), nameGpReg(rm));
emitInst(static_cast<ARMWord>(cc) | BX, 0, 0, RM(rm));
#else
mov_r(ARMRegisters::pc, RM(rm), cc);
@ -836,7 +870,9 @@ namespace JSC {
{
#if WTF_CPU_ARM && WTF_ARM_ARCH_VERSION >= 5
int s = m_buffer.uncheckedSize();
spew("blx%-12s %s", nameCC(cc), nameGpReg(rm));
js::JaegerSpew(
js::JSpew_Insns,
IPFX "blx%-12s %s\n", MAYBE_PAD, nameCC(cc), nameGpReg(rm));
emitInst(static_cast<ARMWord>(cc) | BLX, 0, 0, RM(rm));
#else
ASSERT(rm != 14);
@ -925,7 +961,7 @@ namespace JSC {
JmpDst label()
{
JmpDst label(m_buffer.size());
spew("#label ((%d))", label.m_offset);
js::JaegerSpew(js::JSpew_Insns, IPFX "#label ((%d))\n", MAYBE_PAD, label.m_offset);
return label;
}
@ -1010,7 +1046,8 @@ namespace JSC {
static void linkPointer(void* code, JmpDst from, void* to)
{
staticSpew("##linkPointer ((%p + %#x)) points to ((%p))",
js::JaegerSpew(js::JSpew_Insns,
"##linkPointer ((%p + %#x)) points to ((%p))\n",
code, from.m_offset, to);
patchPointerInternal(reinterpret_cast<intptr_t>(code) + from.m_offset, to);
@ -1018,7 +1055,8 @@ namespace JSC {
static void repatchInt32(void* from, int32_t to)
{
staticSpew("##repatchInt32 ((%p)) holds ((%#x))",
js::JaegerSpew(js::JSpew_Insns,
ISPFX "##repatchInt32 ((%p)) holds ((%#x))\n",
from, to);
patchPointerInternal(reinterpret_cast<intptr_t>(from), reinterpret_cast<void*>(to));
@ -1026,7 +1064,8 @@ namespace JSC {
static void repatchPointer(void* from, void* to)
{
staticSpew("##repatchPointer ((%p)) points to ((%p))",
js::JaegerSpew(js::JSpew_Insns,
"##repatchPointer ((%p)) points to ((%p))\n",
from, to);
patchPointerInternal(reinterpret_cast<intptr_t>(from), to);
@ -1064,7 +1103,8 @@ namespace JSC {
ARMWord* insn = reinterpret_cast<ARMWord*>(code + from.m_offset);
ARMWord* addr = getLdrImmAddressOnPool(insn, m_buffer.poolAddress());
spew("##linkJump ((%#x)) jumps to ((%#x))",
js::JaegerSpew(js::JSpew_Insns,
IPFX "##linkJump ((%#x)) jumps to ((%#x))\n", MAYBE_PAD,
from.m_offset, to.m_offset);
*addr = to.m_offset;
@ -1072,7 +1112,8 @@ namespace JSC {
static void linkJump(void* code, JmpSrc from, void* to)
{
staticSpew("##linkJump ((%p + %#x)) jumps to ((%p))",
js::JaegerSpew(js::JSpew_Insns,
ISPFX "##linkJump ((%p + %#x)) jumps to ((%p))\n",
code, from.m_offset, to);
patchPointerInternal(reinterpret_cast<intptr_t>(code) + from.m_offset, to);
@ -1080,7 +1121,8 @@ namespace JSC {
static void relinkJump(void* from, void* to)
{
staticSpew("##relinkJump ((%p)) jumps to ((%p))",
js::JaegerSpew(js::JSpew_Insns,
ISPFX "##relinkJump ((%p)) jumps to ((%p))\n",
from, to);
patchPointerInternal(reinterpret_cast<intptr_t>(from), to);
@ -1093,7 +1135,8 @@ namespace JSC {
static void linkCall(void* code, JmpSrc from, void* to)
{
staticSpew("##linkCall ((%p + %#x)) jumps to ((%p))",
js::JaegerSpew(js::JSpew_Insns,
ISPFX "##linkCall ((%p + %#x)) jumps to ((%p))\n",
code, from.m_offset, to);
patchPointerInternal(reinterpret_cast<intptr_t>(code) + from.m_offset, to);
@ -1101,7 +1144,8 @@ namespace JSC {
static void relinkCall(void* from, void* to)
{
staticSpew("##relinkCall ((%p)) jumps to ((%p))",
js::JaegerSpew(js::JSpew_Insns,
ISPFX "##relinkCall ((%p)) jumps to ((%p))\n",
from, to);
patchPointerInternal(reinterpret_cast<intptr_t>(from), to);
@ -1341,7 +1385,8 @@ namespace JSC {
char op2_fmt[48];
fmtOp2(op2_fmt, op2);
spew("%-15s %s, %s, %s", mnemonic, nameGpReg(rd), nameGpReg(rn), op2_fmt);
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, %s, %s\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rn), op2_fmt);
}
void spewInsWithOp2(char const * ins, Condition cc, int r, ARMWord op2)
@ -1352,7 +1397,8 @@ namespace JSC {
char op2_fmt[48];
fmtOp2(op2_fmt, op2);
spew("%-15s %s, %s", mnemonic, nameGpReg(r), op2_fmt);
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, %s\n", MAYBE_PAD, mnemonic, nameGpReg(r), op2_fmt);
}
ARMWord RM(int reg)
@ -1510,7 +1556,8 @@ namespace JSC {
void fmem_imm_off(bool isLoad, bool isDouble, bool isUp, int dest, int rn, ARMWord offset, Condition cc = AL)
{
char const * ins = isLoad ? "vldr.f" : "vstr.f";
spew("%s%d %s, [%s, #%s%u]",
js::JaegerSpew(js::JSpew_Insns,
IPFX "%s%d %s, [%s, #%s%u]\n", MAYBE_PAD,
ins, (isDouble ? 64 : 32), (isDouble ? nameFpRegD(dest) : nameFpRegS(dest)),
nameGpReg(rn), (isUp ? "+" : "-"), offset);
ASSERT(offset <= 0xff);
@ -1529,7 +1576,8 @@ namespace JSC {
ASSERT(srcType != dstType);
ASSERT(isFloatType(srcType) || isFloatType(dstType));
spew("vcvt.%s.%-15s, %s,%s",
js::JaegerSpew(js::JSpew_Insns,
IPFX "vcvt.%s.%-15s, %s,%s\n", MAYBE_PAD,
nameType(dstType), nameType(srcType),
nameTypedReg(dstType,dest), nameTypedReg(srcType,src));
@ -1549,10 +1597,12 @@ namespace JSC {
void vmov64 (bool fromFP, bool isDbl, int r1, int r2, int rFP, Condition cc = AL)
{
if (fromFP) {
spew("%-15s %s, %s, %s", "vmov",
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, %s, %s\n", MAYBE_PAD, "vmov",
nameGpReg(r1), nameGpReg(r2), nameFpRegD(rFP));
} else {
spew("%-15s %s, %s, %s", "vmov",
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, %s, %s\n", MAYBE_PAD, "vmov",
nameFpRegD(rFP), nameGpReg(r1), nameGpReg(r2));
}
emitVFPInst(static_cast<ARMWord>(cc) | VFP_DXFER | VFP_MOV |
@ -1562,7 +1612,8 @@ namespace JSC {
void fcpyd_r(int dd, int dm, Condition cc = AL)
{
spew("%-15s %s, %s", "vmov.f64",
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, %s\n", MAYBE_PAD, "vmov.f64",
nameFpRegD(dd), nameFpRegD(dm));
// TODO: emitInst doesn't work for VFP instructions, though it
// seems to work for current usage.
@ -1571,7 +1622,8 @@ namespace JSC {
void faddd_r(int dd, int dn, int dm, Condition cc = AL)
{
spew("%-15s %s, %s, %s", "vadd.f64", nameFpRegD(dd), nameFpRegD(dn), nameFpRegD(dm));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, %s, %s\n", MAYBE_PAD, "vadd.f64", nameFpRegD(dd), nameFpRegD(dn), nameFpRegD(dm));
// TODO: emitInst doesn't work for VFP instructions, though it
// seems to work for current usage.
emitVFPInst(static_cast<ARMWord>(cc) | FADDD, DD(dd), DN(dn), DM(dm));
@ -1579,13 +1631,15 @@ namespace JSC {
void fnegd_r(int dd, int dm, Condition cc = AL)
{
spew("%-15s %s, %s", "fnegd", nameFpRegD(dd), nameFpRegD(dm));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, %s\n", MAYBE_PAD, "fnegd", nameFpRegD(dd), nameFpRegD(dm));
m_buffer.putInt(static_cast<ARMWord>(cc) | FNEGD | DD(dd) | DM(dm));
}
void fdivd_r(int dd, int dn, int dm, Condition cc = AL)
{
spew("%-15s %s, %s, %s", "vdiv.f64", nameFpRegD(dd), nameFpRegD(dn), nameFpRegD(dm));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, %s, %s\n", MAYBE_PAD, "vdiv.f64", nameFpRegD(dd), nameFpRegD(dn), nameFpRegD(dm));
// TODO: emitInst doesn't work for VFP instructions, though it
// seems to work for current usage.
emitVFPInst(static_cast<ARMWord>(cc) | FDIVD, DD(dd), DN(dn), DM(dm));
@ -1593,7 +1647,8 @@ namespace JSC {
void fsubd_r(int dd, int dn, int dm, Condition cc = AL)
{
spew("%-15s %s, %s, %s", "vsub.f64", nameFpRegD(dd), nameFpRegD(dn), nameFpRegD(dm));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, %s, %s\n", MAYBE_PAD, "vsub.f64", nameFpRegD(dd), nameFpRegD(dn), nameFpRegD(dm));
// TODO: emitInst doesn't work for VFP instructions, though it
// seems to work for current usage.
emitVFPInst(static_cast<ARMWord>(cc) | FSUBD, DD(dd), DN(dn), DM(dm));
@ -1601,13 +1656,15 @@ namespace JSC {
void fabsd_r(int dd, int dm, Condition cc = AL)
{
spew("%-15s %s, %s", "fabsd", nameFpRegD(dd), nameFpRegD(dm));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, %s\n", MAYBE_PAD, "fabsd", nameFpRegD(dd), nameFpRegD(dm));
m_buffer.putInt(static_cast<ARMWord>(cc) | FABSD | DD(dd) | DM(dm));
}
void fmuld_r(int dd, int dn, int dm, Condition cc = AL)
{
spew("%-15s %s, %s, %s", "vmul.f64", nameFpRegD(dd), nameFpRegD(dn), nameFpRegD(dm));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, %s, %s\n", MAYBE_PAD, "vmul.f64", nameFpRegD(dd), nameFpRegD(dn), nameFpRegD(dm));
// TODO: emitInst doesn't work for VFP instructions, though it
// seems to work for current usage.
emitVFPInst(static_cast<ARMWord>(cc) | FMULD, DD(dd), DN(dn), DM(dm));
@ -1615,7 +1672,8 @@ namespace JSC {
void fcmpd_r(int dd, int dm, Condition cc = AL)
{
spew("%-15s %s, %s", "vcmp.f64", nameFpRegD(dd), nameFpRegD(dm));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, %s\n", MAYBE_PAD, "vcmp.f64", nameFpRegD(dd), nameFpRegD(dm));
// TODO: emitInst doesn't work for VFP instructions, though it
// seems to work for current usage.
emitVFPInst(static_cast<ARMWord>(cc) | FCMPD, DD(dd), 0, DM(dm));
@ -1623,7 +1681,8 @@ namespace JSC {
void fsqrtd_r(int dd, int dm, Condition cc = AL)
{
spew("%-15s %s, %s", "vsqrt.f64", nameFpRegD(dd), nameFpRegD(dm));
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, %s\n", MAYBE_PAD, "vsqrt.f64", nameFpRegD(dd), nameFpRegD(dm));
// TODO: emitInst doesn't work for VFP instructions, though it
// seems to work for current usage.
emitVFPInst(static_cast<ARMWord>(cc) | FSQRTD, DD(dd), 0, DM(dm));

89
js/src/assembler/assembler/AssemblerBuffer.h
View File

@ -39,20 +39,6 @@
#include "assembler/jit/ExecutableAllocator.h"
#include "assembler/wtf/Assertions.h"
#include <stdarg.h>
#include "jsopcode.h"
#include "methodjit/Logging.h"
#include "ion/IonSpewer.h"
#define PRETTY_PRINT_OFFSET(os) (((os)<0)?"-":""), (((os)<0)?-(os):(os))
#define FIXME_INSN_PRINTING \
do { \
spew("FIXME insn printing %s:%d", \
__FILE__, __LINE__); \
} while (0)
namespace JSC {
class AssemblerBuffer {
@ -248,81 +234,6 @@ namespace JSC {
bool m_oom;
};
class GenericAssembler
{
js::Sprinter *printer;
public:
bool isOOLPath;
GenericAssembler()
: printer(NULL)
, isOOLPath(false)
{}
void setPrinter(js::Sprinter *sp) {
printer = sp;
}
void spew(const char *fmt, ...)
#ifdef __GNUC__
__attribute__ ((format (printf, 2, 3)))
#endif
{
if (printer ||
js::IsJaegerSpewChannelActive(js::JSpew_Insns) ||
js::ion::IonSpewEnabled(js::ion::IonSpew_Codegen))
{
// Buffer to hold the formatted string. Note that this may contain
// '%' characters, so do not pass it directly to printf functions.
char buf[200];
va_list va;
va_start(va, fmt);
int i = vsnprintf(buf, sizeof(buf), fmt, va);
va_end(va);
if (i > -1) {
if (printer)
printer->printf("%s\n", buf);
// The assembler doesn't know which compiler it is for, so if
// both JM and Ion spew are on, just print via one channel
// (Use JM to pick up isOOLPath).
if (js::IsJaegerSpewChannelActive(js::JSpew_Insns))
js::JaegerSpew(js::JSpew_Insns, "%s %s\n", isOOLPath ? ">" : " ", buf);
else
js::ion::IonSpew(js::ion::IonSpew_Codegen, "%s", buf);
}
}
}
static void staticSpew(const char *fmt, ...)
#ifdef __GNUC__
__attribute__ ((format (printf, 1, 2)))
#endif
{
if (js::IsJaegerSpewChannelActive(js::JSpew_Insns) ||
js::ion::IonSpewEnabled(js::ion::IonSpew_Codegen))
{
char buf[200];
va_list va;
va_start(va, fmt);
int i = vsnprintf(buf, sizeof(buf), fmt, va);
va_end(va);
if (i > -1) {
if (js::IsJaegerSpewChannelActive(js::JSpew_Insns))
js::JaegerSpew(js::JSpew_Insns, " %s\n", buf);
else
js::ion::IonSpew(js::ion::IonSpew_Codegen, "%s", buf);
}
}
}
};
} // namespace JSC
#endif // ENABLE(ASSEMBLER)

2
js/src/assembler/assembler/AssemblerBufferWithConstantPool.h
View File

@ -333,7 +333,7 @@ private:
// optionally place a jump to ensure we don't start executing the pool.
void flushConstantPool(bool useBarrier = true)
{
GenericAssembler::staticSpew(" -- FLUSHING CONSTANT POOL WITH %d CONSTANTS --\n",
js::JaegerSpew(js::JSpew_Insns, " -- FLUSHING CONSTANT POOL WITH %d CONSTANTS --\n",
m_numConsts);
if (m_numConsts == 0)
return;

18
js/src/assembler/assembler/MIPSAssembler.h
View File

@ -40,8 +40,17 @@
#define ISPFX " "
#ifdef JS_METHODJIT_SPEW
# define MAYBE_PAD (isOOLPath ? "> " : "")
# define PRETTY_PRINT_OFFSET(os) (((os)<0)?"-":""), (((os)<0)?-(os):(os))
# define FIXME_INSN_PRINTING \
do { \
js::JaegerSpew(js::JSpew_Insns, \
ISPFX "FIXME insn printing %s:%d\n", \
__FILE__, __LINE__); \
} while (0)
#else
# define MAYBE_PAD ""
# define FIXME_INSN_PRINTING ((void) 0)
# define PRETTY_PRINT_OFFSET(os) "", 0
#endif
namespace JSC {
@ -153,7 +162,7 @@ typedef enum {
} // namespace MIPSRegisters
class MIPSAssembler : public GenericAssembler {
class MIPSAssembler {
public:
typedef MIPSRegisters::RegisterID RegisterID;
typedef MIPSRegisters::FPRegisterID FPRegisterID;
@ -161,6 +170,13 @@ public:
unsigned char *buffer() const { return m_buffer.buffer(); }
bool oom() const { return m_buffer.oom(); }
#ifdef JS_METHODJIT_SPEW
bool isOOLPath;
MIPSAssembler() : isOOLPath(false) { }
#else
MIPSAssembler() { }
#endif
// MIPS instruction opcode field position
enum {
OP_SH_RD = 11,

18
js/src/assembler/assembler/SparcAssembler.h
View File

@ -22,8 +22,17 @@
#define ISPFX " "
#ifdef JS_METHODJIT_SPEW
# define MAYBE_PAD (isOOLPath ? "> " : "")
# define PRETTY_PRINT_OFFSET(os) (((os)<0)?"-":""), (((os)<0)?-(os):(os))
# define FIXME_INSN_PRINTING \
do { \
js::JaegerSpew(js::JSpew_Insns, \
ISPFX "FIXME insn printing %s:%d\n", \
__FILE__, __LINE__); \
} while (0)
#else
# define MAYBE_PAD ""
# define FIXME_INSN_PRINTING ((void) 0)
# define PRETTY_PRINT_OFFSET(os) "", 0
#endif
namespace JSC {
@ -109,13 +118,20 @@ namespace JSC {
} // namespace SparcRegisters
class SparcAssembler : public GenericAssembler {
class SparcAssembler {
public:
typedef SparcRegisters::RegisterID RegisterID;
typedef SparcRegisters::FPRegisterID FPRegisterID;
AssemblerBuffer m_buffer;
bool oom() const { return m_buffer.oom(); }
#ifdef JS_METHODJIT_SPEW
bool isOOLPath;
SparcAssembler() : isOOLPath(false) { }
#else
SparcAssembler() { }
#endif
// Sparc conditional constants
typedef enum {
ConditionE = 0x1, // Zero

600
js/src/assembler/assembler/X86Assembler.h
View File

File diff suppressed because it is too large Load Diff

2
js/src/ion/C1Spewer.h
View File

@ -10,6 +10,8 @@
#ifndef jsion_c1spewer_h__
#define jsion_c1spewer_h__
#include "jscntxt.h"
namespace js {
namespace ion {

5
js/src/ion/CodeGenerator.cpp
View File

@ -1457,7 +1457,6 @@ CodeGenerator::generateBody()
printer.construct(GetIonContext()->cx);
if (!printer.ref().init())
return false;
masm.setPrinter(printer.addr());
}
for (; iter != current->end(); iter++) {
@ -1476,10 +1475,8 @@ CodeGenerator::generateBody()
if (masm.oom())
return false;
if (counts) {
if (counts)
counts->block(i).setCode(printer.ref().string());
masm.setPrinter(NULL);
}
}
JS_ASSERT(pushedArgumentSlots_.empty());

4
js/src/ion/arm/Assembler-arm.h
View File

@ -1269,10 +1269,6 @@ class Assembler
static const uint32 * getPtr32Target(Iter *iter, Register *dest = NULL, RelocStyle *rs = NULL);
bool oom() const;
void setPrinter(Sprinter *sp) {
}
private:
bool isFinished;
public:

2
js/src/ion/arm/Trampoline-arm.cpp
View File

@ -5,12 +5,12 @@
* License, v. 2.0. If a copy of the MPL was not distributed with this
* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
#include "ion/IonSpewer.h"
#include "jscompartment.h"
#include "assembler/assembler/MacroAssembler.h"
#include "ion/IonCompartment.h"
#include "ion/IonLinker.h"
#include "ion/IonFrames.h"
#include "ion/IonSpewer.h"
#include "ion/Bailouts.h"
#include "ion/VMFunctions.h"

4
js/src/ion/shared/Assembler-x86-shared.h
View File

@ -128,10 +128,6 @@ class AssemblerX86Shared
dataRelocations_.oom();
}
void setPrinter(Sprinter *sp) {
masm.setPrinter(sp);
}
void executableCopy(void *buffer);
void processDeferredData(IonCode *code, uint8 *data);
void processCodeLabels(IonCode *code);

5
js/src/methodjit/Logging.h
View File

@ -85,11 +85,6 @@ struct Profiler {
#else
static inline bool IsJaegerSpewChannelActive(JaegerSpewChannel channel)
{
return false;
}
static inline void JaegerSpew(JaegerSpewChannel channel, const char *fmt, ...)
{
}